Next Generation FPGAs

8/11/2019 Next Generation FPGAs

1/29

On Chip Networks

for Next Generation FPGAs

By : Alaa Salaheldin


2/29


3/29

Agenda

Why using FPGA

Conventional interconnects problems

NoC advantages

NoC architecture

Previous work

Possible future work


4/29

Why using FPGA

FPGA Compared to ASIC

Faster time-to-market

No NRE (non recurring expenses) Simpler design cycle

High Configurability

Slower than ASIC Consumes more power than ASIC

Cost : depends on volume and technology


5/29

Cost of FPGA Vs ASIC


6/29

Agenda

Why using FPGA


NoC advantages

NoC architecture

Previous work



7/29

Conventional Interconnects Problems

Wire speed doesnt scale with technology

Slow Compilation

Take large area Take large Power


8/29

Area of interconnects


9/29

Conventional Interconnects Problems

Wire speed doesnt scale with technology

Slow Compilation

Take large area Take large Power


10/29

Power Consumption of interconnects


11/29

So routing wires is expensive, slow and power

hungry

What about routing packets instead of wires!


12/29

Agenda

Why using FPGA


NoC advantages

NoC architecture

Previous work



13/29

Simple NoC based system


14/29

NoC Advantages

Can reach high bandwidth

NoC links are re-usable

Less compilation time, Higher abstract level Allows partial reconfiguration

More power efficient

More area efficient


15/29

Agenda

Why using FPGA


NoC advantages

NoC architecture

Previous work



16/29

NoC Router architecture


17/29

Agenda

Why using FPGA


NoC advantages

NoC architecture

Previous work



18/29

On-Chip Interconnection Networks,

2001

Connecting top level modules using

NoC instead of normal wires.

Power dissipation can be reduced to

factor of ten, and speed is increasedthree times.

An on-chip interconnection network facilitates modularity

by

defining a standard interface

He used a VC router and it only consumes 6.6% of tile

area

Wasnt made for FPGAs and flow control methods are

required to reduce buffer size, it doesnt support wide


19/29

Architecture and Routing In NOC based FPGA,

2007

Focused on NoC design for FPGAs, specially routing

schemes.

Explored which NOC functionalities to implement as

Hard cores and which to leave Soft.

Explained the tradeoff between the flexibility of soft

designs and the better performance offered by hard

ones.

Explained that deterministic routing schemes are

enough for FPGAs.

Presented a new routing method designed for FPGA,

the Weighted Toggle XY (WTXY)


20/29

Architecture and Routing In NOC based FPGA,

2007


21/29

Exploring FPGA NOC Implementation (NoCem),

2008

Comparison between a complex NOC built for ASIC

"NoCem" and a simple NOC built for FPGA 'under

certain condition.

Simple NOC

Has one word FIFO as the physical channel link

between any two routers

Has no virtual channels so theres nor need for

Channel Allocation

Only allows one switching operation at any given time


22/29


2008


23/29


2008


24/29


2008


25/29

Design Tradeoffs for Hard and Soft FPGA-based NOCs,

2012

Explores which part of a NOC to be hardened and which

part to be left as soft.

Main system parameters are Port width, Number of

Ports, Number of VCs and Buffer depth.

Contributions:

The Crossbar has to be hardened, it has the largest area and

delay gaps of 85x and 4.4x

Input buffers could be kept soft as it has the smallest gaps, 17x

area and 2.9 delay.

Increasing bandwidth by scaling the width is more efficient way

than increasing Ports or VCs.

A 64-node hard NOC has lower area overhead than a 3-node

soft NOC


26/29


2012


27/29


2012


28/29


Improvement:1) New design for router

2) Links between blocks and routers3) Which router microarchitecture!!!

4) Adaptive and dynamic routing

5) Offline optimization

6) Topology ! Maybe fat tree!

7) TDM wiring for router links and for routers

interfaces to logic fabric

8) DTMOS for router fabric


29/29

Questions and Discussion

Documents

Next Generation FPGAs