TCAD NewsJune 2007Contents

4TCAD Distortion Analysis Based on the Harmonic Balance Method

TCAD for Electrostatic DischargeIntroduction Electrostatic discharge (ESD) is a major threat to the reliability of integrated circuits, where approximately 20% of total integrated circuit (IC) failures are due to ESD [1]. Discharge of charged objects or human discharge into IC chip pins with very high currents (up to 10 A) and short duration (1 ns to 200 ns) causes serious damage to the very sensitive devices of the circuitry. This happens during manufacturing, assembly, shipment, and in the field. This article demonstrates the successful use of TCAD for the simulation and investigation of ESD-related problems, as well as for the development and optimization of ESD protection devices and methodologies with respect to ESD robustness. The full range from ESD calibration, ESD device simulation, to ESD compact modeling for circuit simulation is covered. Background The operational regime of devices under ESD stress is far beyond the range of normal operation conditions. Among the most important effects to be considered within the ESD regime are self-heating, conductivity modulation due to high carrier injection, nonuniform operation (current filamentation), and avalanche breakdown at reverse-biased junctions. To characterize the device high-current regime, mostly the transmission line pulsing (TLP) technique is used [2]. This two-terminal technique consists of feeding a constant current pulse into the device under test (DUT) and monitoring the voltage response. The pulse has a typical duration of 100 ns with a rise-time of 10 ns. The characterization using TLP allows for obtaining device characteristics up to very high current levels, while preventing early destruction due to self-heating. Within the device simulation environment, TLP is used to calibrate high-current, hightemperature regimes to measurements. For the qualification and specification of ESD robustness, other more realistic ESD stress models are used. The most prominent one is the human body model (HBM), which reproduces the discharge of the body of a human being. Additional models used are the machine model (MM) and the charged device model (CDM). Apart from the field of application, they differ from the HBM due to a different rise-time, peak current, duration, and polarity [3]. In summary, the basic functionality of an ESD protection device or circuit is to provide a low-resistivity discharge-current path, which prevents the internal circuitry as well as the protection device/circuit itself from being damaged during an ESD event. The ESD protection functionality is transparent to the internal circuitry under normal operation conditions. Figure 1 shows the most important parameters of the so-called ESD design window. TCAD-Driven ESD Optimization TCAD is a powerful tool for identifying and investigating ESD-relevant effects, providingITrend for Thinner Oxides

5An Efficient Simulation Environment for Modeling Single Event Effects with the Sentaurus Tool Suite

VSUPPLYLatch-Up Margin

VBD

process and device simulation model set in 1D and 2D. In a further step, ESD-related modeling shown in Figure 3 is addressed by: High-temperature calibrated models: Impact ionization and mobility (low-field, carrier-tocarrier scattering, high-field saturation) Bipolar-specific models: Recombination and bandgap narrowing Electrothermal effects: mechanisms and heat flows Self-heating

6Impact of Gettering Effects in Solar Cells

7Simulation of 4H-SiC Vertical Junction FET in Sentaurus Device

Device Damage Margin

Vh

Vt1

V

Figure 1. Typical ESD design window for protection devices.

Latest EditionWelcome to the latest issue of TCAD News. Over the years, TCAD has proven to be an enabling methodology for reducing technology development costs and time. The use of TCAD, however, extends beyond nanoscale silicon CMOS devices. In this issue, I am delighted to present articles showing the wide application of TCAD tools for modeling and analyzing physical phenomena and effects beyond nanoscale silicon CMOS devices. As device features continue to scale down, the threat of device or circuit failures caused by reliability issues such as electrostatic discharge (ESD) and single event effects (SEEs) grows. For example, device engineers face difficult challenges of designing robust ESD protection and meeting the required ESD levels in new designs. The first article outlines a TCAD-driven ESD approach that enables chipmakers to develop a comprehensive methodology to analyze and treat ESD-related problems. Another reliability issue is SEE, which can cause unwanted changes to semiconductor devices when highly energetic particles strike an IC chip. We include an article to show an efficient way of modeling the effects of single event upset on CMOS devices. This edition also includes articles on specialty devices. For readers interested in analog RF devices, one article examines the use of harmonic balance in Sentaurus Device to analyze the distorting characteristics of an SiGe BJT and Si NMOS RF device. Recent progress in improving SiC material with zero micropipe defects is pushing SiC electronic devices for high-power and high-temperature applications into the mainstream. We include an article showing the benefits of using TCAD to explore and optimize an emerging technology such as SiC. In addition, we highlight the impact of gettering effects in solar cells. I trust that you will enjoy this edition of TCAD News. Please contact us for your comments and feedback. With best regards,

insights into the internal device behavior (such as temperature and current distributions, and electric fields) under ESD stress conditions, which are generally not accessible by measurement. In particular, TCAD can be used successfully for the study of 3D effects arising from device layout or inhomogeneous current flow as shown in Figure 2. TCAD is invaluable for modeling these complex ESD effects [4][5], providing simulation results that complement expensive measurements and reducing expensive experiments on wafers. From the device or TCAD engineering perspective, establishing a full-fledged ESD TCAD workbench from process and layout information, and from the calibration of simulation models including the high current/high temperature regime, allows the evaluation of process variation influences, the determination of layout dependency, and the optimization of ESD structures. The improved understanding of the internal device failure modes results in building better input/output protection structures and the possibility of virtual testing and development of new structures. TCAD also helps speed up ESD design to keep pace with IC developments at reduced design-cycle times by reducing time-to-market and cost-to-market. From the circuit or library design perspective, TCAD permits the development and application of physically based SPICE ESD compact models and parameter extraction methodologies from simulation and measurement. The SPICE ESD compact models allow for simple and fast use within circuit and analog design, and for optimization of protection configurations. The simulationbased methodology allows checking of critical input/output protection configurations before IC tape-out and avoiding redesigns. Requirements for ESD Modeling The starting point for a successful calibration of the ESD characteristics of a device is a well-calibrated, low-current and breakdown

Information about layout and measurement setup: Contact resistances and 3D layout features100 Self-heating (mobility, impact ionization) 1500 Snapback (bipolar effect)

Maximum Temperature [K]

Drain Current [A]

10-1

1000

10-2 Breakdown (impact ionization)

500

10-3

0

10

20 30 Drain Voltage [V]

40

Figure 3. Physical effects considered for successful ESD modeling. The example shows the high-current behavior of a power MOS device obtained by simulation.

Essential for correct device modeling and calibration is knowledge about the TLP tester rise-time, the pulse duration, and the voltage extraction method used in measurements in order to implement the same conditions in simulation. The HBM testerequivalent circuit model must be known if HBM robustness is to be simulated and compared to measurements. The mixed-mode simulation capability of Sentaurus Device permits the integration of the HBM testerequivalent circuit model with the physical device model of the DUT in the simulation environment. A comparison of TLP versus HBM measurement/simulation methodologies is shown in Figure 4. Methodology for ESD Device Calibration and Simulation The junction breakdown characteristics due to impact ionization and tunneling should be already in good agreement with measurements at room temperature. Nevertheless, in some cases, a fine-tuning of model parameters may be necessary. The onset of breakdown is influenced mainly by the doping profile (gradient), the bending of material interfaces (for example, LOCOS birds beak), and the doping profile corner effects (3D).

Abs(TotalCurrentDensity) 1.0e+06 6.3e+04 4.0e+03 2.5e+02 1.6e+01 1.0e-00

Terry Ma Group Director, TCAD Business Unit

Figure 2. Formation of current filament leading to temperature hot-spot in a device during an ESD pulse using Sentaurus Device 3D device simulation.

TCAD NewsVoltage Response TLP Current HBM-equivalent Lumped Element Circuit Increasing Current Level S1 Vhbm 70% of tp tr Current tp tf Time Chbm S2 Ls Rhbm Ctb DUT Cs10-2 10-3 DCG = 1 m DCG = 2 m Holding Point Snapback Point

Nonsalicide blockedId [A]

10-4 10-5 10-6 10-7 10-8

Salicide blocked GateDouble Exponential Current Waveform

Drain

10-9 10-10 0 2 4 Vd [V] 6

HBM Current

Source Bulk

0.015

DCG = 1 m DCG = 2 m It2

0.01 Id [A]

Ron

Voltage

Time

Figure 4. TLP versus HBM measurement/simulation methodologies. TLP is more suitable for calibration purposes due to controlled current condition. HBM tries to reproduce the discharge through the human body and is used for ESD robustness assessment. Both methods have comparable pulse energies, and their ESD failure levels show a clear correlation [2].

Figure 6. ESD failure signature: molten silicon between drain and source contacts due to current filaments.

0.005

Holding Point

0

2

4 Vd [V]

6

The temperature dependence of impact ionization must be calibrated as well to obtain the correct behavior at high temperatures. Ideally, breakdown voltage measurements at different temperatures are used for this purpose. For calibrating the snapback point (It1, Vt1), the most important quantity is the effective base resistance Rb of the bipolar device (or the inherent parasitic bipolar device between the drain, body, and source in the case of MOS). Bipolar snapback is triggered after the collector-base junction is driven into avalanche breakdown (see Figure 5). As a result, in the case of NPN, the impact-generated hole current is conducted from the avalanche region (G) through the p-region to the base contacts. Consequently, the hole current causes a voltage drop across the Rb, which induces a forward bias to the base-emitter junction. Eventually, a sufficient base-emitter current flow results in the triggering of the NPN transistor. The positive feedback loop formed by increasing impact ionization and increasing forward bias of the base-emitter junction produces the well-known voltage snapback behavior with a negative differential resistance (NDR) regime until a holding voltage Vh is reached.+ B E h B h G C e

of the bandgap narrowing model may need to be adjusted in this case. Some influence of high-field saturation (carrier velocity saturation) may be seen as well. A further increase of the collector (drain) current leads to an increase of the device voltage due to its on-resistance Ron = collector or drain resistance. Usually, the holding region after snapback in TLP measurements is not very well resolved due to the small load-line resistance (50 W) of the equipment. For the calibration of Vh, such measurements may be sufficient because of the low Ron (almost vertical characteristics) after the holding point. At the current levels, after holding point, selfheating plays the predominant role. Therefore, the definition of suitable thermal boundary conditions for electrothermal simulation is mandatory. The importance of these conditions even increases if the temperature hot-spot lies near the simulation boundary. The temperature distribution may become inhomogeneous in the third dimension as well. In that case, 3D simulation is needed. Similar to the case of the snapback point, this situation can be considered in 2D by adding an external series resistance extracted from 3D simulation. For tuning Ron in this regime, besides the temperature dependence of bulk mobility, carriercarrier scattering and high-field saturation model parameters can be used. The voltage drop across the series resistances of the measurement setup and across the device contacts are taken into account; otherwise, this can lead to erroneous calibration. At the point where the device becomes intrinsic (the thermally generated carrier concentration exceeds the doping concentration), the so-called second breakdown or thermal breakdown sets in. The device is damaged irreversibly by the melting of silicon as a result of the fast thermal runaway caused by the positive feedback loop, consisting of decreasing resistivity and increasing temperature. The current level at which this happens is called It2. By its nature, the second breakdown is a 3D effect. The thermal runaway instability occurs in a very confined region of the device, drawing the total device current into this region and causing the temperature to exceed the melting temperature of silicon locally. Analyzing the device after stressing by physical failure analysis reveals the molten filament, as shown in Figure 6. The most simple and direct criterion for simulating the second breakdown is given by Tmax Tmelt. Using this criterion is questionable because even the more advanced simulation models are calibrated to measurements only up to T = 1000 K, a temperature that is much lower compared to the melting temperature of silicon (Tmelt = 1690 K). Nevertheless, an extrapolation of the model into higher temperature ranges should not lead to dramatic errors and, at least, should preserve the trends. Other more sophisticated methods for extracting It2 from

simulation are found in literature [5][7][8]. They all try to avoid the use of high-temperature device simulations because of expected lower accuracy and convergence problems. In summary, the starting point is a wellcalibrated simulation environment for normal operation conditions, and then models required for modeling ESD behavior are added and calibrated step-by-step from lower to higher current levels. In the end, the goal is to obtain one set of parameters that allow the predictive simulation of ESD behavior and, at the same time, that can be used for normal operation conditions. An accuracy of It1, Vt1, Vh, and Ron compared to TLP measurements of 10% is reasonable. For It2 using the abovementioned method, 30% is feasible. Example of 3D ESD Simulation Electrothermal ESD simulations of a 3D NMOS structure are presented to demonstrate the capabilities of TCAD for ESD. Figure 7 shows the structure of the NMOS simulated. Only half of the device has been modeled to save mesh points by taking advantage of the symmetry plane in the middle of the device. The gate length is 0.35 mm, and the entire simulation area is 6.3 x 3.5 x 10 mm. The distance between the drain-contact and gate has been varied as indicated.DopingConcentration 3.1e+20 9.8e+16 3.1e+13 -2.6e+13 -8.3e+16 -2.7e+20

Figure 8. (Top) Snapback IV characteristics of 3D NMOS in logarithmic current scale and (bottom) linear current scale.

leads to an inhomogeneous current flow. At the holding point, Id = 3 x 103 A, the current flow is still inhomogeneous but starts to homogenize. The current constriction during snapback cannot be modeled with 2D device simulations. Therefore, 2D simulations would predict too low a holding voltage because a larger effective device width is assumed. Above the holding point, the current starts to flow more and more homogeneously over the entire width of the device, and the temperature starts to rise. The hot spot lies at the drain junction towards the gate, and the temperature is higher in the middle of the device. This leads eventually to a destructive current filament in the middle of the device when the temperature approaches the intrinsic temperature of silicon.Id = 3e-4 A Id = 3.4e-4 A Id = 3e-3 A

Id = 1e-2 A

Id = 1.4e-2 A

Id = 1.5e-2 A

TotalCurrentDensity 5.0e+06 9.1e+05 1.7e+05 3.0e+04 5.5e+03 1.0e+03

e

Figure 5. Schematic cross section of NPN transistor (or parasitic NPN transistor in MOS case) showing carrier flow in snapback operation.

DCG

Id = 3e-4 A

Id = 3.4e-4 A

Id = 3e-3 A

The calibration of the snapback current level It1 may require some adjustment of the parameters of the low-field mobility model for low- and medium-range temperatures because self-heating may play a role. If evidence of inhomogeneous current flow is found (inhomogeneous triggering [6]), it is necessary to use 3D simulations to correctly predict snapback behavior (see Example of 3D ESD Simulation). In a later step, the inhomogeneous triggering can be accounted for in 2D simulations by adding an external base resistance Rbext extracted from 3D simulation. Rbext increases the total base resistance and reproduces the effect of current constriction in a physically correct manner. The snapback voltage Vt1 is, in general, more difficult to control. It depends mainly on the voltage drop across the portion of the device between the location of the maximum impact ionization and the base-collector (sourcedrain) terminals. The holding voltage Vh depends on the bipolar transistor effective current gain and on the impact ionization as a function of the internal collector-base voltage and temperature. Recombination lifetimes and the parameters 2

Id = 1e-2 A

Id = 1.4e-2 A

Id = 1.5e-2 A

Figure 7. Three-dimensional NMOS structure simulated; the DCG has been varied.

Figure 8 shows the typical snapback IV characteristics during an ESD surge. The structure with the smaller drain-contact to gate (DCG) spacing shows a lower resistivity in the high-current regime as expected. The important ESD quantities, snapback point, holding point, and Ron, are shown also in Figure 8. Even It2 can be identified by a sudden increase of the voltage due to current filament formation and the subsequent voltage drop when the silicon becomes intrinsic. Figure 9 shows contour plots of the total current density and the temperature at six different current levels. The first picture, at Id = 3 x 104 A, shows the situation immediately before snapback. The breakdown occurs at the drain-to-bulk junction towards the gate. The impact ionization is homogeneous along the junction, indicated by the homogeneous current density. The picture at Id = 3.4 x 104 A is taken immediately after snapback. The parasitic NPN transistor triggers first in the middle of the device, which

LatticeTemperature 1.3e+06 1.1e+05 9.0e+05 7.0e+04 5.0e+03 3.0e+03

Figure 9. Contour plots of total current density (upper six graphics) and temperature (lower six graphics) at the drain current level indicated.

In the last few years, the transient interferometric mapping (TIM) characterization technique from TU Vienna has proven to be invaluable in characterizing internal device behavior such as hot spots during highcurrent pulses [9]. The quantity measured in a TIM measurement is the phase shift of the laser probe beam. Only a qualitative comparison of the measured phase shift to simulation results (temperature, current density) has been possible. To compare TIM measurements directly to simulation results, TCAD News June 2007

TCAD Newsthe tool Absorption and Phase shift Extraction (APEX) was developed by Synopsys. APEX is a postprocessor that extracts the phase shift from Sentaurus Device results so that it can be compared to the measured phase shift directly. An advanced example showing the use of APEX is available from SolvNet [10]. Compact Modeling for ESD There is a great need to include ESD compact models in circuit simulations to predict critical current paths and critical (I,V) node values, and to enhance input/output design quality [11]. The insight gained by TCAD permits developing physically based compact model add-ons for ESD. Internal device characteristics not accessible by measurements can be studied. Calibrated process and device simulation allows parameter extraction for ESD compact models. Expensive, noisy, and destructive measurements can be avoided. To keep the compact model development effort to a reasonable level, a modular modeling strategy is chosen. This strategy is often referred to as macro-modeling or subcircuit modeling in the literature [12]. The standard model of the corresponding device (for example, a GummelPoon or BSIM model) has been retained for normal operation conditions, and it has been extended by ESDspecific add-on modules to form a full ESD compact model. The operational regime of devices under ESD stress is beyond the range in which standard compact models have been tested and verified; whereas, the full ESD compact models allow for reproducing behavior under ESD stress in circuit simulation. Thermal effects are included by establishing a feedback loop between electric and thermal domains. The thermal domain is modeled using first-order or higher-order thermal RC networks, depending on the complexity of the temperature fields of the device (one or more highly localized hot spots or almost homogeneous distribution). Figure 10 shows how the ESD compact models are set up. Figure 11 shows an example of a protection NPN transistor ESD compact model. Current- and temperature-dependent series resistors account for conductivity modulation effects and self-heating, and are modeled externally. Thermal breakdown is modeled by R_Tc, which switches irreversibly from a very high to a very low Ohmic state at a critical temperature. The modeling of avalanche breakdown at the collector-base junction is the key element for simulating the snapback behavior. To eliminate the singularity at Vcb = BVcbo in the original Miller [13] formulation of the avalanche multiplication factor M, the method reported in [4] is followed, with an extension to account for weak avalanche current contribution. The resulting function is an approximation of the original M, but its value is limited at Vcb = BVcbo and it shows a significantly better convergence behavior. Apart from the core transistor itself, the parasitic PNP between the source, collector, and base is included.S Parasitic T Rs C PT Rc T Re EVCC C V_D2Avalanche Source

V_inputVCC C V_D2 A Input HBM 2.0 kV C Vinput A Internal Circuitry Protection Diode D1 B Rbext E C S Protection Diode D2 S ESD Compact Model: Protection Transistor Vce

V_input

Vce Voltage [V]

Vh

V_D2 10-10 10-9 Time [s] t_trigger 10-8 10-7

Solid: Rbext = 0 Dashed: Rbext = 2.5 k

Figure 12. Additional external base resistor Rbext increases the protection NPN triggering speed during an HBM stress simulation. Consequently, the effect of the D2 voltage overshoot peak on the voltage at the input node is reduced. Rbext also leads to a reduction of the holding voltage. Time axis is plotted in logarithmic scale to show the details of the protection NPN transistor triggering.Thermal Overload Tc Protection Transistor Temperature V_input Voltage [V]ESD Compact Model: Protection Transistor C B Rbext E S Vce

1000 Temperature [C]

Protection Diode D2 S

A Input HBM 4.5 kV C Vinput Internal Circuitry Protection Diode D1

Vce

500

Rb B

A

V_D2

R_Tc

Figure 11. Protection NPN transistor ESD compact model: (red) standard models, (black) ESD compact model add-ons, and (green) coupling to thermal network.

0

1e-07 Time [s]

2e-07

3e-07

Transition into permanent low Ohmic state (device damaged)

ESD Compact Model Subcircuit (T dependent) Including Parasitic Devices Electric Contacts Standard Models

Thermal RC Network PelRth1 Cth1 Rth2 Cth2 Rthn Cthn

Rthn+1

ESD Add-ons

Tamb

T1, T2, ..., Tn

Figure 10. Modular setup of ESD compact models including thermal network fed by dissipated power Pel. The resulting temperatures T1Tn complete the feedback loop.

A dedicated methodology for the extraction of ESD compact model parameters is developed, based on TCAD results and measurements. The calibrated ESD compact models can be used within circuit simulations to determine critical current paths, to identify endangered devices, and to optimize protection circuitry. Circuit simulations with up to ten ESD protection devices and 100 standard devices are feasible. The limitation arises from the well-known convergence problems caused by the strong nonlinear behavior of the protection devices under ESD stress conditions and from their interaction with the rest of the circuit. The nonlinearities cannot be eliminated, but they can be reduced to an acceptable level by giving particular attention to numeric issues. While nonlinear behavior (for example, snapback devices) is one key issue to account for in ESD simulations, it makes the numeric treatment extremely unstable and computing intensive. Nevertheless, the circuit complexity extends simple input/output pad protection configurations, including large parts of the internal circuit. For the implementation of the ESD add-on model equations, Verilog-A behavioral modeling language can be used. Verilog-A can be read by most common circuit simulators such as HSPICE and Spectre. TCAD News June 2007

The transient triggering behavior [14] is influenced mainly by the junction capacitances (displacement current triggering), which cause a decreasing trigger voltage peak for increasing stress current rise-times, as well as by the base forward transit time (finite amount of time required by the carriers to traverse the base region leading to base-emitter diffusion capacitance), which reduces the triggering speed. Capacitances and base transit time as well as the current gain of the bipolar transistors, which determines the holding voltage Vh, are parameters belonging to the standard compact model instances. Their extraction is usually performed by simulations or measurements under normal operation conditions. Their values in the very diverse ESD current regimes may differ considerably compared to normal operation conditions. Therefore, a readjustment of these parameters may be necessary to obtain the correct behavior under ESD stress conditions. ESD Circuit Simulation In Figure 12, the ESD compact models for a protection NPN transistor and for two protection diodes are used within an input pin protection HBM circuit simulation. For simplicity, the internal circuitry comprising the first stages of the circuit is sketched by a box only. The protection diode ESD compact models include effects such as voltage overshoot due to forward recovery [15], reverse breakdown, and conductivity modulation due to high injection. Applying a positive HBM stress between the input pin and ground leads to a main current flow through D2 and the protection NPN, which goes into snapback and, therefore, limits the voltage at the VCC line. The voltage at the input pin is given by the sum of the voltages at VCC and the voltage drop across D2. Due to voltage overshoot, the voltage drop across D2 can exceed the stationary DC voltage drop considerably. It is shown that the transient voltage peak at the input pin is

Figure 13. Increasing the HBM stress voltage to 4.5 kV leads to damage of the protection NPN transistor. This is modeled by an abrupt and irreversible voltage drop at a predefined critical temperature Tc. Time axis is plotted in linear scale.

reduced by increasing the triggering speed of the protection NPN using an external base resistance. The external base resistance decreases the amount of current needed to forward-bias the base-emitter junction and, therefore, the snapback occurs earlier. If the HBM precharge voltage increases from 2 kV to 4.5 kV, the protection NPN transistor is damaged by the second breakdown. In the circuit simulation shown in Figure 13, this happens as soon as the protection NPN temperature reaches a predefined critical temperature Tc. Summary ESD is a real threat to IC reliability; therefore, meeting ESD robustness specifications is mandatory. Treating ESD-related problems is a challenging task. The use of TCAD to simulate and investigate ESD-related problems enables robust and reliable design of ESD protection devices/circuits, thereby reducing IC development costs and cycle time. However, reliable modeling of devices and circuits under ESD stress conditions requires specialized knowledge and broad experience. The TCAD-driven ESD methodology, which has been developed by the Synopsys Consulting and Engineering group and has been outlined in this article, has a proven track record of success in helping customers meet their challenges of treating ESD-related problems. The two service offerings, TCAD ESD Workbench and ESD Compact Model Development, can be customized specifically to protect your IC products from ESD damage. Contact tcad_team@synopsys.com for more information on our ESD service offerings.

References[1] Fundamentals of ESD, Part OneAn Introduction to ESD, Electrostatic Discharge Association. Article available at , May 2007. [2] J. E. Barth et al., TLP Calibration, Correlation, Standards, and New Techniques, IEEE Transactions on Electronics Packaging Manufacturing, vol. 24, no. 2, pp. 99108, 2001. [3] G. Notermans, P. de Jong, and F. Kuper, Pitfalls when correlating TLP, HBM and MM testing, in Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), pp. 170176, 1998. [4] M. P. J. Mergens, On-Chip ESD Protection in Integrated Circuits: Device Physics, Modeling, Circuit Simulation, Ph.D. thesis, ETH Zurich, Switzerland, 2001. [5] K. Esmark, H. Gossner, and W. Stadler, Advanced Simulation Methods for ESD Protection Development, Amsterdam: Elsevier, 2003. [6] C. Russ et al., Non-Uniform Triggering of gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Pulsing, in Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), pp. 177186, 1998. [7] C. H. Daz, S.-M. Kang, and C. Duvvury, Simulation of Electrical Overstress Thermal Failures in Integrated Circuits, IEEE Transactions on Electron Devices, vol. 41, no. 3, pp. 359366, 1994. [8] C. Salamro et al., Accurate prediction of the ESD robustness of semiconductor devices through physical simulation, in 43rd Annual International Reliability Physics Symposium, San Jose, CA, USA, pp. 106111, 2005. [9] D. Pogany et al., Quantitative Internal Thermal Energy Mapping of Semiconductor Devices Under Short Current Stress Using Backside Laser Interferometry, IEEE Transactions on Electron Devices, vol. 49, no. 11, pp. 20702079, 2002. [10] Simulation of Current Filament During Electrostatic Discharge Pulse (Z-2007.03), available from SolvNet , May 2007. [11] V. Vassilev et al., A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits, in 15th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), Zurich, Switzerland, 2004. [12] J. Li, S. Joshi, and E. Rosenbaum, A Verilog-A Compact Model for ESD Protection NMOSTs, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, USA, pp. 253256, September 2003. [13] S. L. Miller, Ionization Rates for Holes and Electrons in Silicon, Physical Review, vol. 105, no. 4, pp. 12461249, 1957. [14] H. Wolf, H. Gieser, and W. Wilkening, Analyzing the Switching Behavior of ESD - Protection Transistors by Very Fast Transmission Line Pulsing, in Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Orlando, FL, USA, pp. 2837, September 1999. [15] K. J. Tseng, Modelling of diode forward recovery characteristics using a modified charge-control equation, International Journal of Electronics, vol. 84, no. 5, pp. 437444, 1998.

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TCAD NewsTCAD Distortion Analysis Based on the Harmonic Balance MethodIntroduction The dynamic range of linearity is a critical specification in most analog applications. Even if the output signal changes almost linearly with the input signal, intrinsic device distortion effects are present, and higher harmonics draw power from the fundamental signal. Besides small-signal and noise characteristics, these distortion effects are the most important properties in analog radio frequency (RF) circuits such as power amplifiers, mixers, and drivers. Although distortion is the fundamental mechanism of mixers to generate signals at various frequencies, it must be as low as possible for most other applications. Distortion characteristics are divided typically into two groups: Harmonic distortion: A sinusoidal input signal at frequency f (also called one-tone) results in an output signal with spectral components at f (first harmonic), 2f (second harmonic), and 3f (third harmonic) (see Figure 1 (left)). The extrapolated crossing point of the first and third harmonics is called the third-order interception point (IP3) and is a typical metric to characterize the linearity of a device or system (see Figure 2). Intermodulation distortion: The input signal comprises two sinusoidal signals with fundamental frequencies f1 and f2 (also called two-tone) with equal amplitudes. The resulting, more complex, spectrum of the output signal is shown in Figure 1 (right). The typical quantity to characterize this situation is the extrapolated crossing point of the fundamental signal at f1 with the amplitude at 2f1-f2, which is called the third-order intermodulation intercept point (IIP3). In most applications, the intercept points are not reached due to saturating signals at high input amplitudes. Nevertheless, the intercept points serve as main figures of merit for distortion. Although distortion characteristics are relatively easy to measure, little is known about the physical origin at the device level. In addition, most modeling activity has focused on compact models, which inherently miss the important physics behind distortion and are often not scalable. Harmonic Balance in Sentaurus Device Conventional TCAD time-domain analysis could, in principle, be used to analyze distortion in semiconductor devices, but this approach is often prohibitively expensive in terms of computing resources: The applied input signals in distortion experiments are sinusoids that may have very narrowly spaced frequencies. This requires a time integration over an enormous number of periods of the input frequencies. The steady-state behavior of the system is usually of primary interest. The presence of filtering and matching circuitry around the primary device can introduce extremely long time constants. This results, again, in a huge number of necessary time steps. The harmonic balance module (HBM), the latest analysis technique implemented in Sentaurus Device Version Z-2007.03, uses a mixed frequency-domain time-domain method [1], which addresses the above problems. The HBM captures directly the large-signal steady-state response of nonlinear systems without tedious time-stepping algorithms. In addition, the HBM exhibits an excellent dynamic range to resolve low-level distortion products. Input Output Input Output log(Output) First Harmonic (10 dB/decade)

IP3 (IIP3) Third Harmonic (30 dB/decade) f1 2f1 3f1 4f1 Frequency 2f1-f2 f1 f2 2f2-f1 Frequency log(Input)

Figure 1. (Left) Input signal with modulation frequency f1 (black) results in output signal with spectral components at f1 and integer multiples of f1 (harmonic distortion). (Right) Two-tone input signal at f1 and f2 also generates spectral components at 2f1-f2 and 2f2-f1 (intermodulation distortion).

Figure 2. Schematic of third-order intercept point, which is defined by the extrapolated crossing point of the fundamental first and third harmonics of the output signal.

The HBM can be used for 1D, 2D, or 3D simulation setups using drift-diffusion or hydrodynamic frameworks. Arbitrary devices and circuits can be simulated including various classes of FETs, (hetero) bipolar transistors, HEMTs, as well as optoelectronic devices such as semiconductor lasers [2]. As a major advantage of the HBM, arbitrary large-signal modulation conditions can be captured within one single simulation using a ramping strategy. This is more efficient compared to transient simulations, where a new simulation must be started for each modulation condition. As a consequence of the increased system size that must be solved during an HBM simulation, the memory requirements are typically 520 times higher than for a classical DC, AC, or transient simulation. However, on shared-memory architectures, the simulation speeds up linearly with the number of processors. SiGe Bipolar Transistor Distortion Analysis Silicon germanium (SiGe) is a key technology for RF integrated-circuit design. In the first example, the frequency-dependent harmonic distortion characteristics of a typical SiGe bipolar transistor (BJT) (see Figure 3) are analyzed using a 2D simulation setup. For the harmonic balance investigation, eight harmonics are taken into account. The device is biased (without matching circuit) to Vce = 1.5 V and Vbe = 0.9 V. The biasing is chosen such that the transit frequency ft reaches its maximum value of 77 GHz. In addition, the base voltage is modulated with 10 mV at varying frequencies. Figure 4 shows the frequency-dependent harmonic distortion characteristics for this device. BJTs feature very strong frequencydependent distortion effects. For both bipolar and MOS transistors, the two major nonlinear sources of distortion are the

transconductance and the input impedance. The input impedance diffusion capacitance Cbe in BJTs is more nonlinear compared to the gate capacitance Cgs in MOSFETs, causing the strong frequency-dependent distortion characteristics in BJTs; whereas, the MOS devices feature a very low frequency dependence of distortion. Figure 4 also shows that the third harmonic of the collector current features a second-order low-pass characteristic, causing a strong decrease of the third-order intercept voltage (V_IP3) in the GHz regime.

Figure 5 shows a generic NMOS with a nominal gate length of 65 nm, width of 1 m, oxide thickness of 2 nm, and substrate doping of 5 x 1017 cm3. The device is biased to Vds = 1.2 V and is modulated with a gate source voltage of 0.1 V at 1 MHz. Figure 6 shows the V_IP3 characteristics as a function of the DC gate voltage Vgs for different substrate dopings Ns and oxide thicknesses tox. With increasing Vgs, the linearity increases and features a sharp peak around the threshold voltage, which originates from cancellation effects of the higher order harmonics [3][4]. Figure 7 shows the first harmonic of the electron density in a cut through the channel as a function of the DC bias voltage Vgs. For low bias Vgs, the electron density towards the drain side is modulated remarkably stronger than for high Vgs. This is one cause of the higher distortion at low bias Vgs observed in Figure 6. The HBM can be used also to investigate high-amplitude modulation conditions such as the 1-dB compression point or the saturation behavior of first-order and third-order modulation products in two-tone experiments.Gate

102 101

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Figure 4. Frequency-dependent harmonic distortion characteristics of SiGe. Third-order voltage intercept point (V_IP3) strongly decreases in low GHz regime due to increasing third harmonic of collector current.

65 nm NMOS Distortion Analysis The scaling of CMOS technology offered a significant improvement in RF performance in MOS devices. In view of the fast growth of the wireless communication market, designers are exploring conventional CMOS instead of IIIV or SiGe in RF circuits. Since system requirements on linearity become more stringent for future wideband RF applications, the inherent superior linearity compared to the faster SiGe BJTs is a significant advantage for CMOS [3].

Source

DrainDopingConcentration [cm-3] 1.2e+20 1.2e+17 1.3e+14 -1.7e+12 -1.8e+15 -1.7e+18

Figure 5. Doping profile of 65 nm NMOS.

Emitter Base

Collector

Figure 8 shows the results of an intermodulation distortion simulation for the 65 nm NMOS with a DC bias Vgs of 0.7 V and f1 = 1 MHz, f2 = 1.001 MHz for increasing modulation amplitude Vg1. For gate voltage modulation amplitudes higher than 0.2 V, saturation of both the fundamental harmonic and the thirdorder modulation products of the drain current increases, limiting the maximum available modulation power. The examples without matching circuits investigated so far are used mainly for lowfrequency amplification applications with modulation frequencies below 10% of the transit frequency of the device. For high-frequency amplification, a suitable matching circuit (reactive or resistive) must be optimized for each specific application. This can be performed also using the HBM where the matching elements are added in a SPICE-like manner. TCAD News June 2007

DopingConcentration [cm-3] 1.5e+20 6.6e+16 2.9e+13 -1.9e+13 -4.4e+16 -9.9e+19

Figure 3. Doping profile of npn SiGe bipolar transistor.

TCAD NewsConclusion In summary, the harmonic balance module available in Sentaurus Device opens the possibility to analyze distortion effects at the device level in an efficient way. Applications include harmonic distortion, intermodulation distortion, and signal compression analysis for a wide range of devices using a onedimensional, two-dimensional, or threedimensional geometry, and a mixed-mode simulation setup. Sentaurus Device is the ideal simulation tool for optimization with respect to distortion effects already in the device design phase. References[1] B. Troyanovsky, Z. Yu, and R. W. Dutton, Physics-based simulation of nonlinear distortion in semiconductor devices using the harmonic balance method, Computer Methods in Applied Mechanics and Engineering, vol. 181, no. 4, pp. 467482, 2000. [2] S. Odermatt, B. Witzigmann, and B. Schmithsen, Harmonic balance analysis for semiconductor lasers under large-signal modulation, Optical and Quantum Electronics, vol. 38, no. 12-14, pp. 10391044, 2006. [3] B. Murmann et al., Impact of Scaling on Analog Performance and Associated Modeling Needs, IEEE Transactions on Electron Devices, vol. 53, no. 9, pp. 21602167, 2006. [4] R. van Langevelde et al., RF-Distortion in Deep-Submicron CMOS Technologies, in IEDM Technical Digest, San Francisco, CA, USA, pp. 807810, December 2000.101

Vgs Low2e+11

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n [cm3]

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5e+10Ns = 5e17 cm-3, tox = 2.0 nm Ns = 5e16 cm-3, tox = 2.0 nm Ns = 5e17 cm-3, tox = 1.5 nm Ns = 5e16 cm-3, tox = 1.5 nm0.2 0.4 0.6 0.8 1

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Figure 6. Bias dependence of third-order voltage intercept point (V_IP3) for varying substrate dopings and gate oxide thicknesses. Around the threshold voltage, V_IP3 features a peak due to cancellation effects of higher order harmonics.

Figure 7. First harmonic component of electron density in NMOS channel. At low DC bias voltage Vgs, the electron density is modulated more strongly at the drain side.

Figure 8. NMOS saturation behavior of fundamental and third-order drain current components for increasing modulation voltage. For modulation amplitudes above 0.2 V, saturation effects start limiting the available current and power gain.

An Efficient Simulation Environment for Modeling Single Event Effects with the Sentaurus Tool SuiteIntroduction Single event effects (SEEs) in microelectronics are caused when highly energetic particles present in packaging materials, or in natural space and terrestrial environments (for example, protons, neutrons, alpha particles, or heavy ions), strike sensitive regions of a microelectronic circuit [1]. Similar effects can occur also when an incident particle collides with an atom and produces a reaction product capable of depositing a significant amount of energy. Depending on a number of factors, the particle strike can cause no observable effect, or a transient disruption of circuit operation, or a change of logic state, or even permanent damage to the device or integrated circuit (IC) [1]. SEEs have long been a consideration for electronics applications in space environments (where ionizing radiation is abundant) and for some terrestrial electronic applications. Scaling of CMOS device sizes to nanometer dimensions and low operating voltages mean that the amount of charge associated with bits of information, and circuit noise margins, is becoming extremely small. In addition, the high transistor packing density means that a single ionizing particle potentially impacts multiple transistors. All of this increases the challenge of using advanced CMOS technologies in space and radiation environments and elevates SEEs as a major reliability consideration in commercial electronics. Analysis of SEEs in advanced circuitry involves the determination of the response of multiple interactive devices, coupled with the application-specific overall circuit response, to energy deposition by a particle using ionization or secondary reactions. TCAD and mixed-mode simulations can be used to determine the device and circuit responses to radiation events. The characteristics of the energy deposition produced by the events, as well as the event rates, can be simulated using Monte Carlo codes such as SEMM2 [2] and Geant4-based codes such as MRED [3][4]. The increase in obtainable computing power per cost over recent years enables problems of much larger computational complexity to be examined using such simulations. In this article, a single-event simulation methodology based on the use of the TCAD Sentaurus Version Z-2007.03 tool suite is presented. To fully characterize SEEs, a TCAD News June 2007 multiple devices using 3D TCAD. A sixtransistor 90-nm SRAM cell has been modeled with the Sentaurus tool suite, as shown in Figure 1. As device sizes shrink, memory cells are becoming much more compact in size, with entire cell areas now comparable to single-transistor drain-node areas of only a few generations ago. However, the size of the ion-induced charge filament does not scale. In the past, with larger size devices, the simulation of a cell using a single transistor in TCAD, while the others were represented using compact models (that is, mixed mode), provided a reasonably accurate representation of how the circuit would respond to a single event. However, as we move towards more compact circuitry, issues such as multi-node charge collection and parasitic transistor action are important in determining circuit responses [7]. The SRAM cell comprises two NMOS transistors and two PMOS transistors as the cross-coupled inverter pair, and an additional set of two NMOS transistors that are access transistors and are used to read or write the cell. The mesh consists of 85 000 vertices, or 5000 2D elements and 450 000 3D elements. Each NMOS and PMOS transistor is calibrated to SPICE and process data before building the SRAM cell. This ensures a high level of fidelity in the SRAM cell model. The simulations are all run in the mixed-mode environment, as represented in Figure 1. In this case, the mixed-mode connections are made to allow the cell to operate as it would in real conditions. All transistors are simulated in TCAD, but the mixed-mode connections allow the node voltages to change in response to the ion-induced perturbation and potentially for the cell to flip states, consistent with charge moving through the structure. If all nodes were hardwired to a source, the cell would never change states due to a perturbation. Figure 2 shows the response of the bit lines of the SRAM cell following a heavy ion strike to the drain of the off-state NMOS transistor. Although many of the simulations use the heavy ion statement inside the Sentaurus Device simulator, we have developed an alternative method of depositing charge using the physical model interface (PMI) to Sentaurus. Monte Carlobased codes (such as Geant4) can provide a realistic distribution1.5

1 Bit Line Bit Line Bar

Voltage [V]

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0

-0.5 10-12 10-11 10-10 Time [s] 10-9 10-8

Figure 1. Six-transistor SRAM cell built in a 90-nm process. Circuit schematic represents mixed-mode connections for SRAM cell. Although all six devices are modeled in a single TCAD structure, the nodes are wired up in mixed-mode to allow for voltage perturbations.

Figure 2. Node voltages versus time for bit lines of SRAM cell as a result of a single event strike. In this case, the cell switched states.

systematic and rigorous simulation matrix with more than 100 simulations is needed. The new capabilities in the Sentaurus tool suite allow us to take advantage of a parallel highperformance computing system at Vanderbilt University and to run the simulations efficiently. We use such simulation capabilities to examine various aspects of SEEs, including chargesharing, the impact of nuclear reactions in the overlayers, and single event transients and upsets [5]. The simulations presented in this article focus on the single event response of a baseline (unhardened) 90-nm SRAM cell designed from a commercial 90-nm process. Simulation Environment This work was conducted in part using the resources of the Advanced Computing Center for Research and Education (ACCRE) at Vanderbilt University, Nashville, Tennessee [6]. The ACCRE high-performance computing system consists of approximately 1500 processors and has a capacity of approximately 6 TFLOPS. Each node is built with dual processors, and each processor has at least 1-GB memory. The latest version of the Sentaurus tools allows users to run a TCAD simulation on a node, fully utilizing both processors and all available memory on that node for a single simulation. This provides a significant speedup in simulation time, compared to running the same simulation on a single processor. Device Simulation As noted, the small size and proximity of multiple devices requires the modeling of

of generated charge corresponding to a particular event, rather than an idealized description of an average event. Ions can interact with the Si substrate, dopant atoms, or materials above the active silicon and can cause nuclear reactions [5][8]. The charge distributions generated by these events do not necessarily look like single vector columns of charge. In many cases, the events actually have several fingers of charge, as seen in Figure 3. Having the capability to analyze these realistic events is vital to understanding how reaction products, including those originating in the overlayer materials, can alter the response of the device or circuit. Simulation Matrix and Parallel Simulations To characterize and understand the single event response of an SRAM cell, a large simulation matrix is designed. The matrix includes various ion-strike locations, linear energy transfer (LET) values, and incident ion angles, resulting in more than 100 simulations. Figure 4 shows an example of a matrix of hit locations, where X indicates the area on the surface of the structure where an ion will impact the silicon. The Sentaurus Workbench software package allows us to set up these complex matrices easily, to interface with the ACCRE computing cluster, and to utilize fully the available processing power. This permits many jobs to be run simultaneously, rather than one after another, greatly enhancing data collection and simulation performance.

5

TCAD NewsCurrently, all of the nodes on ACCRE consist of dual processors. Parallelization of the device solver allows the use of both processors and all the memory on a node, reducing the time for each simulation by up to 41%. Accounting for hit location, incident angle, ion species, and energy, characterization of the single event response of the SRAM cell may involve more than 100 simulations that take 45 days each to complete on a single processor; the time savings obtained by using the multiprocessor capability are significant. Conclusion The high level of integration associated with scaled devices requires multiple-device 3D simulations to characterize single event effects. Such simulation capabilities allow the prediction of the performance of design variants operating in different radiation environments. However, these simulations are very complicated and can demand significant amounts of computing power. TCAD Sentaurus Version Z-2007.03 gives users the ability to design and build these cells, and provides the flexibility needed to integrate into a high-performance computing cluster environment such as ACCRE, for a comprehensive characterization of complex physical phenomena such as single event effects. About ISDE ISDE is the applied research division of the Vanderbilt University School of Engineering Radiation Effects Group, which is the largest program of its kind in the United States. ISDE studies radiation effects in microelectronics equipment by leveraging a combination of experienced people, custom-developed software, commercially available software, and the Vanderbilt University ACCRE highperformance computing facility.Figure 3. Representation of charge generated by a Monte Carlo based code in which an ion interacted with materials above the active silicon and showered charge into the device. The output of the Monte Carlo code was used as input to the Sentaurus Device simulation.

References[1] P. E. Dodd and L. W. Massengill, Basic Mechanisms and Modeling of Single-Event Upset in Digital Microelectronics, IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 583602, 2003. [2] P. C. Murley and G. R. Srinivasan, Soft-error Monte Carlo modeling program, SEMM, IBM Journal of Research and Development, vol. 40, no. 1, pp. 109118, 1996. [3] S. Agostinelli et al., Geant4a simulation toolkit, Nuclear Instruments and Methods in Physics Research A, vol. 506, no. 3, pp. 250303, 2003. [4] C. L. Howe et al., Role of Heavy-Ion Nuclear Reactions in Determining On-Orbit Single Event Error Rates, IEEE Transactions on Nuclear Science, vol. 52, no. 6, pp. 21822188, 2005. [5] K. M. Warren et al., The Contribution of Nuclear Reactions to Heavy Ion Single Event Upset Cross-Section Measurements in a High-Density SEU Hardened SRAM, IEEE Transactions on Nuclear Science, vol. 52, no. 6, pp. 21252131, 2005. [6] For more information, go to , May 2007.

Figure 4. Top view of six-transistor SRAM cell; X indicates the locations where heavy ions with varying LETs will strike the device.

[7] O. A. Amusan et al., Charge Collection and Charge Sharing in a 130 nm CMOS Technology, IEEE Transactions on Nuclear Science, vol. 53, no. 6, pp. 32533258, 2006. [8] D. R. Ball et al., Simulating Nuclear Events in a TCAD Model of a High-Density SEU Hardened SRAM Technology, IEEE Transactions on Nuclear Science, vol. 53, no. 4, pp. 17941798, 2006.

Impact of Gettering Effects in Solar CellsIn 2005, the photovoltaic market exceeded US$10 billion, showing an exponential annual growth of 30%. Consequently, the shortage of silicon feedstock has forced cell manufacturers to look for new sources. To satisfy the market in the short-term to mid-term, extending feedstock to low-quality materials such as solar-graded silicon or thin film techniques is feasible and has been widely discussed. These approaches require a detailed understanding of not only the carrier transport mechanisms but also process physics, namely, diffusion and gettering processes. With its comprehensive capabilities in device and process simulation, TCAD can provide solar cell engineers with valuable insights to harness the last percentage of cell efficiency. Weber et al. [1] recently successfully reproduced Fe gettering experiments in boron-doped diffusion processes using Sentaurus Process and Sentaurus Device. In this article, we illustrate the implementation of an aluminum gettering process described by Plekhanov et al. [2]. A crucial material parameter for solar cells to achieve reasonable efficiency is the minority carrier lifetime or diffusion length. A high lifetime is achieved by reducing the number of recombination centers (traps) in the Si wafer. Therefore, for the successful use of solargraded materials, it is essential to consider defect engineering in the design of the fabrication process. In particular, an optimized design of gettering processes, which reduce the amount and impact of impurities present in the Si wafer, is vital to obtain high cell efficiencies. Aluminum gettering uses the fact that, above the eutectic temperature of 577C, the solubility of metals in Al is very high (1021 cm3) compared to their solubility in Si (1017 cm3). This provides a tremendous driving force for metal atoms to segregate into the Al or AlSi liquid layer. As the segregation process occurs simultaneously with the impurity diffusion, the gettering process can be described by: A segregation equation at the AlSi material boundary. A diffusion equation for the impurity diffusion in bulk silicon. Reaction terms for cluster dissolution and formation if impurity clusters such as metal precipitates are taken into account in the model. Basically, for impurity gettering, the same physics can be applied as for dopant diffusion. 6Traps [cm-3]

ShockleyReadHall Lifetime [s]

Plekhanov et al. developed a set of equations to describe the gettering of the impurities C, taking into account the decreasing size of metal precipitates C* in silicon:

10-2

10-3

C C + 4rD (C * C) = D x 2 twhere D is the diffusivity of the impurity, r is the radius of the metal precipitate, and is the precipitate density. Sentaurus Process allows users to define new species in silicon and to define new equations for the diffusion, segregation, and reactions of these new species as simple text strings. For example, the following line defines the partial differential diffusion-segregation equation for the impurity Fe in silicon:pdbSetStringSiliconFeEquation\ ddt(Fe)-$Dm*grad(Fe)-PrecDissol

2

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Figure 2. Spatially varying SRH lifetimes for the device simulation.

In the next step, the trap distribution passes to the device simulator Sentaurus Device. The trap density Ntrap together with a capture cross section n translates to a spatially varying ShockleyReadHall (SRH) lifetime (see Figure 2):

propagation method, and the finite-difference time-domain full-wave Maxwell solver. Finally, the influence of process variation on device characteristics is evaluated. Figure 3 shows the influence of gettering time on solar cell efficiency. In this setup, after 40 minutes, all Fe atoms are gettered by the Al rearside, resulting in a strong increase of the shortcircuit current efficiency. Figure 4 shows the dependency of the gettering time on external quantum efficiency (EQE). Due to a lower minority lifetime, the EQE is lowered in the red part of the spectrum as the carriers generated at the rear are unable to reach the p-n junction. References[1] T. Weber et al., Numerical Simulation of Gettering and Recombination in Iron-Contaminated Boron Emitters, in Proceedings of the 21st European Photovoltaic Solar Energy Conference (EUPVSEC), Dresden, Germany, September 2006. [2] P. S. Plekhanov et al., Modeling of gettering of precipitated impurities from Si for carrier lifetime improvement in solar cell applications, Journal of Applied Physics, vol. 86, no. 5, pp. 24532458, 1999.

SRH, n = 1/NtrapthnFor each time step, Sentaurus Process solves this differential equation and provides the spatial distribution of the species. After the reactions and diffusion equations are set up, the process flow with arbitrary temperature ramps can be defined. Here, a 1D simulation with a very simple ramp, namely, a constant temperature at 900C for four different gettering times (10, 20, 30, and 40 minutes) is investigated. The rear of the 100-m thick silicon wafer is covered by Al (at a depth of 100 m). The main result of the process simulation is the trap distribution shown in Figure 1. In addition to the trap distribution, the emitter doping profile can be modeled for use in subsequent device simulations, but this is not discussed further in this article. where th is the thermal carrier velocity. To calculate the white-light generation, the transfer matrix method is used. Sentaurus Device offers a variety of different optical solvers such as raytracing, the beam18 17

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Figure 3. Dependency of cell efficiency on gettering time.

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Figure 1. Depth-dependent trap distribution in die silicon wafer for different gettering times.

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Figure 4. Influence of gettering time on EQE.

TCAD News June 2007

TCAD NewsSimulation of H-SiC Vertical Junction FET in Sentaurus DeviceIntroduction Silicon carbide (SiC) has long been recognized as a superior semiconductor for high-power and high-temperature applications in view of its high breakdown electric field and excellent thermal conductivity. Since the pioneering work of Tairov and Tsvetkov [1] who developed the modified seed sublimation growth process that spearheaded todays SiC substrate technology, the industry has improved steadily the quality, size, and cost of SiC substrates, all of which are key manufacturability considerations in any semiconductor technology. A major quality concern has been the so-called micropipe defects that are considered to be associated with screw dislocations and to align themselves along the c-axis of the crystal. Since a single micropipe defect in the device active area is sufficient to degrade or destroy the device, these defects have hindered the realization of large-area power devices [2]. Over the last several years, significant progress has been made in reducing micropipe defects, and 100-mm diameter substrates are now commercially available. While the substrate cost is approximately an order of magnitude higher than silicon, SiC technology has already demonstrated commercial feasibility in high-voltage Schottky barrier diodes (SBDs), and new devices and applications are being considered [3]. Emerging Applications for SiC Electronic Devices The recent commercial interest in hybrid electric vehicles has extended the opportunities for electronic content in automobiles. The high temperature and harsh environmental conditions prevalent in automotive applications provide a natural medium for SiC relative to lower-temperature rating semiconductors such as silicon. One of the most intriguing possibilities is the simplification of cooling requirements for example, the elimination of secondary cooling loops necessary to maintain existing siliconbased devices at 85C base plate temperature thereby reducing costs [4]. In this scenario, the higher cost of SiC devices relative to Si devices is offset by the lower system costs. Another high-visibility, potential application is improving power grid efficiency. Wind and solar energy sources produce direct current and rely on inverter modules for conversion to alternating current used by the power grid. Current inverter module technology is based on silicon devices and operates at 9096% efficiency. Though this efficiency seems high, SiC devices offer the potential to increase the efficiencies of inverter modules to the 9598% range, which is significant. An example of the potential for SiC in this application is the recent demonstration of a SiC commutated gate turn-off thyristor (GTO) with a blocking voltage of 12.7 kV [5]. Motivation for Simulating SiC Devices As with other maturer semiconductor technologies, the early stages of process definition, device design, and optimization can greatly benefit from TCAD simulation. Arguably, the motivation for TCAD simulation of SiC devices is even higher than in other technologies since SiC substrate cost is still relatively high, making large-scale experimental wafer splits very costly. Moreover, the exceptional material attributes of SiC provide fertile ground for exploring truly novel device structures that transcend the operational principles and range of silicon-based devices. Since many of these device structures want to exploit the high breakdown field in SiC to realize high-blocking voltages, careful design and simulation of junction terminations are essential [6]. TCAD News June 2007 Another key aspect of exploring a new semiconductor technology is understanding discrepancies between theoretical projections and experimental results. The challenges faced by SiC MOSFETs provide an important illustration of this point. Despite ongoing improvements, the inversion layer mobility is still too low for commercial-grade devices. TCAD simulations suggest that a high number of interface traps can explain the experimentally extracted inversion layer mobility [7]. On the other hand, oxide reliability in SiC MOSFETs is a topic of concern when targeting highvoltage and high-temperature applications. SiC MOSFET design can lead to electric fields in the oxide substantially higher than in silicon devices, which combined with a lower injection barrier for carriers due to the higher band gap of SiC can lead to poor reliability. As a consequence of these remaining challenges, SiC oxide-free power-switching devices have been investigated recently. An example is the vertical junction field effect transistor (VJFET) discussed in the next section. Simulation of H-SiC VJFET TCAD simulations rely on physical models describing the operational phenomena and model parameters calibrated to the process and materials used to fabricate the devices. In a previous article, we compiled the key material and model parameters for the 4HSiC polytype [8]. In this article, we perform simulations of a 4H-SiC trenched-andimplanted VJFET, a type of device that holds commercial promise. The device structure and experimental data are from Zhao et al. [9].0 2 4 6 8 10 12Doping Concentration [cm-3] 6.0e+18 5.8e+15 5.5e+12 -4.7e+13 -5.0e+16 -5.2e+19 4H-SiC Gate SourceSource0.3 0.25Measured Simulated Vg = 2.936 V (4.5 V) Vg = 2.914 V (4.0 V) Vg = 2.877 V (3.5 V) Vg = 2.781 V (3.0 V) Vg = Simulations (Measurements) Vg = 2.954 V (5.0 V)

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Figure 3. Measured (points) and simulated (lines) IdsVds characteristics of VJFET. Gate voltages in parentheses are the actual gate voltages. The discrepancy is due to gate contact resistance, which is not explicitly considered in the simulation [9].4H-SiC100Impact Ionization

Measurement Simulation

Figure 2. Simulation mesh of VJFET. Inset shows mesh refinement surrounding the critical regions at the bottom of the vertical channel.

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Figure 2 shows the meshed VJFET structure. The inset shows a finely meshed p-n junction region and parts of the vertical channel. Such a refinement is needed to resolve properly the space-charge regions and to capture accurately the impact ionization effects for breakdown simulation. These meshing constraints can be easily implemented in Sentaurus Structure Editor using either its graphical user interface or its powerful scripting capabilities. Electrical simulations are performed with Sentaurus Device using physical models incorporating: Doping-dependent and temperaturedependent ShockleyReadHall (SRH) recombination and Auger processes. Doping-dependent mobility models with high-field velocity saturation effects. Impact ionization (OkutoCrowell model). Sentaurus Device accounts for the anisotropic properties of 4H-SiC resulting from the hexagonal crystal structure. Table 1 lists some important model parameters used in the simulations for mobility and impact ionization. Simulation results for a single-cell VJFET with an active area of 320 m x 293 m, showing Idrain versus Vdrain characteristics for various gate biases, are presented in Figure 3. Figure 4 shows the breakdown characteristics for the same device, as well as the region of the device undergoing acute avalanche generation. The simulated results show good agreement with experimental data.

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Figure 4. Measured and simulated breakdown voltage.

References[1] Y. M. Tairov and V. F. Tsvetkov, Investigation of Growth Processes of Ingots of Silicon Carbide Single Crystals, Journal of Crystal Growth, vol. 43, no. 2, pp. 209212, 1978. [2] P. G. Neudeck and J. A. Powell, Performance Limiting Micropipe Defects in Silicon Carbide Wafers, IEEE Electron Device Letters, vol. 15, no. 2, pp. 6365, 1994. [3] P. Friedrichs and R. Rupp, Silicon Carbide Power Devices - Current Developments and Potential Applications, in 11th European Conference on Power Electronics and Applications (EPE), Dresden, Germany, September 2005. [4] R. Kelley, M. S. Mazzola, and V. Bondarenko, A Scalable SiC Device for DC/DC Converters in Future Hybrid Electric Vehicles, in Twenty-First Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 460463, March 2006. [5] Y. Sugawara et al., 12.7kV Ultra High Voltage SiC Commutated Gate Turn-off Thyristor: SICGT, in 16th International Symposium on Power Semiconductor Devices & ICs (ISPSD), Kitakyushu, Japan, pp. 365368, May 2004. [6] X. Li et al., Multistep junction termination extension for SiC power devices, Electronics Letters, vol. 37, no. 6, pp. 392393, 2001. [7] H. Linewih and S. Dimitrijev, Channel-Carrier Mobility Parameters for 4H SiC MOSFETs, in Proceedings of the 23rd International Conference on Microelectronics (MIEL), Ni, Yugoslavia, pp. 425430, May 2002. [8] TCAD Simulation of Silicon Carbide Devices: Part I. Models and Parameters, TCAD News, pp. 35, September 2006. [9] J. H. Zhao et al., 3.6 mcm2, 1726 V 4H-SiC normally-off trenched-and-implanted vertical JFETs and circuit applications, IEE Proceedings Circuits, Devices and Systems, vol. 151, no. 3, pp. 231237, 2004. [10] W. J. Schaffer et al., Conductivity Anisotropy in Epitaxial 6H and 4H SiC, in Materials Research Society Symposia Proceedings, vol. 339, pp. 595600, April 1994. [11] T. T. Mnatsakanov et al., Universal Analytical Approximation of the Carrier Mobility in Semiconductors for a Wide Range of Temperatures and Doping Densities, Semiconductors, vol. 38, no. 1, pp. 5660, 2004. [12] T. Hatakeyama et al., Physical Modeling and Scaling Properties of 4H-SiC Power Devices, in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Tokyo, Japan, pp. 171174, September 2005.

Gate

Y [m]

Drain

0

2

X [m]

4

6

Figure 1. Device structure and doping profile of VJFET.

The VJFET structure allows the realization of normally off devices, which are desirable for fail-safe protection. The device structure is defined in Sentaurus Structure Editor and is shown in Figure 1. The device is created on the Si face of the 4H-SiC material and has an n- vertical channel and drift region with a doping concentration of 6.5 x 1015 cm3. The p+ gate regions, with a doping concentration of 1.0 x 1018 cm3, are created on the sidewalls of the trenches. The p++ contact regions have a doping concentration of 5.0 x 1019 cm3. The n+ substrate, above the drain contact, is doped with a concentration of 6.0 x 1018 cm3, and the n+ source region has a concentration of 1.0 x 1018 cm3. The trench region comprises a 50-nm thick thermal oxide, followed by a 200-nm thick silicon nitride layer, and the remaining portion is filled with oxide. The vertical channel is designed to have an opening of 0.63 m, and the blocking layer or the n- drift region is designed to have a thickness of approximately 9.4 m.

Table 1. Important model parameters used in the simulations for mobility and impact ionization.Model Parameter Coefficients Mobility For Electrons MuMax Anisotropic Mobility MuMax Impact Ionization alpha beta Anisotropic Impact Ionization alpha beta 1.76e+07 3.30e+07 3.41e+08 2.50e+07 1/cm V/cm [12] 700 G = alpha * exp( -beta / E) 2.10e+07 1.70e+07 2.96e+07 1.60e+07 1/cm V/cm [12] 114 cm2/(Vs) [7][11] 947 For Holes 124 Unit cm2/(Vs) Reference [10]

7

TCAD News

TCAD Events 2007 Conferences and Trade ShowsUSA July 1620 SEMICON West San Francisco, California, USA July 2327 Nuclear and Space Radiation Effects Conference (NSREC) Honolulu, Hawaii, USA September 1721 BACUS Photomask Technology Monterey, California, USA September 2427 7th International Conference on Numerical Simulation of Optoelectronic Devices (NUSOD) University of Delaware, Newark, Delaware, USA September 30 October 3 Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) Boston, Massachusetts, USA December 1012 International Electron Device Meeting (IEDM) Washington, DC, USA Asia-Pacific September 714 TCAD Asia-Pacific Seminar Series September 7 Hsinchu September 10 Singapore September 12 Seoul September 14 Shanghai Europe September 1113 37th European Solid-State Device Research Conference (ESSDERC) / 33rd European Solid-State Circuits Conference (ESSCIRC) Munich, Germany September 2527 12th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) TU Wien, Vienna, Austria

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