New Microprocessor 1-Rec

7/28/2019 New Microprocessor 1-Rec

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EX.NO:

DATE:

IMPLEMENTATION OF MICROPROCESSOR

AIM:

To implement Microprocessor using SPARTAN 3E kit.

TOOLS REQUIRED:

(i) SOFTWARE REQUIRED: XILINX 13.1 version

(ii) HARDWARE REQUIRED: SPARTAN 3500 kit

THEORY:

A microprocessor incorporates the functions of a computers central processing

unit (CPU) on a single integrated circuit, (IC) or at most a few integrated circuits. It is a

multipurpose, programmable device that accepts digital data as input, processes it according to

instructions stored in its memory, and provides results as output. it consist of

ALU,registers,decoders,control unit.This logic can be designed in verilog/VHDL using

XILINX.After simulation it is implemented in SPARTAN 3E kit.


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BLOCK DIAGRAM:

MICROPROCESSOR MAIN MODULE

MEMORY


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ADDER SUBTRACTER

ADDER SUBTRACTER:


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ALGORITHM:

STEP 1: Write a Verilog/VHDL code for a simple microprocessor. Each module is defined

separately and their codes are written separately.

STEP 2:Write a verilog coding for read and memory options ,addition,

subtraction,multiplication,shift operations and memory operations.

STEP 3:Then coding for adder subtracter is written.

STEP 4:Similarly in Microprocessor VHDL code is written.

STEP 5:These operations can be simulated and implemented in SPARTAN 3E kit.

CODE FOR SIMPLE MICROPROCESSOR:

modulesimpleprocess(cntrl,clk,en,m,w_nr,rst,data_in1,data_in2,addr_out1,addr_out2,q1,q2,out,co,out2,

n_out);input [ 3:0] cntrl;input clk;

input [7:0] data_in1,data_in2,addr_out1, addr_out2;

output reg en,w_nr,m,rst;

output [7:0] q1,q2;

output [7:0] out;

output reg [7:0] out2,n_out;output co;

reg[7:0] ram_mem [15:0];

reg[7:0]data_reg;reg [3:0] a,b,m1,m2,m3,m4;

reg [7:0] w,x,y,z;

ram_mem mm(data_in1,data_in2,rst, clk,w_nr,addr_out1, addr_out2,q1,q2);

adder_sub as(q1,q2,m,out,co);

always @ (posedge clk)begin

case (cntrl)

4'b0000:rst=1'b0;

4'b0001:w_nr = 1'b1;// memory write4'b0010: w_nr = 1'b0; //memory read

4'b0011: m =1'b0; // addition

4'b0100: m = 1'b1; // subtraction


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4'b0101: begin

en=1'b1; // multiplacation

if(en==1'b1)

begina= q1[3:0];

b=q2[3:0];endm1 = {a[3]&b[0],a[2]&b[0],a[1]&b[0],a[0]&b[0]};

m2 = {a[3]&b[1],a[2]&b[1],a[1]&b[1],a[0]&b[1]};

m3 = {a[3]&b[2],a[2]&b[2],a[1]&b[2],a[0]&b[2]};m4 = {a[3]&b[3],a[2]&b[3],a[1]&b[3],a[0]&b[3]};

w = m1;x = m2


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ram_mem[addr_out1]=n_out;

end

endcaseif ( cntrl==000)

rst =1'b0;else rst=1'b1;

end

endmodule

module adder_sub(a,b,m,out,co);input [7:0] a,b;

input m;output [7:0] out;

output co;

wire [7:0] cout;wire [7:0] d,s;

assign d [0]= b[0]^ m;

assign d [1]= b[1]^ m;assign d [2]= b[2]^ m;

assign d [3]= b[3]^ m;assign d [4]=b[4]^ m;assign d [5]= b[5]^ m;



fa fa1 (s[0],cout[0],a[0],d[0],m);fa fa2 (s[1],cout[1],a[1],d[1] ,cout[0]);

fa fa3 (s[2],cout[2],a[2],d[2],cout[1]);

fa fa4 (s[3],cout[3],a[3], d[3],cout[2]);

fa fa5 (s[4],cout[4],a[4], d[4],cout[3]);fa fa6 (s[5],cout[5],a[5], d[5],cout[4]);



assign out = m?((b>a)? ((~s)+1'b1):s) :(s);

assign co= cout[7];


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endmodule

module ram_mem(data_in1,data_in2,rst, clk,w_nr,addr_out1, addr_out2,q1,q2);

input [7:0] data_in1,data_in2;input clk, w_nr,rst;

input [7:0] addr_out1,addr_out2;

reg [7:0] ram_mem [15:0];output reg[7:0] q1,q2;

always @( posedge clk )

begin

if(rst==1'b0)begin

q1=8'b0;

q2=8'b0;

end

elsebeginif( w_nr ==1'b0)

begin

q1= ram_mem[addr_out1];

q2= ram_mem[addr_out2];end

else

beginram_mem[addr_out1]=data_in1;

ram_mem[addr_out2]=data_in2;

end

endend

endmodule

module fa(sout,cout,a,b,cin);

output sout,cout;

input a,b,cin;assign sout=(a^b^cin);

assign cout=((a&b)|(a&cin)|(b&cin));

endmodule

CODE FOR MICROPROCESSOR VHDL:


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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

use IEEE.NUMERIC_STD.ALL;use IEEE.STD_LOGIC_SIGNED.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;--use UNISIM.VComponents.all;

entity simpl is

port ( cntrl : in std_logic_vector(3 downto 0);

clk: in std_logic;data_in1,data_in2,addr1, addr2:in std_logic_vector(7 downto 0);

en,w_nr,m,rst: buffer std_logic ;

data_reg: buffer std_logic_vector(7 downto 0);co:out std_logic;q1,q2, out1,out2,n_out:inout std_logic_vector(7 downto 0) );

end simpl;

architecture Behavioral of simpl is

type ram_type is array (0 to (addr1'length)-1) of std_logic_vector(data_in1'range);signal ram : ram_type;

signal w,x,y,z: std_logic_vector(7 downto 0);

signal m1,m2,m3,m4:std_logic_vector(3 downto 0);signal a,b : std_logic_vector(3 downto 0);

component sync_ram

port (

clock : in std_logic;

w_nr ,rst : in std_logic;addr1,addr2 : in std_logic_vector (7 downto 0);

data_in1,data_in2 : in std_logic_vector (7 downto 0);

q1,q2 : out std_logic_vector (7 downto 0)

);end component sync_ram;

component add_subb

port ( a,b: in std_logic_vector (7 downto 0);

out1: out std_logic_vector (7 downto 0);


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m: in std_logic;

co:out std_logic);

end component add_subb;

begin

mm : sync_ram port map( clk, w_nr,rst,addr1,addr2,data_in1,data_in2,q1,q2);a1 : add_subb port map(q1,q2,out1,m,co);

p2:process(clk,cntrl) isbegin

case (cntrl) is

when "0000"=> rst w_nr w_nr m m

en


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data_reg


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port (

clock : in std_logic;

w_nr ,rst : in std_logic;

addr1,addr2 : in std_logic_vector (7 downto 0);data_in1,data_in2 : in std_logic_vector (7 downto 0);

q1,q2 : out std_logic_vector (7 downto 0));end entity sync_ram;

architecture RTL of sync_ram is

type ram_type is array (0 to (addr1'length)-1) of std_logic_vector(data_in1'range);

signal ram : ram_type;

begin

RamProc: process(clock) is

begin

if (rst= '0') then

q1


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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_BIT.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;entity add_subb is

port ( a,b: in std_logic_vector (7 downto 0);

out1: out std_logic_vector (7 downto 0);

m: in std_logic;co:out std_logic);

end add_subb;

architecture Behavioral of add_subb issignal cout, d,s,g:std_logic_vector (7 downto 0);

component fa

port ( sum : out STD_LOGIC;

co : out STD_LOGIC;a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC);end component;

begin

d (0)


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s when m='0';

co


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SIMULATION OUTPUT (verilog):

SIMULATION OUTPUT(VHDL):

RESULT:Thus the microprocessor was simulated in VHDL using Xilinx and implemented using FPGA trainer

kit.

Documents

New Microprocessor 1-Rec