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Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

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Page 1: Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

Network-on-Chip

Energy-Efficient Design Techniques for Interconnects

Suhail Basit

Page 2: Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

23/5/2003 Suhail Basit 2

NoC

Micro-network Components

(Resources) Interconnects

(Switches)

Differences from WAN Local proximity of

components Less non-determinism

Mesh Topology

Page 3: Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

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NoC Design Power consumption

Voltage scaling helps Computation and storage energy

Device scaling helps Communication energy

Needs extra effort Netwrok traffic monitoring and control

Clock speed of components according to available bandwidth Design-time specialization

Designing of communication network fabric on silicon from scratch

Standardization of end nodes only Tailored netwrok architecture according to the application

Page 4: Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

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Interconnect Design Implementation of micro-network

stack Physical layer

Data transfer Synchronization

Data-link layer Error handling

Network layer Network architecture Network control

Transport layer Network resources QoS

System layer Power management

Application Layer Distributivity Portability

Page 5: Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

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Physical Layer Design Low swing signaling at transmitter

Reduction in Vdd Less reliable data reception Differential receivers

Pseudo-differential signaling at receiver Reference signal sharing Less signal transitions Reduced noise margin

Synchronization Clocks are extremely energy-inefficient Global synchronization is not optimal GALS units are a possible solution

Page 6: Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

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Data-link Layer Design

Error detection Retransmission of data in case of error Can be costly in energy and performance

Error correction More redundant and complex in decoding More power-hungry in error-free case

Optimal choice System constraints Physical channel characteristics

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Network Layer Design Hierarchical and heterogeneous architecture

Nodes with high bandwidth requirement are clustered and connected together through short channels

Clusters are connected through global channels Small energy cost of intera-cluster communication than

inter-cluster communication Circuit switching

Network control overhead incurrs only once Best in case of persistent communication

Packet switching Distributed network control overhead More energy-efficient for irregular communication

Page 8: Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

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Transport Layer Design

Connection-oriented protocol Energy inefficient under heavy traffic due to

retransmissions

Connection-less protocol Additional work at receiver due to out-of-order delivery of

data

Flow control Network congestion increases cost per transmitted bit due

to contention resolution overhead The amount of data that enters the network, can be

regulated, at the price of throughput

Page 9: Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

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System Layer Design

Node-centric power management System software of each component has its own

dynamic power management (DPM) policy Component changes state based on system state

and workload (obtained by system calls) Network-centric power management

Components request neighbors for a state change

Requests originate and are serviced at system software level

Page 10: Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

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Application Layer Design

Distributivity and Portability Power-aware application programming interfaces

(APIs) for communication between application and system software Information about platform Setting the component in specific power state

Page 11: Network-on-Chip Energy-Efficient Design Techniques for Interconnects Suhail Basit

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Conclusion

Challenges of upcoming technologies Design complexity Reliable and high performance operation Energy consumption

Interconnects are the limiting factor Energy-efficient and communication-centric designs

Some problems were presented Basic strategies have been outlined Need to be explored further