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LETTERdoi:10.1038/nature09979

High-frequency, scaled graphene transistors ondiamond-like carbonYanqing Wu1, Yu-ming Lin1, Ageeth A. Bol1, Keith A. Jenkins1, Fengnian Xia1, Damon B. Farmer1, Yu Zhu1 & Phaedon Avouris1

Owing to its highcarrier mobility and saturation velocity, graphenehas attracted enormous attention in recent years15. In particular,high-performance graphene transistors for radio-frequency (r.f.)applications are of great interest613. Synthesis of large-scale gra-phene sheets of high quality and at low cost has been demonstratedusing chemical vapour deposition (CVD) methods14. However, veryfew studies have been performed on the scaling behaviour of tran-sistors made from CVD graphene for r.f. applications, which holdgreat potential for commercialization. Here we report the system-atic study of top-gated CVD-graphene r.f. transistors with gate

lengthsscaled downto 40 nm, the shortestgate length demonstratedon graphene r.f. devices. The CVD graphene was grown on copperfilm and transferred to a wafer of diamond-like carbon. Cut-offfrequencies as high as 155 GHz have been obtained for the 40-nmtransistors, and the cut-off frequency was found to scale as 1/(gatelength). Furthermore, we studied graphene r.f. transistors at cryo-genic temperatures. Unlike conventional semiconductor deviceswhere low-temperature performance is hampered by carrier freeze-outeffects, the r.f. performance of our graphene devicesexhibitslittletemperature dependence down to 4.3 K, providing a much largeroperation window than is available for conventional devices.

Graphene has zero bandgap, and therefore devices fabricated from ithave a small on-off ratio. Although bandgap engineering techniquessuch as nano-ribbon fabrication or the application of a strong displace-

ment field to bilayer graphenehave been developed to open a smallbandgapingraphene1519,thedevelopmentofareliabletechniquetocreatea sizable gap without degrading the electronic properties of the materialremains challenging. On the other hand, a large on-off ratio is not neces-saryformanyr.f.applications,suchasamplifiersormixers,andsignificantprogress has been made in the development of high-performance r.f.transistors based on graphene materials produced by different synthesistechniques. For example, a maximum cut-off frequency of 300 GHz hasbeen obtained for devices based on exfoliated graphene (ref. 11), and amaximum cut-off frequency of 100 GHz for devices based on epitaxialgraphene grown on silicon carbide (ref. 9). In modern electronics, large

volume production and low cost are crucial properties for any new tech-nology. It has been shown that growing graphene on a Cu substrate byCVD can produce large-size, high-quality sheets at low cost14. Previous

studies on r.f. transistors made from transferred graphene typically usedsilicon dioxide (SiO2) as the substrate. However, graphene devices fabri-cated on SiO2 have been found to suffer from additional scattering asso-ciatedwiththelowsurfacephononenergy(59 meV)andlargetrapdensityinSiO2,resultingindeteriorationofbothdevicepropertiesanduniformityacross the wafer. To mitigate these problems, here we introduce a newsubstrate for graphene r.f. transistors, namely, a diamond-like carbon(DLC) film grownon SiO2. Comparedto SiO2 and mostother substrates,the DLC film has a higher phonon energy (owing to the high phononenergy in diamond (165 meV)) and a lower surface trap density (DLC isnon-polar and chemically inert)20. These desirable properties help thehigh performance of graphene r.f. transistors to be achieved.

Single-layer graphene was grown on copper foil at high tempera-tures close to 1,000uC. Using a polymethylmethacrylate (PMMA) film

as a protecting layer, the graphene sheet formed on Cu was then freedby dissolving theCu using a solution of FeCl3. The transfer process wascompleted by transferring the PMMA-graphene to the DLC substrateand subsequently removing the PMMA. Raman spectroscopy wasused to verify the single-layer nature of the graphene after the transfer(see Supplementary Fig. 1). Arrays of graphene r.f. transistors on aDLC substrate were fabricated using a conventional top-downapproach. The schematic view of the graphene r.f. transistor is shownin Fig. 1a. Electron-beam lithography was used to define the channel,source and drain contacts, and the gate electrodes. Oxygen plasma

etching was used to remove graphene outside the channel. The sourceand drain contacts consist of a thin Pd film covered by a thicker Aufilm. The top-gate dielectric film includes an electron-beam-evapo-rated Al layer, which is then oxidized and an additional layer ofAl2O3 grown by atomic layer deposition (ALD)

21. We note that allfabrication process steps involve standard top-down approaches thatcan be readily implemented in high-throughput production. Figure 1bshows a scanning electron microscope (SEM) image of a dual-channelgraphene r.f. transistor with a ground-signal-ground coplanar paddesign suitable for r.f. measurements. Figure 1d shows an SEM imageof thewell-alignedfinestructure of a devicewith a gate lengthof 40 nm.The transmission electron microscopy (TEM) image in Fig. 1c furtherconfirms the excellent alignment between the gate and the source/drain electrodes and the gate length of 40 nm, the shortest demon-

strated so far. This nearly perfect alignment with a small un-gatedregion of less than 20 nm in our transistors is critical for achievinggood device performance. The access region between gate andsource/drain is nearly constant for all the devices, regardless of theirgate length.

Figure 1e shows the output characteristics of two graphene devices,one with a gate length of 550 nm (left) and one with a gate length of40 nm (right). The drain voltage sweeps from 0V to 1.6 V for the 550-nm device and from 0 to 1 V for the 40-nm device. The gate voltagechanges from28Vto0V,frombottomtracetotoptrace.Asshowninthe insets, the Dirac point voltage obtained from the long-channel(that is, long-gate) device is around27 V asa resultof impurity chargedoping, possibly induced during the transfer process. We attribute thiseffect to fixed impurity doping rather than trap charges because of the

very weak hysteresis and the temperature-independent position of theDirac point observed in these devices. The gate modulation of theshort-channel (that is, short-gate) device is much weaker than thatof the long channel one. This is mainly due to the more dominant roleof the contact resistance in short channel devices. Unlike the case of Simetal-oxide-semiconductor field-effect transistors (MOSFETs), thereis currentlyno provenway to reduce thecontact resistance of graphenetransistors. Another cause of theweak modulation of the40-nmdeviceis the short-channel effect, in which the electrostatic control efficiencyof the top gate is adversely affected by the drain voltage. Although thiseffect is well-studied for conventional Si MOSFETs, it is not wellunderstood in graphene transistors, and may be even more severe inthese devices owing to the conical graphene band structure and theoccurrence of Klein tunnelling.

1IBM Thomas J. Watson Research Center, Yorktown Heights, New York 10598, USA.

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High-frequency scattering parameters (S) of the graphene r.f. tran-sistors were measured up to 30 GHz by an Agilent E8364C networkanalyser using standard ground-signal-ground probes (details of themeasurement set-up and procedures are given in the MethodsSummary). We used a de-embedding procedure that took account ofparasitic effects (such as pad capacitance and wire resistance). This isachieved by measuring on-chip, inactive, open and short testdevices;in theformer,therewas no graphene, and in thelatter, gate, source anddrain electrodes were all connected by metals. High fidelity in the de-embedding process was achieved by ensuring that the layouts of theseopen and short structures were strictly identical to that of the active

device. The cut-off frequency (fT), defined as the frequency at whichthe current gain becomes unity, is one of the most important figures-of-merit for evaluating the performance of r.f. devices. In Fig. 2a, thecurrent gain,calculated fromSparameters, is plotted against frequencyf; a peak cut-off frequencyfTof 26 GHzis obtainedfor the550-nm-longdevice at room temperature. To verify the value of fT independently,Gummels method22,23 was adopted, and the same value of fT wasobtained, as shown in the inset of Fig. 2a. The current gain of deviceswith shorter gate lengths (Lg5 140nm and 40nm) is plotted in a

similar fashion in Fig. 2b and c, respectively. A cut-off frequency of70 GHzwas obtained for the140-nmtransistor from both the interceptofthe1/fdependenceand Gummels method.AnfT ashighas155GHzwas obtained from the 40-nm-long device; this is the highest cut-offfrequency yet achieved on CVD graphene, and 40 nm is also thesmallest gate length reported so far. Although the direct current trans-conductance (gm) suffers from the short-channel effect at this gatedimension, as discussed above, the overall r.f. performance benefitsfrom the reduction of gate length.

In a well-behaved field-effect transistor (FET), the cut-off frequencycan be related to gm by the following equation

9: fT5gm/2pCg, where

Cg5 e0erWgLg/tox. Here Cg is the gate capacitance, e0 is the dielectricconstant of vacuum, er is the relative dielectric constant of the gatedielectric, Wg is the channel width, Lg is the gate length and tox is thegate dielectric thickness. Therefore, the product fTLg is expected to belinearlyproportional togm fordevices with thesamegate dielectric andwidth, and the slope of a plot offT Lgversus gm is determined only bythe physical thickness of the gate oxide. Such a plot of fTLgagainst gmfor three different gate lengths is shown in Fig. 3a; it exhibits theexpected linear dependence, with a slope independent of the gate

Gate

Source

Source

Source

DrainGate

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Gate

Drain

Drain

40 nm

Oxide

Oxide

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Drain

Sourc

e

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c d

0.0 0.5 1.0 1.5 0.0 0.5 1.00

200

400

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800

1,000

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Vg = 8 V to 0 V

Vg

= 8 V to 0 V

Lg = 550 nm

Drain voltage (V)

8 6 4 2 060

120

180

240

Vd = 0.4 V

Vd = 0.4 V

Id(Am1)

Id(Am1)

Vg (V)

8 6 4 2 0

Vg

(V)

20

0

20

40

gm(

Sm1)

gm(

Sm1)

Lg = 40 nm

240

260

280

300

0

10

20

30

e

Figure 1 | Fabrication and output characteristics for graphene r.f.transistors. a, Schematic view of a top-gated graphene r.f. transistor on DLC

substrate. b, SEM image of a typical top-gated dual-channel r.f. device. Scalebar, 3mm. c, Cross-section TEM image of a graphene transistor with a gate

lengthof 40nm.Scale bar, 40nm. d, SEMimageof the 40-nm device. Scale bar,400nm. e, d.c. output characteristics of a 550-nm device (left) and a 40-nm

device (right). Insets, transfer characteristics at drainsource voltageVds5 0.4V.

1 10 100 1 10 100 1 10 1001

10

100

|h21

|

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T= 300 KLg = 550 nm

26 GHz

a b

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70 GHz

T= 300 KL

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0 10 20 300.0

0.2

0.4

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Im(1/h21) = f/fT

Im

(1/h21

)

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0.0

0.4

0.8Im(1/h21) = f/fT

fT = 26 GHzIm

(1/h21

)

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10

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155 GHz

Frequency (GHz)

T= 300 KLg = 40 nm

0 10 20 300.0

0.1

0.2

I

m(1/h21

)

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Im(1/h21) = f/fT

fT = 155 GHz

Figure 2 | Cut-off frequencies for three different devices at roomtemperature. Small-signal current gain |h21 | versus frequency for devices witha gate length of 550 nm (a), 140nm (b) and 40nm (c) at room temperature.

Intercepts give the cut-off frequency as 26 GHz, 70 GHz and 155 GHz,

respectively. Insets, linear fitting using Gummels method, showingextrapolated cut-off frequencies identical to the value obtained in the mainpanel for each device.

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lengths. This shows the uniformity of our devices across the whole

wafer, and also demonstrates the measurement reliability. A highvalueoffTLg5 13 GHzmm is obtained for the 550-nm device; this is signifi-cantly higher than the value of 9 GHzmm for Si MOSFETs obtainedfrom the International Technology Roadmap for Semiconductors(ITRS)24, and is getting close to the best experimental results for SiMOSFETs.

To further test device uniformity and to examine device variationacross the wafer, a systematic study of graphene transistors with fivedifferent gate lengths was performed; the results are shown in Fig. 3b.Foreachgate length, sixdevices from differentdies (each diecontainsacomplete set of devices) on the same wafer are measured and the peakcut-off frequencies are plotted.Theperformance variationis verysmallfor all devices withthesame gatelength, ascanbe seenfromFig. 3aandb. Also, a 1/Lg dependence ( the scaling trend) of the peak cut-off

frequency is shown here, and is valid for devices with short gatelengths, even at the scaling limit of 40 nm. Previously, a 1/Lg

2 depend-ence for fT was observed for graphene FETs with long gate lengthswhere the transport is channel-resistance limited, partly owing to thesevere mobility degradation associated with non-optimized gatedielectrics8. The 1/Lg scaling trend observed in our devices indicatesthat the transport is in a contact-limited regime, so that the electricfield along the channel is dominated by the value of contact resistanceat the source and drain and haslittle gate-length dependence. We notehere that a similar 1/Lg dependence is usually observed for short-channel conventional Si and IIIV FETs. This dependence is mainlydue to the nearly-constant effectivecarrier velocity (obtained by reach-ingthe saturation velocity of thematerial),whichis seldomobserved incurrent graphene devices. The long-channel (550-nm) device is in the

region of transition from channel-limited transport to contact-limitedtransport. The fT values obtained for this gate length are higher thanthe 1/Lg trend line; this is partly due to minimal short-channel effectfor this relatively long gate.

In devices made from conventional semiconductors, the electro-static potential profile will be controlled partly by the drain bias whenthe gate length is reduced. The resulting threshold voltage shift anddrain-induced barrier lowering cause deterioration of the transistorswitching. As in Si MOSFETs, controlling short-channel behaviour isof vital importance for graphene transistors. Moreover, occurrence ofKlein tunnelling in graphene pn junctions would make the short-channel effect worse2527. Therefore, the transconductance is expectedto decrease upon gate length scaling. The trade-off between perform-ance and small device size will be the key factor in determining the

scaling limit of graphene transistors.Nevertheless,as shown in Figs 2c,

3b and 4c, the 40-nm top-gated CVD graphene transistor on DLC is

stillwell-behaved, with high r.f.performance. Theresult alsoshows thegreat potential for graphene transistors to be scaled even further, to amuch smaller device size.

Many interesting studies of graphene physics, including investi-gations of the quantum Hall effect, have been performed at low tem-peratures: in contrast, no graphene r.f. transistors have been operatedand studied below room temperature. A number of applicationsrequire cryogenic operation of r.f. devices, and how the graphene r.f.device performs at low temperatures is also scientifically important.Here we carried out the first study of graphene r.f. transistors down toliquid helium temperatures. Care was taken to ensure measurementaccuracy; this included calibrating the system after the probe temper-ature and sample temperature had reached equilibrium. We foundthatunlike many previous studies of graphene on SiO2 substrates

which showed strong temperature-dependent interface trap densityand occupationthe r.f. performance of the graphene devices onDLC showed very little, if any, temperature dependence, being essen-tially unchanged at 4.3 K (Fig. 4a and b). Different gate biases wereapplied (from 28 V to 0 V) with a fixed drain bias of 1.6 V in a 550-nm-long device, where the current gain follows a 1/f dependencebetween 300 K and 4.3 K. This stability with temperature illustrates asignificant advantage of the high quality DLC substrate, in which thetrap density is very low. Figure 4c shows the current gain as a functionof frequency for three devices with different gate lengths at 4.3 K; allexhibit a well-defined 1/f dependence, as at room temperature. Asshown in the summary plot in Fig. 4d, the cut-off frequency showslittle temperature dependencein the range from 300K to 4.3K. Unlikethe carrier freeze-out effects typically observed in Si MOSFETs at

cryogenic temperatures28, the consistent temperature-independentresults found here open up new opportunities for future graphener.f. applications, such as ultra-low-noise or outer-space operations.

Besides the cut-off frequency, another important figure of merit forr.f. devices is the available power gain28,29; this is assessed using themaximum oscillation frequency (fMAX), defined as the frequency atwhich the power gain is equal to one. Very low power gain has beenachieved previously with graphene r.f. devices, and it was thereforeseldom reported. The poor fMAX of graphene devices usually resultsfrom the lack of clear current saturation and non-optimized gatestructure. Here we show that despite the lack of clear saturation, wecan achieve a high fMAX of 20 GHz from the 550-nm device and13 GHz from the 140-nmdevice (see Supplementary Fig. 4). It is notedthatfMAX, unlikefT, is highlydependent on thedesign of thedevice and

on the details of the interconnects, such as the gate metal thickness.

0.0 0.5 0 100 200 300 400 500 6001.0 1.5 2.00

5

10

15

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Lg

(GHzm)

gm (mS)

Lg = 550 nm

Lg = 140 nm

Lg = 40 nm

a b

0

40

80

120

160

Die 1Die 2Die 3Die 4Die 5Die 6

Cut-offfrequency,

fT

(GHz)

Gate length (nm)

1/L guideline

Figure 3 | Scaling behaviour of cut-off frequencies with gatelength downto40nm. a, fTLgversus direct current transconductance for three gate lengths:550 nm (black squares), 140nm (red circles) and 40 nm (blue triangles). Thedata from three different types of devices fall onto the same line, the slope ofwhich corresponds to theunit areagate capacitance.This shows theuniformity

of the graphene devices, the consistency of the measurements and the accuracyof the de-embedding approach. Data are shown as mean6 s.d., n5 6. b, PeakfT as a function of gate length from 30 devices in 6 different dies located on thesame wafer. Data are fitted well by the curve showing a 1/Lgdependence. Dataare shown as mean6 s.d., n5 3.

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Use of an optimized design, such as a mushroom-shaped gate to

reduce the gate resistance, is expected to further improve fMAX.The r.f. performance of graphene is limited mainly by two factors:

the substrate-limited carrier mobility and the contact resistance.Whereas the mobility dominates in long-channel devices, contact res-istance becomes more critical as the gate length decreases. To furtherimprove the r.f. performance of the graphene devices, efforts shouldbemade to minimize the contact resistance, as short-channel devices arebest suited to achieving ultimate device performance and high-densitycircuits. The contact resistance of graphene transistors is currentlytypically up to an order of magnitude higher than that of SiMOSFETs. Also, the short-channel effect can be mitigated by scalingdown the thickness of the gate dielectric to achieve better electrostaticcontrol by the gate.

METHODS SUMMARYTop-gatedgraphener.f. transistors werefabricated using graphenegrown by CVDon copper14, as follows. After evacuation of the CVD chamber, the Cu foil washeated to 875 uC in forming gas (H2/Ar) and kept at this temperature for 30 min.After reduction, the Cu foil was exposed to ethylene at 975uC for 10 min and thencooled. PMMA was spin-coated on top of the graphene layer that had formed ononesideof theCu foil.The Cufoilwas then dissolvedin 1 M iron chloridesolution.The remaining graphene/PMMA layer was washed and transferred to the desiredsubstrate. Subsequently, the PMMA was dissolved by treatment with hot acetonefor one hour. The CVD graphene after transfer to DLC was characterized byRaman spectroscopy before device fabrication. DLC film was grown on an 8-inchSi substrate using cyclohexane (C6H12) with a vapour pressure of 1.8 p.s.i. in aCVD chamber. The flow rate was typically 2540cm3 STP per min at 100 mtorrpressure.The DLCgrowth rate is 32A s21 at60 uC; this wasfollowedby an annealstep at 400uC for4 h. Thesource/drain contact was20 nm Pd/30nm Audepositedby electron-beam evaporation. The gate oxide was formed by an oxidized Al layer

deposited by electron-beam evaporation, followed by the deposition of 15 nm

ALD Al2O3 film. The direct current and r.f. characterizations were carried out

in a probe station under,1026

torr using an Agilent parameter analyser B1500,and a E8364C network analyser. The system was calibrated using a short-open-load-through method. On-chip open and short structures with the exact design ofthe devices were used to de-embed parasitic effects, such as pad capacitance andinterconnection resistance. The low-temperature measurements were performedusing the same approach, and system calibration was done for each temperature.On-chip de-embedding, using standard open-short structures, was also done ateach temperature.

Received 3 January; accepted 4 March 2011.

1. Novoselov,K. S. et al. Two-dimensional gas of massless Dirac fermions ingraphene. Nature 438, 197200 (2005).

2. Zhang, Y. B., Tan, Y. W., Stormer, H. L. & Kim, P. Experimental observation of thequantumHall effectand Berrysphasein graphene. Nature 438, 201204 (2005).

3. Berger, C. et al. Electronic confinement and coherence in patterned epitaxialgraphene. Science 312, 11911196 (2006).

4. Avouris, P. Graphene: electronic and photonic properties and devices. Nano Lett.10, 42854294 (2010).

5. Lemme,M. C.,Echtermeyer,T. J.,Baus,M. & Kurz,H. A graphene field-effectdevice.IEEE Electron Device Lett. 28, 282284 (2007).

6. Lin,Y.-M. et al. Operation of graphene transistors at gigahertz frequencies. NanoLett. 9, 422426 (2009).

7. Meric,I., Baklitskaya,N., Kim,P. & Shepard, K.L. RFperformance oftop-gated,zero-bandgap graphene field-effect transistors. Tech. Dig. IEDM 14 doi:10.1109/IEDM.2008.4796738 (2008).

8. Lin,Y.-M. etal. Development of grapheneFETs for highfrequencyelectronics.Tech.Dig. IEDM 237240 doi:10.1109/IEDM.2009.5424378 (2009).

9. Lin,Y.-M. et al. 100 GHz transistors from wafer-scale epitaxial graphene. Science327, 662 (2010).

10. Moon, J. S. et al. Epitaxial-graphene RF field-effect transistors on Si-face 6H-SiCsubstrates. IEEE Electron Device Lett. 30, 650652 (2009).

11. Liao, L. et al. High-speed graphene transistors with a self-aligned nanowire gate.Nature 467, 305308 (2010).

12. Lee, J. et al. RF performance of pre-patterned locally-embedded-back-gategraphene device. Tech. Dig. IEDM 568571 doi:10.1109/IEDM.2010.5703422(2010).

30 GHz

10 GHz

4.3 K

1 10 100

1 10 100

1

10

100

1

10

100

6 GHz

|h21

|

|h21

|

|h21

|

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1 10 100

Frequency (GHz)

300 K

26 GHz

a b

dc

1

10

100

40 nm

140 nm

550 nm

T= 4.3 K

Frequency (GHz)

0 100 200 3000

50

100

150

200

40 nm

140 nmfT(GHz)

Temperature (K)

550 nm

Figure 4 | Temperature dependence of cut-off frequency for differentdevices. a, b, Current gain as a function of frequency at 300 K (a) and 4.3 K(b). The gate length is 550nm, with a Vds of 1.6 V and withVgs varying from28 V to 0V. c, Current gain versus frequency for three values ofLg (550 nm,

140 nm and 40 nm) at 4.3 K. The value offT is 28GHz, 70 GHz and 140GHz,respectively. d, Summary plot of the temperature dependence offT for threedifferent devices; little temperature dependence was found.

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13. Schwierz, F. Graphene transistors. Nature Nanotechnol. 5, 487496 (2010).14. Li, X. S. et al. Large-area synthesis of high-quality and uniform graphene films on

copper foils. Science 324, 13121314 (2009).15. Han, M. Y., Ozyilmaz, B., Zhang, Y. B. & Kim, P. Energy band-gap engineering of

graphene nanoribbons. Phys. Rev. Lett. 98, 206805 (2007).16. Wang, X. et al. Room-temperature all-semiconducting sub-10-nm graphene

nanoribbon field-effect transistors. Phys. Rev. Lett. 100, 206803 (2008).17. Chen, Z., Lin, Y.-M., Rooks, M. J. & Avouris, Ph Graphene nano-ribbon electronics.

Physica E40, 228232 (2007).18. Li, X., Wang, X., Zhang, L., Lee,S. & Dai, H. Chemically derived,ultrasmooth

graphene nanoribbon semiconductors. Science 319, 12291232 (2008).

19. Xia,F., Farmer,D. B., Lin,Y.-M. & Avouris,Ph Graphene field-effect transistors withhighon/offcurrentratio andlarge transport bandgap at roomtemperature. NanoLett. 10, 715718 (2010).

20. Robertson, J. Diamond-like amorphous carbon. Mater. Sci.Eng. Rep. 37, 129281(2002).

21. Lee,B. K.etal. Conformal Al2O3dielectriclayerdepositedbyatomiclayerdepositionfor graphene-based nanoelectronics.Appl. Phys. Lett. 92, 203102 (2008).

22. Kim, D. H. & del Alamo, J. A. 30-nm InAs pseudomorphic HEMTs onan InPsubstrate with a current-gain cutoff frequency of 628 GHz. IEEE Electron DeviceLett. 29, 830833 (2008).

23. Gummel, H. K. On the definition of the cutoff frequency fT. Proc. IEEE57, 2159(1969).

24. Arden, W. et al. (eds) ITRS 2009 edition. http://www.itrs.net/Links/2009ITRS/Home2009.htm (21 June 2010).

25. Katsnelson, M. I., Novoselov, K. S. & Geim, A. K. Chiral tunnelling and the Kleinparadox in graphene. Nature Phys. 2, 620625 (2006).

26. Huard, B. et al. Transport measurements across a tunable potential barrier ingraphene. Phys. Rev. Lett. 98, 236803 (2007).

27. Young, A. F. & Kim, P. Quantum interference and Klein tunnelling in grapheneheterojunctions. Nature Phys. 5, 222226 (2009).

28. Sze,S.M. & Ng,K. K.Physicsof Semiconductor Devices 3rd edn (Wiley-Interscience,2006).

29. Lee,T. H. TheDesign of CMOSRadio-FrequencyIntegratedCircuits(Cambridge Univ.Press, 2004).

Supplementary Information is linked to the online version of the paper atwww.nature.com/nature.

Acknowledgements We thank T. Graham, B. Ek, J. Bucchignano, C. V. Jahnes andS. Han for technical assistance, and C. Y. Sung, V. Perebeinos, A. Valdes-Garcia,C. Dimitrakopoulos, W. Zhuand H.-Y. Chiufor discussions. Thiswork was supported inpart by DARPA through the CERA programme (contract FA8650-08-C-7838). Theviews,opinions andfindingscontainedin thisLetter arethoseof theauthorsand shouldnot be interpreted as representing the official views or policies, either expressed orimplied, of DARPA or the US Department of Defense.

Author Contributions Y.W., Y.-m.L. and P.A. designed the experiment, and Y.W.performed device fabrication,electricalcharacterizationand dataanalysis. Y.-m.L. andK.A.J. contributed to the r.f. characterization.A.A.B. performed graphene synthesis, andF.X. helped to prepare the DLC substrate. Y.-m.L and D.B.F. contributed to devicefabrication. Y.Z. performed TEM imaging. Y.W. wrote the Letter, and Y.-m.L. and P.A.discussed and commented on the manuscript. All authors provided feedback.

Author Information Reprints and permissions information is available atwww.nature.com/reprints. The authors declare no competing financial interests.Readers are welcome to comment on the online version of this article atwww.nature.com/nature. Correspondence and requests for materials should beaddressed to Y.-m.L. (yming@us.ibm.com) and P.A. (avouris@us.ibm.com) .

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