NAGENDRA BABU GUNTI1501, 15th Avenue South, Apt#19, Birmingham, Alabama 35205

E-mail: nagsphd@uab.edu � Phone: (337) · 889 · 7284

OBJECTIVE

To gain experience in the design and implementation of ICs by utilizing my skills, abilities and experience inthe field of VLSI.

EDUCATION

University of Alabama at Birmingham, Birmingham July 2016 (Expected)Ph.D. in Electrical and Computer Engineering Overall GPA: 4.0

Indian Institute of Technology Roorkee (IITR), Roorkee June 2012Master’s of Technology in Electronics and Communication Engineering (Major: VLSI) GPA: 7.65 out of 10

Jawaharlal Nehru Technological University, Hyderabad (JNTUH) May 2010B.Tech in Electronics and Communication Engineering Overall GPA: 3.75

EXPERIENCE

Design Intern, Xilinx Inc., Hyderabad, India October 2012 - July 2013Project : Olympus Technology: 20nm

• Performed checks such as Contention check, CheckScheme, XE2 on Interconnect and CONFIG blocksof FPGA to ensure circuit’s stability, performance and reliability.

• Extraction of critical paths and Optimization of interconnects to achieve a better performance.• Responsible for generating spec2lib of CONFIG and nanotime libs for Interconnect blocks.• Generated and released all the .libs for Interconnect blocks for sync4, sync5, sync6 and final tape out

using Nanotime.

AREAS OF INTEREST

Hardware Security, FPGA and ASIC Design, RTL design and ImplementationSTA, Low Power Design, VLSI CAD, Digital Circuit Designing, IC Designing, Reliability

TECHNICAL SKILLS

Tools Cadence Design Suite, Synopsys-HSPICE, Xilinx ISE, ModelSimHDL and Languages VerilogHDL, VHDL, CPre layout Simulator ModelSim (Mentor Graphic), PSPICE, MatlabLayout Editor Virtuoso (Cadence)DRC/LVS Tool Caliber-DRC/LVSSynthesis Tool Design Compiler (Synopsys)STA Nano Time (Synopsys)Scripting Language PERL

ACADEMIC PROJECTS

Ph.D. Dissertation Sept 2013 - PresentAdvisor: Dr. Karthikeyan Lingasubramanian Dissertation: Security Aware Design of Computing Hardwareto Detect and Neutralize the Effect of Malicious Modifications

• Integrated circuits (ICs) are vulnerable to Hardware Trojans (HTs) due to the globalization of IC designand fabrication process.

• In this work we propose a double protected methodology, by making changes in the design, which makesit tough to insert HTs and also helps in increasing the detection sensitivity of inserted HTs at postmanufacturing phase.

• In order to achieve this goal, we have studied the usage of reliability models like Triple Modular Re-dundancy (TMR) and low power models like power gating to enhance post manufacturing detection ofHTs.

Master’s Thesis January 2011 - July 2012Advisor: Dr. B. K. Kaushik Thesis: Design of Low Power Encoder for the Avoidance of Crosstalk in RLCModeled VLSI Interconnects

• Designed a low complexity encoder which reduces both crosstalk delay and power consumption in Inter-connects using Bus invert Method.

• The overhead of the encoder is reduced by 67.86% in power consumption, 46.78% in propagation delayand 37% in area occupied by the encoder.

Special Project August 2014 - Dec 2014Familiarize with VLSI design flow by designing 4-bit ALU

• Designed and implemented 4-bit ALU to get familiarized with VLSI design flow from RTL to physicallayout level.

• The circuit is implemented in Cadence and laid the circuist successfully with clean DRC, LVS and QRC.The extraction has been done and the extracted SPEF is simulated using HSPICE.

RELEVANT COURSES

Digital VLSI Circuit Design VLSI Physical Design Device and Circuit SimulationMOS Device Physics and Modeling Semiconductor Materials and Devices Analog VLSI Circuit Design

PUBLICATIONS

• Nagendra Babu Gunti, Aman Khatri, and Karthikeyan Lingasubramanian, “Realizing a SecurityAware Triple Modular Redundancy Scheme for Robust Integrated Circuits,” 2014 22nd InternationalConference on Very Large Scale Integration (VLSI-SoC), 6-8 Oct. 2014).

• B. K. Kaushik, Deepika Agarwal, and Nagendra Babu Gunti, “Bus Encoder Design for ReducedCrosstalk, Power and Area in coupled VLSI Interconnects,” Microelectronics Journal, Elsevier, vol. 44,no. 9, pp. 827-833, 2013.

• Nagendra Babu Gunti, B. K. Kaushik, Anand Bulusu and Manoj Kumar Majumdar, “Low Complex-ity Encoder for Crosstalk Reduction in RLC Modeled Interconnects,” 16th International Symposium onVLSI Design and Test (VDAT 2012), Shibpur, India, July 1-4, LNCS 7373, pp. 40-45, 2012.

• Nagendra Babu Gunti, Deepika Agarwal, B. K. Kaushik, and S. K. Manhas, “Bus Encoder forCrosstalk Avoidance in RLC Modeled Interconnects,” International journal of VLSI design and Com-munication Systems (VLSICS), vol. 3, no. 1, pp. 181-191, Feb. 2012.

• Nagendra Babu Gunti, Deepika Agarwal, B. K. Kaushik, S. K. Manhas, and Brijesh Kumar, “CrosstalkAvoidance in RLC Modeled Interconnects using Low Power Encoder,” in Proc. IEEE International Con-ference on Recent Advances in Intelligent Computational Systems (RAICS 2011), Trivandum, 22-24 Sept.2011 .

• Nagendra Babu Gunti, Deepika Agarwal, B. K. Kaushik, and S. K. Manhas, “Power and CrosstalkReduction Using Bus Encoding Technique for RLC Modeled VLSI Interconnect,” Proc. 2nd InternationalWorkshop on VLSI, Springer-verlag publication, Chennai, pp. 424-434, 15-17th July, 2011.

• Deepika Agarwal, Nagendra Babu Gunti, B. K. Kaushik, and S. K. Manhas, “Reduction of Crosstalkin RC Modeled Interconnects with Low Power Encoder,” Proc. IEEE Int. Conf. on Emerging Trendsin Networks and Computer Communications (ETNCC-2011), Udaipur, pp. 115-120, 22nd -24th April,2011.

ACHIEVEMENTS

• Poster presentation on ”Detection of Hardware Trojans in Integrated circuits with power gating” at 91stAnnual Meeting of Alabama Academy of Science, 2014, Auburn University.

• Teaching Assistant for a 300 level Electrical circuits course since Spring 2014.

• Organized social service programs like Pulse Polio drops for children, creating awareness about AIDSamong the people in villages and Blood Donation camps with National Cadet Corps (NCC).