Multizone, Multiobject D-TOF System in 55nm · 2019. 5. 29. · MS_TDC1 MS_TDC2 MS_TDC3 MS_TDC4 110 120 130 140 150 160 170 180 190 200 Counts Bins RS_TDC0 MS_TDC1 MS_TDC2 MS_TDC3

ams AG - Shaping the world with sensor solutions

Multizone, Multiobject D-TOF

System in 55nm

Robert Kappel

1st International SPAD Sensor Workshop

Les Diablerets, Feb 27th, 2018

Content

• Time of flight module

Silicon

» Sensor

▪ SPAD

▪ Readout

▪ Time to Digital Converter

▪ Data storage

» Illumination

▪ VCSEL driver

• Measurement Results

VCSEL beam

Distance measurement

» Module only, cover glass, smudge

• Demonstration video

» Distance measurement

» Multi object

» Multi zoneConfidential © ams AG

Page 2

D-TOF SiliconSPAD sensor and light emitter

• Architecture

• Characterization data

Confidential © ams AG

Page 3

Block Diagram

Features:

55nm HV process

node

Custom developed SPAD

sensor

4 zones on main sensor array

TDC and histogram based distance detection

Fully integrated power management

Cortex M0 CPU

Sub-ns pulse generating laser driver

Multi-mesa VCSEL diode

Reference

SPADMeasurement

SPADs


Page 4

High Voltage Power Management

CPUARM M0

Clock Generation

TDC+Memory TDC+Memory


TDC+Memory

Breakdown voltage detection

Main Memory

Low Voltage Power Management

VCSEL Driver

I2C interface

V/IReference

SPADarray

...

...

SPADarray

...

...

SPADarray...

...SPADarray...

...

SPADarray...

...

Block Diagram

Features:

55nm HV process

node

Custom developed SPAD

sensor

4 zones on main sensor array

TDC and histogram based distance detection

Fully integrated power management

Cortex M0 CPU

Sub-ns pulse generating laser driver

Multi-mesa VCSEL diode

Reference

SPADMeasurement

SPADs


Page 5

High Voltage Power Management

CPUARM M0

Clock Generation



TDC+Memory

Breakdown voltage detection

Main Memory

Low Voltage Power Management

VCSEL Driver

I2C interface

V/IReference

SPADarray

...

...

SPADarray

...

...

SPADarray...

...SPADarray...

...

SPADarray...

...

SPAD Details

SPAD characteristics:SPAD cross section:

Parameter Typ Unit

BV 17.7 V

BV temperature coefficient 0.016 V/K

DCR @ 3V 0.28 cps/um²

PDP @ 940nm 1.5 %

Timing Jitter @ 940nm (FWHM) 80 ps

After pulsing probability <0.5 %

Fill factor (SPAD + Quenching) 25 %

DNW

SPAD N

SPAD P

p+p+

HVNW

RPO

anodecathodesub

HVPW

n+

• Isolated SPAD sensor

• Modified process to generate SPAD P and SPAD N layer to

reduce the breakdown voltage

low DCR

low jitter

Low afterpulsing probability


Page 6

PDP=f(Vexc, T, λ)

SPAD Key Characteristics


Page 7

• Photon detection probability PDP depends on wavelength and

excess bias voltage.

• PDP increases with temperature for 940nm because bandgap

decreases with temperature.

• PDP similar to state of the art.

@940nm

Vexc

55nm-HV

(†) Veerappan, C., Charbon, E., “A Low Dark Count p-i-n Diode Based SPAD in CMOS Technology,”

IEEE Trans. Electron Devices 63(1), 65–71 (2016).

(†)

Timing Jitter @940nm

SPAD Key Characteristics


Page 8

• The full width half maximum (FWHM) of the timing jitter

decreases with excess bias voltage.

• The jitter tail is hardly impacted by the excess bias voltage.

• The FWHM at 3V excess bias voltage is 80ps including the

jitter from the Laser source (42ps).

Log scale Linear scale

80ps

Sync pulse of laser

Histogram of

accumulated

event edges

Counter

Timestamps

Arithmetics

VCSEL Clock

STOP

SPAD Array

START

Histogram Memory

Readout

star

tst

op

...

......

...

Multiple SPADs per Macropixel

Distance MeasurementReadout and Time-to-Digital converter

• SPAD readout circuitry

• Symmetrical digital gates

• TDC principle

• TDC architecture

• Distance processing and calibration

• Histogram storage


Page 9

Counter

Timestamps

Arithmetics

VCSEL Clock

STOP

SPAD Array

START

Histogram Memory

Readout

star

tst

op

...

...

...

...

Multiple SPADs per Macropixel

Sensor ReadoutOverview

• Pulse shaper to generate a narrow event pulse independent on SPAD

deadtime

• Multiple SPADs to be combined to a single TDC channel by using an OR-Tree

• Readout time must be equal from each SPAD to the TDC

Light

From

Filter Quenchin

gLight

From

Filter Quenchin

g

Light

From

FilterQuenching

OR

…

TDC

Readout delay

Equal

readout

delay?


Page 10

Time to Digital ConverterOverview

Free running ring oscillator with flip-flop based overflow counter

and latches

• Fine Counter:

LSB represents propagation delay of inverting cell (~50ps)

• Coarse Counter:

Flip-flop based counter detecting overflow of fine counter

• Latch:

To store the actual state of the counter on-the-fly without disturbing

oscillation

• Decoder: decode

Combines fine- and coarse- counter value to a timestamp

• Data is stored in SRAM based histogram memory

» Counter value represent address to be incremented

Counter

Timestamps

Arithmetics

VCSEL Clock

STOP

SPAD Array

START

Histogram Memory

& inv inv inv inv inv inv inv inv inv inv inv inv inv inv counter0 counter1ENABLE

latchesTRIGGER

flopsclk80

clk80

decoder

flops

RINGOSC: Full Custom Design

Time resolving unit of sensor:

TDC core architecture:

Fine counter Coarse countersTwo coarse counters?


Page 11

SRAM based

histogram

memory

TDC Principle ISimplified Example

T0 T1 T2 T3 T4 Fine Counter coarse counter 0

0 1 0 1 1 8 0

0 1 0 1 0 9 0

1 1 0 1 0 0 → 0

1 0 0 1 0 1 0

1 0 1 1 0 2 → 0

1 0 1 0 0 3 1

1 0 1 0 1 4 1

0 0 1 0 1 5 1

0 1 1 0 1 6 1

0 1 0 0 1 7 1

0 1 0 1 1 8 1

0 1 0 1 0 9 1

1 1 0 1 0 0 → 1

1 0 0 1 0 1 1

1 0 1 1 0 2 → 1

1 0 1 0 0 3 2

1 0 1 0 1 4 2

0 0 1 0 1 5 2

0 1 1 0 1 6 2

T1 T2 T3 T4

T0

Flip-flop based counter

Fine counter Coarse counter

trigger Latches

• Transparent latches immediately

freeze counter values in case of

an event

High probability that one latch of

the fine counter is in metastable

state

» could introduce 1LSB error

Coarse counter setup time

causes delayed response on

fine counter overflow

» Unsafe region of counter may

introduce large error

trigger1

trigger2

Setu

p t

ime F

F

16

12

13

22

23

Unsafe

region

Safe

region

Unsafe

region

15


Page 12

TDC Principle IISimplified Example

T0 T1 T2 T3 T4 Fine Counter coarse counter 0 coarse counter 1

0 1 0 1 0 9 0 0

1 1 0 1 0 0 → 0 0(+1)

1 0 0 1 0 1 0 0(+1)

1 0 1 1 0 2 → 0 0(+1)

1 0 1 0 0 3 1 0(+1)

1 0 1 0 1 4 1 0(+1)

0 0 1 0 1 5 → 1 0

0 1 1 0 1 6 1 0

0 1 0 0 1 7 → 1 0

0 1 0 1 1 8 1 1

0 1 0 1 0 9 1 1

1 1 0 1 0 0 → 1 1(+1)

1 0 0 1 0 1 1 1(+1)

1 0 1 1 0 2 → 1 1(+1)

1 0 1 0 0 3 2 1(+1)

1 0 1 0 1 4 2 1(+1)

0 0 1 0 1 5 → 2 1

0 1 1 0 1 6 2 1

0 1 0 0 1 7 → 2 1

T1 T2 T3 T4

T0


Fine counter Coarse counter

trigger Latches


• 2 flip-flop based overflow counters with

complimentary clock edge sensitivity

Consider only the “stable” coarse

counter of a oscillation period when

evaluating the latched counter value of

the TDC at point in time of trigger signal

» Fine counter values indicates region

and therefore coarse counter to be

used

» Coarse counter value need to be

corrected in certain region to cover

overlap

Overall 1 LSB error could be introduced

Setu

p

tim

e

FF

22

23

1615


Page 13

How to calibrate the fine counter?

Digital Calibration Scheme

TDC Calibration


Page 14

Before calibration

After calibration

• Each TDC contains one ring oscillator

Absolute ring oscillator speed is unknown

(-50%..+100%)

Relative ring oscillator speed amongst

each other (+-5%)

• Pure digital solution for calibration is used.

Each TDC is able to measure its own ring

oscillator speed using the system clock as

reference.

Correction factor can be determined for

individual histograms

110 120 130 140 150 160 170 180 190 200

Counts

Bins

RS_TDC0

MS_TDC1

MS_TDC2

MS_TDC3

MS_TDC4

110 120 130 140 150 160 170 180 190 200

Counts

Bins

RS_TDC0

MS_TDC1

MS_TDC2

MS_TDC3

MS_TDC4

Illumination of sceneVCSEL and VCSEL Driver

• VCSEL architecture

• VCSEL driver

• Optical characteristics of beam


Page 15

Key Performance Parameter

VCSEL Driver

Block Diagram


Page 16

• Charge Pump

Decouples min supply voltage from VCSEL

forward voltage

Small loop of VCSEL current (low EMI)

No extra PMOS switch required

• Eye Safety Control

Short on VCSEL anode/cathode

Current limitation through VCSEL (charge pump)

Clock failure detection (charge pump)

• Pulse generation

Pulse width: ~300ps FWHM

High peak current

• Laser safety: Class 1

VCSEL Power Management

Eye Saftey Control

Pulse Generator

Open/short fail

Trigger

VDD

System performanceMeasurement results

• VCSEL pulse

• Crosstalk and smudge removal

• High accuracy, Independent of object

color

• Demonstration video


Page 17

VCSEL beam measurements


Page 18

Characteristics:

• Optical pulse 150ps

• FOI 15° (1/e²)

Optical pulse VCSEL emission profile

• Sub-ns pulsed mode allows

increased peak power

200mm to 3000mm in 50mm steps

Measurement conditions


Page ‹#›

• Target size:

1m x 1m

50fps/800 000 integration cycles

• Color:

90% white

18% grey

4% black

• Conditions:

Without cover glass

With cover glass (85% transmissivity)

Cover glass + smudge

• Background light on the target:

0.2klux

1klux

5klux

10klux

20klux

TOF module

Cover

glass

with

smudge

Cover

glass

without background light

Histogram comparison


Page ‹#›

0 50 100 150 200 250

Counts

Bin (timing information)

0 50 100 150 200 250

Counts

Bin (timing information)

crosstalk

200mm

500mm

1000mm1500mm

2000mm

200mm

500mm

1000mm

1500mm

2000mm

crosstalk

• Smudge on coverglass

significantly increases cross talk

• Reduced signal causes limited

maximum distance

• Target peak bin position is not

affected by crosstalk

without Coverglass Coverglass + smudge

0.2klux and 1klux

Distance measurement I


Page ‹#›

0

500

1000

1500

2000

2500

3000

0 500 1000 1500 2000 2500 3000

TO

F d

ista

nce

[m

m]

real distance [mm]

0.2klux

white_0.2klux_noCG white_0.2lkux_CG

white_0.2klux_Cgsmudge grey_0.2klux_noCG

grey_0.2klux_CG grey_0.2klux_Cgsmudge

black_0.2klux_noCG black_0.2klux_CG

black_0.2klux_Cgsmudge

0

500

1000

1500

2000

2500

3000

0 500 1000 1500 2000 2500 3000

TO

F d

ista

nce

[m

m]

real distance [mm]

1klux

white_1klux_noCG white_1klux_CG

white_1klux_Cgsmudge grey_1klux_noCG

grey_1klux_CG grey_1klux_Cgsmudge

black_1klux_noCG black_1klux_CG

black_1klux_Cgsmudge

5klux, 10klux and 20klux

Distance measurement II


Page ‹#›

0

500

1000

1500

2000

2500

0 500 1000 1500 2000 2500

TO

F d

ista

nce

[m

m]

real distance [mm]

5klux





0

500

1000

1500

2000

2500

0 500 1000 1500 2000 2500

TO

F d

ista

nce

[m

m]

real distance [mm]

10klux





0

500

1000

1500

2000

2500

0 500 1000 1500 2000 2500

TO

F d

ista

nce

[m

m]

real distance [mm]

20klux





Conclusion


Page 23

• Direct Time of Flight system using robust histogram-based architecture

• Custom developed SPAD sensor in 55nmHV process node

• Symmetrical readout structure

• Free running TDC architecture

Digital calibration scheme

Double differential measurement principle

• 940nm VCSEL laser in pulsed operation

Laser class 1 safe

• Distance measurement over a wide range of conditions

Distance measurement insensitive to crosstalk and smudge

• Multi-object

• Multi-zone capability

Thank you!Please visit our website

www.ams.com

Documents

Multizone, Multiobject D-TOF System in 55nm · 2019. 5. 29. · MS_TDC1 MS_TDC2 MS_TDC3 MS_TDC4 110 120 130 140 150 160 170 180 190 200 Counts Bins RS_TDC0 MS_TDC1 MS_TDC2 MS_TDC3