Multilayer photonic logic gate integratedinto microelectronic chip

Amihai MeiriShai TzurYosi CohenOri BassAlexander FishZeev Zalevsky

Multilayer photonic logic gate integrated intomicroelectronic chip

Amihai Meiri,a Shai Tzur,a Yosi Cohen,a Ori Bass,b Alexander Fish,b andZeev Zalevskya

aBar-Ilan University, Faculty of Engineering, Ramat-Gan, 52900, Israelmeiria1@gmail.com

bBen-Gurion University, The VLSI Systems Center, ECE Department, Beer Sheva, Israel

Abstract. An all-optical XOR gate was designed to take advantage of the previously unusedsilicon dioxide (SiO2) interconnect layers in a microelectronic chip. The device relies on thecoupling of modes between parallel waveguides and the interaction of the modes with themetal interconnects of a silicon chip to obtain a phase difference between input arms. Whenthe signals from the two input arms interfere, the result is a logic XOR operation due to thephase difference. The design was numerically implemented, and a contrast of 18.7 dB wasobtained with a 13.2-μm-long logic gate. © 2012 Society of Photo-Optical Instrumentation Engineers(SPIE). [DOI: 10.1117/1.JNP.6.061607]

Keywords: integrated optics; all optical devices; logic gates; photonics; silicon.

Paper 12021SS received Feb. 28, 2012; revised manuscript received Aug. 25, 2012; accepted forpublication Aug. 27, 2012; published online Sep. 25, 2012.

1 Introduction

In the last few years, there has been an ongoing effort to design electro-optical and all-opticaldevices to be used as modulators, transistors, and logic gates.1 This trend emphasizes the need toreduce size while using silicon due to the well-known fabrication processes of the microelectronicsindustry. Whereas structures such as Mach–Zehnder interferometers resulted in devices with a sizeof a few millimeters,2,3 ring resonators4,5 reduced the size to just a few micrometers. The proposeddevices use nonlinear effects such as plasma dispersion6,7 and two-photon absorption.8

Optics has a few advantages over electronics in data processing, among them relative immu-nity to electronic interference, high signal noise ratio (SNR), high bandwidth, and low channelcross-talk. While optical fibers are used for long distance communications, the data processing isperformed electronically on silicon chips. Currently, these electronic chips are built in layerswhere interconnect layers are fabricated on top of the silicon transistor layer. Those interconnectlayers are composed of silicon dioxide (SiO2) and metal lines.9

In this work, we propose the use of the interconnect layers, which are currently used only aselectrical insulators. These SiO2 layers can be used to waveguide optical signals, and with the aidof the metallic lines, realize all optical logic operations, such as a XOR gate.10 This approachenables us to combine electronic and optic data processing on the same chips, instead of reducingthe size of the photonic devices; we can potentially utilize the entire space of the silicon chipfor data processing. This approach enables better use of the volume of microelectronic chip inaddition to electronic and optical computation side by side.

In Sec. 2 we describe the background and theory behind the operation of the device.Sections 3 and 4 report the investigation methodology and numerical simulations, respectively.The paper is concluded in Sec. 5.

2 Background and Theory

The device operation is pillared on the coupled-mode theory and the structure of a microelec-tronic chip. In this section, we describe how these principles are used together to obtainall-optical logic operation.

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2.1 Chip Structure

Modern microelectronic chips are built in a layer structure.9 First the silicon wafer, whichcomposes the basic layer, is manufactured. The silicon layer is created to house the firstlayer, the transistor layer where all the transistors, diodes, and other semiconductor devicesare located. To complete the fabrication of the transistor, a high k dielectric and poly siliconare placed on top of this layer.

Next to be fabricated are the interconnect layers, which are the actual electronic routes inthe chip. Today, interconnects are characterized by copper or copper-based metal and low kdielectrics. In the first layer (layer 1), the interconnects are used to connect the transistors toeach other and to the outside world. The next layers (layer 2, layer 3, etc.) have differentmetal sizes than layer 1. Usually the size of the metal grows as we move further from thetransistor layer.

2.2 Coupled-Mode Theory

It is well known that when light is inserted into a structure made of two identical parallel slabwaveguides with subwavelength separations between them, the electric field can be expressedas the sum of modes in each waveguide:

E ¼ AðzÞE1 þ BðzÞE2; (1)

where E1, E2 are the modes in the two waveguides and A, B are the amplitudes that depend onthe propagation distance, and obey the coupling equations

dA

dz¼ −jCB and

dB

dz¼ −jCA: (2)

Here C is the coupling coefficient, and we assume the waveguides and propagating modesare identical. Solving these equations yields

AðzÞ ¼ cosðCzÞAð0Þ − j sinðCzÞBð0Þ and BðzÞ ¼ −j sinðCzÞAð0Þ þ cosðCzÞBð0Þ: (3)

From these equations we can see that when there is a single input signal (e.g., Bð0Þ ¼ 0), thelight transfers back and forth between the waveguides, with a constant phase shift of π∕2,11–13

and the power crossing is periodic with a first crossing at z ¼ π∕2C. The coupling coefficient canbe written as

C ¼ ωε0R∞−∞

R∞−∞ðN2 − N2

1ÞE�1 · E2dxdyR

∞−∞

R∞−∞ uz · ðE�

1 ×H1 þ E2 ×H�2Þdxdy

: (4)

Here N is the refractive index over the entire structure and N1 is the refractive index of thewaveguide cores.

The introduction of metal between the waveguides contributes to additional accumulatedphase which depends on the interaction length.10,11 If we choose the length of the metalsuch that it causes a phase difference of π, when a signal is inserted into both waveguides,the phase difference causes a negative interference and the output is low. When light is insertedinto only a single waveguide, the output is high, thus resulting in all-optical XOR operation.

Because layer 1 of a microelectronic chip is composed of SiO2 blocks with metal betweenthem, we can use these layers to build an all-optical XOR gate. The structure of such a device isdemonstrated in Fig. 1. The gate consists of two SiO2 waveguides with a width of 995 nm and a10-nm chromium barrier between them. At the output port, the signals are combined into oneSiO2 waveguide with a width of 2 μm.

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3 Methodology and Design

The numerical investigation of the device was carried out using Comsol Multiphysics, a com-mercial software that relies on the finite element method to solve partial differential equations.We used the RF module, which solves the wave equation, where the materials are modeled bytheir refractive index. The conductivity of metal is expressed by using a complex refractive indexN ¼ n − ik. For the simulations, we used a typical optical communications wavelength ofλ0 ¼ 1.55 μm, and the refractive index of the SiO2 structures was 1.48.

To test the ability to use such structures as light waveguides and photonics devices, the lossesof the guiding SiO2 layers with metal between them were computed. Due to the nature of lightpropagation in coupled waveguides, the interaction with the metal depends on where it ismeasured. Therefore the losses were averaged over a distance of 10 μm, and the result was0.11 dB∕μm.

In each phase of the design process of the device, we concentrated on a single parameter, andthe best parameter value was used in subsequent phases. The first parameter we tested was thewidth of the metal layer. For that simulation, the width of the SiO2 waveguides was 1 μm, and themetal used was cobalt with a refractive index N ¼ 5 − 6j. (The choice of cobalt is just an initialchoice according to Ref. 10; later the material chosen for the metal layer may be different.) It isevident from the results in Fig. 2 that a metal width of more than 10 nm will result in reflection ofthe electric field inside the waveguides rather than power transfer between them. We found that ametal width of 10 nm allows exchange of power between the waveguides. (This conclusion istrue for metals with refractive index close to that of cobalt, while other metals might allow forwider metal layers.)

The desired refractive index of the metal was determined by splitting the simulation into twoparts: finding the real part of the refractive index and the imaginary part. First, we examined theinfluence of the imaginary part and found that for high values the phase accumulation is slow,whereas for low values the accumulated phase can reach the desired value quickly; however, atthat point the power is not divided equally between waveguides. The best value for this simula-tion was determined to be k ¼ 5, as demonstrated in Fig. 3(a).

Fig. 1 Structure of the XOR gate. The silicon bottom layer appears in red.

Fig. 2 Electric field distribution for a metal width of 10 nm (a), 30 nm (b), and 50 nm (c).

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Next we looked at the real part of the refractive index, while keeping the imaginary part as aconstant, k ¼ 5. Here, lower values of the refractive index resulted in rapid power exchangebetween waveguides; however, the accumulated phase was not equal to the desired value ofπ in the point of equal power. For the higher values of the refractive index, the phase accumulatedquickly; however, the power exchange was slow, a fact which would require longer waveguides,thus enlarging the device. The best value appeared to be n ¼ 4.1 [see Fig. 3(b)]. Thus, the bestresults are obtained for a refractive index of N ¼ 4.1 − 5j, which is close to that of chromium[4.13 − 5.03j (Ref. 14)].

To minimize power loss, we want the device to be as short as possible, while maintainingequal power in the two waveguides and obtaining a phase difference of π. Looking at the electricfield in Fig. 3(c), at a distance of 12.5 μm, we obtain both requirements. Note that zero phasebetween input waveguides is an important requirement. Assuming a single data source for thechip (i.e., the data come from a single fiber), the data is split between the different logic gates.Since the fabrication processes of the microelectronic industry are capable of a precision of tensof nanometers, the errors in length of the waveguides between the logic gates are of a fraction ofa wavelength; therefore, the phase can be controlled precisely by proper choice of waveguidelengths.

To determine the length of the output port (where the waves from the two waveguides inter-fere), we located a multimode waveguide at the output of the two waveguides. The width of theport was 2 μm, and the initial length was 1 μm. We focused our attention to the y position in theoutput port, which corresponds to the middle of the two waveguides as depicted in Fig. 4(a).We conclude from the electric field at the output port in Fig. 4(b) that the highest ratio betweenlow-power output and high-power output (logical 0 and logical 1, respectively) is obtained whenthe length of the output port is 700 nm; therefore the length of the entire device is 13.2 μm.

4 Numerical Analysis

Using the results of Sec. 3, we set the final dimensions of the device, as described in Fig. 1.The results of the simulations that tested the performance of the device can be seen in Fig. 5. TheXOR operation is evident in the results of Fig. 5(a) and 5(b), where, when only one input signalis present, the output is high, while when we have a signal in both inputs, the output is low.In Fig. 5(c) we see the electric field in a cross-section at the output of the system. Whenthe output corresponds to a logical one, the output signal is high at the sides of the output wave-guide and low in the middle. However, when integrating over the entire face, we find that the

Fig. 3 Electric field along the two waveguides in the case of only one input signal. (a), Imaginarypart of the refractive index is k ¼ 5. (b) and (c), refractive index is N ¼ 4.1 − 5j .

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ratio between the electric field norm outputs of the 1–0 case to the 1–1 case is 12.4 dB. Note thatthe thickness of the metal and SiO2 should be the same, while the only requirement is that thefinal dimensions of the waveguides result in a single-mode waveguide.

The reading of the gate’s output can be achieved using a photodiode fabricated at the lowertransistor layer. To deflect the beam toward the silicon layer, a photonic crystal made of SiO2

with silicon holes, shown in Fig. 6, can be used. The diameter of each hole is 115 nm, and thedistance between holes is 250 nm. The gap in the photonic crystal is located at the output face ofthe device where the electric field is highest in the 1–0 input, as can be seen in Fig. 5(c). Thischoice enables us to take advantage of the maximal effect of the interference between arms.

The results for the XOR gate with the photonic crystal are shown in Fig. 7. Here we see thatthe results match those of the earlier structure without the photonic crystal. While the efficiencyin that case is lower, the ratio between logical high state and low state is 18.7 dB.

Subsequent to the monochromatic wave input, we tested the performance of the device for arange of wavelengths 1550� 50 nm. We see in Fig. 7(c) that the contrast between logical 1 and0 at the output of the device is at least 13.7 dB, with an average of 18.5 dB. The cascading ofXOR gates can be obtained using multiple wavelength inputs.

4.1 Fabrication Process

Following the suggested design, the fabrication for experimental validation includes severalstages. In this fabrication process the device is rotated by 90 deg. Now the two waveguidesare side by side and the photonic crystal’s cylinders are perpendicular to the surface of the silicon

Fig. 4 Results at the output port. (a), The electric field was calculated along the red line. (b), Theelectric field along the last 1 μm of the cut line.

Fig. 5 Results of the XOR operation. (a), The input is 1–0, i.e., there is only one input signal. Theoutput in both waveguides is high. (b), The input is 1–1, i.e., light is inserted in both waveguides,the output is low in both waveguides. (c), The norm of electric field at the output along the y axisfor both cases.

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wafer. The SiO2 layer can be grown from the silicon wafer to create the waveguides. Thene-beam lithography followed by etching is used to create the cavity for the metal. In thenext step, electron resist is placed and the area above the cavity is exposed through e-beamlithography. Then the metal is deposited followed by a lift-off process to create the metallayer between the waveguides. For the simplicity of the fabrication, the silicon cylinders aresurrounded by air instead of SiO2. Although different from our design, this structure will resultin a confinement and guiding of the light toward the silicon layer. This is achieved by e-beamlithography and etching around the cylinders, for a depth of the waveguiding layer. The result issilicon cylinders surrounded by air for a depth of the waveguiding layer, while at the bottomthese cylinders are attached to the silicon layer.

5 Conclusions

The use of interconnect layers on a silicon chip as photonic data processing units was demon-strated through the use of mode coupling between two SiO2 waveguides separated by a thin

Fig. 6 XOR gate with photonic crystal at the output. The crystal is made of SiO2 with silicon holes.The silicon bottom layer appears in red.

Fig. 7 Results for the XOR gate with the photonic crystal. (a), 1–0 input. (b), 1–1 input.(c), Contrast between logical 1 and 0 in the output of the photonic crystal for different signalwavelengths.

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metal layer. An all-optical logic XOR gate was obtained with dimensions of 13.2 × 2 μm andcontrast of 18.7 dB between ON and OFF states.

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Amihai Meiri received his BSc in 2007 from Bar Ilan University, and he iscurrently a PhD student in the Faculty of Engineering in Bar Ilan Univer-sity. His research is focused on silicon photonics, optical devices that incor-porate nanoparticles, and microscopy.

Shai Tzur received his BSc degree in electrical engineering from Bar IlanUniversity, Israel, in 2011. His specialties are communication and micro-electronics. His final project is in the field of electro-optics, and is focusedon multi layers hybrid chips. Currently he is working as front-end engineerat Freescale Semi Conductor Israel.

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Yosi Cohen received his BSc degree in electrical engineering from Bar IlanUniversity, Israel, in 2011. Today he is a QA Engineer in Valens Semicon-ductor. His final project involved the design of an all-optical XOR gate.

Ori Bass is currently a student of electrical engineering in the VLSI LowPower Center, Ben-Gurion University, Israel. His current research focuseson memristors.

Alexander Fish received his BSc (1999) from Technion, Israel, and MSc(2002) and PhD (2006, summa cum laude) from Ben-Gurion University,Israel. He was a postdoctoral fellow in the ATIPS laboratory at the Uni-versity of Calgary (Canada) from 2006 to 2008. Currently he is a facultymember in Electrical and Computer Engineering Department, Ben-GurionUniversity, Israel. His research interests include low-voltage digital design,energy-efficient SRAM and flash memory arrays, and low-power CMOSimage sensors.

Zeev Zalevsky received his BSc and direct PhD degrees in electrical engi-neering from Tel-Aviv University in 1993 and 1996, respectively. He iscurrently a full professor in the Faculty of Engineering in Bar-Ilan Univer-sity, Israel. His major fields of research are optical super resolution, bio-medical optics, nano-photonics and electro-optical devices, RF photonics,and beam shaping. He has published more than 285 refereed journalpapers, more than 165 conference proceedings papers, more than 260 inter-national presentations, of which more than 80 were invited or plenary,25 issued patents and more than 15 patents pending, 5 authored books,

3 books as an editor, 24 book chapters, and 4 papers in the SPIE Milestone series.

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