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The Microelectronics Training Center, IMEC v.z.w.www.imec.be/mtc
delfi.imec.be
MTC 2003 : Silicon Processing courseIMEC© 2003
David J. SteinPage 1
CMP
David J. Stein, Ph.D.Sandia National Laboratories
andUniversity of New MexicoAlbuquerque, NM USA
Acknowledgements
Sandia National LabsDale Hetherington, Reid Bennett
IMECKatia Devriendt
RodelMike Oliver
CabotPaul Feeney
Sharp Microelectronics USADave Evans
Laredo TechnologiesTom Tucker
The Microelectronics Training Center, IMEC v.z.w.www.imec.be/mtc
delfi.imec.be
MTC 2003 : Silicon Processing courseIMEC© 2003
David J. SteinPage 2
Outline
IntroductionWhat is CMP?– Overview – CMP Consumables (focus on slurries and pads)
CMP processes and applicationsGlass polishing basicsDielectric CMP– ILD, STI
Metal CMP– W, Cu
Novel applications– MEMS, Ag, replacement gates…
Chemical-Mechanical Polishing (CMP)
Film topography
Post CMP
Process ParametersPad and slurry typePolishing tool
Pressure (carrier/backside)Velocity (carrier/platen)Carrier design Flow rate of slurryTemperature (slurry/pad)
Pad conditioning
Down Force
CarrierBacking filmWaferPad
SlurryRotation
Platen
Pad Conditioner
The Microelectronics Training Center, IMEC v.z.w.www.imec.be/mtc
delfi.imec.be
MTC 2003 : Silicon Processing courseIMEC© 2003
David J. SteinPage 3
CMP Images
Polish head (holds wafer)
Conditioning disk
Slurry dispense
IR probe
Technology enabled by CMP
1985-90 19971980
Spin-on resist& etchback
CMP of PECVD
dielectrics
Damascene Cu CMP
1995
STI CMP
2.5 µm
LOCOS
LOCOS isolation
STI
2000+
IBM, 1997
1987-92
CMP of WPolyNoble metalsMEMS…
The Microelectronics Training Center, IMEC v.z.w.www.imec.be/mtc
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MTC 2003 : Silicon Processing courseIMEC© 2003
David J. SteinPage 4
Driving Forces Behind Planarization
A) Film DepositionStep coverage
B) LithographyDepth of focus
C) EtchEtch stringers
Diagram - C. Paumier, SEMICON/Europa 95 Technical Conference
D) New materials and manufacturingex. damascene Cu CMP
Moore’s Law and CMP Applications
1970 1980 1990 2000 20100.01
0.1
1
10
Copper CMP
STI CMP
Tungsten CMP
ILD CMP
Mic
ron
Feat
ure
YearMinimum Feature Size Data: IEDM Short Course, 1999
New Applications
Poly CMP
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MTC 2003 : Silicon Processing courseIMEC© 2003
David J. SteinPage 5
Planarization Roadmap
1999 INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS
1999 2000 2001 2002 2003 2004 2005
0.1
0.2
0.3
0.4
Year
Min
imum
Fea
ture
(µm
)
0.2
0.4
0.6
0.8
1.0
Dep
th o
f Foc
us (µ
m)
Feature size decreasingChip size increasingDecreasing depth of focus budget:
stepper issues (~ 80%)wafer flatness (~20 %)
100 nm technology nodedesire < 50 nm of planarization within the die*
Global Planarity Issues
* CMPMIC Conference Roadmap Discussion March, 2001.
CMP Infrastructure
Process Technology
Process parameters:film & substrate type, polish speed, pressure, slurry flow
Process Specs:Uniformity, Planarity, Final Thickness
Pad Technology
Material properties:density, filler, porosity mechanical modulus
Pad Engineering:thickness, subpad, adhesive, grooves, pad life, conditioning
Slurry Technology
Material properties:colloid type, size, shape, stability
Formulation:pH, % solids, buffer, viscosity
Distribution:bulk mixing, recycling
Polisher Technology
Polisher Design:rotary, linear, orbital
Carrier Design:gimballing, floating, bellows, membrane
Throughput Design:single/multiple heads,multiple platens
Manufacturing Technology
Endpoint techniques:pad temperature, motor current, vibration, film thickness
CMP Process
Manufacturing Technology
Pad Conditioning:end effector type, cut rate, pad break-in, removal rate stability
The Microelectronics Training Center, IMEC v.z.w.www.imec.be/mtc
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MTC 2003 : Silicon Processing courseIMEC© 2003
David J. SteinPage 6
CMP Market
Tom Tucker, Laredo Technologies Inc. email: [email protected]
The Microelectronics Training Center, IMEC v.z.w.www.imec.be/mtc
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MTC 2003 : Silicon Processing courseIMEC© 2003
David J. SteinPage 7
Tom Tucker, Laredo Technologies Inc. email: [email protected]
Tom Tucker, Laredo Technologies Inc. email: [email protected]
The Microelectronics Training Center, IMEC v.z.w.www.imec.be/mtc
delfi.imec.be
MTC 2003 : Silicon Processing courseIMEC© 2003
David J. SteinPage 8
Tom Tucker, Laredo Technologies Inc. email: [email protected]
Tom Tucker, Laredo Technologies Inc. email: [email protected]
The Microelectronics Training Center, IMEC v.z.w.www.imec.be/mtc
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MTC 2003 : Silicon Processing courseIMEC© 2003
David J. SteinPage 9
CMP Process Sector
Polisher
CMP Process
Wafers In
Slurry Mixand
Distribution
Pad & InsertTechnology
SlurryReclaim
ConditioningTechnique
End PointDetection
ProcessMonitoring Post CMP Cleaning
Brush Scrubber
MegasonicClean
Metrology Defects and Film Thickness
Wafers Out
The current generation CMP tool is a dry-in dry-out system.
2 of 3 Basic Types of CMP Processes
Polish oxide
Stop on oxide
METAL-VIA FILLOXIDE
M
OXIDE
Polish metal
Stop on oxide
M
Continuous Layer CMP Damascene CMP
Tungsten, Copper, Aluminum,Shallow Trench, and Trench DRAM Poly
Dielectric (backend ILD)
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3rd Type (not discussed in presentation)
CMP smoothing process
Surface finishing
surface roughness
Examples: silicon surface finishing, polysilicon smoothing.
Polishing Terminology
Removal Rate
pre,post = thickness measurementsn = number of measurementst = polish time
Within Wafer Non-Uniformity (WIWNU)
RR implied; equals standard deviation of RR
Wafer To Wafer Non-Uniformity (WTWNU)
standard deviation of wafer-level RR means
Edge exclusiondistance from edge that measurements are excluded fromfor blanket wafers typically wafer diameter is reduced by 2 X edge exclusion for calculation of measurement point locations
Within Die Non-Uniformity (WIDNU)
standard deviation, across a wafer, of RR or TTV within a die
( )
nt
postpreRR
n
nn∑ −= 1
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Polishing Characterization
Wafer Level(due to tool and
consumable issues)Die Level
Wafer edge effects
Within-die effects (due to pattern density layout)
CMP Consumables
SlurriesPadsSlurry filtersPad conditioning disksCarrier insert films (backing films)Carrier retaining ringsChemicalsPolyvinyl alcohol (PVA) brushesDe-ionized waterMonitor wafers
√√
Subject of remainder of introduction presentation√
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CMP Slurries
Ultra fine solid particles dispersed in a solutionnormally water basedcolloid stability is important
Particle size and concentration varies10 nm < primary particle size < 1000 nm0.1 % < weight percent concentration < 30 %
Abrasive typesSilica, alumina, ceria
AdditivesOxidizers, buffers, surfactants, chelating agents, corrosion inhibitors, (other proprietary stuff).
Important Slurry Properties
Average particle size and distributionSpecific surface areaPercent of abrasive in solutionChemical additivesSpecific gravity, viscosity, and pHImpuritiesSettling characteristicsManufacturing processes and other details in Appendix
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David J. SteinPage 13
TEM of Fumed Silica Particles*
* Courtesy of Cabot Microelectronics
TEM of Colloidal Silica Suspensions*
*Klebosol Colloidal Silicas
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Important Pad Properties
ThicknessSpecific GravityPore Structure
sizedensity or volume
CompressibilityHardnessChemical durability
IC1000specific gravity 0.7
IC1000specific gravity 0.9
Closed Cell Foam Pads - IC1400 (Class III)
top pad
bottom sub-pad
100 µm
IC1400 pad is manufactured by Rodel Corp.
glue layer
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Images of Molded Urethane Pad*
*Cabot EPICTM Pad
surface Open (interconnected) cells
Fixed Abrasive Polishing Pad*
PRESSURE-SENSITIVE ADHESIVE
Resilient Foam ( 50 - 90 mils)
ADHESIVE
ADHESIVE
Polycarbonate ( 20 - 60 mils)
BACKING
Structured Abrasive
SUBPAD
~ 250 µm
* 3M/Rodel Fixed Abrasive Pad
SEM images - A. L. Moy, SNL
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Micro-replicated Surface Contains Ceria Abrasive
0.001 0.01 0.1 1.0 10.0 100.0 103 104 µm
Aqueous Salts
Metal Ion
Atomic Radii
Colloidal Silica/Particles
Feature Size
Pad AsperityWafer
Die SizePad Groove
Polishing mechanisms Manufacturing Yield
CMP Length Scales - 9 Orders of Magnitude!
*M. Verhoff, Sandia National Labs
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Relative Scale of Asperities
10 µm
Oxide Fill Material Silicon Wafer
Polyurethane Pad
Al/Cu Metal
1µm step heights
20 µm pore diameter
Summary - Introduction Section
CMP continues to enable manufacturing of advanced IC’s
Driving forces for improved planarization– Photolithography (depth of focus)– Etching (clearing)– Deposition (step coverage)– New materials and manufacturing methods that involve
CMPLarge infrastructure (worldwide)– equipment, consumables, manufacturing methods and
controlApplications include:– STI, polysilicon, ILD, tungsten, copper, etc.
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Dielectric CMP
Mechanisms and Processing
Empirical wear equation
Brown(2) and Cook(3) showed derivationelastic Hertzian indentationmaterial removed equals indentation cross-sectional area * distance traveledwhere E = Young’s modulus
Cook(3) noted experimental kp and (2E)-1 don’t agree
E2PvPR =
Preston - Removal rate(1)
vPkRR rp ⋅⋅=
PR - Glass polish ratekp - Preston coefficient
(process dependent)P - Applied pressurev - Linear velocity
PR
(1) F. Preston, J. Soc. Glass Tech. 11 (1927) 214.(2) N. J. Brown, P. C. Baker, and R. T. Maney, SPIE 306 Contemporary Methods of
Optical Fabrication, 1981, 42.(3) L. M. Cook, J. Non-Cryst. Solids 120, 1990, 152.
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travel
compressiontension
particle oxide surface
Stress Contours - Travelling Hertzian Indenter*
SiO2 material in tensiondiffusion processes (layer becomes hydrated)
SiO2 material in compressiondissolution processes (pressure dependent dissolution)
*L. M. Cook, J. Non-Cryst. Solids 120, 1990, 152.
Water Reaction with SiO2
Water is necessary for effective polishing.Penetration of water into film is governed by diffusion.
a few atomic layers (Jaso, et al., PMIC 1997) (experiment Hydrogen profiling)1.2 nm (Cook, J. Non-Crystalline Solids, 1990) (calculation)75 -150 nm (Trogolo, et al., MRS Symp.1992) (experiment FTIR/TEM)
Reaction may produce thin hydrated (gel) layer which is abraided away during polishing exposing a fresh surface (process repeats itself).Dissolution of SiO2 enhanced at high pH (~ 10).Contact (wetting) angle on oxide surface decreases to 0 after CMP.
Si - O - Si + H2O 2SiOHSi
Si
O O
H
H
Si
Si
O
O
H
H
Si
Si
O
O
H
H
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0 1 2 3 4 5 6 7 8 9 10 11 120
1000
2000
3000
4000
5000
6000
7000
20 rpm
50 rpm
Carrier and platen speed - 90 rpmR
emov
al R
ate
(Å/m
in)
Carrier Pressure (psi)
rp vPkRR ∗∗=
Polishing Kinetics
kp varies with slurry, glass type, etc.
Oxide CMP Removal Rate ModelsPreston
wear equationCook
inclusion of elastic properties of particleMore recent
Zhang, et al. (hertzian-type plow describes removal)Tseng, et al. (expanded hertzian indenter to include shear stress)Zao, et al. (proposed pressure threshold mechanism but never confirmed experimentally)
See appendix I
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Degrees of Planarization
NoPlanarization
Smoothing
CompleteLocalPlanarization
CompleteGlobalPlanarization
Initial Step Height = t
Final Step
Final Step
t
Near GlobalPlanarization
Final Stepmm distances
CMP Processes
Planarization Length
Final Surface
Uniform polish Uniform polishNon-uniform polish region
Planarization Length
Typical polishing processes result in 3 - 5 mm planarization lengths.
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Back End of Line Dielectric CMP
Al/Cu MetalTungsten plug
Intermetal Dielectric Deposit Dielectric
Polish
CMP Issues:• No automatic endpoint• Global pattern density
variation• Deposition technique• Deposition thickness• Tight thickness control
Premetal Dielectric
Back-end Dielectric CMP
PreMetal Dielectric (PMD) CMP
Typically a phosphorous doped layerCritical layer for depth of focus (pattern density and planarity are key concerns)
Intermetal Dielectric (IMD) CMP
HDP commonly usedDielectric roadmap - low k dielectric materials
M1
M2
M3
WPMD
IMD1
IMD2
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Surface Profile and Gap-fill Technique
VoidingSiO2 Plasma Enhanced CVD TEOS(1)
Faceted topography
(1) L. Roherty-Osmun, Sandia Labs (2) J. T. Pye et al., Solid St. Tech., Dec. 1995.
Simultaneous dep-etch
PETEOS deposited with 5x dep/etch cycles
SiO2High Density Plasma(2)
PETEOS deposited without any dep/etch cycles
No Voiding
Pattern Density Variations - Measurement
84 % density - thickest oxide post CMP
4% density - thinnest oxide post CMP
Post-CMP Die Image4 8 16 28 44
12 20 32 48 64
24 36 52 68 80
40 56 72 84 92
60 76 88 96 100
aa
84% density
Section a-a
210 µm 40 µm
2 µm oxide
MIT/Sandia Density Mask Layout
2 mm
2 mm
10 mm
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Final Dielectric Thickness Vs. Pattern Density
Within-die range 520 nm
Target thickness
MIT/Sandia Density Mask
Case Study 1
Role of the Sub-pad on Die-level and Wafer-level Nonuniformity
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Sub-pad Experiment
foam sub-pad
(a) IC1000/foam sub-pad (b) IC1000/fiberglass sub-pad
Investigate 2 extreme cases of variations in sub-pad stiffnessCompare polishing results– within-die uniformity using Sandia/MIT density mask
Perform mechanical measurements– 3-point bending, compression, micro-indentation
IC1000 K groove
soft foam sub-pad
IC1000 K groove
fiberglass sub-pad
50 mil
50 mil
50 mil
50 mil
Bulk Mechanical Properties
0.000 0.002 0.004 0.006 0.008 0.010
0
200
400
600
800
1000 IC1000/fiberglass sub-pad IC1000/foam sub-pad
Flex
ural
Stre
ss (p
si)
Strain (in/in)0 5 10 15 20
0
200
400
600
800
1000
1200
1400 IC1000/fiberglass sub-pad IC1000/foam sub-pad
Com
pres
sive
Stre
ss (p
si)
Strain (%)
3-point bending test Compression test
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Micro-indentation Effects from Subpad
0 100 200 300 400 5000
5
10
15
20 IC1000/foam sub-pad IC1000/fiberglass sub-pad
load 10.2g
Pene
tratio
n de
pth
(µm
)Time (s)
Measurement data
The tip penetrates ~ 5 µm further into the IC1000/foam sub-pad compared to the IC1000/fiberglass under a 10 g load.
M
Quartz probe
60 mil radius+
1 mm 50 mil
50 mil
Penetration depth
WIDNU - Effect of Sub-pad
• IC1000/foam sub-pad shows highest die-level NU.• Speed has no effect on WIDNU.• Pressure shows effect on WIDNU but less than IC1000/foam sub-pad.
0.2 0.4 0.6 0.8 1.0 1.2
3 psi 30 rpm 3 psi 90 rpm 9 psi 30 rpm 9 psi 90 rpm
Normalized Polish Time (s)
0.2 0.4 0.6 0.8 1.0 1.2 1.40
1000
2000
3000
4000
5000
6000
7000
3 psi 30 rpm 3 psi 90 rpm 9 psi 30 rpm 9 psi 90 rpm
Oxi
de T
hick
ness
Var
iatio
n (Å
)
Normalized Polish Time (s)
IC1000/foam sub-pad IC1000/fiberglass sub-pad
SS-12 slurry SS-12 slurry
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WIW Oxide CMP Thickness Uniformity - Subpad Effect
Within-wafer non-uniformity shows opposite trend from within-die non-uniformity. The mechanical
properties of the sub-pad must be optimized to produce the lowest WIDNU and WIWNU.
02468
1012141618
90 rpm30 rpm90 rpm30 rpm
9 psi3 psi
Waf
er-le
vel n
on-u
nifo
rmity
(%1σ
) IC1000/fiberglass sub-padIC1000/foam sub-pad
Note: SS-12 slurry used in all processes.
Case Study 2
Role of Pad Thickness on WIDNU and WIWNU
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Experimental Description
Thicker pad showed faster time to planarization.Stiffer pad (no sub-pad) showed faster time to planarization.Increase in time to planarize larger step heights is not proportional to the step height.
Pad type 800 nm initial stepheight 2000 nm initial stepheight55 mils FX-9/subpad 300 s 450 s80 mils FX-9/subpad 250 s 400 s
80 mils FX-9/no subpad 200 s 350 s
K. Devriendt, Proceedings of the 1999 CMP-MIC Conference, VMIC, Tampa, 227
Effect of Top Pad Thickness on WIDNU*
* K. Devriendt, Proceedings of the 1999 CMP-MIC Conference, p. 227.
WIDNU defined as the level difference between the up features of the 75% dense structures and the down feature of an isolated structure (0% density).
0
500
1000
1500
2000
2500
0 100 200 300 400 500
WIDNU - Effect of pad thickness
55 mils FX-9/subpad80 mils FX-9/subpad
WID
NU
(nm
)
Polish time (s)
Klebosol 30N50 PHN slurry
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Wafer-level Non-uniformity: Down Features
* K. Devriendt, Proceedings of the 1999 CMP-MIC Conference, p. 227.
0
50
100
150
200
250
0 50 100 150 200 250 300 350
800 nm initial stepheight50 % pattern density
55 mils FX-9/subpad80 mils FX-9/subpad80 mils FX-9/no subpad
WIW
NU
(nm
)
Polish time (s)
Klebosol 30N50 PHN slurry
Case Study 3
Conditioning and Pad Wear Effects
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10 20 30 40 50 60500
1000
1500
2000
Rem
oval
Rat
e (Å
/min
)
Cumulative Polishing Time (min)
Removal Rate Reduction - No Conditioning
SEMs of pad surface
No Pad Conditioning IC1400 Pad
200 µm
Mesas
100 µm
Removal Thickness Vs. Time
1 2 3
2000
4000
6000
8000
10000
12000
14000
Pad Conditioningin-situex-situ
in-situex-situ
Pad Conditioning
Process B
Process A
4475 Å/min
3735 Å/min
973 Å/min1146 Å/min
Oxi
de T
hick
ness
Rem
oved
(Å)
Polish Time (min)
A: 9psi, 90 rpm
B: 5 psi, 20 rpm
Process
IC1400 PadSS-12 SlurryThermal OxideIPEC 472 Rotary
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Within-Die Uniformity - Pad Wear Effects
Oxi
de T
hick
ness
Var
iatio
n (Å
)
Data: K. Achuthan, Clarkson U. Thesis, 1998.
MIT/Sandia pattern density mask
Each data point represents a wafer polished to planarization at a particular moment of the pad life.
Case Study 4
Silica versus Ceria slurry
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Blanket Polish Rates - PECVD oxide
0
2000
4000
6000
8000Speed Slurry
9 psi3 psi
Rem
oval
Rat
e (Å
/min
)
Pressure
30 rpm, silica, SS12 90 rpm, silica, SS12 30 rpm, ceria, STS1000DV 90 rpm, ceria, STS1000DV
Pad type IC1400
Die-level Uniformity - IC1000/foam Sub-pad
0.2 0.4 0.6 0.8 1.0 1.2 1.40
1000
2000
3000
4000
5000
6000
7000
3 psi 30 rpm 3 psi 90 rpm 9 psi 30 rpm 9 psi 90 rpm
Die
-leve
l Oxi
de T
hick
ness
Var
iatio
n (Å
)
Normalized Polish Time (s)
SS-12 Silica slurry STS1000DV Ceria slurry
0.2 0.4 0.6 0.8 1.0 1.2 1.4
3 psi 30 rpm 3 psi 90 rpm 9 psi 30 rpm 9 psi 90 rpm
Normalized Polish Time (s)
Ceria slurry shows better die-level uniformity.
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Wafer-level Non-uniformity*
0
5
10
15
20
90 rpm
90 rpm
30 rpm
30 rpm
9 psi3 psi
Waf
er-le
vel n
on-u
nifo
rmity
(% 1σ)
Silica slurry Ceria slurry
IC1000/foam sub-pad
Summary of Results*
Die-level uniformity Wafer-level uniformityBest Worst Best Worst
PAD IC1000/fiberglass
IC1000/foam IC1000/foam IC1000/fiberglass
SLURRY Ceria Silica Ceria or Silica Ceria
SETTING 3 psi 90 rpm 9 psi 30 rpm 9 psi 30 rpm 9 psi 90 rpm
* D. L. Hetherington, et al., ECS Symposium on CMP in IC DeviceManufacturing, Oct., 1999.
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Shallow Trench Isolation CMP
Device Isolation Techniques - LOCOS vs. STI
LOCOS-based techniques in 0.25 µm technology
+ Manufacturable, simple,good know-how
- Large ‘bird’s beak’- Deep submicron scalability
Shallow Trench Isolation with Chemical Mechanical Polishing
+ Small active area pitch possible+ Denser device packing+ Superior planarity!
Further down-scaling
LOCOS LOCOS
p-well
n-wellp-wellSTI STI
n-well
Lateral isolation candidates
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Si
Si
Si3N4
Si
Si
Si3N4
Si3N4
Si3N4
Isolation stack :Thermal oxide growth (pad oxide)Active protecting nitride
Pattern and etch ofSi3N4 and SiO2
Trench etch into Si
Thermal oxidation of trench sidewall,corner rounding
SiO2
SiO2
SiO2
SiO2
SiO2
STI Process Flow
STI Process Flow
Si3N4
Si
SiO2
Si3N4
Si
SiO2
Si
SiO2
Deposition of trench fillingoxide (f.ex. HDP-CVD)
Oxide CMP Polish step with stop on nitride
Removal of nitride layer(wet etch in phosphoric acid)
SiO2
SiO2
SiO2
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CMP STI Polishing Regimes
I. Removing step height and oxide over the active area
II.Over-polish to ensure that all oxide is removed over active area everywhere on the die.
Trench OxideNitride
Silicon Active Area
Trench Oxide
Trench OxideSilicon Active Area
Nitride
Incomplete Polish or Erosion?→ Dependent on fill and integration approach ! Over-polished
Si
SiO2
SiO2Si3N4
densitypattern1
STI-CMP Issues
Pattern layout effectslocal removal rate ~ local pressure ~
variations in the active area to field step height after nitride strip – problems at subsequent lithography steps!
dishing in large field areas influence on surface planarity!
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The Problem
overpolished open area
underpolished dense area
Residual nitride in dense SRAM area
TEOS-Ozone HDP-CVD OxideLocal planarization as a function of active area width:
+/- Same oxide thickness everywhere
Different pyramids dependenton active area width
Difference in CMP behavior! (pattern density effects)
Trench Fill Method
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Solutions to Pattern Density CMP STI Problem
(1) Dummy fill(2) Oxide reverse etch (blockout) mask(3) Dual Nitride(4) Resist Block/Etchback Assisted CMP(5) Without Additional Litho Step
approaches(6) Consumables(7) Oxide dummy structures(8) Combinations of the above
Dummies widely used in oxide CMP BEOLeasiest way to solve pattern density variations
Similar idea for STI levelLarge field areas around isolated active areas can be filled up with dummy active areasrisk of overpolishing is reduced
Dummies offers a lot of design issuesdesigners don’t like itmixed signal technologies are especially sensitive to dummy charging–capacitive coupling and noise
Use of Dummy Structures
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Examples of Dummy Metal-FillGrounded metal-fill for DEC 600 Mhz Alpha chip(a)
Active Lines Metal fill(a) P. Gronowski, et al. IEEE J. Solid-State
Circuits, vol. 33, 5, p. 676, (1998).
Floating metal-fill
Active Lines Metal fill
STI Dummy Fill
STI dummy fill
Courtesy of J. Soden Sandia National Labs
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Modifying Existing Layouts
Requires analysis of within-chip layout density variationsdummy fill optimization
Optimized fill structure reduces density variation from 29% to 18%
Dummy FillPhysical process model-based dummy structure design:
Without dummystructure:
With dummystructure:
A
R Tian and X. Tang, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 1, JANUARY 2002
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Oxide Dummies - 6.25% Density
2000
3000
4000
5000
6000
7000
8000
40 60 80 100 120 140 160 180
1 - Field1 - Dummy4 - Field
Thic
knes
s (Å
)
Time (s)
yellow = dummy
blue = active
3000
4000
5000
6000
7000
8000
9000
40 60 80 100 120 140 160 180
2 - Field3 - Field3 - Dummy
Thic
knes
s (Å
)
Time (s)
Oxide Dummies - 25% Density
yellow = dummy
blue = active
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Oxide Dummies - Field to Dummy Comparison
2 3
4000
5000
6000
7000
8000
9000
10000
11000
12000
20 40 60 80 100 120 140 160 180
ata 5 38 8/8/ 00
2 - Dummy2 - Field3 - Dummy3 - Field
Thic
knes
s (Å
)
Time (s)
yellow = dummy
blue = active
Oxide Reverse Etch Approach
Oxide Reverse Etch (ORE), followed by CMP :
pad oxide / nitride depositiontrench patterning and etchingsidewall oxidation / deposition of trench filling oxideremove (most of) the oxide on large active areas with additional litho and etch stepremove remaining oxide from the active areas during the CMP stepnitride removed during etch step
Parameters to be optimized:• Oversize (litho misalignment)• Amount of oxide etched back?
Etch of (part of the) oxidein large active areas
Process flow : HDP oxideNitride
Oversize
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Dual Nitride Approach*
Protection of isolated active areas and wide field regions
No field protection in dense areas!
Oversize of 0.4 µm
Patterning of 2nd nitride (DN), followed by CMP:
Parameters to be optimized:• Oversize (litho misalignment)• Topography nitride on active to nitride on field
* G. Badenes, et al. JECS October 2000
– Isolation patterning – Etching of trenches / filling trenches with oxide– Patterning of a block resist over the large field areas to
bring up the surface to about the same level as oxide on the active areas / hardening of block resist
– Spinning of planarizing resist and cure– Reactive Ion Etch (RIE with 1:1 selectivity of resist to
oxide): flat resist surface transformed to flat oxide surface– (stopped before removing all oxide on active nitride)– Removal of spikes during short CMP step– Excellent planarization performance– RIE process and a planarizing resist required
Resist Block Approach
Process flow :
Planarizing resist
*B. Davari et al., IEDM Tech. Digest, p 61 (1989)
Block resistHDP Oxide
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Deposit thin nitride overcoat
HDP Oxide
Without Additional Litho Steps
Trench filling with oxide and deposition of a thin nitride layer
CMP with low selectivity slurryNitride overcoat is removed after a short polishing time in the dense active areas and on the small isolated ones
The large field areas are protected until the nitride overcoat above the dense areas is removed
*J.M. Boyd, J. P. Ellul, J. Electrochem. Soc, 143, p 3718 (1996) J.M. Boyd, J. P. Ellul, J. Electrochem. Soc, 144, p 1838 (1997)
approach applicable? Depending on the design!
Fixed Abrasive Pad
Abrasive: Cerium oxideSelectivity: (topography vs planarized film)
200 : 1Selectivity: oxide to nitride (planarized film)
1.2 : 1.0Low overfill thickness required:
CVD oxide higher throughputLess polishing time, higher throughput
Other advantages:Selective toward topography self stopping behavior!
Issues:Very dependent on mask set layout!Tight control on overfill thickness
M3100 3M/Rodel pad
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Fixed Abrasive Pad
0
200
400
600
800
1000
1200
1400
1600
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Pattern Density (100 µm Line Pitch)
Low selectivity slurry
High selectivity slurry
M3100 Fixed Abrasive
Nitr
ide
Loss
(Å)
Fixed Abrasive Pad
0
500
1000
1500
2000
2500
3000
3500
4000
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Pattern Density (100 µm Line Pitch)
Tren
ch O
xide
Los
s (Å
) Low selectivity slurry
High selectivity slurry
M3100 Fixed Abrasive
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Defects
Defects
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Defect Wafer Map
Die X Value
Die
Y Va
lue
STI
Trench Cut
Defect Source
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Edges
Edges can’t be ignored!
Edge ComparisonUnprotected Protected
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EBR to Bevel
Summary - Dielectric CMP
Pattern density effects is the key problem to solve for dielectric CMPDefectivity is also importantSlurry and pad engineering is focused on solutions for improving planarity and minimizing defectsChip layout can be optimized for CMP process
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Developments In Metal CMP Processes
CMP Removal to Stop Layer
Material removal and planarizationW plugs, copper dual damascene, aluminum (dual) damascene, STI, polysilicon-filled trenches
non-selective materialdeposition (conformal
or non-conformal)
CMP is selectiveto the stop layer
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CMP Removal to Stop Layer
Tungsten CMP
Process Overview
Multiple level etch stop
Photo Pattern and Etch Contacts
Sputter Ti/TiN & CVD W
Tungsten CMP
W
Plug erosion/ ILD scratching
CVD W
High aspect ratio contact fill
CVD Tungsten Filled Vias
Post Polished Tungsten Via
Process Sequence Cross-section of Via Fill
Post W CMP Surface
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Process and Technology ConsiderationsW CMP (vs. etchback) is the preferred method for sub - 0.5 µm technologiesW dual damascene has also been integrated into DRAM manufacturingIssues
removal rate and non-uniformitypad life and pad conditioningbarrier stack polish rateselectivity W to oxide removal ratesW plug key-holing, corrosion, and dishingdeep scratches in oxideoxide erosionpost CMP cleaningprocess stabilityprocess end-point
W CMP ConsumablesSlurries
abrasives– alumina– silica– ceria (only commercial in fixed-abrasive pad)
oxidizers– potassium ferrocyanide– potassium iodate – ferric nitrate– hydrogen peroxide– hydrogen peroxide with catalyst
pH range– acidic
pH 1.5 for ferric-based solutionspH 4.0 (buffered) iodate-based solutionsup to ~ pH 6
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W CMP ConsumablesPads
polyurethane– hard pad (closed pore, /w or w/o grooves)
Rodel IC1400, Thomas West P777, Freudenberg FX9 & PANW, Universal Photonics LP line
– soft pad (/w or w/o embossed channels)Rodel Politex, Universal Photonics UNI-NAP 12
new pad developments– open-celled polishing pad material (Cabot)– fixed abrasive pad material (3M)
conditioning disksNi-diamond end effectors
– higher corrosion rate in metal CMP slurry– reliability is a concern (diamonds may fall out and stick in the pad)
CVD diamond end effector (e.g. Diamonex)nylon brush for soft pads
Grain Size EffectAl
W
W-T. Tseng, Y-L. Wang, J. Niu, Thin Solid Films 370
Al
W
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Defects
erosion
Electrical contactnot made
Tungsten CMP
Metal patternand etch
Formation of nextmetal level
tungsten
PETEOStungsten plugs
Tungstenkeyhole
Locallyplanar
Locallyunplanar
Dishing
dishing and planarity
erosion
Dishing and Erosion Examples
P-11 profile scan location
4x4 array of tungsten vias (diameter 0.9 µm space 1.5 µm)
D. J. Stein, 1998 CMP-MIC, p. 161
Thin oxide lines
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Pattern Erosion Comparison
-2500
-2000
-1500
-1000
-500
0
500
0 1000 2000 3000 4000 5000
Prof
ile (Å
)
Distance (µm)
Politex pads
IC pads
IC1400 (24 °C)
IC1400 (44 °C)
Politex embossed (24 °C)
Politex regular (24 °C)
D. J. Stein, 1998 CMP-MIC, p. 161
Relationship Between Erosion / Pattern Density
densitypattern area totalarea metal
=Φ
=Φ ( )ott −Φ−
Φα=ε
1
KvPerosion
=α=ε
N. Elbel at al., J. Electrochem. Soc. 145 (5), May 1998
t,,P,v)erosion( Φ↑ε
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Dishing - AFM Scans
IC1400 pad Politex pad
D. J. Stein, 1998 CMP-MIC, p. 161
Pattern Density Effects on Dishing
area totalarea metal
=ΦDishing decreases withline width (thinner lines less dishing)increase in metal pattern density (more erosion)oxide polish rate (more erosion)
more metal
N. Elbel at al., J. Electrochem. Soc. 145 (5), May 1998
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Comparison of Metal CMP End-Point Methods
Study focuses on W CMP process
End-PointMethod
Detector Technique Issues
Padtemperature
IRtemperaturesensor
Sense change in padtemperature
pad wear
Carriercurrent
Motor currentsensor
Sense change infriction
motor currentnoise
Platen current Motor currentsensor
Sense change infriction
motor currentnoise
Filmreflectivity
Spectrometer Sense change inwafer surfacereflectivity
positioning ofspectrometer
Ming-Cheng Yang, et al., Proceedings CMP-MIC, 1998, p. 216
Pad Temperature and Motor Current Endpoint
Ferric nitrate based alumina slurry
G. Springer, Proceedings CMP-MIC, 1999, p. 45.
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Reflectivity End-point
Ref
lect
ivity
wavelength (λ)
time (s)Det
ectio
n al
gorit
hm
Ming-Cheng Yang, et al., Proceedings CMP-MIC, 1998, p. 216
CMP Removal to Stop Layer
Cu CMP
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Process Flow
previous level metal nitride hard mask via ILDpattern and etch hard mask
for vias
deposit line ILD over viahard mask, deposit, pattern,
and etch line hard mask
Process Flowdry etch (complicated!) to openspaces for damascene metal
seed layer deposition and ECDgrowth of Cu
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Process Flow - CMP
Cu dual-damascene CMP is similar to W CMP
CMP of conductor and barrier materialsstop on ILD/barriersimilar defect issues - dishing and erosion
Some issues in Cu CMP are different and harder to solve
CMP removal of excess materialto leave damascene vias and lines
Comparison to W CMPBoth W and Cu CMP require:
polish deposited metal through nitride barrier to oxide stopminimal dishing and erosiongood selectivity to oxide polish stoplow defects
Cu CMP is complicated by:polishing lines instead of plugs - electrical performance directly impacted by overpolishvery non-uniform deposition profile - can be worse than oxide CMPCu corrosion
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Cu and Dual-damascene CMP IssuesCu as a ECD material
very soft and susceptible to corrosionspontaneously anneals after deposition (up to or over 48 hours for stabilization at room T)
Cu as line metal in dual damasceneline thickness now determined by CMPline thickness directly affects electrical performance
Cu deposition profile affects CMPBarrier material
can it be removed using Cu slurry?
Approach 1 - 1:1:1 Selective Slurry
1:1:1 slurry may create die- and wafer-levelnonuniformity.
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Approach 2 - 2-step Stop on Barrier
2-step (stop on barrier) may dish copper.Too little barrier in isolated areas may beremoved (similar to STI)
Approach 3 - 2-step Stop on Oxide
1 step (stop on oxide) may dish copper anderode oxide.
st
2 step (1:1:1) creates die- and wafer-levelnonuniformity.
nd
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Topography After 1st Step of 2-step Slurry
The dishing is very small at the clear time
Dishing as a function of the polishing timeMeanders with a line width of 10 um
Different pattern densities
10 %20 %50 %67 %96 %
Pattern density
0
200
400
600
800
1000
0 50 100 150 200
Dis
hing
(nm
)
Polishing time (s)
clear time
J. Grillaert et al., 2000 CMP-MIC Proceedings, p. 75 and presentation at SEMICON Europa, April 2000.
Topography After 1st Step of 2-step Slurry
0.4 µm spacing - no dishing but excessive erosion
Dishing increasesas pattern densitydecreases
Dishing as a function of the polishing timeMeanders with a line width of 10 um
Different pattern densities(Enlargement)
0
50
100
150
200
250
300
0 50 100 150 200
10 %20 %50 %67 %96 %
Dis
hing
(nm
)
Polishing time (s)
clear time
J. Grillaert et al., 2000 CMP-MIC Proceedings, p. 75 and presentation at SEMICON Europa, April 2000.
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Topography After 1st Step of 2-step Slurry
Pattern densityincrease
•Lowest density: no erosion•Highest density: erosion increases immediately after the clear time•Intermediate density: first no erosion, then increase
Erosion as a function of the polishing timeMeanders with a line width of 10 um
Different pattern densities
0
50
100
150
200
250
300
350
400
0 50 100 150 200
96 %67 %50 %20 %10 %
Eros
ion
(nm
)
Polishing time (s)
Pattern densityclear time
J. Grillaert et al., 2000 CMP-MIC Proceedings, p. 75 and presentation at SEMICON Europa, April 2000.
Topography Issues
Dishing and erosion increasing with polishing timelow density features – heavy dishing but low erosionhigh density features – low dishing but heavy erosion
Accurate end-point detectionminimize dishing and erosionminimize process time thus increase throughput
Most uniform process is desiredleast WIW and WID NU
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Cu 112"Cu 122"Cu 132"
Electrical Results - Various Pattern Densities
Increase in time
20
25
30
35
40
96916650332010
Sheet resistance as a function of polishing timeMeanders with a line width of 10 um
Different pattern densities
Shee
t res
ista
nce
(moh
m/s
q)
Pattern density (%)Increase in erosionIncrease in dishing
Pattern density has a large influence on sheet resistanceJ. Grillaert et al., 2000 CMP-MIC Proceedings, p. 75 and presentation at SEMICON Europa, April 2000.
Electrical Results - Various Pitch Constant Density
Sheet resistance as a function of polishing timeMeanders with a pattern density of 50 %
Different line widths
20
25
30
35
40
0.3 0.4 0.5 0.7 1 2 5 10 30
Cu 112"Cu 122"Cu 132"
Shee
t res
ista
nce
(moh
m/s
q)
Line width (um)The line width has only a minor influence
Increase in time
J. Grillaert et al., 2000 CMP-MIC Proceedings, p. 75 and presentation at SEMICON Europa, April 2000.
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Electrical Results (Density)
The variation in the sheet resistance is the largest for the lowest andthe highest pattern density, i.e. the structures that are most sensitivefor dishing or erosion. ==> crucial importance of a uniform polishing and deposition processes.
20 25 30 35 40
96 %
91 %
67 %
50 %
33 %
20 %
10 %
Distribution of the sheet resistanceMeanders with a line width of 10 um
Different pattern densities
Sheet resistance (mohm/sq)
Pattern densityincreases
J. Grillaert et al., 2000 CMP-MIC Proceedings, p. 75 and presentation at SEMICON Europa, April 2000.
20 25 30 35 40
0.3 um0.4 um0.5 um0.7 um
1 um2 um5 um
10 um30 um
Distribution of the sheet resistanceMeanders with a pattern density of 50 %
Different line widths
Sheet resistance (mohm/sq)
The distribution of the sheet resistance across the waferis independent of the line width.
Line widthincreases
Electrical Results (Pitch)
J. Grillaert et al., 2000 CMP-MIC Proceedings, p. 75 and presentation at SEMICON Europa, April 2000.
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Time and Chemistry Effects on Dishing
SlurryAluminaH2O2carboxylic acid complexantproprietary stabilizer
Wafers6000 Å trenches in thermal SiO2500 Å sputtered TiCu by sputter
Timed endpointDifferent slurry than previous case study!
V. Nguyen et al., “Dependency of Dishing on Polish Time and Slurry Chemistry In Cu CMP”, Microelectronic Engineering 50, 403.
Linewidth and Pattern Density
Dishing increases with linewidth.
Dishing is roughly independentof pattern density.
(note difference with previous example)
V. Nguyen et al., “Dependency of Dishing on Polish Time and Slurry Chemistry In Cu CMP”, Microelectronic Engineering 50, 403.
Without overpolish
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Overpolish
V. Nguyen et al., “Dependency of Dishing on Polish Time and Slurry Chemistry In Cu CMP”, Microelectronic Engineering 50, 403.
Dishing increases with overpolish.
Dishing increases with linewidth.
[Oxidizer] and Cu Dep Thickness
Dishing decreases with H2O2 concentration.
Dishing decreases with thicker Cu depositions (1.5 µm vs. 0.8 µm).
V. Nguyen et al., “Dependency of Dishing on Polish Time and Slurry Chemistry In Cu CMP”, Microelectronic Engineering 50, 403.
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Cu CMP Consumables
Padssame as for W except 3M fixed abrasive also workssimilar issues as W CMP pads (discoloration, short lifetimes, conditioning)
Slurriesdepends on if one or two step process is usedall have to, at a minimum, meet these requirements– low Cu and barrier corrosion rates– low defect generation
Cu Slurry Chemical Effects
M. Pourbaix, Atlas of Electrochemical Equilibira in Aqueous Solutions, NACE, Houston, 1974
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Example Cu SlurriesFe(NO3)3 or HNO3 and inhibitor (BTA)
acidic pH (<3) - inhibitor needed to prevent Cu corrosionhigh Cu / low SiO2 polish ratecolloidal alumina is stable
H2O2 and amino acidsacidic pH (<7) - inhibitor needed high Cu / moderate SiO2 polish ratecolloidal alumina is marginally stable
Neutral oxidizerneutral to akaline pH (>7) - inhibitor not needed to control Cu corrosion ratelow Cu / high SiO2 olispolish ratecolloidal alumina is not stable
Grain Structure Evolution
48:000:45
SΩ
0 10 20 30 4015
16
17
18
19
20
R(m
/sq)
Time (hours)
Similar time dependence as RS !
24:003:45
10 µm
5:00 8:00
Source: S. Brongersma (Imec)
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Hardness and Resistivity vs. Anneal Time
room temperature anneal
K. Smekalin et al. MRS Proceedings 566, p. 143, April 1999
PR and Resistivity vs. Anneal Time
room temperature anneal
K. Smekalin et al. MRS Proceedings 566, p. 143, April 1999
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Elevated Temperature Anneals
5 minutes in inert gas
K. Smekalin et al. MRS Proceedings 566, p. 143, April 1999
Novel CMP Consumable
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Slurry-free Cu CMP
V. H. Nguyen et al., Microelectronic Engineering 55, 2001, p 305.
Slurry-free Cu CMP
V. H. Nguyen et al., Microelectronic Engineering 55, 2001, p 305.
A = slurry free
B = IC1000/Suba IVand QCTT1010 slurry
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Slurry-free Cu CMP
A = slurry free
V. H. Nguyen et al., Microelectronic Engineering 55, 2001, p 305.
B = IC1000/Suba IVand QCTT1010 slurry
Abrasive-Free (AF) Cu CMP
RR vs. downforce30 rpmnon-linear (saturates)WIWNU decreases to asymptote
RR vs. platen speed22 KPa fixed downforceremoval rate saturatesWIWNU decreases to asymptote
S. Kondo et al., JECS 147 (10), 3907
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Role of Grooves in AF CMP
Erosion and Dishing in Abrasive-Free Cu CMP
Both dishing and erosion are significantly reduced by using abrasive-free CMP
S. Kondo et al., JECS 147 (10), 3907
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Erosion and Dishing, Slurry vs. AF CMP
Slurry-based CMP (top left) shows significant dishing in the bond pads while AF CMP shows no dishing (bottom left)Less dishing results in lower line resistance (above)
S. Kondo et al., JECS 147 (10), 3907
Low-K
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Process Needs: Pre-metal Dielectric (PMD)
PMD layer issuesCritical layer for lithography depth of focusPlanarity/pattern density improvements requiredAt 100 nm Technology node: WIDNU < 50 nm.
Short TermConventional SiO2 materials
Long TermLow k (which materials?)
Process Needs: Low k / Ultra low k Low k and Ultra Low k CMP processes must be compatible with copper material
Current scenario: No direct CMP of low k– Capping layer CMP (Conventional SiO2)– Touchup post Copper CMP (dielectric exposed)
CMP of low k materialsNew consumables / process parametersDefectivity/Reliability issues– poor adhesion, scratching– change in surface properties
low friction low k CMP process– see S. M. Jang, et al. VLSI Tech. Symp., p. 18,
2002.
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1 kÅ
4 kÅ1 kÅ
5.5 kÅ
1 kÅ PVD Cu seed250 Å PVD Ta
Sematech CMP Study: low - k films*
*J. T. Wetzel, et. al. IEDM 2001, p. 73
CMP adhesion test for various low-k dielectric films
CMP test blanket film stack
CMP Failures vs. Hardness/Modulus*
Note: Process of record for Cu CMP used
at facility
*J. T. Wetzel, et. al. IEDM 2001, p. 73
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Cu/CVD Low-k (k< 2.5) Interconnects*
1 µm
~1000 Å
Cu pad AFM scan AFM results
8 levels of Cu/Low-k (k< 2.5) 1 level Cu/USG
*T. I. Bao, et al., IEDM Tech. Digest, Dec. 2002.
CMP of porous SiOC:H films (low friction polishing)
Cu Summary
Cu CMP is not easy!Similar to W CMP except– highly corrosive– soft (susceptible to dishing and erosion)– dishing and erosion enhanced because polishing lines
not plugs (higher density Cu exposed at end of process)
– hard to find a slurry that will polish Cu and barrier - 2 step slurry systems common
Pattern density references (ILD also)– http://www-mtl.mit.edu/Metrology/Publications.html
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Novel Metal CMP Processes
Silver Metallization
R. Manepallei et al., IEEE Transactions on Advanced Packaging 22 (1), 4.
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Silver Metallization
M. Hauder, Microelectronic Engineering 64, 73.
Noble Metal CMP
Enabling New Memory Devices
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DC icorr Measurements
Tafel plots are used to determine icorr
Electrode i-E behavior under activation polarization is described by the Butler-Volmer equationDetermine icorr by fit of i-E data to Butler-Volmer equation
i i e ecorr
nFRT
nFRT= −
−α η β ηButler-Volmer
Equation 10-6 10-5 10-4 10-3 10-2-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10measuredfit
abs(i) (A cm-2)
E vs
. SC
E (V
)
OCPicorr
Noble Metal CMP - Pt
Pt w/ abrasion250 Å min-1
Pt w/o abrasion8 Å min-1
Pt w/ abrasion, no chemistry300 Å min-1 on polisher
Pt w/o abrasion, no chemistry
Actual polish rate610 Å min-1
K. Moeggenborg et al., CMP-MIC 2001 Proceedings, Santa Clara, VMIC, 150.
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Noble Metal CMP - Pt
K. Moeggenborg et al., CMP-MIC 2001 Proceedings, Santa Clara, VMIC, 150.
Noble Metal CMP - Pt
K. Moeggenborg et al., CMP-MIC 2001 Proceedings, Santa Clara, VMIC, 150.
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Noble Metal CMP – Pt/Ir
0
500
1000
1500
2000
0 20 40 60 80 100
Polis
h ra
te (Å
min
-1)
Fraction Ir
D. Evans, personal communication.
Novel Gate Structures
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Damascene Metal Gate
Why damascene metal gates instead of poly?
high poly gate resistance limits speedboron penetration from doped poly changes threshold Vgate leakage degrades device reliabilitythreshold voltage deviation
A. Yagishita et al., IEEE Transactions on Electron Devices 47 (5), 1028.
Damascene Metal GateSi N3 4
PolyCombination of wet and dry etch
A. Yagishita et al., IEEE Transactions on Electron Devices 47 (5), 1028.
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Damascene Metal Gate
Damascene metal gatesallow for high-K gate dielectricsMinimizes plasma damagecomplete planarity and high scalabilitylow sheet resistivity thus lower RC time delayno depletiondrastic improvement in GOI
A. Yagishita et al., IEEE Transactions on Electron Devices 47 (5), 1028.
Acknowledgments
Dale Hetherington, Katia Devriendt, Mike Oliver, Dave Evans
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And Finally…
Si-Ge Smoothing with CMP*Device structure
AFM Results
*N. Sugii, et. al., IEDM 2001, p. 737.
CMP surface
CMP applied after the Si0.7Ge0.3layer grown.
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CMP Eliminates MEMS Design Constraints
Without CMP Planarized with CMP
Microgear, Linkage, and Hub Assembly
Planar linkage arm
Design Interference
Advanced MEMS Structures
Latch Mechanism Gear and Track Assembly - 5 Levels of Poly
Torque ConverterPop-up Mirror
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CMP really is rocket science!
Appendix IOxide CMP Removal Rate
Models and Studies Adapted from: D. J. Stein, D. L. Hetherington,
ECS Third International Symposium on Chemical Polishing in IC Device Manufacturing,October 17-22, 1999, Honolulu, Hawaii.
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Oxide CMP Removal Rate Models
Prestonwear equation (1)
Cookinclusion of elastic properties of particle (2), (3)
More recent Zhang, et al. (hertzian-type plow describes removal) (4)Tseng, et al. (expanded hertzian indenter to include shear stress) (7)Zao, et al. (proposed pressure threshold mechanism but never confirmed experimentally) (8)
Empirical wear equation
Brown(2) and Cook(3) showed derivationelastic Hertzian indentationmaterial removed equals indentation cross-sectional area * distance traveledwhere E = Young’s modulus
Cook(3) noted experimental kp and (2E)-1 don’t agree
E2PvPR =
Preston - Wear Rate(1)
vPkRR rp ⋅⋅=
PR - Glass polish ratekp - Preston coefficient
(process dependent)P - Applied pressurev - Linear velocity
PR
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Zhang and Busnaina(4) - PR=K(Pv)1/2
Total force is applied force plus electrostatic Van der Waals attractive force
either particle or surface deforms
A = Hamaker constant, zo is particle-surface separation distance
They assume Hertzian plowing removal, surface roughness equals particle indentation depth, and MP model(5):
2o
o z6ARF =
+=
o
2
oa Rza1FF
HaFF 2a π=+
Zhang and Busnaina(4) - PR=K(Pv)1/2
Normal stress = contact pressure:
From MP model(5) :
Use tribological approximation
Runnels(6) model
They obtain:
2a
c aFFP
π+
==σ
HaFF 2a π=+ HPc ==σ
snCPR τσ=
( )21
s PvC µ=τ
( )21
sn Pv'KKPR =τσ= 21
KH'K µ=
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Tseng et al.(7) - PR=KP5/6v1/2
Started with Runnels(6) PR=Cσnτs
Hertzian indenter
soUses Runnels shear stress approximation
Combining yields
KPD
23
NLF
2
== 2n aFπ
=σ31
2
22
1
21 r
E1
E1L
43a
ν−+
ν−=
31
Pn ∝σ
21
s PvPC ∝µ=τ
21
65
vKPPR =
Shi and Zhao(8,9,10) - PR=KP2/3v
Pad material is softer than particles or wafer hence particles must sink into padAssuming elastic deformation of pad
Number of particles per area of pad assumed constantHertzian plowing removalEach particle removes the same amount regardless of applied pressure hence
32
32
PFA ∝∝
vKPPR 32
=
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Zhao and Shi (8,9,10) - Pressure Threshold
Modification of previous derivationParticles roll in pad if applied pressure below threshold value
−= 3
2
threshold32
PPKPR
Polish Rate Experiments(11)
Thermal oxide
PECVD TEOS
VTR TEOS(710 °C)
HDP(SiH4 and
O2)varying
[Si]
BPSG5 flavors
Klebosol 1498-50
neutral pH 50 nm silica
neutral pH and pH 10,
5.5, 2.5
Klebosol 1508-50
NH4OH stabilized pH 10.8
50 nm silica√
Klebosol 30H50
pH 2.5 50 nm silica tried twice
Cabot SS12 pH 10.9-11.2130-180 nm √ √ √ Limited √
Rodel STS1000DV
pH 6.1 300 nm
predominately ceria
√ √ Limited
Films investigated
Slurry Description
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Polish rate (K P v) Comparison- Silica Slurries(11)
0
1000
2000
3000
4000
5000
6000
0 20 40 60 80 100
SS121508-50 pH 10.81498-50 pH 7.0
Polis
h ra
te (Å
min
-1)
P*v (kPa m s-1)
PR = K P v K = 72.1, R2 = 0.8891K = 64.1, R2 = 0.9626
K = 51.9, R2 = 0.9790
Thermal Oxide
Polish Rate - Silica Slurries Variable pH(11)
0
1000
2000
3000
4000
5000
0 20 40 60 80 100
1498-50 pH 7.01498-50 pH 10.01498-50 pH 5.51498-50 pH 2.5
Polis
h ra
te (Å
min
-1)
P*v (kPa m s-1)
PR = K P v
K = 51.9, R2 = 0.9790K = 55.6, R2 = 0.9701
K = 46.8, R2 = 0.9792
K = 50.6, R2 = 0.9156
Thermal Oxide
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Silica and Ceria Slurries(11)
0
1000
2000
3000
4000
5000
6000
7000
8000
0 20 40 60 80 100
ThOx SS12ThOx STS1000DVVTR TEOS SS12PECVD TEOS SS12
Polis
h ra
te (Å
min
-1)
P*v (kPa m s-1)
K = 72.1, R2 = 0.8891
K = 61.8, R2 = 0.8738K = 66.5, R2 = 0.8985
K = 88.9, R2 = 0.9353
IV-67
BPSG with Silica Slurry(11)
0
2000
4000
6000
8000
10000
12000
14000
16000
0 20 40 60 80 100
0/00/55/55/02.5/2.5
Polis
h ra
te (Å
min
-1)
P*v (kPa m s-1)
K = 167.2, R2 = 0.8817
K = 156.8, R2 = 0.9207K = 165.6, R2 = 0.8973
K = 261.0, R2 = 0.6563
K = 99.5, R2 = 0.9373
IV-68
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HDP Oxide with Ceria Slurry(11)
0
1000
2000
3000
4000
5000
6000
0 20 40 60 80 100
1.4551.4791.5141.562
Polis
h ra
te (Å
min
-1)
P*v (kPa m s-1)
K = 29.9, R2 = 0.3842
K = 7.2, R2 = n/aK = 8.4, R2 = n/a
K = 77.3, R2 = 0.4920
R2 Fit - All Models(11)
Preston Zhang, et al Tseng, et al Shih, et alK*P*v K*(P*v)1/2 K*P5/6*v1/2 K*P2/3*v
SS12 ThOx 0.8891 0.7549 0.9299 0.78501508-50 ThOx 0.9629 0.8146 0.9454 0.90741498-50 ThOx 0.9790 0.7896 0.9165 0.9192
1498-50 pH 10.0 ThOx 0.9701 0.8119 0.9386 0.91531498-50 pH 5.5 ThOx 0.9792 0.7925 0.9217 0.91851498-50 pH 2.5 ThOx 0.9156 0.8647 0.9529 0.9168
STS1000DV ThOx 0.8738 0.8179 0.9410 0.8356SS12 VTR TEOS 0.8985 0.7567 0.9326 0.7832SS12 PECVD TEOS 0.9353 0.7583 0.9211 0.8338SS12 0/0 BPSG 0.9373 0.7547 0.9123 0.8370SS12 0/5 BPSG 0.9207 0.7656 0.9323 0.8180SS12 5/5 BPSG 0.6563 0.6534 0.9002 0.4167SS12 5/0 BPSG 0.8973 0.7330 0.9235 0.7159SS12 2.5/2.5 BPSG 0.8817 0.7220 0.9221 0.6916
STS1000DV HDP n=1.455 0.4920 0.6649 0.7090 0.5550STS1000DV HDP n=1.479 0.3842 0.5321 0.4929 0.5071STS1000DV HDP n=1.514 0.2367 0.1039
Slurry Film
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ANOVA - All Models(11)
Anova: Single Factor α=0.05
SUMMARYGroups Count Sum Average VarianceK*P*v 16 13.57 0.85 0.03
K*(P*v)1/2 18 12.35 0.69 0.04K*P5/6*v1/2 18 14.69 0.82 0.06K*P2/3*v 16 12.36 0.77 0.02
ANOVASource of Variation SS df MS F P-value F crit
Between Groups 0.26 3 0.09 2.20 0.10 2.75Within Groups 2.50 64 0.04
Total 2.76 67
ANOVA - All Models(11) (HDP Excluded)
Anova: Single Factor α=0.05
SUMMARYGroups Count Sum Average VarianceK*P*v 14 12.70 0.91 0.01
K*(P*v)1/2 14 10.79 0.77 0.00K*P5/6*v1/2 14 12.99 0.93 0.00K*P2/3*v 14 11.29 0.81 0.02
ANOVASource of Variation SS df MS F P-value F crit
Between Groups 0.24 3 0.08 11.83 0.00 2.78Within Groups 0.36 52 0.01
Total 0.60 55
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Analysis of Pressure Threshold - Experimental(11)
0
1000
2000
3000
4000
5000
6000
0 5 10 15 20 25
PECVD TEOS SS12ThOx STS1000DV
Polis
h ra
te (Å
min
-1)
P2/3 * v (kPa2/3 m s-1)
3 psi30 rpm
1.5 psi90 rpm
10
100
1000
10000
0 5 10 15 20 25
PECVD TEOS SS12ThOx STS1000DV
Polis
h ra
te (Å
min
-1)
P2/3 * v (kPa2/3 m s-1)
3 psi30 rpm
1.5 psi90 rpm
Analysis of Pressure Threshold - Experimental(11)
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Conclusions From Oxide Models(11)
All models with predicting equationsare based on Hertzian indentationignore slurry and particle chemistry
Performance of each model studied R2 term was good for some but not all process conditionsR2 KPv and KP5/6v1/2 best when ceria and high [Si] HDP oxide removed from analysisPressure threshold model did not agree with experimental polish results
Simplicity of models studied indicates extensive work still needs to be done
Selected Bibliography for CMP Oxide Models
1. F. Preston, J. Soc. Glass Tech. 11, 1927, 214.2. N. J. Brown, P. C. Baker, and R. T. Maney, SPIE 306 Contemporary
Methods of Optical Fabrication, 1981, 42.3. L. M. Cook, J. Non-Cryst. Solids 120, 1990, 152.4. F. Zhang and A. Busnaina, Electrochem. Solid-state Lett. 1 (4), 1998, 184.5. D. Maugis and H. M. Pollock, Acta Matall. 32, 1984, 1323.6. S. R. Runnels and L. M. Eyman, J. Electrochem. Soc. 141 (6), 1994, 1698.7. W-T. Tseng, C-W Liu, B-T. Dai, and C-F Yeh, Thin Solid Films 290-291,
1996, 458.8. F. G. Shi and B. Zhao, Appl, Phys. A 67, 1998, 2499. B. Zhao and F. G. Shi, 1998 IEDM, 341.10. B. Zhao and F. G. Shi, 1999 CMP-MIC, 13.11. D. J. Stein, D. L. Hetherington, ECS Third International Symposium on
Chemical Polishing in IC Device Manufacturing, October 17-22, 1999, Honolulu, Hawaii.
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Appendix II: Polishing Motions
Kinematics of the relative velocity of a point on the wafer with respect to the polishing pad.
Rotary - Relative Velocity of Point on Wafer
The linear velocity of a arbitrary point Q on the wafer in the coordinate frame of the platen P is derived*:
*W. J. Patrick, et al., J. Electrochem. Soc., Vol. 138, No. 6, June (1991).
Platen/P
Wafer/H
•Q rq
rp
ωc ωp
rc
cpq rrrrrr
+=
)]([)()()( pccppccqpHQPCPQ xrrxrxrxVVV ωωωωω −−−=+−=+= ′
rrrrrrr
C’
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Linear - Relative Velocity of Point on Wafer
Wafer/H
•Qrc
ωc
VB
)( ccBHQBBQ rxVVVVrrrrr
ω+=+=
The linear velocity of a arbitrary point Q on the wafer in the coordinate frame of the platen B:
Platen/B
Orbital - Relative Velocity of Point on Wafer
The linear velocity of a arbitrary point Q on the wafer in the coordinate frame of the platen O:
)()(' ccooHQOCOQ rxrxVVVrrrrr
ωω −=+=
Wafer/H
• Q
ωc
rc
Orbital Motion
ro
ωo
C’
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About Sandia
Sandia National Laboratories is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000