MSJ-1

Alignment Network

MSJ-2

Alignment Network

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ALU32

32

general purpose registers

32 bits

memory width − a.k.a., block size(8 bytes, in this example)

main memory

‘a’‘a’

For this discussion, let’s assume our CPU is a 32 bit CPU; so the general purpose registers are 32 bits and the inputs to the ALU are 32 bits

CPU

Let’s further assume a main memory that is 8 bytes wide ‒ i.e., it has a block size of 8

• The significance of the block size is that a block is the quantum of output from the memory ‒ all output from the main memory is 8 bytes

• Even if the CPU only wants a single byte, what will leave main memory is a block

First, the entire block must come out of the memory

Then the correct byte must be extracted

Then it has to be right shifted by the correct amount so that it winds up right justified in the destination register, R[4], so that addition will work properly ‒ otherwise ‘a’+1 will not come out equal to ‘b’

Suppose the CPU wants to load a single byte into some general purpose register, let’s say R[4] …

1

… so that it can add 1 to an ASCII code to get the ASCII code for the next character

alignmentnetwork

• The functional unit that does the extraction and shifting is called the alignment network

• It sits between the CPU and the memory

MSJ-3

The Reality is Slightly More Complicated (But Only Slightly)

CPU

alignmentnetwork

cache

main memory

In reality, the alignment network is between cache and the CPU

• But collectively, the cache and the main memory are often referred to as the memory hierarchy

• So it is correct to say that the alignment network sits between the memory hierarchy and the CPU and mediates all transfers between the twomemory

hierarchy