Moore’s Law is Unconstitutionalvlsi2005/keynotes/walden_rhines.pdf · WCR, Moore's Law is Unconstitutional, January 2005 3 Moore’s Law The Number of Transistors QDoubles every

Moore’s Law is Unconstitutional

Walden C. RhinesCHAIRMAN & CEO

WCR, Moore's Law is Unconstitutional, January 20052

Moore’s Law

Source: Intel, Intel Developers Forum, 2/2003


Moore’s LawThe Number of Transistors

Doubles every year ~ April 1965Doubles every 2 years ~ December 1975Doubles every 18 months ~ May 1997

“… In about a decade, were going to see a distinct slowing … it might be half as fast” ~ May 1997“We’re starting to shrink chips less rapidly than we have done in the past” ~ July 2002“The fact that we have been able to accelerate it by a third just amazes me” ~ Nov 2002“Moore’s Law good for another decade” May 2003


Moore’s “Law” – An Empirical ObservationLaws Empirical Observations

• Newton’s Laws of Motion

• Laws of Thermodynamics

• The Code of Hammurabi

• Stock market prices and women’s dress lengths rise and fall together

• Ratio of I/O pins to logic gates is constant ~ 1.5 *

• Revenue per unit area of silicon is a constant

Note: * Rents Law k = I / (C)0.5


“No Exponential is Forever” Physical Limits of Scaling

1999 ~ 1000 electrons available to switch a transistor2003 ~ 20 atoms in the smallest layer of a Pentium chip2010 ~ 8 electrons available to switch a transistor2020 ~ < 1 electron available to switch a transistor

Quantum collapse ~ 5 atoms

Source: California Computer News, 2003 & Physics Today, January 2000, “No Exponential is Forever” Gordon Moore, June 2003


So Why Has Moore’s Law Been A Useful Approximation for 40 Years?

Based upon a basic “Law” of nature – The Learning CurveMoore’s Law is a special case of the learning curve when two things are true:1. Cumulative transistors produced

increase exponentially with time(e.g. 2x cum volume => fixed % cost decrease)

2. Almost all cost reduction comes from shrinking feature sizes (and growing wafer diameter)


Learning CurvesCost per unit decreases by a fixed percent every time total cumulative volume doubles

Applies to all products (over centuries) when measured in constant currency

Used to predict future costs— Aircraft industry— Semiconductor industry

Also true for subsystem or component costs and improvements in reliability, quality, yield, etc.


Integrated Circuit Learning Curve

$1.00

$10.00

$100.00

1 10 100 1000Industry Total Accumulated Volume ( million units )

Pric

e pe

r uni

t ( $

Con

stan

t )

Source: Boston Consulting Group

8


0.0001

0.001

0.01

0.1

1

10

100

1 10 100 1,000 10,000 100,000 1,000,000 10,000,000

Cumulative Bit Volume (Bits x 10 12 )

DRAM Price Learning Curve

1978 19791980

19811982

19841983

1985

19871986

1988 19891990

19911992

1993

1994

1995

1997

1996

19991998

2001

2000

20022003

Excess Capacity Price Erosion

Strong DemandWeak Supply

Excess Capacity Price Erosion

Source: ICE Status 1998 & 2003 McClean Report IC Insights


Personal Computer Learning CurvePersonal Computer 2003 Cost per Mips

0.0

0.1

1.0

10.0

100.0

1,000.0

10,000.0

100,000.0

10,000 100,000 1,000,000 10,000,000Cumulative Unit Shipments (thousands of units)

2003 Cost/Mips

Source: Hans Moravec, Carnegie Mellon University & Woodrow Federal Reserve Bank & Dataquest “The Billionth PC Ships” 6/02


Japanese Beer

$10.00

$100.00

1000 10000 100000Industry Total Accumulated Volume ( million tons )

$0.20

$0.50

1951 1960 1968

Source: Mentor Graphics

11


1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

1.E+12

1.E+13

1.E+14

1.E+15

1.E+16

1.E+17

1.E+18

1954

1956

1958

1960

1962

1964

1966

1968

1970

1972

1974

1976

1978

1980

1982

1984

1986

1988

1990

1992

1994

1996

1998

2000

Transistors Shipped/Year vs Semiconductor Revenue

Transistors/Year

Semiconductor Revenue/Year

Source: Semiconductor Industry Association

Non-Linearity of Growth in Transistor Consumption Led to Moore’s Law Adjustments


Reduction in Cost per Function WillContinue Forever…

Semiconductor Learning Curve

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

1.00E+01

1.00E+02

1.00E+03

1.00E+00 1.00E+02 1.00E+04 1.00E+06 1.00E+08 1.00E+10 1.00E+12 1.00E+14 1.00E+16 1.00E+18 1.00E+20

Cummulative Transistors Shipped

Semiconductor Learning Curve1959 – 2000 … Adjusted for Inflation

Source: Mentor Graphics, SIA, Woodrow Federal Reserve Bank


Methods for Achieving the Cost Reduction Will Change

Changes in system design and component packaging & assemblyFixed costs of design, verification, software and toolingPower and performance constraints on cost reductionManufacturing methods

— Test— Design-for-manufacturability






Innovative Assembly & Packaging of Multiple Chips Will Drive Lowest Cost

Source: Amkor Technology


Changing Printed Circuit Board Technology Is Handling More of the Complexity Burden

Des

ign

Com

plex

ity

10+GigaBit10+GigaBit

MicroViasMicroVias

Embedded Actives & Passives

Embedded Actives & Passives

Multiple 1500+ Pin

FPGAs

Multiple 1500+ Pin

FPGAsGlobal Team

Design

Global Team

Design

1990 2000 2010






The $30M System-on-Chip (SoC)

CPUCore

Original HardwareContent

OriginalSoftwareContent

Glue Logic

BlueToothController

IR &RS232

Compression& Encryption

Engine

DSPCore

Composite SoC

Design costs $15 - $50 MVerification is 50-70% of effort$1M+ Tooling cost


Big Design Cost Requires Big MarketsR&D Spending $30MR&D as % of Revenue 20%

Revenue $150M

R&D Spending $30MR&D as % of Revenue 20%

Revenue $150MMarket Share 10%

Resulting Market $1.5B


Photomask Costs Are Increasing

$102$167

$310

$985

$62826 2830 32 34

$-

$100

$200

$300

$400

$500

$600

$700

$800

$900

$1,000

0.35m 0.25m 0.18m 0.13m 0.09m

Process

($T

hous

ands

)

05101520253035404550

Tota

l Mas

k La

yers

Mask Set Cost Mask Layers

Source: IC Insights, 1/2003


Software Development a Growing Part of System Design

0

10

20

30

40

50

60

.35 micron .25 micron .18 micron .13 micron 90 nm

Des

ign

Cos

t ($M

illio

n)

Hardware Design Cost Software Design Cost

2 Million Logic Transistors





Source: IBS, Analysis of the Relationship Between EDA Expenditures and Competitive Positioning of IC Vendors


System Design Attention ShiftsFrom Hardware to Software


SoC Design Requires Integration of Disparate Parts


Verification Is the Largest Part of the SoC Design EffortBreakdown of Design Teams by Main Function

Source: 2002 IC/ASIC Functional Verification Study, Collett International Research, Used with Permission

Verification & Test46%

Other6% Software

14%

Design34%

Verification 47%

Design53%


IP Re-use Doesn’t Necessarily ReduceVerification Requirements

IP DominantIP Dominant

IP selection, evaluation, integration

Early assessment performance and power

Trade-off hardware vs. FPGA vs. software

Single algorithm, many hardware architectures


Idealized Design CycleStart

FCS

Software

SystemSystemLevel DesignLevel Design

ImplementationPhase

RTL BoundaryPhysical Verification

HardwareImplementation

HardwareSpecification

HardwarePrototype

CodeFreeze

SoftwareSpecification

IntegrationAnd Test

SoftwareImplementation

Hardware


Typical Design Cycle

SystemLevel Design

RTL BoundarySoftw

are

HardwareSpecification

HardwarePrototype

CodeFreeze

SoftwareSpecification

SoftwareImplementation

BeginsHardware

TimingTimingClosureClosure

I&TI&T


System Design Exploration and Optimization Require ESL and C-Based Tools

PlatformBased Design

~1 MHzTransaction

LevelModeling

PerformanceOptimization

~ 100 KHzHardware/Software

Co-Verification

~ 1 HzC-based

Simulation

C-basedSynthesis


TYPICAL RTL DESIGN FLOW C DESIGN FLOW

Floating PointModel

Fixed PointModel

Micro-architectureDefinition

RTLDesign

RTL Area/TimingOptimization

RTLSynthesis

Place & Route

HardwareASIC/FPGA

HardwareASIC/FPGA

Place & Route

RTLSynthesis

Fixed PointC++ Model

Floating PointModel

Catapult CSynthesisConstraints

Logic Analyzer

++

LogicAnalyzer

ASIC or FPGAVendor

Algorithm Functional Description

Algorithm Functional Description

Replaces manual RTL creation with automationConnects system domain to hardware designSingle source for ASIC or FPGAUp to 20X reduction in RTL creation

Reducing Design Time with C Synthesis

ManualMethods

MATLAB

C/C++

Precision RTLor DC

Syst

em D

esig

ner

Har

dwar

e D

esig

ner

Vend

or


Raising the Level of Abstraction for Design

Performancedriven HWR

3G ENGINE

BlueTooth Controller

IR &RS232

Compression& Encryption

Engine

CPUCore

DSPCore

RTOSBlueTooth Driver

Comp/Enc DriverIR/RS232 Driver FPGA

FunctionalDifferentiation

SoftwareRTL

IP Blocks & Buses

Gate

Transistor


Platforms Enable the Rapid System Evolution of SoC Design

Customer demands— Fast turn-around time— Easy access to pre-qualified

building blocks— Web enabled

Design technology— Core platforms— ‘Big’ IP— Emerging SoC bus standards— Embedded software— HW/SW co-verification

Far Peripherals

Near Peripherals

Core


And Automation of IP Selection & Integration


A Major Shift in System/SoC DesignIP & Platform Creation

5,000+Designers

100,000+Designers


Field Programmable Logic Will Continue to Gain Share of Designs …

0

5,000

10,000

15,000

20,000

25,000

30,000

1995 1996 1997 1998 1999 2000 2001 2002 2003

# of D

esig

n St

arts

ASIC COT PLDs >100K

Source: Dataquest, ASIC/SOC: “Rebuilding After the Storm”, 11/19/02


… And FPGA Design Complexity Will Approach the Complexity of ASICs

High-End FPGA/FPSoC- IP integration- Complex timing- HW/SW design- Complex debug- Prototyping- SDC constraints- C-based design- Physical timing problems- PCB integration issues- Team design

Mainstream FPGA/PLDs

-Simulate/Debug-Synthesize

-Place/Route

Low cost toolsPush button flow

Sophisticated tools ASIC-like flow


ASIC Methodologies Must Change to Reduce Fixed Cost

Structured or platform ASICs?Embedded FPGA’s in standard products and vice versaRicher design reuse librariesE-Beam direct slice writingChange the ASIC methodology…






Increasing Frequency and Leakage Create Power Density Problems

Source: “Circuit, Platform Design and Test Challenges in Technologies Beyond 90nm”, Grundmanm, Galivanch, DATE 2003











Power-Aware Design Requires Design Changes at All Levels

Architectural level— Clock speeds of computational elements (CPUs, DSPs)— Frequency of buses— Memory access - optimized caches and tightly coupled memories— Static vs. dynamic design

Device/interconnect level— Reduce capacitance of interconnects— Reduce operating voltage— Reduce size of transistors— Reduce hot spots via analysis

Process level— Reduce static current drain

High K dielectricsSelective oxide thicknessBack Bias? Oxide isolation?


Power Aware Design Starts With Hardware/Software Partitioning Tradeoffs

Synthesize power hungry software functions into hardware— Slowing the CPU clock saves milliwatts— New hardware blocks add microwatts

Equivalent Function in HardwareEmbedded Code


SoC Verification, Integration, SynthesisVe

rific

atio

nIn

tegr

atio

nSy

nthe

sis

ALGORITHM-C/C++

COMPILATION SYNTHESIS

AAP

OS

HARDWARE DEBUG

PERIPHERAL

SOFTWARE DEBUG

PERFORMANCE ANALYSIS


Power Optimization Example

Gaussian calc.

FFT

Hamming window

Fixed pt divider

48.0 mW

Watt WatcherPower Est

12.3 mW

11.1 mW

0.4 mW

0.4%

0.3%

4.7%

2.1%

TimeActive

0.19 mW

0.04 mW

0.52 mW

0.01 mW

HW powerEst

Total power consumed 0.76 mW

CPU 0.57 mW 32 MHz

43.89 mWSW only algorithms (0.57 mW x 77MHz) =

Function converted to hardware

18.24 mW

19.00 mWCustom Hardware + CPU =Project Goal 25 mW


Battery Driven Power Management

llc_mem

fcs_memfcs_comp

wep_memwep_initwep_compicv_mem

pli_mem

icv_comp

0

50

100

150

200

250

300

0 20 40 60 80

time (ms)

Cu

rre

nt

(mA

)

Ex. T

race

s

Current Profile

Original profile

Ex. T

race

s

Current Profile

0

50

100

150

200

250

300

0 20 40 60 80 100 120

time (ms)

Cu

rren

t (m

A)

llc_mem

fcs_memfcs_comp

wep_memwep_initwep_compicv_mem

pli_mem

icv_comp

Rated Ct.

OptimizedProfile

Rated Ct.

New “Battery Driven” Power Management Customizes Current Discharge Profile

Traditionally power management has targeted reduction of average power / total energy

For battery powered systems:

— Minimizing average power ≠ maximizing battery life

— Power management needs to shape the power profile










Test Complexity Has Been Offsetting Cost Reduction

Source: IC Knowledge, 2004


New Failure Modes Require New Failure Models

EE Times Article: Failures plague 130-nanometer IC processes, By Ron Wilson, August 27, 2002

Transition FaultsBridging FaultsOther Models


At-Speed Testing Will IncreaseStuck-at-test alone is no longer sufficient

— Defects uniquely detected by “at-speed” tests increase 12X - 20X from .18 micron to .13 micron

Source: Nvidia, Fabless Forum March 2003


Compression of Test Patterns Will Make Increased Test Possible at Reduced Cost

““stuckstuck--atat””

““atat--speedspeed””

compressedtest

EmbeddedTest

Compression

Requires 3X-5X pattern volume10X-100X pattern compression and tester throughput






Lithography Costs Are Increasing Faster Than Wafer Throughput


Resolution Enhancement Technology Will Increase Lithography Equipment Lifetime


What You Design Is Not What’s Printed on the Photomask

Layout Result on Silicon Wafer

WithoutOPC

WithOPC


Resolution Enhancement Requires Optical Modeling


At 250nm RET was for Yield Enhancement

Target No RET


At 250nm RET was for Yield Enhancement

Target With RET


At 130 nm RET Began to be About Yield Creation

Target No RET


At 130 nm RET Began to be About Yield Creation

Target With RET


At 90nm There is No Yield Without RET

No RETTarget



Target – Poly OPC Silicon Simulation - Poly



No RETTarget



With RETTarget


Growing Importance of RET

250 nm 180 nm 130 nm 90 nm1

35

Incr

easi

ng N

umbe

r of C

hip

Laye

rs W

ith R

ET

13• OPC

• 248nm Scanner

• OPC• Attenuated PSM• Annular Illumination• 248nm Scanner

• OPC• Attenuated PSM• Annular Illumination• Quadrapole/Quasar Illumination

• 248/193nm Scanner

• OPC• Attenuated PSM• Annular Illumination• Quadrapole/Quasar

Illumination• 248/193nm Scanner

65 nm

28

• OPC• Attenuated PSM• Annular Illumination• Quadrapole/Quasar

Illumination•Double Exposure• 248/193nm Scanner


Manufacturing Yield is Becoming a Design Problem

IC Generation (µ)Source: PDF Solutions/Solida State Technology


And Designers Need to Help- Design-for-Manufacturability -

DRC Rules– Check design

compliance with process rules

DFM Guidelines– Define the optimal layout

for highest yield– Must be implemented in

RET-aware environment


Evaluation of Designs For Manufacturability Requires Statistical Analysis of the Design

Software highlights an area that is a potential problemVisualize the appearance ofcircuit in siliconCalculate metrics based onevaluation of DFM rules

# of transistors involved% of transistors that can be fixed

Make suggestions of possible fixes

Overlay Statistical Color MapsPinpoint specific problems

Via Check Adequate spacing todouble 45% of single via instances.

Display locations

Make global change

Find first instance

Defect density at 85%


Integration of Physical Verification and Test Will Enhance Debug and Yield

Improvement

Logic view

AA

Layout view

C

B

D

E

Possible bridging sites


Physical Yield Analysis Will Connect Design With Statistical Physical Layout Analysis

99.97%

99.97%

99.97%

99.97%

99.98%

99.98%

99.98%

99.98%

99.98%

99.99%

99.99%

99.99%

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4Min Space M1

Act

ual Y

ield

CompressedNet Yield

Diagnostics

Defect Type Pareto

poly1/poly1 bridge

metal2/metal2 bridge

metal1/metal2 via open

poly1/p-well bridge

metal1/metal2 via res.

poly1/n-well bridge

open contact

metal1 open

metal2/gnd bridge

metal2 open

Unit # mm mm mm # %

Single Vias

Length M1

Length M2

Min Space

M1

Min Space M1-45

N348342 2 3.72992 1.29073 0.70642 3 99.979%N723000 5 2.41953 2.13749 0.55512 3 99.979%N722774 4 4.54991 1.95610 0.52412 3 99.977%N868686 2 4.81466 1.90007 0.26846 2 99.981%N906825 3 0.82530 1.95039 0.44865 3 99.984%N430501 2 0.24455 2.05877 0.72941 2 99.985%N306671 2 3.05894 2.20033 0.25910 2 99.985%N960836 3 3.19550 2.00096 0.24427 3 99.983%N631146 2 3.50581 1.57913 0.48508 4 99.980%N899470 4 1.33828 2.59918 0.39739 4 99.979%N001955 2 4.36102 1.68437 0.41973 2 99.978%N022249 2 4.39427 1.62443 0.66852 2 99.981%N309851 3 2.48415 2.88285 0.72739 2 99.978%

Actual Yield

Open Mechanisms Bridging Mechs

NetName

Net LevelDesign Feature toYield Correlation

Design Featureand Volume

Test Data Extract

Net FeatureExtraction

StatisticsdBGDSII

Feature TargetedCompressed ATPG

DefectRules


DFM Design Guidelines Feature AnalysisCombine rule priority and degree of severity with statistical occurrence information by region or cell Identify layout features

— Polygon, edge, edge clustersPresent statistics of occurrence

— Whole Chip— By Area— By Cell— Single feature or multi-feature— Equations Regions of High Occurrence

of Low Yielding Feature


Grayscale Analysis of DFM Guidelines

MinimumDesign Rule

Optimal DFMDesign Rule

Priority Fixes

Determine “grayscale” of adherence to recommended and guideline rulesPresent statistics

— Whole Chip— By Area— By Cell

Visualization with viewer— By rule priority— Histograms— Color Maps


Feed Forward Process ModelingProcess Models

Litho Etch

CMP

Overlay

Identify weak post-RET regions

Probability to failure report

Probability of failure ranking

Best

Worst

12% Underdose 8% Underdose 4% Underdose

Silicon Validation


The Cost per Function Will Continue to Decline Long After Moore’s Law is Obsolete

Vacuum-Tube1941 - 1955

2003 Cost/MIPs

1.000E-021.000E-011.000E+001.000E+011.000E+021.000E+031.000E+041.000E+051.000E+061.000E+071.000E+081.000E+091.000E+101.000E+111.000E+121.000E+13

1940 1950 1960 1970 1980 1990 2000 2010

Discrete Transistor1955 - 1966

Integrated Circuit1966 - Today


Documents

Moore’s Law is Unconstitutionalvlsi2005/keynotes/walden_rhines.pdf · WCR, Moore's Law is Unconstitutional, January 2005 3 Moore’s Law The Number of Transistors QDoubles every