Monte carlo simulation

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Monte Carlo Simulation

in Statistical Design Kit

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Monte Carlo simulation in statistical design kit

1. Monte Carlo Simulation

2. Practical demonstration in Cadence

3. Simulation and Measurement

Overview

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... allows the random variation of

- process parameters

- mismatch parameters

- process & mismatch parameters


Monte Carlo Simulation

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Wafer production will always show some variation of techno- logical parameters

The MC process simulation is the adequate tool to give an early estimation how it will affect the circuits function.


Monte Carlo process simulation

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For each simulation run a new random set of process parameters is generated and is valid for all active and passive components in the circuit


Monte Carlo process simulation

...dw_rpyhl_skewrcs_rpyhl_skewrsh_rpyhl_skewa_wc_skew_nsica_be0_skew_nsicr_nsu_skew_nsicr_nbl_skew_nsicr_ncx_skew_nsicr_nci_skew_nsicr_wb_skew_nsicr_jbei_skew_nsicr_nbei_skew_nsic ...

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Even optimum layoutcannot completely avoid mismatch between components.

The MC mismatch analysis gives insight in the effect of these slight variations.


Monte Carlo mismatch simulation

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For each device an individual mismatch random variable is generated and is valid only for a single run.

The mismatch property can be set globally or for selected devices only.


Monte Carlo mismatch simulation

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In addition to the global random process parameter set each device gets an individual mismatch random variable.

This combined simulation will give an estimation of a real wafer fabrication


Monte Carlo process & mismatch

simulation

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Monte Carlo Tool

Demonstration


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Testbench

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Operational Amplifier V1

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Opamp V1 Mismatch and Process Variation

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Sweep of Process Parameter Model Setup

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Sweep of Process Parameter Model Setup

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Variation of Process Parameter with Corner Tool

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Variation of

Process

Parameter

with

Corner

Tool

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Sweep of Process Parameter

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Opamp V1 Mismatch and Process Variation

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Circuit optimisation

Step 1:

Add base current compensation

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Circuit optimisation Step 1

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Step 2:

Add buffer stage

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Step 3:

Adjust bias current andadd cascode stage

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Improvement in DC-Offset

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DC-Offset N = 1000 simulation runs

Simulation

MM Proc MM&Proc

before optimisation 3.82 22.77 24.94mV

after optimisation 1.16 0.09 1.16mV


Overview

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- Run sensitivity analysis

- MC Simulation with individual mismatch enable

- Perform correlation check after process simulation in Monte Carlo Tool

- sweep of single process parameters


Identify critical components and

process parameters

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Wide spread at Mismatch Simulation:

-> Increase area factor of critical components

Wide spread at Process Simulation:

-> Check circuit topology

e.g.: - add base current compensation - add cascode or buffer stage


Rules of thumb for Design

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Simulation and

Measurement


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Circuit Topology

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First approach to

DC-Offset

compensation

with dummy stage

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First silicon of a test circuit did show a wide spreading of DC offsets especially in high gain mode.

The yield was unacceptable low :

DC offset voltages Specification: +/- 20mV First silicon : ~ 40mV (1-sigma)


Results from first Silicon

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Typical DC Offset Distribution (Wafer probing)

1-Sigma 38.7mV


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Resimulation: Mismatch & Process Variation

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Evaluation of the circuit without statistical models is possible - but takes a lot of time.

Monte Carlo Analysis with new statistical design kit provides a fast insight in the circuits behaviour at mismatch and process variation.

The conformity of measurement and simulation is rather good


Redesign

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- enlarge area factor at critical elements

- add base current compensation

- decrease current of differential amplifier to limit influence of beta variation

- limit influence of early effect by cascode stages and dummy amps

- revise the complete channel topology and gain chain (omit dummy OP stage)


Circuit improvements

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Redesign

without

dummy stage

but

OP design

improved

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New Design: Mismatch & Process Variation

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DC Offset @ Opamp output (300 simulation runs)

Simulation Measurement

MM Proc MM&Proc Wafer

First Design 13.6 32.9 32.9mV 38.7mV

New Design 6.3 0.8 5.9mV ?


Overview

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More Information

[1] Kraus, W. : PCM- and Physics-Based Statistical BJT

Modeling Using HICUM and TRADICA,

6th HICUM Workshop, 2006

[2] Schröter, M., Wittkopf, H., Kraus, W. : Statistical

modeling of high-frequency bipolar transistors,

Proc. BCTM, pp 54 - 61, 2005

Documents

Monte carlo simulation