module ALU(in1,in2,select,out);

input [3:0] in1,in2;

input select;

output[3:0] out;

reg [3:0] out;

always @ (in1,in2,select)

begin

if(select==0) out=in1+in2;

end

endmodule

module ALU(in1,in2,out);

input [3:0] in1,in2;

output [3:0] out;

reg [3:0] out;

always @ (in1,in2)

begin

out=in1*in2;

end

endmodule

module Register(in,clock,out);

input [3:0] in;

input clock;

output[3:0] out;

always@(posedge clock)

begin

out=in;

end

endmodule

module MUX(in1,in2,select,out);

input select;

output[3:0] out ;

input [3:0] in1,in2;

always @(in1,in2,select)

begin

case(select)

0: out=in1;

1: out=in2;

end

endmodule

module FSM(clk, reset,out1,in1,in2);

input clk,reset,in1,in2

output out1;

reg out1;

reg [1:0] state;

reg [1:0] nextstate;

parameter S0 = 0;

parameter S1 = 1;

parameter S2 = 2;

parameter S3 = 3;

// State Register

always @(negedge clk or negedge reset)

if (reset == 0) state <= S0;

else state <= nextstate;

// Next State Logic

always @(state,in1,in2)

case (state)

S0:

begin

nextstate = S1;

end

S1:

begin

nextstate <= S2;

end

S2:

begin

nextstate <= S3;

end

S3:

begin

nextstate <=S0;

end

default: nextstate <= S0;

endcase

endmodule