MODERN ENIAC WP2 Meeting

Project Review MeetingCatania, Nov.09-10, 2010

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MODERN ENIAC WP2 Meeting

WP2 Tasks review summary

Catania, 2010 Nov. 09-10

Contents• WP2

• Task 2.1 to 2.5 summary

• Matrix, Gantt chart, relation with other Wps

• Action points from meeting

Project Review MeetingCatania, Nov 09-10, 2010

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3 MODERN General

MeetingsCatania, Nov. 9 & 10, 2010

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WP2: Relationship among work packages


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WP2 Objectives• Objectives • Provide a chain of TCAD simulations tools which enable

simulation of the impact of process variations and reliability on device level, including compact models and mixed mode device/circuit simulation

• Assess the impact of process and device variations for relevant technologies, mainstream planar bulk CMOS down to 45/32nm, new device architectures on bulk & on SOI suitable for 22nm, NVM technologies, and non-silicon technologies

• Compare simulation results with hardware and calibrate them on hardware to verify PV methodology and to foster physical understanding of major sources of PV in above technologies

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WP2 Key Figures• 5 Tasks/18 deliverables (reports):

– Process (2) & device (6) simulation– Electrical characterization (4) & Reliability(3)– Compact modeling (3)– Covering both Tools/Methodology improvements and Application results

• Wide spectrum of technologies & devices applications– 45nm: planar Mosfet– 32nm: planar Mosfet, FinFet– 22nm: FD SOI Mosfet– State-of-art NVM – Discrete Power Device, SiC, GaN/AlGaN– HV CMOS

• TOTAL EFFORT: 638.6 PM =53.22 PY

• Reference: MODERN Rev2.1.7 project description


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WP2 meetingDomain overview per task and partner

MODERN General MeetingsCatania, Nov. 9 & 10, 2010

Technologies

Process simulation

Device simulation

Electrical Charact.

Reliability Compact Modeling

Task 2.1 2.2 2.3 2.4 2.5

HVMOS AMS TUW AMS TUW AMS TUW

Planar CMOS 65nm UNCA

45nm UNGL POLI SNPS (STF2)

IMEP STF2 UNGL UNGL POLI STF2 NXP

32nm UNGL POLI (STF2)

IMEP STF2 UNGL

NVM 41nm UNET NMX SNPS

UNET NMX UNET (NMX) UNET NMX

FDSOI IMEP (STF2) LETI IMEP LETI

Finfets, MUG, GAA

STF2 NXP IMEP

SiC Power MOS

STI STI STI

AlGaN-GaN HEMT

STI STI STI

PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of technologies (Project book rev2 v2.4.1).

Significant communalities of technology targets, except different ones for Process and Device simulation.

(not funded)

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WP2 Task Definition and Contributors

WP2 Process/Device to Compact Modeling Contributors

T2.1 PV aware process simulation ST-I, AMS, TUW

T2.2 PV aware device simulationUNGL, IMEP, UNET, NMX, POLI, STF2, ST-I, SNPS

T2.3Electrical characterization of PV, software (TCAD) / hardware comparison & calibration

NXP, AMS, IMEP, UNET, LETI, NMX, STF2, ST-I

T2.4Correlation between PV and reliability, reliability modeling

AMS, IMEP, UNET, TUW, UNCA, UNGL

T2.5 PV aware compact modelingUNET, AMS, LETI, NMX, NXP, POLI, STF2, ST-I, UNG


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WP2 Task Leaders

WP2 STF2 [email protected]

T2.1 ST-I [email protected]

T2.2 UNGL [email protected]

T2.3 NXP [email protected]

T2.4 AMS [email protected]

T2.5 UNET [email protected]

Contents• WP2 introduction





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MODERN General MeetingTask 2.1 summary

Catania, Nov. 9-10 2010

Project Review Meeting Catania, Nov. 9-10, 2010

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Process simulation: T2.1 Deliverables

Ref Deliverable/ Contributors Due date

D2.1.1 First process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools

(ST-I, AMS, TUW)

M15

Done

D2.1.2 Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools

(ST-I, AMS, TUW)

M27

Task Leader: [email protected]

12 MODERN General


ST-I WP2 Activity

High Level factory

Process recipes

Specific process

conditions

Mask Layout

Process flowVirtual device

TCAD Experiments

Process Compact model derived

from TCAD

PCM

PCM

FAB1FAB1

FAB2FAB2

Technology Technology transferred to transferred to

FAB2 using PCMFAB2 using PCM

13 MODERN General


13

PCM approach

Parameter screening to identify the process parameters that have an important impact on target electrical parameters.

Parameterized simulation setup (DOE) generating several simulation runs.

Device simulations of breakdown and I-V characteristic for each experiment.

Extraction of RSM model of device characteristics as function of process parameters using PCM Studio.

DOE

EHD5 SEMICELL

SENTAURUS WORKBENCH

PCM STUDIO

PCM

Synopsys platform:Sentaurus and PCM Studio

Simulation of Power-Mos semi cell with the nominal values of the process input parameters

14 MODERN General


Process Variation at AMS - TUW

• Process Flow

Parameters

SentaurusWork Bench

Minimos

ParameterExtraction

CorrelationInterface between commercial Synopsys Process Simulator and Minimos Device Simulator

WP2 T2.1 action items

• Task 2.1: Process simulation

– D2.1.2 (M27): « Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) »

AI (STI, AMS, M27): HVMOS and AsGaN-SiC device sensitivity analysis to Process variations to be validated on HW data available from D2.3.2


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Device Simulation: T2.2 DeliverablesRef Deliverable/ Contributors Due date

D2.2.1 Assessment of state-of-the-art TCAD methodology and usability concerning PV for industrial purposes including identification of current deficiencies of tools (UNGL)

M6

D2.2.2 Device simulation analysis of dominant variability sources in 45nm planar bulk CMOS technologies, and Discrete Power Device,SiC, GaN/AlGaN technologies.

Prototype implementation of the treatment of individual dopants and traps in the device modeling tools

(UNGL, UNET, NXP, ST-I, SNPS)

M12

D2.2.3 Device simulation analysis of dominant variability sources in state of-the-art Non-Volatile-Memory technologies (UNET, UNGL, NMX, SNPS)

M18

D2.2.4 Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET).

Efficient compact model extraction procedures for modeling process variations and device fluctuations (NXP, UNET, POLI)

M24

D2.2.5 Application of mixed-mode device-circuit simulations for the analysis of the impact of fluctuations (UNET)

TCAD based assessment of PV effects of potential 22nm device architectures (UNGL)

M27

D2.2.6 Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET)

Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD

Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2)

M36


T2.2.2 OverviewVD=50mV VD=1.0V

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VD=50mV VD=1.0V

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T2.2.2 Overview

21/04/2321/04/23

(UNET-Università di Udine)(Synopsys)

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T2.2.2 Overview

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(UNET-Università di Bologna)

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T2.2.3 Overview<VT> [V] σVT [mV]

RDD (Glasgow) 1.02 141RDD (Numonyx) 1.15 146RDF (Synopsys) 1.025 137

RDD LER LWR

OTF ITCPSG

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T2.2.3 Overview

<VT> [V] σVT [mV]

RDD (Glasgow) 1.02 141

RDD (Numonyx) 1.15 146

RDD+Rounded (Numonyx) 1.19 161

Flat AA &FG

RoundedAA & FG

<VT> [V] σVT [mV]Calc. σVT

[mV]

Uniform 1.04 - -

All Sources 1.32 169 166.3

T2.2 action items

• Task 2.2: Device simulation– D2.2.4 (M24): « Forecast of the magnitude of statistical variability in 32nm planar

bulk CMOS devices via device simulation (UNGL, IMEP, UNET)” AI (STF2, Nov 2010): to provide TCAD decks. 5-way NDA between UNGL-

UNET-SNPS-POLI-ST applies.

– D2.2.5 (M27): « TCAD based assessment of PV effects of potential 22nm device architectures (UNGL)”

=> AI (WP leader, Nov 2010): contact LETI on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011.

– D2.2.6 (M36): « Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET) . Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD. Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2)”

=> AI(T2.2 Leader): Contact SNPS if they intend to contribute to toolbox


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Project Review MeetingCrolles, June 22, 2009

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Project Review MeetingCrolles, June 22, 2009

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Electrical Characterization: T2.3 DeliverablesRef Deliverable/ Contributors Due date

D2.3.1 Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm (STF2, IMEP, UNET, NXP)

Experimental characterization of Non-Volatile- Memory devices in the presence of PV (NMX, UNET)

Parametric mismatch fluctuation effects in 32 nm FinFETs, first PV results on 22nm FDSOI MOSFETS (LETI, NXP)

M12

D2.3.2 Characterization of major sources of PV in SiC technologies/devices, and AlGaN/GaN HEMT devices (ST-I)

Report on 1/f noise dispersion behavior in 45nm bulk CMOS (NXP)

M18

D2.3.3 Identification of most relevant process variations in planar bulk CMOS devices down to 32nm, parameter fluctuation effects based on hardware (STF2, NXP, UNET, AMS)

Sources for PV in new device architectures, suitable for 22nm CMOS; major deltas in comparison to standard planar bulk CMOS (IMEP, NXP, LETI)

M30

D2.3.4 Report on high-level models, both analytical and graphical , for PV of Non-Volatile-Memory devices (NMX)

Report on 1/f noise dispersion behavior in 32 nm planar bulk CMOS (NXP)

M36


26 MODERN 1st Year Review

June 30, 2010

26MODERN 1st Year ReviewJune 30, 2010


Task T2.3 D2.3.1: Characterization of the influence of variability sources in planar bulk CMOS devices down to 45nm (ST, IMEP, UNGL)

W (µm) L (µm)

0.12 5

1 0.04

5 0.04

0.15 0.04

0.15 1

0.12 1

1 0.05

1 0.08

0.12 0.05

0.12 0.2

0

2

4

6

8

10

12

Idealscaling law

σ

Vt.(

WL

)1/2

(mV

.µm

)

0.01 0.1 1 10L (µm)

Example of 45nm Nmos with pocket implants: Conventional DOE and electrical characterization technique Geometry scaling on transistor area impacted by Lateral doping gradient Compact analytical model developed with 3 channel regions wi/wo pockets explains qualitative trend of Lscaling for VT mismatch UNGL 3D simulation (D2.2.2) in line with experiments


June 30, 2010



Task T2.3 D2.3.1: Experimental characterization of NVM devices (41nm, xGbits )in the presence of PV (NMX)

Neutral device scaling: Local random variations for W,L, Oxide, Interpoly dielectric, RDD fluctuations (top)Local systematic: Cell to cell interference (bottom)

After programming:Local randomLocal systematic VT Shift induced by neighbouring cells (top), or string series resistances (bottom)


June 30, 2010



Task T2.3 D2.3.1: First PV results on 22nm FDSOI MOSFETS (Leti, NXP)

0

10

20

30

40

50

60

0 5 10 15 20

1/sqrt(LxW) (µm)

nFETs

pFETs

σ(Δ

Vt)

(m

V)

AVt=1.4mV.µm

AVt=1.2mV.µm

P10 - HfSiO 2,3nm / TiN PVD 5nm - CESL neutre

VT mismatch (@ 1V Vd) for FDSOI nFETs and pFETs. High-k/metal gate stack. STI isolation. TSi=6nm, Lmin=30nm, Wmin=80nm

Record matching performance for FDSOI (top)VT matching not degraded by UTBOX vs Thick box substrates (bottom)

0

10

20

30

40

50

0 5 10 15 20 25

VT (

mV

)

1/sqrt(WxL) (µm)

AVT

=1.45mV.µm

Open: Thick BOXClosed: UT2B

pMOS

nMOS

VT mismatch for UT2B vs thick BOX MOSFETs. High-k/metal gate stack. STI isolation. TSi=8nm.


June 30, 2010



Task T2.3 D2.3.1: Parametric mismatch fluctuation effects in 32 nm SOI FinFETs (NXP, LETI)

Mismatch signature analysis on FinFET population. WFin=10 nm, Lg=100 nm

a: collection of 96 (VDS=1.2 V) transfer curves for transistor 1 (ID1) of each pair.

b: ΔID/ID vs. VGS for all pairs of the population (ΔID/ID = 200 x (ID1-ID2)/(ID1+ID2) ).

c: mismatch signature: σ_ΔID/ID (red triangles) and mismatch auto-correlation (black X’s) vs. VGS.

Rseries

VT

GIDL

a: Drain access resistance improvement from 700 to 280 Ωμm . θ vs. β slope corresponds to RSD. b: VT mismatch fluctuations vs. area. AΔVT increases from 1.9 mVμm (solid line) to 2.4 mVμm (dashed line) with 1018 channel doping

Powerful Mismatch signature analysis concept demonstratedAΔVT down to 2 mVμm range demonstrated

T2.3 action items• Task 2.3: Characterization and simulation verification

– D2.3.2 (M18)/D2.3.4 (M36): « 1/f noise dispersion”

=> AI (WP leader): Ask NXP about plan to develop compact model within Modern

– D2.3.4: (M36) « Report on high-level models, both analytical and graphical , for PV of in Non-Volatile-Memory devices (NMX)”

AI change title: « Report on high-level models, both analytical and graphical , for PV of devices in Non-Volatile-Memory technologies (NMX)”


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Reliability: T2.4 Deliverables


D2.4.1 Specification of considered degradation effects, modeling approaches and device parameters (UNGL, TUW)

M6

(Done)

D2.4.2 Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA)

M24

D2.4.3 Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA)

M33



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WP2/ Task 2.4 contributions

Effects ->Technologies

HCI NBTI TDDB RTN/Trapping/De-trapping

SBD/BD

HV mos AMSTUW

AMSTUW

65nm cmos UNCA(NXP)

45nm cmos UNGLUNCA(NXP)

UNGL UNGL

NVM UNET(NMX)

Thin Si IMEP


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AI(all, end 2010): WP2 and per Task work matrix completion

T2.4 Review Summary

• Activity done so far, with highlights on technical results, and dissemination

- D2.4.1 deliverable: done. - NBTI and HC data (0.35 µm LV-CMOS & HV-CMOS): available for TCAD simulations. - Initial physics-based analytical model for NBTI to implement in circuit simulator. - Time dependent modeling of degradation for NBTI & HC.

• Plan for D2.4.2 deliverable (M24): - TCAD reliability simulations focused on HV-CMOS. - Hot-Carrier lifetime model for HV-CMOS by modified Hu-model. - Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node.

• Plan for D2.4.3 deliverable (M33): - Statistical compact Models will be extracted at different levels of NBTI and PBTI. - Time dependence of the statistical compact models will be provided based on NBTI and PBTI models of trap charge as a function of time. - Analytical NBTI and HC model developments for LV- & HV-CMOS.


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NBTI & Hot-Carrier Activities (1)

• Extraction of capture/emission time maps– Compact modeling using RC circuits


• SE-mechanism:

• ME-mechanism:

• Idlin degradation represented by the compact model

2/10,

)(

minmax0

_

,

)exp(1

,1

1max

min

tNN

dxexx

NN

MEMEit

x

x

xtISEit

36 MODERN General MeetingsCatania, Nov. 9 & 10, 2010

NBTI & Hot-Carrier Activities(2)


37

Threshold Voltage Mismatch Induced by Hot-Carrier in 65 and 45 nm Technology Node

Lifetime Models for High-Voltage NMOS

gV

D

BgD I

ITVCI

,

Modified Model of Hu:

blue data points: -40°Cred data points: +25°CVd: 35V, 40V, 45V, 50V, 55V


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WP2 action items

• Task 2.4: Statistical Reliability

– D2.4.2 (M24): « Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA)”

=> AI (UNCA, working with NXP): addition of sub-Vt slope to Vt figure for HCI effects

– D2.4.3 (M33) « Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA)”

AI (AMS, TUW): Implementation of process variations in NBTI/HCI degradation compact models for HV devices remains challenging task (physics complexity); nevertheless achievable with some approximations to physics

AI (UNGL): UNGL to clarify contents of contribution to NBTI/HCI compact models


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Compact Modeling: T2.5 Deliverables


D2.5.1 PV-aware circuit-level models for standard CMOS technologies (down to 45nm) (UNGL, UNET, NXP, POLI, ST-I, STF2) , and Non-Volatile-Memory technologies (NMX, UNET), and Discrete Power Device,SiC, GaN/AlGaN technologies (ST-I). State-of-the-art based statistical models, based on hardware and/or TCAD

M18

DONE

D2.5.2 Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS)

M30

D2.5.3 PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2)

Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET)

M33


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Local Statistical

Channel dopants

Poly Si granularity

Line edge roughness

Across chip

Global Process

Die to die

Wafer to wafer

Variations in statistical models: sources

Local Systematic (Layout dependent)

H.Tsuno, Sony, VLSI 2007

Source: A.Asenov

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UNGL Deliverable 2.5.1

• Extraction of accurate uniform compact models, DC and AC

43MODERN General MeetingsCatania, Nov. 9 & 10, 2010

NMOS IDVD

NMOS with substrate bias

Capacitance fit atVD=0V

Capacitance fit atVD=1.1V

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UNGL Deliverable 2.5.1• Selection of optimal statistical parameter set and statistical compact model extraction• Preservation of parameter correlations

44MODERN General MeetingsCatania, Nov. 9 & 10, 2010

Distribution of fitted error fordifferent parameter sets

NMOS and PMOS parametercorrelations

Statistical Models for Circuit Simulation

45

Circuit environmentVDD, T, …

Settings for Variations: Corners/ MC/ DOEs

Design inputs

DistributionsCornersYield

Design Analysis

Complete simulation file

Core Compact model

Simulation engine

Elementary Circuit Responses

Statistical models: MC, Corners

Variations: GlobalLocal

Layout Proximity / Middle end Parasitics

Spice model

Nominal Corners construction

Netlist extracted from Layout

T2.5 action items• Task 2.5: compact modeling

– D2.5.2 (M30): » Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS)”

AI (STF2, Dec 2010): To clarify if D2.5.3 contribution (45nm Analog) effectively transforms into D2.5.2 contribution (32nm Digital)

– D2.5.3 (M33): « PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2). Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET)”

=> AI(WP leader, same as AI as D2.2.5, Nov 2010): to contact LETI, cc UNGL on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011.


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WP2 meetingDomain overview per task and partner


Technologies

Process simulation

Device simulation

Electrical Charact.

Reliability Compact Modeling

Task 2.1 2.2 2.3 2.4 2.5

HVMOS AMS TUW AMS TUW AMS TUW

Planar CMOS 65nm UNCA

45nm UNGL POLI SNPS (STF2)

IMEP STF2 UNGL UNGL POLI STF2 NXP

32nm UNGL POLI (STF2)

IMEP STF2 UNGL

NVM 41nm UNET NMX SNPS

UNET NMX UNET (NMX) UNET NMX

FDSOI IMEP (STF2) LETI IMEP LETI

Finfets, MUG, GAA

STF2 NXP IMEP

SiC Power MOS

STI STI STI

AlGaN-GaN HEMT

STI STI STI

PV aware tools and methods are of common interest; they are developped and applied to a wide spectrum of technologies (Project book rev2 v2.4.1).

Significant communalities of technology targets, except different ones for Process and Device simulation.

(not funded)

WP2/ Task 2.4 contributions

Effects ->Technologies

HCI NBTI TDDB RTN/Trapping/De-trapping

SBD/BD

HV mos AMSTUW

AMSTUW

65nm cmos UNCA(NXP)

45nm cmos UNGLUNCA(NXP)

UNGL UNGL

NVM UNET(NMX)

Thin Si IMEP


49

AI(all, end 2010): WP2 and per Task work matrix completion


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WP2 meeting: Gantt chart

WP2 WP2: Process/device to compact modelling01/03/2009 30/11/2011T2.1 T2.1: PV-aware process simulation 01/03/2009 28/02/2011D2.1.1 D2.1.1 01/03/2009 31/05/2010D2.1.2 D2.1.2 01/03/2010 31/05/2011 D2.1.1T2.2 T2.2: PV-aware device simulation 01/03/2009 29/02/2012D2.2.1 D2.2.1 01/03/2009 31/08/2009D2.2.2 D2.2.2 01/03/2009 28/02/2010 D2.2.1D2.2.3 D2.2.3 01/03/2009 31/08/2010 D2.2.1 D2.2.2 D2.3.1D2.2.4 D2.2.4 01/03/2010 28/02/2011 D2.2.1 D2.2.2D2.2.5 D2.2.5 01/03/2010 31/05/2011 D2.2.1 D2.2.4D2.2.6 D2.2.6 01/03/2010 29/02/2012 D2.2.1 D2.2.3T2.3 T2.3: Electrical characterization of PV, software (TCAD) / hardware comparison & calibration 01/03/2009 29/02/2012D2.3.1 D2.3.1 01/03/2009 28/02/2010 D2.2.2D2.3.2 D2.3.2 01/03/2010 31/08/2010D2.3.3 D2.3.3 01/09/2010 31/08/2011 D2.2.4 D2.2.5D2.3.4 D2.3.4 01/09/2010 29/02/2012 D2.2.3 D2.3.1T2.4 T2.4: Correlation between PV and reliability, reliability modeling01/03/2009 30/11/2011D2.4.1 D2.4.1 01/03/2009 31/08/2009 D2.2.1D2.4.2 D2.4.2 01/03/2009 28/02/2011 D2.4.1D2.4.3 D2.4.3 01/03/2009 30/11/2011 D2.4.1 D2.4.2 D2.2.2 D2.2.3T2.5 T2.5: PV-aware compact modelling 01/03/2009 30/11/2011D2.5.1 D2.5.1 01/03/2009 31/08/2010 D2.2.2 D2.2.3 D2.3.1 D2.5.2 D2.5.2 01/03/2009 31/08/2011 D2.2.4 D2.3.3D2.5.3 D2.5.3 01/03/2009 30/11/2011 D2.2.2 D2.2.3 D2.5.1

AI(all): requires completion (links with other WPs), and review by email within 2 months

WP2 action items• WP2

– Need to Complete WP2 matrix + 1 matrix per task – Need to Complete Gantt chart

AI (all, Jan 2010). WP leader to send email for feedback collection Nov 2010. WP2 members to feedback to Task Leaders, who will compile and update

per task.


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• Backup: List of Action points from meeting


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WP2 action items• WP2

– Need to Complete WP2 matrix + 1 matrix per task

– Need to Complete Gantt chart

=> AI (all, Jan 2010). WP leader to send email for feedback collection Nov 2010. WP2 members to feedback to Task Leaders, who will compile and update per task.

• Task 2.1: Process simulation

– D2.1.2 (M27): « Enhanced process simulation including treatment of PV for Discrete Power Device, HV-CMOS, SiC, GaN/AlGaN technologies, interfaced to commercial TCAD tools (ST-I, AMS, TUW) »

AI (STI, AMS, M27): HVMOS and AsGaN-SiC device sensitivity analysis to Process variations to be validated on HW data available from D2.3.2

• Task 2.2: Device simulation

– D2.2.4 (M24): « Forecast of the magnitude of statistical variability in 32nm planar bulk CMOS devices via device simulation (UNGL, IMEP, UNET)”

AI (STF2, Nov 2010): to provide TCAD decks. 5-way NDA between UNGL-UNET-SNPS-POLI-ST applies.


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WP2 action items• Task 2.2

– D2.2.5 (M27): « TCAD based assessment of PV effects of potential 22nm device architectures (UNGL)”

=> AI (WP leader, Nov 2010): contact LETI on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011.

– D2.2.6 (M36): « Sensitivity analysis of Non Volatile Memory device performance as a function of individual trap position (NMX,UNET) . Toolbox (methodologies, models, tools) to make dominant variability effects accessible to industrial usage of TCAD. Outlook to 16nm device architecture robustness using MASTAR (UNGL, STF2)”

=> AI(T2.2 Leader): Contact SNPS if they intend to contribute to toolbox


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WP2 action items• Task 2.3: Characterization and simulation verification

– D2.3.2 (M18)/D2.3.4 (M36): « 1/f noise dispersion”

=> AI (WP leader): Ask NXP about plan to develop compact model within Modern

– D2.3.4: (M36) « Report on high-level models, both analytical and graphical , for PV of in Non-Volatile-Memory devices (NMX)”

AI change title: « Report on high-level models, both analytical and graphical , for PV of devices in Non-Volatile-Memory technologies (NMX)”

• Task 2.4: Reliability

– D2.4.2 (M24): « Hardware results of aging measurements available, on planar bulk CMOS technologies (AMS, TUW, UNET, UNCA)”

=> AI (UNCA, working with NXP): addition of sub-Vt slope to Vt figure for HCI effects

– D2.4.3 (M33) « Implementation of statistical degradation effects into aging models, hardware calibration of degradation effects (IMEP, AMS, TUW, UNGL, UNET, UNCA)”

AI (AMS, TUW): Implementation of process variations in NBTI/HCI degradation compact models for HV devices (Challenging, nevertheless achievable with some approximations to physics)

AI (UNGL): UNGL to clarify contribution to NBTI/HCI compact models


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WP2 action items• Task 2.5: compact modeling

– D2.5.2 (M30): » Statistical PV-aware models for planar bulk CMOS generation devices (down to 32nm) (POLI, UNGL, UNET, NXP, AMS)”

AI (STF2): Clarifies if D2.5.3 contribution (45nm Analog) transforms into D2.5.2 contribution (32nm Digital)

– D2.5.3 (M33): « PV-aware circuit-level models for 45nm analog CMOS technology (ST-F2). Modeling of additional variability sources of 3-dimensional device architectures, for new device architectures for 22nm (LETI, UNGL, UNET)”

=> AI(WP leader, same as AI as D2.2.5, Nov 2010): contact LETI on demonstrator devices (FDSOI, Finfets?,…) and associated templates. Backup template devices already available at UNGL. Need decision latest Feb 2011.


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Documents

MODERN ENIAC WP2 Meeting