CONCORDIAVLSI DESIGN LAB

1

Models for Hand Analysis

NMOS Transistor

IDS N KN VG SN VTN– VD SN12---VD SN

2–

=

ID SN12---KN VG SN VTN– 2 1 VD SN+ =

PMOS TransistorI D SP KP– VGS P VTP– VD SP

12---VD SP

2–

=

ID SP12---– Kp VGS P VTP– 2 1 VDS P– =

VDSN VGSN-VTN

VDSN VGSN-VTN

VDSP VGSP -VTP

VDSP VGSP-VTP

KN=(W/L)K’N

KP=(W/L)K’P

CONCORDIAVLSI DESIGN LAB

2

pMOS Current model

I D SP KP– VGS P VTP– VD SP12---VD SP

2–

=

ID SP12---– Kp VGS P VTP– 2 1 VDS P– =

VDSP>VGSP -VTP

VDSP <VGSP-

VTP

CONCORDIAVLSI DESIGN LAB

3

Channel Resistance

)(

1

tgsn VVB 2][

2

tgsn VV R= R=

CONCORDIAVLSI DESIGN LAB

4

Variation of resistance with Vgs

CONCORDIAVLSI DESIGN LAB

5

LENGTH L S L/S

WIDTH W S W/S

THIN OXIDE tox S tox/S

DIFFUSION DOPING ND 1/S ND . S

SUBSTRATE DOPING NA 1/S NA . S

SUPPLY VOLTAGE VDD 1/S VDD/S

Linear Scaling

CONCORDIAVLSI DESIGN LAB

Scalling Effects

6

CONCORDIAVLSI DESIGN LAB

7

Velocity Saturation and mobility Degradation

CONCORDIAVLSI DESIGN LAB

8

TOH’s Model for Short Channel

]2

[2

dsgsoxnD

VV

L

WCI dsatds VV fo

r)( tgsoxsatD VVWCkVI dsatds VV for

))(1( tgsdsat VVkV

)(1

1

1

1

tgssat

sat

VV

LE

E

EK

n

satsat

VE

2

CONCORDIAVLSI DESIGN LAB

9

Secondary Effects

Subthreshold current: is the small current that flows from drain at Vgs < Vt

Punch through: If a large voltage is applied to Vds, then the depletion region of the drain can extend to the source, a punch through occurs and under these condition a large current can flow from the drain to source.

Hot carrier: As a results of scaling, device dimensions are reduced while, doping concentrations are increased, while voltages are not reduced to the same proportion, as a consequence there is an increase in electric field in the channel region while, the thickness of the gate insulating layer is thinner. Due to the acceleration of electrons by the Vds, electrons and holes gaining high speed can penetrate the gate insulator and change its characteristics.

Channel hot electrons: If the Vds is increased, then the lateral electric field is increased and the electric field accelerates the electrons near the drain with high kinetic energy they are injected into the oxide near the drain.

CONCORDIAVLSI DESIGN LAB

10

Semiconductor Resistors

Resistance

R= (l /A) = (/t). (l /w) = Rsh. (l /w)

Rsh = sheet resistance Ω/

For 0.5u process: N+ diffusion : 70 Ω/ M1: 0.06 Ω/ P+ diffusion : 140 Ω/ M2: 0.06 Ω/ Polysilicon : 12 Ω/ M3: 0.03 Ω/ Polycide:2-3 Ω/ P-well: 2.5K Ω/ N-well: 1K Ω/

w

current

l t

(A)

1

n n q p p q + ------------------------------------------------=

CONCORDIAVLSI DESIGN LAB

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Semiconductor Resistors

AlAl

n+

Diffusionn+

Field oxide

polysilicon

Polysilicon Resistor Diffusion Resistor

SiO2

CONCORDIAVLSI DESIGN LAB

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Variations in Width and Length

Weff

Wdrawn

WD WD

1. Width Oxide encroachment Weff = Wdrawn- 2WD

2. Length Lateral diffusion LD = 0.7Xj Leff = Ldrawn- 2LD

Ldrawn

LD Leff LD

polysilicon

polysilicon

CONCORDIAVLSI DESIGN LAB

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Semiconductor Capacitors

1. Poly Capacitor: a. Poly to substrate b. Poly1 to Poly2

2. Diffusion Capacitor

n+ (ND)

depletion region

substrate (NA)bottomwallcapacitance

sidewallcapacitances

CONCORDIAVLSI DESIGN LAB

14

Transistor Resistance

:

Two Components:

Drain/ Sources Resistance:

RD(S) = Rsh x no. of squares+ contact resistance.

Channel Resistance: Depends on the region of operation:

L

W

(D) (S) n+ n+

(G)

RS Rch RD

Linear

RCH2

K' WL----- V

GSVT– 2

----------------------------------------------------= Saturation

RCH1

K'WL----- VGS VT– VDS–

---------------------------------------------------------------- '=

CONCORDIAVLSI DESIGN LAB

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Dynamic Behavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB

Prentice Hall/Rabaey

CONCORDIAVLSI DESIGN LAB

16

The Gate Capacitance

Prentice Hall/Rabaey

CONCORDIAVLSI DESIGN LAB

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Average Gate Capacitance

Most important regions in digital design: saturation and cut-off

Different distributions of gate capacitance for varying

operating conditions

Prentice Hall/Rabaey

CONCORDIAVLSI DESIGN LAB

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Diffusion Capacitance

Prentice Hall/Rabaey

CONCORDIAVLSI DESIGN LAB

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Diffusion Capacitance

MJSW

B

BD

DJSW

MJ

B

BD

DJD

P

VP

C

P

VA

CC]1[]1[

)22(*** WLCWLCC JSWJD

CONCORDIAVLSI DESIGN LAB

20

SPICE TRANSISTOR MODEL

CONCORDIAVLSI DESIGN LAB

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SPICE MODELS

Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes VelocitySaturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fittingto measured devices

Level 4 (BSIM): Emperical - Simple and Popular

CONCORDIAVLSI DESIGN LAB

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MAIN MOS SPICE PARAMETERS

Prentice Hall/Rabaey

CONCORDIAVLSI DESIGN LAB

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SPICE Parameters for Parasitics

Prentice Hall/Rabaey

CONCORDIAVLSI DESIGN LAB

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SPICE Transistors Parameters

Prentice Hall/Rabaey

CONCORDIAVLSI DESIGN LAB

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Example