Modeling Effects of Dynamic BTI Degradation on Analog and ... · Lehrstuhl für Technische Elektronik Technische Universität München MOS-AK/GSA Workshop, April 11-12, 2013, Munich

Lehrstuhl für Technische Elektronik Technische Universität München

MOS-AK/GSA Workshop, April 11-12, 2013, Munich

Modeling Effects of Dynamic BTI Degradation on Analog andMixed-Signal CMOS Circuits

Leonhard Heiß, Cenk Yilmaz, Christoph Werner, Doris Schmitt-Landsiedel

Contact: [email protected]

Lehrstuhl fur Technische ElektronikProf. Doris Schmitt-LandsiedelTechnische Universitat Munchen

mailto:[email protected]


Lehrstuhl fur Technische Elektronik

Head: Prof. Doris Schmitt-Landsiedel

12 PhD Students and Research Assistants

Circuit ReliabilityRobust/LP DesignNML

Digital CMOS

Timing Monitors

Adaptive VoltageScaling

AMS/RF CMOS

AgeingModeling/Simulation

Ageing Test Structures

Impact of Degradationon Circuit Performance

Nano Magnetic Logic

April 12th, 2013 2


Content

1 Introduction and Motivation

2 Physical NBTI Model

3 New Simulation Method for NBTI in Analog CMOS Circuits

4 SC Comparator

5 SAR ADC

6 Conclusion and Outlook

7 References

April 12th, 2013 3


Content




4 SC Comparator

5 SAR ADC


7 References

April 12th, 2013 4


Introduction

NBTI: Negative Bias Temperature Instability:

Degradation of pMOSFETSMain impact: Increase of |Vth|

NBTI stress vs. NBTI relaxation:

Dynamic NBTI:

Sequence of stress/recovery phase causes fast changing ∆Vth(t)∆Vth(t) potential error source in high-precision analog circuits

April 12th, 2013 5


Introduction




1. Stress:

Dynamic NBTI:


April 12th, 2013 5


Introduction




1. Stress: 2. Relaxation:

Static NBTI

Dynamic NBTI

Dynamic NBTI:


April 12th, 2013 5


Introduction




1. Stress: 2. Relaxation:

Static NBTI

Dynamic NBTI

Dynamic NBTI:


April 12th, 2013 5


Motivation

Starting point for our research:

State of the art reliability simulators do not include relaxation

Impact of relaxation on analog performance got hardly investigated

Sequence of stress/relaxation might cause circuit malfunction

Aim of our research:

1. Physical NBTI model, including relaxation

2. Integration of NBTI model into circuit simulator

3. Impact of relaxation on analog/mixed-signal circuits

4. Design of sophisticated test structures for analog circuits

April 12th, 2013 6


Motivation

Starting point for our research:

State of the art reliability simulators do not include relaxation

Impact of relaxation on analog performance got hardly investigated

Sequence of stress/relaxation might cause circuit malfunction

Aim of our research:

1. Physical NBTI model, including relaxation

2. Integration of NBTI model into circuit simulator

3. Impact of relaxation on analog/mixed-signal circuits

4. Design of sophisticated test structures for analog circuits

April 12th, 2013 6


Content




4 SC Comparator

5 SAR ADC


7 References

April 12th, 2013 7


Recent Understanding and Modeling of NBTI

p+

n-Sub.

++

p+

++ + + + + + + + + ++ + + + + + + + + +

p++

SiO2

Stress Case:Charge capture increases |Vth|

Single defect:Capture time constant τc

p+

n-Sub.

++

p+

+

p++

+ +++ + +

SiO2

Relaxation Case:Charge emission decreases |Vth|again

Single Defect:Emission time constant τe

April 12th, 2013 8


Capture and Emission Time Constants

τc and τe widely spreadDistribution modeled by 2 bivariate log-normal p.d.f’s [1]:

τc and τe temperature and bias dependentDistribution depends on: T ,VGS, CMOS technology

April 12th, 2013 9


Markov Model for a single Defect Group

1 21: neutral state

2: positively charged

Defect group ( , ),

density within

Expectation value for threshold shift of single defect group:

|∆Vth(t)| ∝ dτe

τe + τc︸︷︷︸

a(VGS)

+(

|∆Vth(t0)| − dτe

τe + τc︸︷︷︸

a(VGS)

)

exp(

−( 1

τe+

1

τc︸︷︷︸

b(VGS)

)

t)

Bias dependence regarded by model parameters k1 and k2:

|∆Vth(t)| =(

k1VGS

)k2

a+(

|∆Vth(t0)| −(

k1VGS

)k2

a)

exp(

−bt)

April 12th, 2013 10



1 21: neutral state


Defect group ( , ),

density within



τe + τc︸︷︷︸

a(VGS)

+(


τe + τc︸︷︷︸

a(VGS)

)

exp(

−( 1

τe+

1

τc︸︷︷︸

b(VGS)

)

t)


|∆Vth(t)| =(

k1VGS

)k2

a+(

|∆Vth(t0)| −(

k1VGS

)k2

a)

exp(

−bt)

April 12th, 2013 10



1 21: neutral state


Defect group ( , ),

density within



τe + τc︸︷︷︸

a(VGS)

+(


τe + τc︸︷︷︸

a(VGS)

)

exp(

−( 1

τe+

1

τc︸︷︷︸

b(VGS)

)

t)


|∆Vth(t)| =(

k1VGS

)k2

a+(

|∆Vth(t0)| −(

k1VGS

)k2

a)

exp(

−bt)

April 12th, 2013 10



1 21: neutral state


Defect group ( , ),

density within



τe + τc︸︷︷︸

a(VGS)

+(


τe + τc︸︷︷︸

a(VGS)

)

exp(

−( 1

τe+

1

τc︸︷︷︸

b(VGS)

)

t)


|∆Vth(t)| =(

k1VGS

)k2

a+(

|∆Vth(t0)| −(

k1VGS

)k2

a)

exp(

−bt)

April 12th, 2013 10



1 21: neutral state


Defect group ( , ),

density within



τe + τc︸︷︷︸

a(VGS)

+(


τe + τc︸︷︷︸

a(VGS)

)

exp(

−( 1

τe+

1

τc︸︷︷︸

b(VGS)

)

t)


|∆Vth(t)| =(

k1VGS

)k2

a+(

|∆Vth(t0)| −(

k1VGS

)k2

a)

exp(

−bt)

April 12th, 2013 10


Where do the model parameters k1 and k2 come from?

EF

Gate

EC

ChannelDielectric

VGS ≈ Vth

Channel ChannelGate GateDielectric Dielectric

VGS = Vs,1 VGS = Vs,2

EC

EC

EV

EV

EF

EF

EF

EF

EF

EV

N1N1

∆N

Number of active traps is bias dependent [2]

Make amplitude of ∆Vth bias dependent with prefactorA = (k1VGS)

k2 [1]

April 12th, 2013 11


Content




4 SC Comparator

5 SAR ADC


7 References

April 12th, 2013 12


Modeling Dynamic NBTI on Circuit Level

S

M1

ΔVth(t,VGS)

GextGint

Verilog-A BSim4

Dynamic ∆Vth modeled inVerilog-A subcircuit

Gext

S

Gext

Gint

Verilog-A model acts as voltagecontrolled voltage source(VCVS)

∆Vth adapted online duringtransient simulation

April 12th, 2013 13


Example for Transient NBTI Simulation

Example circuit & VGS, ∆Vth(t) of Mp1:

Mp1

ΔVth

Vin

−1.4

−1.2

−1

−0.8

−0.6

VG

S [V

]

0 5 10 15−3

−2

−1

0

Time [µs]

∆ V

th [m

V]

April 12th, 2013 14


LTERely Simulator

Netlist

Analyzer (1)

Virgin Netlist

Aged Netlist

Verilog-A (1)

NBTI Modelfor PMOS (1)

Automated reliabilitysimulation of complexanalog blocks

Verilog-A model forshort term reliability

Extrapolator for longterm reliability

April 12th, 2013 15


Content




4 SC Comparator

5 SAR ADC


7 References

April 12th, 2013 16


Switched Capacitor Comparator

Mp1

Mn1

Mp2

Mn2

C1 C2

CL

outVin

Vref

Use case:VDD = 1.3 V

Vref = 0.65 V

Clock Phase φ1 : Offset sampled on C1 and C2

Clock Phase φ2 : Comparator Mode

April 12th, 2013 17


Switched Capacitor Comparator

Use case:VDD = 1.3 V

Vref = 0.65 V

Clock Phase φ1 : Offset sampled on C1 and C2

Clock Phase φ2 : Comparator Mode

NBTI critical for Mp1: Largest stress for Vin = 0 V

April 12th, 2013 17


SC Comparator: Test Case

Verify correct function by input step from Vin = 0 V to Vref + 20 µV:

0

0.65

1.3

φ 1 [V]

0

0.65

1.3

φ 2 [V]

0

0.65

1.3

Vin

[V] V

in = V

ref + 20µV

0 1 2 3 4 5 6 7 8 9 100

0.65

1.3

Vou

t [V]

Time [µs]

April 12th, 2013 18


SC Comparator: Include Dynamic NBTI

Consider only short term stress:

0

0.65

1.3

Vin

[V] V

in = V

ref + 20µV

0

0.65

1.3

Vou

t [V]

no NBTI with NBTI

0 1 2 3 4 5 6 7 8 9 10

−1

−0.5

0

Time [µs]

∆ V

th [m

V]

∆ Vth of Mp1

Failure is caused by dynamic NBTI component, before end of life time

April 12th, 2013 19


SC Comparator: Include Dynamic NBTI

Consider only short term stress:

0

0.65

1.3

Vin

[V] V

in = V

ref + 20µV

0

0.65

1.3

Vou

t [V]

no NBTI with NBTI

0 1 2 3 4 5 6 7 8 9 10

−1

−0.5

0

Time [µs]

∆ V

th [m

V]

∆ Vth of Mp1

Failure is caused by dynamic NBTI component, before end of life time

April 12th, 2013 19


SC Comparator: Offset Compensation Failure

Offset compensation failure due to NBTI relaxation:

0

.65

1.3

Vout[V

]

�1.3

�.65

VG

S[V

]

0 1 2 3 4 5 6 7 8 9 10�1

�.5

0

Vth

[mV

]

Time [µs]

Contribution of Mp1 to Voff,

sampled on C1

Relaxation: Voff reduces,

i.e. sampled offset no longer valid

April 12th, 2013 20


SC Comparator: 10a Stress Case

Simulation after 10a stress using the stress extrapolator

0

0.65

1.3

Vin

[V] V

in = V

ref + 20µV

0

0.65

1.3

Vou

t [V]

virgin 10a stress: dynamic 10a stress: static

0 1 2 3 4 5 6 7 8 9 10−12.5

−12

−11.5

Time [µs]

∆ V

th [m

V]

∆ Vth of Mp1 after 10a: dynamic ∆ Vth of Mp1 after 10a: static

Failure not detected by classical simulation with constant ∆Vth

April 12th, 2013 21


SC Comparator: 10a Stress Case

Simulation after 10a stress using the stress extrapolator

0

0.65

1.3

Vin

[V] V

in = V

ref + 20µV

0

0.65

1.3

Vou

t [V]

virgin 10a stress: dynamic 10a stress: static

0 1 2 3 4 5 6 7 8 9 10−12.5

−12

−11.5

Time [µs]

∆ V

th [m

V]

∆ Vth of Mp1 after 10a: dynamic ∆ Vth of Mp1 after 10a: static

Failure not detected by classical simulation with constant ∆Vth

April 12th, 2013 21


Content




4 SC Comparator

5 SAR ADC


7 References

April 12th, 2013 22


SAR ADC

Successive Approximation Register (SAR) principle:

S & H

NBTI degradation causes comparator offset Voff

Solution: Offset Compensation with typical requirement:

Vref ≈ 1 V, N = 10 Bit ⇒ VLSB = 1 V210

≈ 1 mV

i.e. residual Voff < 1 mV necessary

Unproblematic for slowly varying Voff , but:

Even small ∆Voff < 1 mV due to short term NBTI can cause malfunction

April 12th, 2013 23


SAR ADC


S & H



Vref ≈ 1 V, N = 10 Bit ⇒ VLSB = 1 V210

≈ 1 mV




April 12th, 2013 23


SAR ADC


S & H



Vref ≈ 1 V, N = 10 Bit ⇒ VLSB = 1 V210

≈ 1 mV




April 12th, 2013 23


SAR ADC


S & H



Vref ≈ 1 V, N = 10 Bit ⇒ VLSB = 1 V210

≈ 1 mV




April 12th, 2013 23


SAR ADC


S & H



Vref ≈ 1 V, N = 10 Bit ⇒ VLSB = 1 V210

≈ 1 mV




April 12th, 2013 23


Example: 10 Bit Charge Redistribution SAR ADC

Vin

Vref

SAR ADC use case:

Fs = 1 MHz

fclk = 13 MHz

VDD = 1.3 V

Vref = VDD

Mp1

Mn1

Mp2

Mn2

CC�2 �3

CC2C

...

...

...

...CMPin CMPout ...

Comparator circuit:

Offset compensated

NBTI critical forMp1

April 12th, 2013 24


Example: Error @ 2nd Bit

April 12th, 2013 25


SAR ADC: Errors due to short term NBTIWrong output codes can occur for large variety of input levels

Code deviations of more than |1 LSB| were not found

Observed error rates depend on:

Input signal waveformClock frequency...

Example for full scale sine wave input @ Fs = 1 MHz:

April 12th, 2013 26


SAR ADC: Errors due to short term NBTIWrong output codes can occur for large variety of input levelsCode deviations of more than |1 LSB| were not found

Observed error rates depend on:Input signal waveformClock frequency...

Example for full scale sine wave input @ Fs = 1 MHz:

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.20

5

10

15

20

25

Stress Time [ms]

Err

or R

ate

[%]

fin = 100 kHzfin = 400 kHz

April 12th, 2013 26


Guideline for Transient Error Detection

Systematic approach to detect transient BTI errors:

1. Which devices are mainly susceptible against parameter drifts?→ Confine (complex) problem

2. Study transient VGS of critical devices

3. Do large |VGS| values on critical devices occur?→ High |VGS| causes ∆Vth (NBTI stress)

4. Abrupt changes in VGS possible?→ Dynamic ∆Vth can cause a transient error

April 12th, 2013 27








April 12th, 2013 27








April 12th, 2013 27








April 12th, 2013 27








April 12th, 2013 27








Note:In high-precision analog circuits even small ∆Vth (≈ 1 mV) can causetran. error

April 12th, 2013 28


Content




4 SC Comparator

5 SAR ADC


7 References

April 12th, 2013 29


Conclusion

Physics based model for dynamic NBTI

Verilog-A model to study NBTI impact on circuit level

LTERely: Simulation of NBTI for complex analog blocks

Transient errors due to dynamic NBTI:

Example: SC Comparator & SAR ADC65 nm design: No show stopper, but:Effects will worse with further technology scaling

April 12th, 2013 30


Conclusion

Physics based model for dynamic NBTI

Verilog-A model to study NBTI impact on circuit level

LTERely: Simulation of NBTI for complex analog blocks

Transient errors due to dynamic NBTI:

Example: SC Comparator & SAR ADC65 nm design: No show stopper, but:Effects will worse with further technology scaling

April 12th, 2013 30


Outlook

What happens if technology is further scaled?

NBTI effects become more relevant:

Non-constant field scaling increases local stress fieldsFast trapping/detrapping enhanced by new gate materials (cf. [1])

High-κ metal gate technologies:

Same effect also on nMOSFET (PBTI)Sources for errors increase, short term effects become worse (cf. [3])

April 12th, 2013 31


Outlook

What happens if technology is further scaled?

NBTI effects become more relevant:

Non-constant field scaling increases local stress fieldsFast trapping/detrapping enhanced by new gate materials (cf. [1])

High-κ metal gate technologies:

Same effect also on nMOSFET (PBTI)Sources for errors increase, short term effects become worse (cf. [3])

April 12th, 2013 31


Thank you for your attention

Please feel free to ask questions

April 12th, 2013 32


Content




4 SC Comparator

5 SAR ADC


7 References

April 12th, 2013 33


References I

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T. Grasser, B. Kaczer, H. Reisinger, P.-J. Wagner, andM. Toledano-Luque.On the frequency dependence of the bias temperature instability.In Reliability Physics Symposium (IRPS), 2012 IEEE International,pages XT.8.1 –XT.8.7, april 2012.

April 12th, 2013 34


References II

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References IV

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T. Grasser, T. Aichinger, H. Reisinger, J. Franco, P.-J. Wagner,M. Nelhiebel, C. Ortolland, and B. Kaczer.On the ’permanent’ component of nbti.In Integrated Reliability Workshop Final Report (IRW), 2010 IEEEInternational, pages 2 –7, oct. 2010.

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References VI

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T. Grasser, B. Kaczer, W. Goes, T. Aichinger, P. Hehenberger, andM. Nelhiebel.A two-stage model for negative bias temperature instability.In Reliability Physics Symposium, 2009 IEEE International, pages 33–44, april 2009.

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References VIII

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April 12th, 2013 47


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Modeling Effects of Dynamic BTI Degradation on Analog and ... · Lehrstuhl für Technische Elektronik Technische Universität München MOS-AK/GSA Workshop, April 11-12, 2013, Munich