Modeling and designing of high-gain, wide-band and fast-speedoperational transconductance amplifier

Jin Wu • Ma Ke • Ning Qu • Weiwei Zhang

Received: 31 December 2010 / Revised: 16 June 2011 / Accepted: 28 July 2011 / Published online: 6 August 2011

� Springer Science+Business Media, LLC 2011

Abstract Based on the analysis of the inherent limita-

tions of conventional OTA, this paper introduces a basic

strategy by combinating linear-nonlinear adaptive current

mirror and local cross-pair to solve the mutual restraint

between AC and DC characteristics of the circuit. In order

to simplify the multi-mode complicated circuit design, an

analytical model for the new OTA is proposed, which is

consistent with SPICE simulation results. Under the limi-

tation of the static current consumption, the maximum limit

of the circuit performance can be predicted by the proposed

model. Under the condition of 29 lA quiescent current and

30 pF load capacitance, a chip is implemented in 0.18 lm

CMOS technology, and the test results show that the DC

gain, GBW and slew rate achieve 73 dB, 6 MHz and

14 V/lS, respectively, and the optimal performance of DC,

AC and transient can be obtained almost simultaneously.

Keywords Operational transconductance amplifier �Linear-nonlinear adaptive current mirror � Cross-pair �Modeling

Abbreviations

DC Direct current

AC Alternating current

AV DC gain

GBW Gain-bandwidth product

SR Slew rate

PM Phase margin

OTA Operational transconductance amplifier

FVF Flipped voltage follower

1 Introduction

As a fundamental unit in analog system, OTA is mainly

used for control and signal processing, such as in LDO and

filter circuits, where high-gain, wide-band and fast-speed

are all required improving the performance of the system.

As for high gain, small current and cascode structure are

conventionally adopted; on the contrary, large current is

benefit for GBW and SR boosting. Clearly, it is difficult to

satisfy all these requirements due to the restraint between

static and dynamic behavior in linear amplifier, especially

under the low current consumption and low supply voltage

conditions. Several techniques have been proposed to solve

these problems. Ref. [1] added two comparators in the

output stage to enhance the driving current of transient

response with circuit area increased significantly. Refer-

ences [2, 3] using their additional transient control ele-

ments independently to improve the transient response,

while both of their circuits are complicated and the gain is

low. The class AB operation mode in [4] is used to improve

the gain of OTA, however, the SR is not high enough.

Local positive feedback proposed in [5–8] is another

effective way to boost the DC gain and GBW of OTA,

while the transient response is still remaining to be

improved. Dynamic tail current biasing technique sum-

marized in [9] is used to improve SR at the cost of large

dynamic current consumption and relative small gain. FVF

and nonlinear current mirror proposed in [10–12] achieve

high SR, but the gain is still low, and the mechanism and

limitation has not been analyzed completely. On the biases

of physical mechanism analysis for the restraint of

J. Wu � M. Ke (&) � N. Qu � W. Zhang

Wuxi Branch of Southeast University, Wuxi 214135, China

e-mail: aqishisi@sina.com

J. Wu

e-mail: jwu@seu.edu.cn; aqishisi@sina.com

123

Analog Integr Circ Sig Process (2012) 71:255–263

DOI 10.1007/s10470-011-9736-0

conventional OTA, this paper introduces a basic strategy

by combination linear-nonlinear adaptive current mirror

and local cross-pair to solve the mutual restraint between

AC and DC characteristics of the circuit and achieves the

multiplication of gain, GBW and SR, where the small and

large signal characteristics are well compatible. Besides,

the proposed accurate analytical model can be used in this

kind of OTA design.

This paper is organized as follows: Sect. 2 analyzes the

performance enhancement mechanism due to the positive

feedback cross-pair; Sect. 3 presents a new method

of controlling linear-nonlinear adaptive current mirror

through status factors; Sect. 4 proposes a new OTA

accommodating above two physical effects, and accurate

analytical model is also given in this section; In Sect. 5

analytical calculation results and the SPICE simulation

results are compared and the experiment results are also

given; Finally summarizes the full text in the last section.

2 Linear transmission controlled by cross-pair

In order to solve the inherent restraint between AC and DC

characteristics of conventional OTA, a couple of cross-pair

[7, 8] is added in parallel with the load diode transistors

M3, M5, respectively, as shown in Fig. 1. If the W/L ratio

of M4/M6 is scaled as unit, then the scaled W/L ratios of

load diode transistors and the cross-pair are N and K,

respectively. Thus, for conventional OTA without cross-

pair, the current transmission ratio between the output and

the differential input stage is 1/N. Clearly, a smaller N

leads to a larger GBW and SR, unfortunately, the static

current is increased and forces the voltage gain decrease.

As a result, it is impossible for conventional OTA to

compromise the inherent restraint of the circuits only by

the N where the suitable N value is often selected as 1 in

above situation.

The static and dynamic behaviors of the OTA are

completely changed if the cross-pair added. Supposing VA

and VB are the gate voltage of the load diode transistors, as

shown in Fig. 1. So under the DC condition, we get

VA = VB, and the effective N is increased, as given by

NDC = N ? K = NT, therefore, the static current is

reduced. Under the AC situation, VA and VB driven by

differential input signal are also differential signal, and the

effective N is decreased, as given by NAC = N - K = NS,

which leads to a higher voltage gain and a larger GBW.

However, if the input signal exceeds the maximum

dynamic range of the differential pair, the cross-pair loses

its function as the current in it decreases to zero, and at this

moment, the effective N remains the same, as indicated by

NDY = N which brings a higher SR. Therefore, the varia-

tion of the effective N under different operation mode

provides a preliminary possibility to meet the requirements

of AC, DC and transient performance simultaneously.

3 The transmission characteristics of the linear-

nonlinear adaptive current mirror

3.1 Nonlinear status factor

Figure 2 shows the linear-nonlinear adaptive current mirror

obtained by removing the upper transistor in the output

branch of the classical wide-swing cascode current mirror,

where transistors M1 and M2 can operate in different

regions.

As shown in Fig. 2, supposing that P is the scaled W/L

ratio between M1 and M3, and N is the ratio between

M1 and M2. The overdrive voltage DMB = Vbn - VTN =

(2Ibias/kB)1/2 where kB, Ibias are the gain factor and the

biasing current of the biasing transistor MB, respectively.

Thus, a = DM1/DMB and g = VDS1/DMB can be defined as

the status factors of the current mirror in this paper. Under

`

M10

M0

M1 M2

M4 M3 M7 M8 M5 M6

VDD

Vin+Vin-

M9

CL

Vo

1 : N : K K : N : 1

Cross-pair

Vbp

A B

Fig. 1 Classical OTA with cross-pair

M1 M2

N : 1

Iin

Vbn

P:

1

Io

M3

MB

Vbn

Ibias

Fig. 2 Linear-nonlinear adaptive current mirror

256 Analog Integr Circ Sig Process (2012) 71:255–263

123

the critical point where M1 is just at the edge of the triode

resistance region, a is equal to g. When a[ g, the current

mirror operates in the nonlinear mode, where M1 enters

into the triode resistance region while M2 remains in sat-

uration region. Therefore, a larger current is obtained at the

output stage of current mirror. Totally, in nonlinear oper-

ation mode, the larger a or the smaller g, the larger output

current.

According to the continuous equation of quiescent cur-

rent through M1 and M3

Iin ¼ kin1D2MB ag� 1

2g2

� �¼ 1

2kin3D

2MBð1� 1gÞ2 ð1Þ

Then we can get the relationship between the status

factors a and g, as given by

a ¼ 1

2P12 þ P� �

gþ 1

g� 21

� �ð2Þ

where 1 is the substrate biasing coefficient. If the current

mirror is set in the linear-nonlinear critical point by

suitable static current Iin0, a0 = g0 = 1/(1?HP) can be

derived from (2) by the constraints of DM1 = VDS1, where

subscript 0 in status factors indicates that the corresponding

parameters are in static conditions. For MOSFET in strong

inversion condition, d times of current increasing will make

overdrive voltage increase Hd times. Since DMB =

DM3 ? DVTN ? VDS1, where DVTN ? VDS1 = 1VDS1 =

1gDMB and DM3 = (2Iin/k3)1/2, DM3 = (1 - 1g)DMB is

finally obtained. When Iin changes within the scope of dtimes, the status factor g and a can be respectively written

as

g ¼1�

ffiffiffidp� 1

� � ffiffiffiPp

=1

1þffiffiffiPp ð3Þ

a¼ 12P

1þ P

12

1�ffiffiffidp�1

� � ffiffiffiPp

1þffiffiffiPp þ 1þ

ffiffiffiPp

1�ffiffiffidp�1

� � ffiffiffiPp �2

24

35

ð4Þ

3.2 The current transmission characteristics related

to status factors

According to saturation current in the output transistor

driven by the overdrive voltage DM1, we obtain

Io ¼1

2koutðVGS1 � VTNÞ2

¼ 1

2k3 Vbn � 1VDS1 � VTNð Þ2k1

k3

kout

k1

D2M1=D

2MB

1� 1V2DS1=D

2MB

� �

¼ Iin1

NP

a1� 1g

2

¼ Iin1

NbDC

ð5Þ

where bDC is the additional multiplied factor due to

nonlinear effects within the current mirror in static mode,

and can be expressed as

bDC ¼ Pa

1� 1g

2

ð6Þ

The AC small signal current transmission coefficient can

be deduced from Eq. 5, which is

oIo

oIin¼ 1

NbDC þ Iin

obDC

oaoaoIin

¼ 1

NbAC ð7Þ

where bAC is the additional multiplied factor due to

nonlinear effects under AC mode, which is definitely larger

than bDC because qbDC/qIin is positive. Therefore, the

current transmission multiplication under AC mode is

much more evident. If qbDC/qa and qa/qIin have been

derived from above equations, bAC can be finally given as

bAC ¼ Pa

1� 1g

2

ð1þ mÞ ¼ ð1þ mÞbDC ð8Þ

Where m can be expressed as

m ¼ 21

aþ 1

Pg2

ðPagþ 1g� 1Þð1� 1gÞ

� �

� ½a� ð1=2Þg�ðPagþ 1g� 1Þ2Pagþ 1g� Pg2 � 1ð Þ

ð9Þ

Define the DC multiplied factor under the large signal

condition as bDY. In the critical point with d = 2, when

neglecting the substrate biasing effect we can obtain

bDY = 2 from (3), (4), (6), which is not large enough.

When d increases to 4, theoretically, the minimum g or

the maximum a will bring an upper limit of bDY. However,

the gate voltage of the output transistor is restrained by the

circuits structure, the supply voltage and the input common

mode voltage, so that the actual maximum a is limited by

the maximum gate voltage VGS1,max, and the maximum

multiplied factor in large signal condition is limited to

bDY,max, where bDY,max = bDY(amax, gmin).

4 The model of new OTA circuit

Replacing the linear current mirror with the linear-non-

linear adaptive current mirror in conventional OTA with

cross-pair, the new OTA is obtained as shown in Fig. 3.

The performance improvement for this new OTA will be

discussed in detail as follows.

4.1 The model of the multiplied factor

According to the definition of circuit transconductance

Gm = (qIo/qIo1)(qIo1/qVid), where qIo1/qVid = gm1,2 is the

Analog Integr Circ Sig Process (2012) 71:255–263 257

123

transconductance of the input differential stage, and

qIo/qIo1 is the current transmission coefficient in AC mode.

Since the cross-pair is still effective, the linear factor N

switches to NAC(=NS) from NDC(=NT), so that the total

transconductance of the circuit can be expressed as

Gm ¼ gm1;21

NACbAC

¼ gm1;2

NT

NT

NSbAC

¼ ðaACbACÞGm;ref ð10Þ

where Gm,ref = gm1,2/NT is the transconductance of

that referenced OTA. The multiplied factor for trans-

conductance consists of the linear factor aAC = NT/NS and

the nonlinear factor bAC. If the second pole located at node

A(B) is much higher than Gain Bandwidth, we can obtain

GBW = Gm/CL, thus the multiplied factor of GBW is as

large as aACbAC. The corresponding DC gain of the new

OTA changed by Gm and static output current variation can

be expressed as

AV ¼Gm

kIo¼ aACbACGm;ref

kbDCIo;ref¼ aAC

bAC

bDC

AV ;ref ð11Þ

where AV,ref = Gm,ref/kIo,ref is the DC gain of that refer-

enced OTA and k is the channel length modulation

coefficient.

Under large signal condition, bDC increases significantly

with the stronger non-linear effect, while the cross-pair is

invalid because the large input signal exceeds its maximum

dynamic range, and the linear transmission coefficient

returns back to its original N. Assuming the referenced

slew rate (SR) and output current are presented as

SRref = Io,ref/CL, Io,ref = IB/NT, respectively. Then the

output current in the new OTA increases to Io = (bDY/

NDY)IB, as a result the SR of the new circuit is

SR ¼ Io

CL¼ bDY

NT

NDY

IB=NT

CL

¼ ðaDYbDYÞSRref ð12Þ

where aDY = NT/NDY = 1?K/N, since K \ N, then

aDY,max \ 2, so the multiplied factor of SR is achieved

mainly by bDY.

4.2 The limitation of the linear transmission multiplied

factor aAC,lim

As shown in Fig. 3, the dominant pole is located at the

output stage under the large load capacitance condition,

and the second pole is formed at node A(B) by its relative

large parasitic capacitance Ca(or Cb) and output imped-

ance. Under nonlinear mode when transistor M6a operates

in the triode resistance region, the transconductance of M6a

is gm6a = kM6ag0DMB. Taking the back-gate effect indi-

cated by e into consideration, the total transconductance of

M4 is enlarged to gm4 ? gmb4 = egm4, where

gm4 = km4(DMB - 1VDS6). The output admittance of M6a

is gd6a = kM6a(a0 - g0)DMB. The transconductance of

M6b and M8 compensate each other under AC condition,

while their output admittance is still increased, so the total

output admittance of M6 and M8 is aACgd6a. Because

gd3(or gd4) � gm6a, gd3 can be neglected. Since

kM6a = kM10/aAC = kM4/aAC, pA(pB) can be finally written

as

pa ¼ pb �kM10DMb

Ca

g0

aAC1� a0 � g0

dþ a0 � ð1þ d1Þg0

� �

¼ ga0

Ca

g0

aACð1� q0Þ ð13Þ

where ga0 = kM10DMB is the normalized transconductance

of the referenced transistor M9(or M10), and q0 = (a0 -

g0)/[1 ? a0 - (1 ? 1)g0]. With the increase of nonlinear

degree, a smaller g0 will make q0 increase, so the second

pole is decreased. By the constraints of pa C 2GBWmax

with PM [ 60�, we can obtain the upper limit of the linear

transmission multiplied factor aAC,lim as follow

aAC;lim�ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffig0ð1� q0Þ

2bAC

ga0

gmp1;2

CL

Ca

sð14Þ

where gmp1,2 is the transconductance of the differential

pair. Under the critical point when bAC = 1 and q0 = 0,

aAC,lim & 20 if g0ga0 & gmp,12 as well as CL/Ca & 103.

The stronger nonlinear effect, the smaller aAC,lim, when

CL/Ca keeps constant.

4.3 The limitation of the nonlinear multiplied factor

bDY,lim

The peak SR is controlled by the maximum overdrive

voltage of transistor M6(DM6,max), which is DM6,0 =

a0DMB under the static condition. Set the source voltage

of the differential pair as VS, which gives VS =

`

M12

M0

M1 M2

M3 M4

M9 M5a M7 M8 M6a M10

VDD

Vin+Vin-

Vbn Vbn

M5b M6b

M11

MB1b

MB1a

MB0

Vbp

CL

Vo

1 : Ns : K : K K : K : Ns : 1

A B

Fig. 3 The new OTA with the integration of linear-nonlinear

adaptive current mirror and cross-pair

258 Analog Integr Circ Sig Process (2012) 71:255–263

123

Vcom ? DMp1,max ? VTP, where Vcom is the common-

mode voltage of input signal, and DMp1,max is the overdrive

voltage of the differential pair driven by tail current IB. The

differential pair works in triode resistance region under

large signal situation, so that DM6,max & VS - VTP

because its VDS can be neglected. To ensure that the tail

current transistor is always in the saturated region,

VS,max = VDD - DMp0, where DMp0 is the overdrive volt-

age of the tail current transistor. VTN and VTP are the

threshold voltages of NMOS and PMOS, respectively.

Extracting from (5) we obtain Io = (bDC/N) Iin, so that the

static output current is Io,0 = (bDC,0/NT)(IB/2), and the

maximum output current is Io,max = IBbDY/(NS ? K) when

the output transistor keeps in saturation region. According

to Io,max/Io,0 = (DM6,max/DM6,0)2 and DM6,0 = a0DMB, we

can obtain

bDY ;lim ¼bDC;0

2aDY

VS � VTN

a0DMB

2

ð15Þ

When VS & VS,max, bDY given by (15) will be

extraordinary large without considering the output current

limitation when the output transistor enters into triode

resistance region. If the delay at node A(B) cannot be

neglected, when the gate voltage of the input stage

increases to a larger VS, the output voltage decreases

significantly during this delay time, which makes the

output transistor enter into triode resistance region, so that

the output current is actually decreased and limited. When

the delay of the input stage is comparable to that of output

stage, the Eq. 15 is not accurate. To simplify the analysis,

the peak current of the output stage is regarded as the

current when the output transistor is at the edge of

saturation region. To some extent, the relative delay

between input and output stage as indicated by coef-

ficient s, can be described by the ratio of the peak SR at the

output (SRout,max) and the input (SRin,max), that is

s ¼ tin;delay

tout;delay¼ SRout;max

SRin;max

¼ Io;max=CL

Iin;max=Ca¼ aDY

NTbDY

Ca

CLð16Þ

Therefore, if the coefficient s is relative large, the

effective gate voltage corresponding to the peak output

current is given by

VS;eff ¼VS

1þ s1þ s

VGS10;0

VS

¼ VS

1þ s1þ s

a0DMB þ VTN

VS

ð17Þ

In this situation, Eq. 15 becomes more accurate when

VS is replaced by VS,eff as given in (17), where the more

accurate bDY,lim can be calculated under large transient

signal condition. As can be seen, bDY,lim cannot be large

enough for the limited VS,eff.

5 Model verification

In order to verify the validity and accuracy of the model, the

new OTA shown in Fig. 3 is implemented in CSMC

0.18 lm CMOS technology. The supply voltage VDD, the

load capacitance CL, the fixed tail current IB, the substrate

biasing factor 1, the back-gate factor e, and the gate capac-

itance per area Cox are 3.3 V, 30 pF, 9.35 lA, 1.35, 1.2,

5.26 fF/lm2, respectively, and the designed Ca(Cb) is 25 fF.

The status factor a and P are set as 0.75 and 1, respectively.

Linear transfer coefficients, status factors under the critical

point and multiplied factors are showed in Table 1.

Under different status and parameters variation condi-

tion, the theoretical values of the designed OTA on DC,

AC and transient response are compared with the SPICE

simulation results in details. The quiescent current, DC

gain, GBW and SR of the referenced conventional OTA by

simulation is 19.1 lA, 48.6 dB, 316 kHz and 0.321 V/lS,

respectively.

The linear factors remain constant when considering the

impact of nonlinear status factors, as shown in Table 1.

Figure 4 shows the relationship between the nonlinear

status factor a with the biasing voltage and the tail current.

So both the biasing voltage and the tail current can be used

to set the nonlinear status factor. amax can be obtained from

the intersection of the bDY and the bDY,lim curve, as shown

in Fig. 5. When a\ amax, thus bDY \bDY,lim, which

means that it’s necessary continuing to increase a to obtain

a higher SR. When a[ amax, due to the increased s which

makes bDY,lim \ bDY, the SR will decrease on the contrary.

Figure 6 shows the relationship between a with DC, AC

and large signal performance with a fixed aAC = 3 because

if a grows large with a large aAC, the PM may decrease to

60� below. There is a certain DC offset between the the-

oretical values and the SPICE simulation results of the

static current because the model has neglected the channel

length modulation effect.

The impact of linear coefficients on circuit performance

is shown in Fig. 7.

Table 1 Linear transfer coefficients and status factors under the critical point

N K NT NS aAC aDY a0 g0 bDC,0 bAC,0 bDY

4/7 3/7 1 1/7 7 7/4 0.426 0.426 1.000 1.002 2.364

Analog Integr Circ Sig Process (2012) 71:255–263 259

123

In Fig. 7(a) and (b), the status factor a is fixed at about

0.52. The relationship between aAC and AC performance is

linear approximately, and the quiescent current doesn’t

change with aAC because a is unrelated with aAC. The

increase of SR is not significant because the variation of the

W/L ratio of the transistors M5(M6) and M7(M8) is very

small. P represents the W/L ratio of the transistors

M3(M4), and its influence on the performance of the OTA

is similar with that of a.

When the DMB is fixed, increasing the tail current IB not

only leads to the increase of the output current and trans-

conductance directly, but also brings to the increase of a,

which further improves the circuit performance. However,

the quiescent current is increased at the same time, as

shown in Fig. 8.

As can be seen, the simulation results match well with

the theoretical model under different conditions. The

maximum error of the gain, GBW, SR and the quiescent

current between theoretical model calculation and the

SPICE simulation are 15, 20, 15 and 11%, respectively.

The new OTA is designed and implemented according

to the model under the constraints of PM = 60�. Table 2

shows the size of transistors of the new OTA. The gain of

Relationship between α with IB and ΔM3/ΔMB

0

0.5

1

1.5

5.61 7.48 9.35 11.22 13.08

IB(µA)

α

ΔM3/ΔMB=0.5

ΔM3/ΔMB=0.56

ΔM3/ΔMB=0.61

Fig. 4 Static a determined by biasing voltage and IB

Relationship between α with βDY and βDY,lim

0

50

100

150

200

0.43 0.52 0.64 0.8 0.853 0.882 0.892 0.944 0.972 1

α

βDY

βDY,lim

Fig. 5 Relationship between a with bDY and bDY,lim

Relationship between α with AV and GBW

50

55

60

65

70

75

0.4337 0.5233 0.6427 0.7981 1

α

AV(d

B)

0

2

4

6

8

10

GB

W(M

Hz)

Anal.Av

Sim.Av

Anal.GBW

Sim.GBW

Relationship between α with SR and IQ

0

10

20

30

40

0.4337 0.5233 0.6427 0.7981 1

α

SR

(V/µ

S)

0

10

20

30

40

I Q(µ

A)

Anal.SR

Sim.SR

Anal.IQ

Sim.IQ

(a)

(b)

Fig. 6 a Relationship between a with AC performance. b Relation-

ship between a with DC parameters and large signal performance

Relationship between αAC with AV and GBW

5860

6264

6668

70

5 6 7 8 9 10

αAC

AV (d

B)

01

23

45

6

GB

W (

MH

z)

Anal.Av

Sim.Av

Anal.GBW

Sim.GBW

Relationship between αAC with SR and IQ

5

5.5

6

6.5

7

7.5

5 6 7 8 9 10

αAC

SR

(V

/µS

)

20

21

22

23

24

25

I Q (µ

A)

Anal.SRSim.SRAnal.IQSim.IQ

Relationship between P with AV and GBW

55

60

65

70

0.41 0.5 0.64 0.875 1.08 1.25 1.4

P

AV (d

B)

0

2

4

6

8

GB

W (

MH

z)

Anal.Av

Sim.Av

Anal.GBW

Sim.GBW

Relationship between P with SR and IQ

0

10

20

30

40

0.41 0.5 0.64 0.875 1.08 1.25 1.4

P

SR

(V

/µS

)

0

10

20

30

40

I Q (µ

A)

Anal.SR

Sim.SR

Anal.IQ

Sim.IQ

(a)

(d)

(c)

(b)

Fig. 7 a Relationship between aAC with AC performance. b Rela-

tionship between aAC with DC and large signal performance.

c Relationship between P with AC performance. d Relationship

between P with DC and large signal performance

260 Analog Integr Circ Sig Process (2012) 71:255–263

123

the new OTA is 71.6 dB and GBW is 6.5 MHz under

30 pF load capacitance as shown in Fig. 9(a). Fig-

ure 9(b) shows the transient performance of the new OTA

and its peak positive SR is 12 V/lS and peak negative SR

is 13 V/lS. The whole OTA consumes 29 lA quiescent

current. Compared to the referenced OTA in Table 2, the

multiplied factors of the gain, GBW, SR are 14, 20.6 and

42, respectively. The quiescent current is only increased to

1.5 times of the referenced OTA.

The experiment results for AC and transient character-

istics of the chip when configured as a buffer are shown in

Fig. 10. The upper curve is the input voltage and the lower

one is the output voltage. When the frequency of the input

sinusoidal signal (the amplitude is 0.6 V) is quite low, the

output can fully follow the input signal with the same

amplitude and no phase delay. When the frequency of the

input sinusoidal signal increases to 6 MHz, the amplitude

of the output decreases to the 0.707 times of that the input

and 45� phase delay appears as shown in Fig. 10(a).

According to the fact that the -3 dB frequency of the

buffer (close-loop) is the GBW of the OTA in open-loop,

thus the GBW of the OTA can be obtained to be 6 MHz

indirectly. Figure 10(b) shows the SR of the OTA. The

input signal is a step signal from 0.9 to 1.5 V with a 40 nS

edge. The tested positive and negative SR both are 14 V/lS

approximately. The DC gain tested is 73 dB. The practical

test results are close to the simulation results, so the model

presented in this paper can satisfy the analysis of nonlinear

characteristic and the precision of engineering design.

Table 3 compared the results of this work with those of

other works, where [4, 5] showed the simulation results and

[10] and our work are experiment results. In order to

compared the different results more clearly, we introduce a

parameter of Q to represent the comprehensive perfor-

mance of the OTA, which is expressed as

Q ¼ AV � GBW � SR

AVr � GBWr � IQ=CLð Þ ð18Þ

where AVr(= 60 dB), GBWr(= 10 MHz) and IQ/CL are the

scaled values of DC gain, GBW and SR, respectively. It’s

obvious that the comprehensive performance of the

Relationship between IB with AV and GBW

55

60

65

70

5.61 7.48 9.35 11.22 13.08

AV (d

B)

024681012

GB

W (

MH

z)

Anal.Av

Sim.Av

Anal.GBW

Sim.GBW

Relationship between IB with SR and IQ

0

10

20

30

40

5.61 7.48 9.35 11.22 13.08

IB (µA)

SR

(V

/µS

)

0

10

20

30

40

50

I Q (µ

A)

Anal.SR

Sim.SR

Anal.IQ

Sim.IQ

IB (µA)

(a)

(b)

Fig. 8 a Relationship between IB with AC parameters. b Relationship

between IB with DC and large signal parameters

Table 2 Size of transistors used in the new OTA in Fig. 3

Transistor W/L (lm/lm) Transistor W/L (lm/lm)

M0 (2/2) 9 20 M7 (0.7/0.7) 9 3

M1 (10/2) 9 3 M8 (0.7/0.7) 9 3

M2 (10/2) 9 3 M9 (0.7/0.7) 9 7

M3 (7/1) 9 1 M10 (0.7/0.7) 9 7

M4 (7/1) 9 1 M11 (15/1.5) 9 4

M5a (0.7/0.7) 9 1 M12 (15/1.5) 9 4

M6a (0.7/0.7) 9 1 MB0 (2/2) 9 10

M5b (0.7/0.7) 9 3 MB1a (4.3/1) 9 1

M6b (0.7/0.7) 9 3 MB1b (4.3/1) 9 1

Fig. 9 a The AC performance of the new OTA. b The transient

performance of the new OTA

Analog Integr Circ Sig Process (2012) 71:255–263 261

123

proposed OTA has been improved greatly compared to the

other works except Ref. [5] which is at the same level.

However, Ref. [5] employs a more complex current feed-

back circuit at the cost of much more chip area and

consuming considerable dynamic power. Due to compli-

cated relationship between circuit’s performances with

corresponding parameters, the characteristics of the pro-

posed OTA in DC, AC and transient can be further

improved if optimization design considered.

6 Summary

This paper proposed a new OTA combinating linear-non-

linear adaptive current mirror and local cross-pair. It breaks

the inherent constraints between static and dynamic per-

formance of the conventional OTA, and enhances the

performance of the amplifier significantly, especially in

low power condition. Compared to the conventional one,

the multiplied factors of the gain, GBW, SR of proposed

OTA achieve 14, 20.6 and 42, respectively, and DC biasing

current nearly unchangeable. Besides, according to the new

model of the circuit, this paper compared the analytical

calculation values with the SPICE simulation results.

Moreover, the experiment results verified the validity and

accuracy of the model, which provides an effective guid-

ance for the optimization of this new OTA.

References

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Fig. 10 a Sinusoidal signal following characteristics of the imple-

mented chip. b SR characteristics of the implemented chip

Table 3 Summary of performance and comparison with other works

Parameter [4] [5] [10] This work

CMOS technology 0.35 lm 90 nm 0.5 lm 0.18 lm

Supply voltage (V) 3 1.2 3.3 3.3

Quiescent current (IQ) (lA) 273 48.7 67 29

Load capacitance (pF) 10 10 80 30

DC gain (AV) (dB) 62 79.2 37 73

GBW (MHz) 46 7.6 3.27 6

PM (simulation) 64� 83.5� 56� 60�Positive SR (V/lS) 70.8 32 10 14

Negative SR (V/lS) -70.8 -32 -15 -14

Q 15.0 45.5 0.4 38.8

262 Analog Integr Circ Sig Process (2012) 71:255–263

123

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Jin Wu was born in Jiangsu

Province, China in 1965. He

received B.S., M.S. and Ph.D.

degrees in Electrical Engineering

from Southeast University, China,

in 1988, 1991, 1997 respec-

tively. His research interests are

low-power high-speed configura-

ble analog integrated circuit

design, fully integrated LDO,

Charge pump and DC–DC design

in Power Management Unit for

SoC system application. He is

currently with Integrate School of

Wuxi Branch in Southeast Uni-

versity, Wuxi, China.

Ma Ke was born in Jiangsu

Province, China in 1987. He

received the B.S. degree in

Information Engineering from

University of Science and Tech-

nology, Beijing, in 2009 and is

currently M.S. student of South-

east University. His research

interest is low-power high speed

configurable operational ampli-

fier design. He is currently with

IC School of Wuxi Branch in

Southeast University, Wuxi,

China.

Ning Qu was born in Shandong

Province of China, in 1986. He

received the B.S. degree from

Shandong Normal University,

Jinan, China, in 2009. He is

currently M.S. of Analog Inte-

grated Circuit Design in South-

east University, Wuxi, China.

His research interests include

analog circuit design, BGR and

charge pump design.

Weiwei Zhang was born in

Jiangsu Province, China in

1988. She received the B.S.

degree in Information Science

and Engineering of Southeast

University in 2010, and is cur-

rently M.S. student of IC School

at Southeast University. Her

research interests are analog and

digital integrated circuit design,

amplifier design, and low-power

device.

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