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ECE 511 DESIGN PROJECT

Design of CMOS Fully-differential Operational

Transcondcutance Amplifier

Abhijit Kuvar – 001081139

Group 4

North Carolina State University

Honor Pledge

I, Abhijit Kuvar have neither given nor received unauthorized aid for this project.

- 12/7/2013

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INDEX

Executive Summary

1. Circuit Design

1.1 Design Results

1.2 Design Approach

1.3 Gain-boosting amplifiers

1.4 Common Mode Feedback Circuit

1.5 Compensation

1.6 Supply Independent Biasing

1.6.1 Current Generator with start-up circuit

1.6.2 Voltage Bias Generator

2. Simulation Results

2.1 Frequency Response (Gain, Phase Margin)

2.2 CMRR (Common Mode Rejection Ratio)

2.3 PSRR (Power Supply Rejection Ratio)

2.4 Input Common Mode Range

2.5 Output Swing

2.5.1 Peak-to-peak Differential Swing

2.5.2 Single-Ended Output Swing

2.5.1.1 Positive Output (Outp)

2.5.1.2 Negative Output (Outn)

2.6 Noise

2.7 Slew Rate and Settling Time

2.8 Power Dissipation

Conclusion

References

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Executive Summary

Design for the fully-differential operational transconductance amplifier (OTA) was implemented

using a folded cascode operational amplifier with PMOS differential pair input. The required gain

was achieved by implementing the gain-boosting amplifiers with OTA. The common mode

feedback circuit (CMFB) was implemented using series-shunt topology. The design specifications

were met except for output swing. The overall design was aimed for wider GBW product, higher

phase margin and low power design (almost half of 6mW)

1. Circuit Design:

1.1 Design Results:

Parameter Required Specification Achieved Values

Low Frequency Gain 85 dB 86.475 dB

Gain-bandwidth product >180 MHz 602.56 MHz

Phase Margin >75 deg, for unity gain

feedback, no external load

79.06 deg

Settling time (1% of

final value)

<90 nsec with 3pF external cap

load

89.32 ns

Output Swing 0.85 V-pk-to-pk single-ended

1.7 V-pk-to-pk differential

(ppd)

0.655 V pk-to-pk single ended

1.59 V pk-to-pk differential

(ppd)

Input common-mode

range

At least 0.8-V overlap with

output signals

0.935 V overlap with output

signals

CMRR >120 dB 134.01 dB

PSRR+ >120 dB 282.76 dB

Supply Voltage 1.8 V 1.8 V

Power dissipation Pdiss < 6mW (as low as

possible)

3.28 mW

Slew rate > 20 V/usec 22.79 V/µsec

Input-Referred Noise

Voltage Floor < 15 nV/√𝐻𝑧 in white portion.

Also, in table please report the

1/f corner frequency.

14.98 nV/√𝐻𝑧

1/f corner frequency–102.8 MHz

1.2 Design Approach:

The folded cascode design topology for design of operational transconductance amplifier has been

considered from the onset of the project. The choice for folded cascode topology was clear because

of its high common mode input range and high output swing. The simple folded OTA was designed

and its single ended output was tested. The single ended was output was around 58 dB which was

still lesser than gain specification required. The additional gain was obtained by implementing

gain boosting amplifiers. The gain of folded cascode topology depended on gm and ro of input

PMOS differential pair, ro of bottom NMOS pair and intrinsic gain of upper PMOS pairs.

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The sizing of PMOS and NMOS was determined by gain requirements. The sizing of the gain

boosting amplifiers was also determined in the same fashion. The OTA uses PMOS differential

pair to provide for higher slew rate. The OTA is sized in such a way that magnitude of currents in

lower NMOS pair is greater than PMOS tail current provided. This kind of design takes care of

the worst case situation i.e. if all the current is drawn from one leg of input rails to one side.

After implementing OTA with gain-boosting amplifiers and determining the sizes, all the

MOSFETs were sized proportionately i.e. their width and length were sized in proportion with

each other just for the sake of convenience that FET sizing, if required to be changed, can be done

through ADL window. For all the schematics below, w = 40µm and l = 240nm

Fig. 1 - OTA Schematic

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Fig. 2 - Schematic: Basic Op-Amp

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Fig.3 - DC Operating Points: Basic Op-Amp

1.3 Gain-boosting amplifiers

The additional gain of around 28 dB was achieved by inserting gain-boosting amplifiers for PMOS

and NMOS pairs in the basic OTA. Gain-boosting amplifiers were biased by voltage bias

generators and the values were determined so that all the CMOS in saturation. Values of ‘Vsetn’

and ‘Vsetp’ for gain-boosting amplifiers were selected in order to implement wide swing

operation. Simple differential amplifier topology of gain-boosting amplifier was only able to

provide 18 dB of gain. In order to improve the gain, a cascode stage was implemented at the output.

The NMOS gain-boosting amplifier takes input from the drain voltage of lowermost NMOS and

its output is applied to gate of NMOS above it. This adds as the cascaded effect for improving the

gain of the circuit. Topologically same is done for the PMOS pair and PMOS gain-boosting

amplifier was inserted. Gain-boosting amplifiers implement negative feedback loop which is made

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sure to be stable. Input common mode range of gain-boosting amplifiers is ensured to be in the

range of basic OTA.

Gain-boosting amplifier circuit increases capacitance between gate and source of the PM2 and

PM3 due to Miller effect. Capacitance increases by a factor of (1+A), where A is the gain of gain-

boosting amplifier leading to reduction in frequency of secondary pole which makes worsens the

phase margin of the circuit. For compensating this, the gain-boosting amplifiers are provided with

compensation, which is discussed in more detailed way in section 1.5

Fig.4 - Schematic: PMOS Gain-boosting amplifier

Fig.5 - DC Operating Points: PMOS Gain-boosting amplifier

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Fig.6 - Schematic: NMOS Gain-boosting amplifier

Fig.7 - DC Operating Points: NMOS Gain-boosting amplifier

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1.4 Common Mode Feedback Circuit (CMFB)

Any fully-differential circuit driving the active loads requires common mode feedback circuit.

CMFB circuit senses the common-mode voltage and compares it with a reference value via

differential pair. The topology implemented in series-shunt topology for CMFB (topology 4). This

topology only implements active loads thus reducing the power consumption required for CMFB

circuit.

The tail NMOSes of differential pair are biased by the gate voltages of lower NMOS pair. The

differential pair converts difference to a current which is fed to diode connected load. The diode

connected load is then used to bias the pair of top PMOSes in basic OTA, which actually is output

of CMFB circuit.

Fig.8 - Schematic: Common Mode Feedback Circuit

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Fig.9 - DC Operating Points: Common Mode Feedback Circuit.

1.5 Compensation

The circuit implements four gain-boosting amplifiers and one CMFB circuit, all of them are

feedback networks. Addition of feedback network deteriorates the stability of the network and

hence is needed to be compensated for getting adequate phase margin. As discussed in section 1.3,

miller effect worsens phase margin in main OTA and thus compensation has to be provided at the

output of the basic OTA. It is made sure that cross-over frequency of the gain-boosting amplifier

lies between 3dB frequency and crossover frequency of the basic OTA.

Gain-boosting amplifiers are compensated with 300fF capacitors and main OTA with 150fF

capacitors at both the outputs. Common mode feedback network is also compensated by

compensation capacitor of main OTA.

1.6 Supply Independent Biasing

1.6.1 Current Generator with start-up circuit.

The simulation was initiated with an ideal current source and the current was mirrored through the

circuit to achieve required specifications. After many specifications were met, the current source

was replaced with current generator. Constant-gm biasing technique is used for generating

reference current. This current is generated by adjusting gate-to-source voltages and value of

resistance and implementing bootstrapping technique. It is made sure that dc-biasing points of

OTA, gain-boosting amplifiers and CMFB remain almost the same after introduction of current

generator in the circuit. A start-up circuit is implemented with PMOS and NMOS tied.

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Fig.10 - Schematic: Current Generator

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Fig.11 - DC Operating Points: Current Generator

1.6.2 Voltage Bias Generator

Gain-boosting amplifiers and common mode feedback network require range of biasing voltages

in order to keep them in saturation and function properly. During initial design steps, external

supply voltages were provided for the biasing. Voltage bias generators are employed to generate

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voltages as close possible by changing sizing of the diode connected NMOSes and PMOSes.

Voltage bias generator only uses supply voltage Vdd to generate these voltages.

Fig.12 - Schematic: Voltage Bias Generator

Fig.13- DC Operating Points: Voltage Bias Generator

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2. Simulation results

2.1 Frequency Response (Gain, Phase Margin)

Fig.14 – Frequency Response

The low frequency gain as seen from the graph is 86.475 dB and unity gain frequency is 602.56

MHz. The phase margin as observed is 79.06 degrees.

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Fig.15 – Frequency response of CMFB

As seen from the diagram, phase margin of CMFB is 131.14 degrees thus, ensuring that feedback

loop is stable.

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2.2 CMRR (Common Mode Rejection Ratio)

Fig.15 – CMRR

As seen from the graph, M8 shows CMRR which shows that low frequency CMRR is 134.01 dB

which is above 120 dB.

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2.3 PSRR (Power Supply Rejection Ratio)

Fig. 16 – PSRR

As seen from graph, it can be seen that PSRR of the OTA for the low frequency is 282.76 dB

which sits comfortably above required specification of 120 dB.

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2.4 Input Common Mode Range:

Fig.17 – Input Common Mode Range

For plotting the input common mode range we sweep the Vcm and obtain the frequency response.

From the simulation and graph it was seen that the range for which the gain remains within 6dB

of the maximum gain is 0 to 1.12 V.

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2.5 Output Swing

2.5.1 Peak-to-peak Differential Swing

Fig.18 – Differential Output Swing

The output swing is plotted by sweeping value Vdc at the differential over a small range and

differential gain is plotted. Voltage range for which the gain remains within 6dB of maximum gain

is 1.59 V (pk-pk) fully differential. This does not meet the required specification. The probable

reason for this might be higher value of currents due to which Vdsat of PMOSes might be

considerably high, thus failing to achieve the required output swing range.

The efforts were made to improve the output swing by changing Vset voltage given to CMFB but

if Vset was increased above a certain critical value, -6dB horizontal trace was not able to intersect

the differential output. This is the maximum output swing that was possible by this OTA.

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2.5.2 Single-Ended output swing

2.5.2.1 Positive output (Outp)

Fig.19 – Single ended output swing (Outp)

Single ended swing obtained = 0.655 V

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2.5.2.2 Negative output (Outn)

Fig.20 – Single-ended output swing (Outn)

Single ended swing obtained = 0.633 V

We get the DC output voltage 0.98 V and swing of 1.59 V (pk-pk) this means the output is

swinging 0.795 V about DC value i.e. between 0.185 and 1.775. The input common mode range

is 0 to 1.12 V, thus overlap of 0.935 V is obtained which is above design specification of 0.8 V.

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2.6 Noise

Fig.21 - Noise

The noise response of the OTA is done by calculating the equivalent input noise and plotting it on

log scale. The noise floor comes out to be 14.98 nV/√𝐻𝑧.

1/f corner frequency comes out to be about 102.8 MHz.

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2.7 Slew Rate and Settling Time

Fig.22 – Slew Rate and Settling Time

Using the 3pF external cap load, the slew rate was calculated to be around 22.79 V/µsec which is

above required specification of 20 V/µsec. The settling time was found to be 89.32 ns which is

below requirement of 90ns at 1% of the value.

2.8 Power Dissipation

The power consumption by OTA should be as minimal as possible. Power dissipation of this OTA

was 3.28 mW which is significantly lower than requirement of < 6mW.

signal OP("/Vdd" "??")

i -1.82389m

pwr -3.28301m

v 1.8

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Conclusion

Design of an operational transconductance amplifier was successfully implemented meeting all

design specifications except output swing. The main aim of the design was for higher GBW

product, low power consumption and high phase margin. The conclusion that could be drawn from

this is OTA and CMFB could have been designed better to improve output swing.

The project gave great insights into second order effects on circuit operation by using superior

simulation package of Cadence Virtuoso.

References

ECE 511 Fall 2013 Analog Integrated Circuits course material by Dr. Brian Floyd