Mixed-Signal Simulation User Guide

Mixed-Signal Simulation User GuideVersion J-2014.09, September 2014

ii Mixed-Signal Simulation User Guide

Copyright and Proprietary Information Notice© 2014 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.

Destination Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them.

DisclaimerSYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

TrademarksSynopsys and certain Synopsys product names are trademarks of Synopsys, as set forth athttp://www.synopsys.com/Company/Pages/Trademarks.aspx.All other product or company names may be trademarks of their respective owners.

Synopsys, Inc.700 E. Middlefield RoadMountain View, CA 94043www.synopsys.com

J-2014.09

http://www.synopsys.com/Company/Pages/Trademarks.aspx

http://www.synopsys.com

Contents

Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi

Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi

1. Getting Started with Mixed-Signal Simulation . . . . . . . . . . . . . . . . . . . . . . 1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Three Mixed-Signal Simulation Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Verilog-SPICE (Flow #1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

VHDL/Verilog-SPICE (Flow #2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Verilog-AMS-SPICE (Flow #3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Preparing for a Mixed-Signal Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Donut Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Mixed-Signal Simulation Setup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Compiling and Running a Mixed-Signal Design. . . . . . . . . . . . . . . . . . . . . . . . 8

Mixed-Signal Report Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

simv.msv Directory and Mixed-signal Report Files . . . . . . . . . . . . . . . . . 9hierarchy.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9interface_element.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mview.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11names_map.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11port.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12runtime_interface_element.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14through_net.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14use_cell_view.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Save and Restore Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Basic Save and Restore Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Running Multiple Simulations with Save and Restore . . . . . . . . . . . . . . . 16

Changing the Analog Configuration in the Middle of a Simulation. . . . . . . . . . 18

The ace reread command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Changes Allowed in the Configuration File . . . . . . . . . . . . . . . . . . . 19Changes in the SPICE Netlist Allowed with the reread Command . 20

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Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Meta-Encrypted SPICE Netlists in Mixed-Signal Design . . . . . . . . . . . . . . . . . 23

2. Running a Mixed-Signal Simulation with Verilog-AMS-SPICE . . . . . . . . . 25

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Running a Mixed-Signal Simulation in Verilog-AMS-SPICE . . . . . . . . . . . . . . 25

Compile Options Specific to Verilog-AMS-SPICE . . . . . . . . . . . . . . . . . . 26-ams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-ams_discipline logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-ams_iereport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Required Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Verilog Netlist Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Mixed-Signal Simulation Setup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Files Containing Connect Rule and Connect Module Definitions. . . . . . . 28

Compiling and Running the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Part I: Verilog-SPICE Mixed-Signal Simulations

3. Using Verilog-SPICE Mixed-Signal Features. . . . . . . . . . . . . . . . . . . . . . . . 33

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mixed-Signal Feature Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Verilog-top/SPICE-top Flows and Donut Configurations . . . . . . . . . . . . . 34

Multiple Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34SPICE View Selection for Multi-View Cells Under Verilog . . . . . . . . 35Verilog View Selection for Cells Under a SPICE Parent. . . . . . . . . . 35

Automatic Verilog Dummy Module Generation . . . . . . . . . . . . . . . . . . . . 35

Verilog-A Model Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Parameter Passing Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

XMR (Cross Module Referencing) Across Analog-Digital Boundary . . . . 37Logic XMR Access to Analog Nodes . . . . . . . . . . . . . . . . . . . . . . . . 37Real XMR Access to Analog Nodes . . . . . . . . . . . . . . . . . . . . . . . . 39$snps_force_volt() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39$snps_release_volt() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40$snps_get_volt() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40$snps_get_port_current() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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snps_above ( ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42snps_cross ( ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Interface A/D and D/A Signal Conversions . . . . . . . . . . . . . . . . . . . . . . . 44Cases Where A/D and D/A Converters are Not Inserted . . . . . . . . . 46

Signal Conversion from Verilog-to-SPICE and SPICE-to-Verilog. . . . . . . 49Converting Signal Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Dynamic Supply in Mixed-Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Converting Signal Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Creating a Resistance Map File . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Postlayout Simulation Through Back-annotation . . . . . . . . . . . . . . . . . . . . . . . 58

Using the SDF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Known Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Known Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4. Mixed-Signal Simulation in the Verilog-SPICE Flow. . . . . . . . . . . . . . . . . . 61

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Mixed-signal Setup Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Netlist-Related Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Identical Module/Subcircuit Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Case Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Method #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Method #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Method #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Netlist Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Simulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Port-Related Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Duplicate Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Parameterized Bus Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Creating a Mixed-Signal Simulation Control File . . . . . . . . . . . . . . . . . . . . . . . 72

Mixed-Signal Control Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

The a2d Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

The bus_format Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

The choose Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

The d2a command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

The duplicate_net_inst_name Command . . . . . . . . . . . . . . . . . . . . . . . . 85

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The e2r command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

The ie_activity_rpt Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

The insert_cell Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

The map_by_node Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

The mview_vlog_noportswap Command . . . . . . . . . . . . . . . . . . . . . . . . . 90

The optimize_shadowfile Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

The param_pass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

The port_connect Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

The port_dir Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

The print_ie_res Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

The print_thru_net Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

The r2e command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

The remove_d2a Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

The rt_a2d Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

The rt_d2a Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

The rt_e2r Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

The rt_r2e Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

The rmap_file Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

The shadow_file_dir Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

The spice_port_order_as_vlog Command. . . . . . . . . . . . . . . . . . . . . . . . 109

The spice_top Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

The use_spice Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

The use_verilog Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Summary of Mixed-Signal Simulation Commands. . . . . . . . . . . . . . . . . . 117

Known Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

5. Running a Mixed-Signal Simulation in the Verilog-SPICE Flow . . . . . . . . 121

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Setting Up the Simulation Environment for the Verilog-SPICE Flow . . . . . . . . 122

Version Compatibility Between Analog and Digital Engines . . . . . . . . . . 122Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Required UNIX Paths and Variable Settings . . . . . . . . . . . . . . . . . . 123


Compiling the Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Running the Simulation in the Verilog-SPICE Flow . . . . . . . . . . . . . . . . . . . . . 126

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Invoking the Interactive Mode with the UCLI Debugging Feature with Verilog-SPICE127

The ucli% ace Analog Interactive Commands . . . . . . . . . . . . . . . . . . . . . 128

DC Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Recompiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

6. Mixed-Signal Simulation Output and Display in Verilog-SPICE . . . . . . . . 131

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Capturing Analog and Digital Signals in the Output File(s) . . . . . . . . . . . . . . . 131

Generating an Analog Output File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Generating a Digital Output File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Generating a Unified Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Merged VPD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Part II: VHDL/Verilog-SPICE Mixed-Signal Simulation

7. Using the VHDL/Verilog-SPICE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

VHDL/Verilog-SPICE Flow Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Donut Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Multiple Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140View Selection for Cells Under a VHDL Parent . . . . . . . . . . . . . . . . 141View Selection for Cells Under a Verilog Parent. . . . . . . . . . . . . . . . 141View Selection for Cells Under a SPICE Parent . . . . . . . . . . . . . . . 141

Real Port Support at the Analog/Digital Boundary. . . . . . . . . . . . . . . . . . 142

Interface A/D and D/A Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Generating a Merged Output file for Analog and Digital Signals . . . . . . . 145

Known Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

8. Mixed-Signal Simulation in the VHDL/Verilog-SPICE Flow . . . . . . . . . . . . 147

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Input Netlist Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

VHDL and Verilog Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Transistor-level Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Using a VHDL Setup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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Using a Verilog Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Creating a Mixed-signal Simulation Control File for VHDL/Verilog-SPICE . . . 153

The use_vhdl Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

The use_verilog Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

The use_spice Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

9. Running a Mixed-Signal Simulation in VHDL/Verilog-SPICE . . . . . . . . . . . 157

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Installation Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Setting up the Simulation Environment for the VHDL/Verilog-SPICE flow. . . . 158

License. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159


Compiling the Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

The Design Analysis Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160Analyzing Verilog Files Using the vlogan Utility . . . . . . . . . . . . . . . . 161Analyzing VHDL Files Using the vhdlan Utility . . . . . . . . . . . . . . . . . 163

The Design Elaboration Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Running the Simulation in VHDL/Verilog-SPICE . . . . . . . . . . . . . . . . . . . . . . . 167

Simulation Time Resolution in VHDL/Verilog-SPICE . . . . . . . . . . . . . . . . 168

Interactive Simulation with UCLI using VCS-MX . . . . . . . . . . . . . . . . . . . 168

Back-Annotation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

10. Creating Verilog Wrappers in VHDL/Verilog-SPICE . . . . . . . . . . . . . . . . . . 169

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

The VHDL/Verilog-SPICE Autowrapper Utility . . . . . . . . . . . . . . . . . . . . . . . . . 169

Using the Autowrapper Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

11. Mixed Simulation Output and Display in VHDL/Verilog-SPICE . . . . . . . . . 177

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Generating an Analog Output File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Generating a Digital Output File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Generating a Merged VPD Output File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

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Part III: Verilog-AMS-SPICE Mixed-Signal Simulation

12. Mixed-Signal Simulation in the Verilog-AMS-SPICE Flow . . . . . . . . . . . . . 183

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Analog and Digital Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Understanding Analog and Digital Blocks in Verilog-AMS . . . . . . . . . . . . . . . . 184

Nets and Disciplines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

13. Using Multiple Views, Donut Partitioning and Connect Modules with Verilog-AMS-SPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Selecting Multiple Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Understanding Hierarchical Layering of SPICE and Verilog-AMS in a Design 190

Unsupported Features in Verilog-AMS-SPICE . . . . . . . . . . . . . . . . . . . . . . . . 191

Resolving Keyword Conflicts between SystemVerilog and Verilog-AMS . . . . . 192

Converting Signals with Interface A/D and D/A Connect Modules . . . . . . . . . 192

Identifying the Correct Connect Module. . . . . . . . . . . . . . . . . . . . . . . . . . 193

Understanding Connect Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

14. Preparing a Mixed-Signal Simulation with Verilog-AMS-SPICE . . . . . . . . 199

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Preparing a Mixed-Signal Simulation in Verilog-AMS-SPICE . . . . . . . . . . . . . 199

Files Containing Connect Rule and Connect Module Definitions . . . . . . . . . . 201

Part IV: Appendices

A. Mixed-Signal Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

B. Reserved Keywords. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

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Reserved Keywords for Verilog-SPICE and VHDL/Verilog-SPICE . . . . . . . . . 207

Reserved Keywords for Verilog-AMS-SPICE. . . . . . . . . . . . . . . . . . . . . . . . . . 210

C. Verilog/VHDL/HSIM VPI Mixed-Signal Simulation . . . . . . . . . . . . . . . . . . . . 213

Setting Up System Environment Variables for Mixed-Signal Simulation . . . . . 214

Mixed-Signal Simulation with Verilog as the Top Instance . . . . . . . . . . . . . . . . 215

High-Level Mixed-Signal Simulation Instructions . . . . . . . . . . . . . . . . . . . 215

Detailed Mixed-Signal Simulation Instructions . . . . . . . . . . . . . . . . . . . . . 216

Instance Based Instantiation with Verilog Configuration . . . . . . . . . . . . . . . . . 220

Mixed-Signal Simulation with VHDL as the Top Instance . . . . . . . . . . . . . . . . 222

Mixed-Signal Simulation with SPICE as the Top Instance . . . . . . . . . . . . . . . . 228

Spectre/Verilog Mixed-Signal Simulation Running Under the Virtuoso Analog Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Donut Partitioning with Verilog as the Top Instance (V-S-V) . . . . . . . . . . . . . . 232

Using Verilog-on-Top Partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

First Run Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Second Run Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235Verilog and SPICE Files: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Donut Partitioning with SPICE as the Top Instance (S-V-S) . . . . . . . . . . . . . . 239

Using SPICE-on-Top Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

First Run Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Second Run Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241Verilog and SPICE Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Save-Restart in Mixed-Signal Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Appending a Waveform in Mixed-Signal Simulation. . . . . . . . . . . . . . . . . 244

Configuration File Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

analog_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

auto_vsrc_warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

correct_netlist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

define_print_variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

define_strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

digital_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

digital_cell_inst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

dump_interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

dump_port_prop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

dump_setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

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Contents

keep_iface_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

map_subckt_name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

map_unfound_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

report_logic_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

report_port_resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

set_args . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

set_intr_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

set_fall_step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

set_port_prop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

set_port_prop_warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

set_print_progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

set_rise_step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

set_slope_step. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

set_verbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

set_verilog_supply1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

set_verilog_supply0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

verilog_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Automatic Voltage Level Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Voltage Setting Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260Rule 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260Rule 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260Rule 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Mixed-Signal Simulation Interactive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

List Interface Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261csli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Print Global Interface History in Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 263csh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Print Interface Node History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264csnh, csinh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Set the Number of Entries Printed By csnh and csinh . . . . . . . . . . . . . . . 264csnph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Set Watchpoint to Interface Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265csnw, csinw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Delete Watchpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266csdnw, csdinw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Verilog System Tasks for Mixed-Signal Simulation . . . . . . . . . . . . . . . . . . . . . 266

Mixed-Signal Simulation Setup Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Map Correct Port Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Define Clear Port Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

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Set Input Ports As Voltage Sources If Possible . . . . . . . . . . . . . . . . . . . . 268

Define SPICE Netlist Bus Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Handle Bi-Directional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Partitioning Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Partition Boundary with Clear Digital Behavior . . . . . . . . . . . . . . . . . . . . 269

Avoid Partitioning at Timing Sensitive Signals . . . . . . . . . . . . . . . . . . . . . 269

Avoid Reach-in Signals in Analog Partitions . . . . . . . . . . . . . . . . . . . . . . 269

Avoid Partitioning at Bi-directional Signals Involved Strength Fighting and PassSwitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Avoid Fine Grain Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Strength Table Setup Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Mixed-Signal Simulation with ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

ModelSim/HSIM Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Running ModelSim/HSIM Mixed-Signal Simulation with Stand-alone ModelSim273

Running ModelSim/HSIM Mixed-Signal Simulation Under the ADMSEnvironment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

HSIM Features Not Supported by Mixed-Signal Simulation . . . . . . . . . . . . . . 274

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

D. Mixed-Signal Simulation for Three-Dimensional Integrated Circuits (3D-IC) 277

Introduction to the 3D-IC Mixed-Signal Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 277

How 3D-IC Works in the Standalone CustomSim Tool . . . . . . . . . . . . . . . . . . 277

Basic Mixed-Signal 3D-IC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

Enhanced Mixed-Signal 3D-IC Implementation . . . . . . . . . . . . . . . . . . . . . . . . 278

Specifying a Verilog-Top with SPICE Leaf . . . . . . . . . . . . . . . . . . . . . . . . 279

Cell-Based Mixed-Signal Commands Affected by 3D-IC Scope . . . . . . . 280

Support for Verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Wildcard Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280Standalone 3D-IC Global Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . 280Direct Supply Connections Through the Mixed-signal Interface. . . . 281

E. Resolving Inconsistencies Between Digital and Analog Hierarchical Paths 283

Reusing a Single Testbench for Multiple Design Hierarchies. . . . . . . . . . . . . . 283

Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

Recommended Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

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Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

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xiv

About This Manual

The Mixed-Signal Simulation User Guide describes how to set up and use mixed-signal simulations using one of the following setups: ■ CustomSim™, FineSim™, HSIM® or NanoSim®-VCS■ CustomSim, FineSim, HSIM, or NanoSim-VCS-MX ■ CustomSim- or NanoSim-VCS-AMS

Audience

This user guide is meant for designers who use the Mixed-Signal Verification (MSV).

Knowledge of UNIX, the analog tool used in mixed-signal (the CustomSim, FineSim, HSIM or NanoSim tools), VCS/VCS-MX, and a waveform viewer is assumed.

Related Publications

For additional information about these interfaces, see■ The CustomSim/FineSim/HSIM/ NanoSim Release Notes, available on

SolvNet (see Accessing SolvNet on page xvii)■ Documentation on the Web, which provides HTML and PDF documents and

is available through SolvNet at http://solvnet.synopsys.com

You should also refer to the documentation for the following related Synopsys products:■ CustomSim or FineSim or HSIM or NanoSim tools■ VCS■ VCS-MX

Mixed-Signal Simulation User Guide xvJ-2014.09

http://solvnet.synopsys.com

Conventions

Conventions

The following conventions are used in Synopsys documentation.

Customer Support

Customer support is available through SolvNet online customer support and through contacting the Synopsys Technical Support Center.

Convention Description

Courier Indicates command syntax.

Italic Indicates a user-defined value, such as object_name.

Bold Indicates user input—text you type verbatim—in syntax and examples.

[ ] Denotes optional parameters, such as:

write_file [-f filename]

... Indicates that parameters can be repeated as many times as necessary:

pin1 pin2 ... pinN

| Indicates a choice among alternatives, such as

low | medium | high

\ Indicates a continuation of a command line.

/ Indicates levels of directory structure.

Edit > Copy Indicates a path to a menu command, such as opening the Edit menu and choosing Copy.

Control-c Indicates a keyboard combination, such as holding down the Control key and pressing c.

xvi Mixed-Signal Simulation User GuideJ-2014.09

Customer Support

Accessing SolvNetSolvNet includes an electronic knowledge base of technical articles and answers to frequently asked questions about Synopsys tools. SolvNet also provides access to a wide range of Synopsys online services, which include downloading software, viewing Documentation on the Web, and entering a call to the Support Center.

To access SolvNet:

1. Go to the SolvNet Web page at http://solvnet.synopsys.com.

2. If prompted, enter your user name and password. (If you do not have a Synopsys user name and password, follow the instructions to register with SolvNet.)

If you need help using SolvNet, click SolvNet Help in the Support Resources section.

Contacting the Synopsys Technical Support CenterIf you have problems, questions, or suggestions, you can contact the Synopsys Technical Support Center in the following ways:■ Open a call to your local support center from the Web by going to

http://solvnet.synopsys.com (Synopsys user name and password required), then clicking “Enter a Call to the Support Center.”

■ Send an e-mail message to your local support center.

• E-mail [email protected] from within North America.

• Find other local support center e-mail addresses at http://www.synopsys.com/support/support_ctr.

■ Telephone your local support center.

• Call (800) 245-8005 from within the continental United States.

• Call (650) 584-4200 from Canada.

• Find other local support center telephone numbers at http://www.synopsys.com/support/support_ctr.

Mixed-Signal Simulation User Guide xviiJ-2014.09



http://www.synopsys.com/support/support_ctr

http://www.synopsys.com/support/support_ctr

Customer Support

xviii Mixed-Signal Simulation User GuideJ-2014.09

1

1Getting Started with Mixed-Signal Simulation

This chapter provides an overview of the simulation flows as well as the basic steps for simulating a mixed-signal design.

Overview

A mixed-signal simulation enables simulating a design partly modeled in analog and partly modeled in digital.

Mixed-signal simulation is possible through different solutions, depending on which of the analog simulators available you use.

The solutions are:■ CustomSim-VCS/VCS-MX■ FineSim-VCS/VCS-MX■ HSIM-VCS/VCS-MX■ NanoSim-VCS/VCS-MX

Each of the above solutions supports some or all of the following flows:■ Verilog-SPICE ■ VHDL/Verilog-SPICE ■ Verilog-AMS-SPICE

Table 1 on page 2 maps the solutions to the flows.

Mixed-Signal Simulation User Guide 1J-2014.09

Chapter 1: Getting Started with Mixed-Signal SimulationOverview

Note: Throughout this manual, any reference to Verilog implies System-Verilog as well. For example, wherever Verilog is supported in the mixed-signal flows, System-Verilog is supported as well.

See the following topics for more detail:■ Three Mixed-Signal Simulation Flows

• Verilog-SPICE (Flow #1)

• VHDL/Verilog-SPICE (Flow #2)

• Verilog-AMS-SPICE (Flow #3)■ Preparing for a Mixed-Signal Simulation

• Donut Configuration

• Mixed-Signal Simulation Setup File■ Compiling and Running a Mixed-Signal Design■ Mixed-Signal Report Files■ Save and Restore Feature■ Meta-Encrypted SPICE Netlists in Mixed-Signal Design

This section briefly describes these features and the components required to perform a mixed-signal simulation. More detail can be found in the subsequent sections of this chapter.

Table 1 Mapping Solutions to Flows

Solutions Flow #1 Flow #2 Flow #3

Verilog-SPICE VHDL/Verilog-SPICE Verilog-AMS-SPICE

CustomSim-VCS/VCS-MX

X X X

FineSim-VCS/VCS-MX X X

HSIM-VCS/VCS-MX X X

NanoSim-VCS/VCS-MX X X X

2 Mixed-Signal Simulation User GuideJ-2014.09

Chapter 1: Getting Started with Mixed-Signal SimulationThree Mixed-Signal Simulation Flows

Three Mixed-Signal Simulation Flows

You can use any of the following three flows for simulating a mixed-signal design, depending on the description language used to model the netlists ( SPICE, VHDL, or Verilog):

1. Verilog-SPICE (Flow #1)

2. VHDL/Verilog-SPICE (Flow #2)

3. Verilog-AMS-SPICE (Flow #3)

Verilog-SPICE (Flow #1)The Verilog-SPICE flow is required when the analog parts of the design are modeled in one of the SPICE formats supported by the analog engine or behavioral analog (Verilog-A, ADFMI), and the digital parts are modeled in Verilog. This flow is supported in three mixed-signal solutions (depending on the analog engine used for the mixed-signal simulation): CustomSim-VCS, FineSim-VCS, HSIM-VCS, and NanoSim-VCS.

VHDL/Verilog-SPICE (Flow #2)The VHDL/Verilog-SPICE flow is required when a part, or all, of the digital portion of the design, is modeled in VHDL. In this flow, VCS-MX (which supports VHDL as well as Verilog) must be used as the digital engine. This flow is almost identical to Flow #1, but with the additional capability of supporting VHDL blocks in the digital netlist. This flow is supported in three mixed-signal solutions (depending on the analog engine used for the mixed-signal simulation): CustomSim-VCS, FineSim-VCS, HSIM-VCS, and NanoSim-VCS.

Verilog-AMS-SPICE (Flow #3)The Verilog-AMS-SPICE flow is required when a part, or all, of the design, is modeled in the Verilog-AMS language. Parts of the design can also be modeled in SPICE and/or conventional digital Verilog. Only the CustomSim-VCS-AMS and NanoSim-VCS-AMS solutions support Verilog-AMS. The HSIM and FineSim tools cannot be used as the analog engine in this flow.


Chapter 1: Getting Started with Mixed-Signal SimulationPreparing for a Mixed-Signal Simulation

Note: VHDL is not currently supported in this flow.

Preparing for a Mixed-Signal Simulation

To run a mixed-signal simulation in any one the three flows, a mixed-signal control file must be created. This file contains mixed-signal commands that control the configuration of the mixed-signal simulation.

This section describes the donut configuration concept in a mixed-signal simulation, and the mixed-signal control file:■ Donut Configuration■ Mixed-Signal Simulation Setup File

Donut ConfigurationOne of the factors that affects the setup of a mixed-signal simulation is the netlist formats used in different layers of the design hierarchy. For example, if the top level of a design is in SPICE format, the design is called SPICE-top. A design could also be Verilog-top, VHDL-top or Verilog-AMS-top.

Also, a design in which Verilog is on top of SPICE in the hierarchy is called a Verilog-SPICE donut configuration. There are many possible donut configurations for each of the three flows. There are also restrictions on certain types of donut configurations that are described in detail in following sections.

Figure 1 shows a simple design and its hierarchy. The top_blk (top block) instantiates two child blocks blk-1 and blk-2. Child block blk-2, in turn, has child block blk-2-1.



Figure 1 Sample Design with Hierarchy

Cells blk-1 and blk-2-1 are referred to as leaf cells, because they are located at the bottom of a hierarchy branch.

Figure 2 shows a Verilog-SPICE-Verilog donut configuration.



Figure 2 Verilog-top Configuration

In Figure 3, another example of a possible donut configuration is shown where a SPICE-top design has a SPICE-Verilog donut configuration.



Figure 3 SPICE-top Configuration

Any one block in the hierarchy can have definitions in more than one format. For example, blk-2 in Figure 3 can have both SPICE and Verilog definitions—such a cell is called a multi-view cell.

The tool automatically selects a view for each multi-view cell. By default, the view that matches the parent block is selected (if available). For example, if blk-2 (in Figure 3) is a multi-view cell with both SPICE and Verilog views, by default the analog engine selects the SPICE view because it is the view for its parent block top_blk.

The default behavior can be changed by using a command that explicitly instructs the tool to select a particular view for a given cell. The view selection commands are described in detail in Chapter 4, Mixed-Signal Simulation in the Verilog-SPICE Flow.

Mixed-Signal Simulation Setup FileTo run a mixed-signal simulation, a mixed-signal simulation setup file must first be created. This file is passed to VCS during compile time, and contains the


Chapter 1: Getting Started with Mixed-Signal SimulationCompiling and Running a Mixed-Signal Design

call to the analog engine (CustomSim, FineSim, HSIM, or NanoSim tools) and optional mixed-signal commands. Here is a sample mixed-signal setup file for the NanoSim-VCS flow.

use_spice -cell blk-1;use_spice –cell blk-2;choose nanosim -n blk-1.spi blk-2.spi -C ns.cfg ;bus_format _%d;

Compiling and Running a Mixed-Signal Design

Before running a mixed-signal simulation, the netlist must be compiled. This is the stage where all digital and analog netlists are parsed, and the design hierarchy is built with analog and digital components. After the compilation, an executable binary file is generated that must be run to start the mixed-signal simulation with a compilation command such as:

vcs -ad=control.init top_blk.v blk-2-1.v -l comp.log -o simv -l comp.log

In the previous command line, VCS is called and the Verilog files top_blk.v and blk-2-1.v are passed to it. Also passed to VCS is the mixed-signal simulation setup file control.init. This command generates an executable file called simv and a log file called comp.log.

To start the simulation, run the executable file.

Note: The -ad option is supported in VCS 2009.06 and later releases, and replaces the old +ad option. Although the +ad option is still supported, it will be phased out in a future release.

Mixed-Signal Report Files

This section provides a detailed description of the intermediate files generated in these mixed-signal simulation flows: Verilog-SPICE, VHDL/Verilog-SPICE, and Verilog-AMS-SPICE.


Chapter 1: Getting Started with Mixed-Signal SimulationMixed-Signal Report Files

simv.msv Directory and Mixed-signal Report FilesIn all flows of a mixed-signal simulation, a directory with the .msv extension is created to store mixed-signal report files. By default, the name for the directory is simv.msv unless the VCS -o option is used to change the name of the executable generated by VCS. In that case, the name of the directory is vcs_output.msv.

The following sections describe the report files that are stored in the .msv directory and explains their contents. ■ hierarchy.rpt■ interface_element.rpt■ mview.rpt■ names_map.rpt■ port.rpt■ runtime_interface_element.rpt■ through_net.rpt■ use_cell_view.rpt

hierarchy.rptThis file lists the hierarchical paths to all cells in the design along with their cell names. Each hierarchical instance name is followed by the cell name of the instance encapsulated in parentheses, "( )", if the cell is in Verilog/VHDL or angle brackets, "< >", if it is in SPICE or Verilog-A (which is read in through SPICE `hdl) , or "{ }" if the cell is deemed by the tool to be Verilog-AMS. An example of the file content is shown below:

top(top).dut<addr4>.x4<addr>.x9<nor2>top(top).dut<addr4>.x1<addr>.x2<xor2>.x2<inv>top(top).dut<addr4>.x1<addr>.x2<xor2>.x3<inv>top(top).dut<addr4>.x1<addr>.x2<xor2>.x4<xfer>

The first entry above (top(top).dut<addr4>.x4<addr>.x9<nor2>) shows that the full hierarchical path to instance x9 of the SPICE cell nor2 is: top.dut.x4.x9

It also shows that the cells addr4, addr and nor2 are all SPICE (cell names are encapsulated in angle brackets, "< >") ,while the cell top is Verilog or VHDL (encapsulated in parentheses, "( )").



interface_element.rptThis file is only generated in Verilog-SPICE and VHDL/Verilog-SPICE flows. It contains all information related to interface nets in the design in the following format:■ A header explaining the meanings of acronyms used in the file (a2d, e2r

etc.)■ Total number of all resistors added to the netlist because of interface

elements■ A list of resistance map files used■ A list of all interface nodes

The following comment lines appear at the top of the report file. They explain the meaning of the acronyms used in describing the type of interface nets:

# a2d: Analog to Digital interface node# d2a: Digital to Analog interface node# inout: bidirectional interface node# e2r: Real interface node with an Analog to Digital direction# r2e: Real interface node with a Digital to Analog direction

The header is followed a list of resistance map files used in the design. If no explicit resistance map file is used, only the default resistance map will be listed:

rmap_file 1 = tool_install_dir/resistance.map

otherwise all resistance map files that apply to interface nets will be listed as shown below:

rmap_file 1 = ./global_res.maprmap_file 2 = ./cust_res_a.maprmap_file 3 = ./cust_res_b.maprmap_file 4 = ./cust_res_lv.maprmap_file 5 = ./cust_res_hv.map

The next section in the report file is the list of interface nodes, which looks like the following:

…a2d loth=0.2v hith=1.7v node= snps_sptop.xpll.lock;d2a hiv=3.3 lov=0.0 node= snps_sptop.xpll.xpfd.xlock.lock; inout hiv=3.3 lov=0.0 loth=0.3v hith=2.7v node= top.i1.clk; e2r node=top.i2.ctl;r2e node=top.i3.data;…



The “loth” and “hith” values for “a2d” and “inout” nodes are reported as absolute values and not as ratios (percentages). It is important to note that for “a2d” and “d2a” nodes, the reports are generated with correct syntax for “a2d” and “d2a” commands. Consequently, to change the default settings, these lines can be copied and pasted into mixed-signal control file (vcsAD.init) and the only changes needed will be the ones to the high and low levels/thresholds.

The equivalent report in the Verilog-AMS-SPICE flow is the Connect Module report which can be generated with the VCS option -ad_iereport -ams_iereport.

mview.rptThis file lists all cells in the design that have more than one view (for example, SPICE, Verilog, Verilog-A).

Here is an example of the file content:

; Lists of modules: Verilog Spice Verilog-A Adfmipll pll * * * inv inv *

In this example, multi-view cell “pll” has Verilog and SPICE views, while cell “inv” has SPICE and Verilog-A views.

names_map.rptThis file is only generated in the Verilog-SPICE and VHDL/Verilog-SPICE flows. Each line in this file corresponds to an interface element and contains two entries in the following format:

interface_low_conn : interface_hi_conn

where low_conn and hi_conn refer to the two ends of a mixed-net. ■ low_conn refers to the net name in the child cell that connects to the

interface. ■ hi_conn refers to the net name in the parent cell that connects to the

interface.

If Verilog/VHDL instantiates SPICE, the hi_conn node will be in Verilog/VHDL net and the low_conn will be a SPICE one.

If SPICE instantiates Verilog/VHDL, the hi_conn will be a SPICE net and low_conn will be a Verilog/VHDL one.



In the following example, signal top.ctl is the hi_conn for the given interface net and top.i1.x4.ctl_sig is the low_conn net.

top.i1.x4.ctl_sig:top.ctl:

port.rptThis file contains information about how ports are mapped when one SPICE or HDL view is replaced by the other. If multiple views are present, the port order, names, or direction are often not consistent between them. The mixed-signal interface tries to reconcile the differences according to the rules and commands described elsewhere in this manual.

The results in the port.rpt file contain syntactically correct commands that can be cut, edited, and pasted back into the mixed-signal control file.

Note: The port.rpt file does not display connectivity from the high to low (from parent to child). It displays the mapping between child views

The port.rpt file is useful when ports were mapped by the tool successfully and you want to compare the results to the intended mapping, or when some ports were not mapped successfully and you want to find out why.

The report contains:■ A header that provides a reminder of the syntax used within the report.■ Reports on cells with multiple views, organized by cell name.■ Reports on cells with single view. Contains port direction only.

Entries are grouped by cell name.

The following example shows Cell names, modules and sub-circuit references for cells with multiple views, including:■ Each cell name.■ Where to find the cell definitions within the overall design.■ The port list for the Verilog and SPICE views.■ The total port count for both views.

For example:



-----------------------Cell: addr4 ---------------------------*** Port Warnings Encountered For this Cell ***

subckt addr4: file "addr4.spi" line "49" ports=15verilog addr4: file "adder.v" line "1" ports=14

verilog module addr4([3:0]a, [3:0]b, cin, [3:0]s, cout); input a, b, cin; output s, cout;subckt addr4 a_4, a_3, a_2, a_1, a_0, b_3, b_2, b_1, b_0, cin, s_3, s_2, s_1, s_0, cout

Each port_map entry contains the entire set of resolved and unresolved ports for each multiview cell:■ Ports specifically mapped by port_map command.■ Ports unable to resolve.■ Ports mapped by default as snps_by_name.

Busses are reported, where possible, in the busname[m:n] format. They are resolved and printed, as much as possible, as a unit. A mismatch in one bus should not generally affect the reporting of another.

Ports unable to resolve should be presented with double question marks - ??. They are collapsed where possible, but if you define the port map, it is expressly shown. For example:

use_spice -cell addr4 port_map( a[3:0]=>a[4:0]??, //bus width mismatch *=>snps_by_name);

When extra SPICE ports are detected, they are shown mapped to ??. For example:

use_spice -cell addr4d port_map( <??=>vdd1, <??=>vss1, *=>snps_by_name);

After the port mapping information, the resolved port directions of cells with a SPICE view are reported in the format of the port_dir command. For example:

port_dir -cell addr4b( input a, b, cin; output s, cout) //derived from verilog



runtime_interface_element.rptIn an HDL testbench and ucli run scripts, the hdl_xmrs, hdl_xmr_force and ucli force commands are required on an analog target. When a cell view is switched from a digital HDL view to an analog view, the same hdl_xmr, hdl_xmr_force or ucli force commands must be applicable for the analog target.

Correct digital-to-analog conversion must take place for a digital 0,1,X,Z force on a digital target that has now changed to an analog target. An automatic vdd detection mechanism, similar to that used for traditional interface element thresholds and voltage swings, must be used to automatically select voltage thresholds and voltage swings for analog-to-digital conversions and digital-to-analog conversions required for the hdl_xmr, hdl_xmr_force or ucli force commands.

You can manually change the voltage thresholds and swings with:■ The rt_a2d Command■ The rt_d2a Command■ The rt_e2r Command■ The rt_r2e Command

The runtime_interfact_element.rpt file is generated and dynamically updated for any hdl_xmr, hdl_xmr_force/release or ucli force/release command on an analog target. The automatically generated voltage swings, thresholds, and options are recorded in the report file. You can use the rf* commands and options generated in runtime_interfact_element.rpt (cut and paste) in the mixed-signal control file (vcsAD.init) to change or modify any generated voltage swings or thresholds or options. When you use an hdl_xmr, hdl_xmr_force/release or ucli force/release command on an analog target, a runtime message is output on screen with information about the options that have been used for any analog-to-digital or digital-to-analog conversion, electrical-to-real, or real-to-electrical conversion.

through_net.rptThis file is only generated in Verilog-SPICE and VHDL/Verilog-SPICE flows. It contains the list of all thrunets in the design and gets generated only if there is at least one a2a or d2d net in the design. If both a2a and d2d thrunets exist in the design, the a2a nets will be listed first, followed by d2d nets, as shown in the example below:


Chapter 1: Getting Started with Mixed-Signal SimulationSave and Restore Feature

snps_sptop.lock a2asnps_sptop.reset a2asnps_sptop.f6g_b d2dsnps_sptop.xpll.lfin d2d …

use_cell_view.rptThis file lists all the cells that match each of the use_spice, use_verilog and use_vhdl commands. The list is broken into sections, and each section corresponds to each use statement. Each section contains a full hierarchical path to the matching element. Here is an example of the file content:

#==============================================================# Command used on line 3 of mixed-signal control file vcsAD_1.init # followed by instances partitioned by that command#==============================================================use_verilog -module addr4;

#x_dut.x_sp

In this example, there is one use_verilog command and the design has one instance that matches this use_verilog command.

Save and Restore Feature

In a CustomSim-VCS or FineSim-VCS mixed-signal simulation you can save the state of the simulation at any given time point and then restore it at a later time to continue the simulation. This feature allows a "memory image" of the simulation to be saved and restored at a later time. Since at the restore time the exact memory image of the simulation executable is copied into memory, no change in the simulation setup (for example, accuracy, temperature) or any change to the netlists can take effect.

This feature is useful when a long simulation has to be interrupted (for machine power down for example). Instead of losing the simulation data, you can save the state of the simulation up to the current time point and restore it later.

Another application of this feature is when multiple tests are run on the same design (each with a different set of input stimulus for example) and all those tests share the same power-on or initialization phase (for example they all wait for PLLs to lock). You can use save and restore to run one of the tests up to the point where the initialization phase is complete, save the state, and then for each subsequent test use the saved state to restore the simulation and



continue the run from that point on. The testbench, however, has to be designed in such a way that you can select different tests after restore, for example by forcing the content of an RTL variable that selects between tests to a different value after each restore.

Basic Save and Restore Usage The Save and Restore feature in a the CustomSim-VCS and FineSim-VCS tools is based on the VCS save and restore mechanism. In VCS save and restore operations can be performed in the UCLI interactive mode through save and restore commands. The UCLI save and restore commands have the following syntax:

save <filename>restore <filenams>

You can use these commands to capture and save the memory image of the simulation executable at a given point and quit the simulation. The following example shows how the mixed-signal simulation can start in the UCLI interactive mode using the -ucli command line option and then the steady state image of the simulation can be saved:

% simv -ucliucli% run 100ucli% save sim_stateucli% quit

You can restore the saved state of the simulation at a later time and the simulation can resume. The following example shows how the simulation can start in the interactive mode, the saved state of the simulation be restored, and run from the saved time point on:

% simv -ucliucli% restore sim_stateucli% run

Running Multiple Simulations with Save and RestoreYou can use the save and restore feature in the CustomSim-VCS and FineSim-VCS tools to run many tests on the same design. That application is useful when multiple tests all share the same initialization or power-up phase, for example they all wait for PLL's in the design to lock or for all the blocks complete a power-on reset sequence. These initialization phases can take a



long time to simulate. By using the save and restore feature, a simulation can be run past the initialization phase, then the save command can be used to save the state of the simulation. Then the subsequent simulations can restore that state and continue the simulation from that point on. That way they skip the time needed to simulate the initialization phase.

In order for the testbench to execute different tests after the restore operation, the testbench has to be written in a way that allows different tests to be run and each test can be selected by, for example, the numerical value of a variable. You can force that test selector variable to different values after the restore operation and before resuming the simulation.

Here is an example for a Verilog testbench that allows multiple tests to be run. In this example the value of a variable called tst is used to select different tests:

module testbench;int tst;

… case (tst) 0: test0( ); // Run Test No 0 1: test1( ); // Run Test No 1 2: test2( ); // Run Test No 2 3: test3( ); // Run Test No 3 4: test4( ); // Run Test No 4 5: test5( ); // Run Test No 5default: tst0 ( ); endcase

…end

You can use such a test selecting mechanism in save and restore to run a different test after each restore. The following example shows how that can be done.

In this example the simv -ucli command takes the simulation into the UCLI interactive mode. The simulation is run for 10 digital timepoints and then the simulation image is saved in file sim_st. Then the saved image is restored in two separate simulations. Each one of those two restores the image, but one forces the variable testbench.tst to 3 in order to select test number 3 and the other forces that variable to 4 so that the test number 4 is executed.

As a result each simulation runs a different test as identified by the green and yellow graphs in Figure 4.


Chapter 1: Getting Started with Mixed-Signal SimulationChanging the Analog Configuration in the Middle of a Simulation

Figure 4 Save and Restore Example

Changing the Analog Configuration in the Middle of a Simulation

This feature, which is currently unique to the CustomSim-VCS tool, allows certain analog configurations, such as simulation accuracy, temperature, or limited aspects of a netlist. to be changed in the middle of a simulation. This feature internally relies on the CustomSim OP based save and restore feature.

You can change the analog configuration with an "ace" reread interactive command, which you needs to use in the VCS UCLI interactive command line.



The ace reread command This command internally uses the CustomSim OP based save and restore feature to allow a new configuration file or netlist to be read in the middle of a simulation, with some limitations described later in the sections. It save the state of the analog simulator in .ic and .ic.sup files, and then the saved state is restored while the analog engine reads in a new CustomSim configuration file and SPICE netlists.

The internal OP save and restore operations allows the CustomSim tool to read in a new a configuration file and all the SPICE netlists in the middle of a simulation. And this operation allows you to make changes to the configuration file or the SPICE netlist and pass them to the CustomSim tool. This command only applies to analog netlists and the CustomSim configuration and cannot capture any changes to VCS command line options or the digital netlist.

Syntax

ace reread [-c config file] [-ad setup file] [-o output file name]

Changes Allowed in the Configuration File The same limitations that apply in the case of OP based save and restore in the CustomSim tool apply here as well. Those limitations mean that you can change the accuracy commands: set_sim_level, set_tolerance_level, set_ccap_level, set_model_level and use the reread command to enforce the changes.

Options Description

-c config file Specifies a new CustomSim configuration file name.

-ad setup file Specifies a new mixed-signal control file. Only the hiz attributes of The e2r command and The r2e command can be overwritten. All other commands in the new mixed-signal control file are ignored.

-o output file name

The restored waveform file and log file are prefixed with the specified output file name.



Changes in the SPICE Netlist Allowed with the reread CommandYou can change simple resistance or capacitance only if it does not change the interface signals. You can also:■ Change the temperature.■ Change the SPICE stimuli.■ Add or remove probes.

You cannot change the .tran values, or change the structure of the netlist such as changing the cell instantiations in any way; such as the instance name, the number of ports or names of ports, or their connectivity.

Limitations■ You cannot change the Verilog or VHDL models or their content between

save and restore. Generally speaking, you cannot change anything that would imply re-compiling or re-elaborating (re-running any of the following commands: vlogan, vhdlan, or vcs).

■ Changes to the original CustomSim configuration file are not honored. The only way to change the CustomSim configuration is by providing a new configuration file through the -c <new_xa_cfg_file> option of the reread command.

■ It is possible to specify a new mixed-signal control file with ace reread -ad <new setup file>, but only the hiz attribute of The e2r command and The r2e command can be changed. All other commands in the new setup file are ignored.

■ Merged vpd does not work with the reread command.

Examples

Changing the CustomSim Accuracy Setting

You might want to use save and restore in order to change the CustomSim accuracy settings during a simulation. Assume you want to run the simulation with a loose accuracy setting until some supply signals have ramped up and stabilized, and then you want to tighten the accuracy setting. You do not have to quit the simulation. You can load a new configuration file with more accurate settings using the ace reread -c <new config file> command. The commands in the new configuration file overwrite the similar commands in the original configuration file; however the commands of the original configuration



files are still valid. The new configuration file is appended to the original file. For example:

unix> more xa.cfgset_seim_level 3\set_waveform_option -format wdf

unix> more xa_after1m.cfgset_sim_level 4

unix> ./simv -ucli\ucli% run 1000000[simulation runs for 1000000 VCS time units, or 1ms, if time unit is 1ps]ucli% ace reread -c xa_after1m.cfg[enforce XA config changes by reading in the xa_after1m.cfg file]ucli% run[resume the simulation]

After reread, there are two waveform files in your SPICE output directory. The previous example specified wdf format in the original configuration file, so you see:

ucli% run 1000000

ucli% ace reread -cxa_after1m.cfg



■ A xa.wdf file that contains the waveforms until the execution of reread.■ A xa.1e-6.wdf file that contains the waveforms after reread.

If you are using vpd format for the analog output, the vpd file is appended so that the waveforms pre- and post reread are dumped in a single vpd file.

Changing the Temperature or SPICE Stimuli

Another reason to use the reread command is when you want to change analog stimuli or change the temperature for the analog design during transient simulation. You can run the simulation with a given temperature and a given stimulus until a certain point. Then you can modify the netlist to change the temperature and/or the stimulus, and then execute the reread command from UCLI. The new netlist is read in and the new temperature and stimulus are applied to the simulation. For example:

unix> ./simv -ucliucli% run 1000000[simulation runs for 1000000 VCS time units, or 1ms, if time unit is 1ps]unix> vi netlist.spi[ change .TEMP 27 to .TEMP 125][ change vdd vdd 0 1.2 to vdd vdd 0 3.0]ucli% ace reread [enforce the temperature and stimulus changes in the SPICE netlist]ucli% run[resume the simulation]

After executing reread there are two waveform files in your SPICE output directory. The previous example specified wdf format in the original config file, so you see:■ A xa.wdf file that contains the waveforms until the execution of reread,

where the temperature is 27 degrees and VDD is 1.2V.■ A xa.1e-6.wdf file that contains the waveforms after the execution of

reread, where vdd is set to 3.0V and temperature is 125C.

If you are using vpd format for the analog output, the vpd file is appended so that the waveforms pre- and post reread are dumped in a single vpd file.

Multiple Changes to the Analog Configuration in one Simulation

The analog configuration in an CustomSim-VCS mixed-signal simulation can be changed multiple times with multiple reread commands at different timepoints. For example you can change the temperature of the analog design


Chapter 1: Getting Started with Mixed-Signal SimulationMeta-Encrypted SPICE Netlists in Mixed-Signal Design

multiple times over the course of a simulation by changing the .TEMP statement in the SPICE netlist followed by a reread command several times.

You can also use the reread command used in combination with the save and restore feature to allow each restored simulation to run with a different analog configuration (accuracy setting or analog temperature) compared to the saved simulation. This objective can be achieved by restoring the saved simulation first and then before resuming the simulation a reread command is executed in order for the new analog configuration to take effect.

unix> more xa.cfgset_seim_level 3…

unix> ./simv -ucliucli% run 1000000ucli% save sim_state[simulation state at 1000000 VCS time units is saved]

unix> ./simv -ucliucli% restore sim_state[simulation state at 1000000 VCS time units is restored]

unix> vi netlist.spi[ change .TEMP 27 to .TEMP 125]

unix> more xa_after1m.cfgset_sim_level 4

ucli% reread[enforce XA config changes by running the "reread" command]

ucli% run

Meta-Encrypted SPICE Netlists in Mixed-Signal Design

SPICE subcircuits or models that have been encrypted by the HSPICE metaencrypt utility are supported in the CustomSim-VCS and FineSim-VCS mixed-signal simulations. These encrypted SPICE entities can be used in HDL-top, SPICE-top or in a donut configuration.

However, the encrypted SPICE subcircuits are treated as a black box. No block inside the encrypted SPICE can be mapped to Verilog or VHDL with the use_verilog or use_vhdl commands. But an encrypted SPICE block can


Chapter 1: Getting Started with Mixed-Signal SimulationMeta-Encrypted SPICE Netlists in Mixed-Signal Design

be at the analog/digital boundary, and if that happens proper interface elements are inserted just as they would have been for a non-encrypted SPICE block.


2

2Running a Mixed-Signal Simulation with Verilog-AMS-SPICE

This chapter describes the steps required for running an Verilog-AMS-SPICE mixed-signal simulation.

Overview

The following topics are described in this section:■ Running a Mixed-Signal Simulation in Verilog-AMS-SPICE

• Compile Options Specific to Verilog-AMS-SPICE■ Required Input Files■ Verilog Netlist Files■ Mixed-Signal Simulation Setup File

• Files Containing Connect Rule and Connect Module Definitions■ Compiling and Running the Design

Running a Mixed-Signal Simulation in Verilog-AMS-SPICE

The steps required for running a Verilog-AMS-SPICE mixed-signal simulation are, mostly, identical to the steps outlined in Chapter 5, Running a Mixed-Signal Simulation in the Verilog-SPICE Flow. The only differences between the two


Chapter 2: Running a Mixed-Signal Simulation with Verilog-AMS-SPICERunning a Mixed-Signal Simulation in Verilog-AMS-SPICE

flows are:■ Compile options specific to Verilog-AMS-SPICE ■ Required input files■ Compiling and running the design

Compile Options Specific to Verilog-AMS-SPICEThe following compile options are specific to the Verilog-AMS-SPICE flow:■ -ams (mandatory)■ -ams_discipline logic (optional, but highly recommended)■ -ams_iereport(optional)

-ams-ams

To enable the Verilog-AMS-SPICE feature, include the -ams switch in the compile script:

vcs -ad -ams …

-ams_discipline logicThe -ams_discipline logic option tells the simulator that all nets without an explicit discipline definition must assume discipline type logic. This compile option is used when importing legacy Verilog-D code in which no disciplines are defined for module ports.

By using this option, discipline logic is assigned to all such ports avoiding a compile-time error.

While logic is the digital discipline commonly used, any other discipline name can be used in Verilog-AMS as the default discrete discipline. Especially if Verilog-AMS is used along with System-Verilog, a name different from logic must be used for default discrete discipline because logic is a reserved System-Verilog type. The following example shows how to identify a discrete discipline called logical as the default discrete discipline.

-ams_discipline logical


Chapter 2: Running a Mixed-Signal Simulation with Verilog-AMS-SPICERequired Input Files

-ams_iereportThe -ams_iereport compile option prints—both on the screen and the compile log file—a list of all the instances of connects modules in the design with the following information:■ instance name under which the connect module was inserted■ instance name of the connect module■ module name of the connect module■ discipline resolution mode used (i.e., merged or split)■ net and port that connect to each end of the connect module

Required Input Files

Most of the input files required for the Verilog-AMS-SPICE flow are identical to those in the NanoSim-VCS flow, with some differences in the following categories:■ Verilog netlist files■ Mixed-signal simulation setup file■ Files containing connect rule and connect module definitions

Verilog Netlist Files

In Verilog-AMS-SPICE, all Verilog files, whether Verilog-D, Verilog-A or full Verilog-AMS, are passed to the simulator at compile time, as shown in the following example.

vcs -ams -ad testbench.v block1.va block2.vams …

In this example, testbench.v contains Verilog-D code, block1.va contains Verilog-A code, and block2.vams contains a full Verilog-AMS code.

Note: It is possible to pass Verilog-A files to the simulator using the SPICE .hdl command, but it is highly recommended to pass the files at compile time.


Chapter 2: Running a Mixed-Signal Simulation with Verilog-AMS-SPICEMixed-Signal Simulation Setup File

Mixed-Signal Simulation Setup File

Verilog-AMS-SPICE requires a mixed-signal control file, just like NanoSim-VCS. The format and content of this file is identical between the two flows, and the file (just like in the NanoSim-VCS flow), is called at compile time using the -ad switch.

The only difference is when there are no SPICE file(s) used in the Verilog-AMS-SPICE flow. This occurs when all analog blocks are described in Verilog-AMS or Verilog-A code. In such a case, the call to a fastSPICE engine in the mixed-signal control file can be as simple as the following:

choose nanosim -C nanosim.cfg;

or

choose xa -c xa.cfg;

Files Containing Connect Rule and Connect Module DefinitionsIn Verilog-AMS-SPICE, definitions for connect rules and connect modules are passed to VCS just as any other Verilog file. The NanoSim installation directory contains default connect rule and connect module files with default values. They can be used as is or as templates for customized connect modules and connect rules.

Whether they are used as is in the NanoSim installation directory or they are copied into local directory and modified, the full path to these files must be passed to VCS.

These default files can be used, or new files can be created by creating a copy of the default files and modifying them to suit the specific design characteristics (for example, changing the vsup supply voltage parameter for the connect module).

The following example shows how connect rule and connect module definitions can be passed to the simulator.

vcs -ad -ams snps_cm_a2d_1.vams snps_cm_d2a_1.vams snps_crules_1_18.vams …

In this example, it is assumed that the files are in the local directory. If not, a full path to the location of these files is required (just as in any other Verilog file).


Chapter 2: Running a Mixed-Signal Simulation with Verilog-AMS-SPICECompiling and Running the Design

Compiling and Running the Design

Similar to the NanoSim-VCS flow, the design is compiled and run using the generated binary executable:

vcs -ad -ams -f verilog_file_list snps_cm_a2d_1.vams snps_cm_d2a_1.vams snps_crules_1_18.vams -ams_discipline logic -l comp.log

To run the Verilog-AMS-SPICE simulation, add the -R switch to the compile script so the simulation starts automatically after compiling or,

% simv [run-time options]

to run the mixed-signal simulation.

Note: simv is the default name for the binary executable generated after compilation that can be overwritten using the -o

exec_file_name compile time switch.


Chapter 2: Running a Mixed-Signal Simulation with Verilog-AMS-SPICECompiling and Running the Design


Part 1: Verilog-SPICE Mixed-SignalSimulations



3

3Using Verilog-SPICE Mixed-Signal Features

This chapter provides a detailed description of the features supported in all flows of mixed-signal simulation.

Overview

In a mixed-signal simulation of a design some parts of the design are modeled in SPICE and other parts in HDL (Verilog, VHDL, or Verilog-AMS, depending on the mixed-signal flow).

Note: It is recommended that before starting a mixed-signal simulation, both SPICE subcircuits and Verilog modules be verified individually to make sure they are error-free.

The content in this chapter assumes you have a basic familiarity with both VCS and the analog simulator involved in mixed-signal simulation. Refer to the respective manuals for each product for more information.

This chapter describes the following topics:■ Mixed-Signal Feature Highlights■ Known Limitations

Mixed-Signal Feature Highlights

The following features are described in detail in this section:■ Verilog-top/SPICE-top Flows and Donut Configurations■ Multiple Views


Chapter 3: Using Verilog-SPICE Mixed-Signal FeaturesMixed-Signal Feature Highlights

■ Automatic Verilog Dummy Module Generation■ Verilog-A Model Instantiation

• Parameter Passing Rule■ XMR (Cross Module Referencing) Across Analog-Digital Boundary■ Interface A/D and D/A Signal Conversions

• Cases Where A/D and D/A Converters are Not Inserted■ Signal Conversion from Verilog-to-SPICE and SPICE-to-Verilog

• Converting Signal Values

• Converting Signal Strength

• Creating a Resistance Map File■ Postlayout Simulation Through Back-annotation

• Using the SDF File

Verilog-top/SPICE-top Flows and Donut ConfigurationsMixed-signal simulation supports both Verilog-top/VHDL-top and SPICE-top configurations.

In a SPICE-top configuration, the spice_top command must be used in the mixed-signal simulation setup file, which by default is assumed to be called vcsAD.init. For Verilog-top or VHDL-top configuration, no specific command is required. For a description of the spice_top command, as well as other mixed-signal commands used in mixed-signal simulation, see Chapter 4, “Mixed-Signal Simulation in the Verilog-SPICE Flow.”

Mixed-signal simulation allows any type of donut configuration (for example, VHDL/Verilog-SPICE-Verilog/VHDL, SPICE-VHDL/Verilog-SPICE, etc.) with the following:■ In mixed-signal flow with NanoSim, ADFMI models can only be at the leaf

level and cannot contain a child block with a SPICE or Verilog view.

Multiple ViewsEach block in the design can have definitions in more than one view. For example, a block can have both SPICE and Verilog definitions.



By default, Verilog-SPICE selects the view of the multi-view cell that is identical to the parent block view. A particular view of a multi-view cell can also be selected explicitly by using "use_spice" or "use_verilog" mixed-signal commands.

SPICE View Selection for Multi-View Cells Under VerilogBy default, if a multi-view child cell is instantiated under Verilog, the Verilog view of the child is used. But the mixed-signal command "use_spice" can be used to direct the tool to instantiate the child cell in SPICE view instead.

If a multi-view cell is instantiated under SPICE, by default the SPICE view of the child is used. Using the "use_spice" command on the child cell will have no impact because the child view is already SPICE.

Please refer to The use_spice Command on page 110 for more details.

Verilog View Selection for Cells Under a SPICE ParentBy default, if a multi-view child cell is instantiated under SPICE, the SPICE view of the child is used. But the mixed-signal command "use_verilog" can be used to direct the tool to instantiate the child cell in Verilog view instead.

If a multi-view cell is instantiated under Verilog, by default the Verilog view of the child is used. Using the "use_verilog" command on the child cell will have no impact because the child view is already Verilog.

Please refer to The use_verilog Command on page 114 for more details.

Note: In mixed-signal simulation using NanoSim, the views for ADFMI and Verilog-A cannot be switched in the mixed-signal simulation setup file. To switch views for ADFMI, the NanoSim command-line option -fm adfmi file(s) must be used. To switch views to Verilog-A, see the section Verilog-A Model Instantiation.

Automatic Verilog Dummy Module GenerationMixed-signal simulation requires an internal Verilog view for every cell in the design—even SPICE cells.

The tool automatically generates dummy Verilog modules for all subcircuits available in the SPICE netlist that do not have a corresponding Verilog module. A Verilog dummy module, also called a dummy wrapper or shadow file, is defined as a spicemodule instead of module, and contains the port name,



port direction, net name, and instance module definitions (if available). These dummy Verilog modules are generated during the compile time, and are kept in the simv.daidir directory (for more information about the compile and simv.daidir directory, please refer to Chapter 5, Running a Mixed-Signal Simulation in the Verilog-SPICE Flow.

Verilog-A Model InstantiationIn mixed-signal simulation, Verilog-A can be used as the analog view of a cell. Such a Verilog-A cell can be instantiated under SPICE or Verilog.

There are two ways to read in Verilog-A blocks in mixed-signal simulation depending on the mixed-signal flow used.■ For the Verilog-SPICE and VHDL/Verilog-SPICE flows, Verilog-A blocks are

read in by:

• Using the .hdl command in the SPICE netlist to readin Verilog-A file(s).

• Using the appropriate command in the analog simulator to select the Verilog-A view, in case there are both SPICE and Verilog-A definitions for the same block. For NanoSim, the command is use_model_veriloga. For HSIM, the command is .param HSIMUSEVA=<module name>. For the CustomSim, HSIM, and NanoSim tools the command is set_va_view. For details about the syntax of these commands, see the HSIM Simulation Reference Manual and the CustomSim Command Reference Manual.

■ For the Verilog-AMS-SPICE flow, all Verilog files, including Verilog-A, are passed to VCS at compile time. In this flow it is still possible, although not preferable, to read in Verilog-A files through SPICE .hdl as well.

Parameter Passing RuleParameters can be passed between HDL blocks (Verilog or VHDL) and SPICE.■ In CustomSim-VCS and CustomSim-VCS-MX parameter passing between

HVA blocks is supported by default.■ In HSIM-VCS and HSIM-VCS-MX parameter passing between HVA blocks

is not an issue because these solutions do not support HVA.



■ In Verilog-SPICE and VHDL/Verilog-SPICE flows, parameter passing between HDL and SPICE is not enabled by default. To enable parameter passing, the mixed-signal command "param_pass enable;" must be used (see the mixed-signal command section of this manual).

■ Parameter passing between SPICE and Verilog-A is always enabled in all solutions if Verilog-A is read in via the SPICE .hdl command. For example:

■ .hdl "inv_verilog_a.va"x1 in out inv_verilog_a vhigh=3.3 vlow=0 td=10

■ In NanoSim-VCS and NanoSim-VCS-MX, parameter passing between HVA (Hierarchical Verilog-A) blocks is disabled by default. To enable parameter passing, the following environment variable must be set:

setenv HVA_ON 1

■ In the Verilog-AMS-SPICE flow parameter passing between Verilog and SPICE and parameter passing between HVA blocks are enabled by default.

XMR (Cross Module Referencing) Across Analog-Digital BoundaryMixed-signal simulation provides two XMR options to access internal analog nodes in Verilog:■ Logic XMR Access to Analog Nodes■ Real XMR Access to Analog Nodes

Logic XMR Access to Analog Nodes In this method, the Verilog code can simply treat an internal analog node as a logic value for read or write operations. The same XMR principles used to access a digital net must be used to access an analog net. This means that the full hierarchical path to the analog node must be given whenever an XMR read or write is made.

Mixed-signal simulation inserts a2d or d2a converters automatically depending on whether Verilog is reading from or writing to the internal analog node. The inserted converters will be subject to the same rules that govern the conventional interface nets, including resistance map lookup. These a2d and d2a converters will appear in the "simv.msv/interface_element.rpt" file along with all other interface elements. And just like any other interface element, the "a2d" and "d2a" mixed-signal commands can be used to



change the default settings for the a2d or d2a converters inserted for logic XMR.

The following example shows a logic XMR read on an analog node with the hierarchical path "top.i1.i2.x1.clk" into a Verilog wire. It assigns the logic value corresponding to the voltage of an analog node.

assign verilog_wire = top.i1.i2.x1.clk;

The following example shows a logic XMR read on an analog node with the hierarchical path "top.i1.i2.x1.strb" into a Verilog register. It assigns the logic value corresponding to the voltage of an analog node.

initial begin...verilog_reg = top.i1.i2.x1.strb;...end

The following example shows how a logic XMR write can be done on an analog node. The d2a converters inserted by mixed-signal simulation translates the logic values to voltage values and apply them to the analog node.

reg rst_reg;assign top.i1.i2.x1.rst = rst_reg;

initial begin... rst_reg = 1'b0;#5 rst_reg = 1'b1;...end

Because SPICE does not have an inherent notion of "bus", if the target of a logic XMR is a SPICE bus, the members of the SPICE bus must be encapsulated in a braces, { }, when they are referenced in a logic XMR. The following example shows a SPICE subcircuit with bus ports and how those SPICE bus members must be used in a logic XMR. Here, the subcircuit spice_blk has bus ports a_2, a_1, and a_0:

.subckt spice_blk a_2 a_1 a_0

This is how these SPICE bus ports can be used in an assign statement that uses logic XMR:

wire [2:0] verilog_wire;assign verilog_wire = { top.i1.x1.a_2 , top.i1.x1.a_1 , top.i1.x1.a_0 };



Here, the wire verilog_wire is a Verilog bus. To assign a vector composed of SPICE bus members a_2, a_1, and a_0, braces, { } must be used along with the full hierarchical paths to the SPICE bus ports.

Real XMR Access to Analog Nodes In this method, internal analog nodes are accessible to Verilog as real values. The access is made through calls to Verilog system tasks or system functions as described in Table 2.

The following Verilog system tasks and system function provide real XMR access to Analog nodes from Verilog:

Limitation: These Real XMR system tasks/functions are not yet supported in the VHDL/Verilog-SPICE and Verilog-AMS-SPICE flows.

$snps_force_volt()This system task allows Verilog to force a voltage on any analog node, even one connected to an ideal voltage source. In such a case this system task overrides the ideal voltage source.

Syntax

$snps_force_volt(analog_node_name, verilog_real_value | verilog_real_variable);

Table 2 Accessing Analog Nodes with System Tasks or System Functions

System Tasks ■ $snps_force_volt(analog_node, voltage)■ $snps_release_volt(analog_node)

System Function ■ $snps_get_volt(analog_node)

Event generator ■ snps_cross (expression, dir)

Argument Description

analog_node_name The full hierarchical node name for the internal SPICE node. This can also be a mixed net (an A/D interface net).



Examples

$snps_force_volt (top.i1.spcell.n1, 3.3);

or

$snps_force_volt (top.i1.spcell.n1, real_var);

The voltage of the analog node will stay at the given real value until the next $snps_force_volt or $snps_release_volt system task calls.

$snps_release_volt()This system task removes the voltage source applied by a previous $snps_force_volt task, and from that point on, allows the analog node to assume voltages determined by the analog circuit. If the node has not been forced with $snps_force_volt or is already released, this system task will have no effect.

Syntax

$snps_release_volt (analog_node);

Examples

$snps_release_volt (top.i1.spcell.n1);

$snps_get_volt()This is a Verilog function that allows sampling of voltage values for internal analog nodes.

This function can be used to assign a value to a Verilog real variable or it could be used as a real value in an expression.

verilog_real_value, verilog_real_variable

An explicit real value or a Verilog real variable. The value will be applied to the analog node as an ideal voltage source.






Syntax

$snps_get_volt (analog_node_name)

Examples

real_var = $snps_get_volt(top.i1.spcell.n2);

if($snps_get_volt(top.i1.i2.sp1_node > 2.5) …else…end

$snps_get_port_current()This is a Verilog function that allows sampling of current through analog subcircuit ports or SPICE primitive pins.

You can use this function to assign a value to a Verilog real variable or as a real value in an expression.

Syntax

$snps_get_port_current (analog_port_name | spice_primitive_pin)




analog_node_name The full hierarchical path to the SPICE subcircuit port or the pin of a SPICE primitive such as a resistor, capacitor, inductor or a transistor.

spice_primitive_pin The names of SPICE primitives, which follow the HSPICE convention. For example, "p" and "n" represent positive and negative pins of two port primitives such as R's, C's and L's and "d", "g" and "s" represent drain, gate and source of MOS transistors.



Examples

real_var = $snps_get_port_current(top.i1.amp.out);res_curr = $snps_get_port_current(top.i1.x1.r2.p);

$ current through the$ "p" pin of a resistor

mos_curr = $snps_get_port_current(top.i3.x1.m5.d); $ current through the$drain of a MOS transistor

if($snps_get_port_current(top.i1.i2.bias > 1e-3)…else…end

Limitation: These system tasks and functions operate on an on-demand basis and are not event-driven. This means that they sample/apply analog voltages only at times when they are called in the Verilog code.

snps_above ( )Generates a digital event that allows Verilog to sense when a given analog voltage has gone above or below a certain threshold. This event can be used in the sensitivity list of a Verilog always block, which would then allow a piece of Verilog code to be executed depending on the voltage transitions on the given analog node.

Syntax

snps_above ( expression )

In the following example snps_above is used in conjunction with $snps_get_volt() in a Verilog always block to sense when the voltage of analog node top.dut.x4.rst rises above 1.85V.

Examples

always @ (snps_above($snps_get_volt(top.dut.x4.rst) - 1.85))begin...end

In the next example snps_above triggers an event when signal test_top.i1.x3.strb falls below 0.9V.



always @ (snps_above(0.9 - $snps_get_volt(test_top.i1.x3.strb) ) ) begin...end

snps_cross ( )Generates a digital event that allows Verilog to sense when a given analog voltage has gone above or below a certain threshold. This event can be used in the sensitivity list of a Verilog always block, which would then allow a piece of Verilog code to be executed depending on the voltage transitions on the given analog node.

Syntax

snps_cross ( expression, dir )

In the following example snps_cross is used in conjunction with $snps_get_volt() in a Verilog always block to sense when the voltage of analog node top.dut.x4.rst rises above 1.85V.

Examples

always @ (snps_cross($snps_get_volt(top.dut.x4.rst) - 1.85,1) ) begin...end

In the next example snps_cross triggers an event when signal test_top.i1.x3.strb rises above or falls below 0.9V.


expression A mathematical expression which would cause an event to be generated whenever it crosses 0. Normally the expression contains a $snps_get_volt() system task.

dir Determines when the event is generated. A value of "1" generates an event when the expression crosses 0 in the rising direction, when transitioning from a negative value to a positive value. A value of "-1" generates an event when the expression crosses 0 in the falling direction, when transitioning from a positive value to a negative value. A value of "0" generates an event in both directions.



always @ (snps_cross($snps_get_volt(test_top.i1.x3.strb) - 0.9, 0) ) begin...end

Interface A/D and D/A Signal ConversionsMixed nets are the signals that enable the connection between analog and digital blocks in a mixed-signal simulation. These signals are the interface signals located at the analog-digital boundary.

Depending on whether the direction of the signal transfer is from digital-to-analog or from analog-to-digital, mixed-signal simulation must perform D/A or A/D conversions to convert logic values to analog voltages or vice versa.■ In the Verilog-AMS-SPICE flow, the A/D and D/A conversions are done via

"Connect Modules" (see Converting Signals with Interface A/D and D/A Connect Modules on page 192).

■ In the Verilog-SPICE and VHDL/Verilog-SPICE flows, A/D and D/A converters are inserted automatically by the tool to carry out A/D and D/A conversions.

Note: Verilog-SPICE allows SystemVerilog net types of "real"to connect to SPICE ports, or alternatively SPICE nets to connect to SystemVerilog "real" ports. In these cases e2r (electrical to real) or r2e (real to electrical) interface elements are inserted to convert analog voltages to digital real values or vice versa.To allow such connectivity vcs switch "-realport" must be used at compilation.

Interface elements are inserted automatically for mixed-nets based on the following principles:■ Mixed nets can be unidirectional, in which case they are either a2d or d2a.■ Mixed nets can be bidirectional, or inout, which implies that at different

simulation times they can be either of an a2d or d2a nature.■ The direction of the mixed nets is determined from Verilog port directions:

• In a Verilog child under a SPICE parent configuration, the port direction of the Verilog child determines the direction of the mixed nets.



• In a SPICE child under a Verilog parent configuration, and if the SPICE child has a Verilog view as well, the port directions in that Verilog view determine the direction of the mixed nets.

• If the SPICE child does not also have a Verilog view, the direction of all mixed nets will be inout.

■ The default high and low voltage values in a d2a conversion are the local analog VDD and 0V, respectively.You can use the mixed-signal "d2a" command to override these default values (see Mixed-Signal Control Commands).

■ The default high and low voltage threshold for A/D conversion is 50% of the local analog VDD. You can use the mixed-signal"a2d" command to override these default values (see Mixed-Signal Control Commands).

■ In the d2a conversion, the digital driver is modeled as an ideal source in series with a resistor on the analog side. The value of the resistor depends on the Verilog drive strength, and is determined by the resistance map file (see the section Creating a Resistance Map File).

■ The behavior of a2d conversion depends on the direction of the mixed-net interface:

• If the interface is a unidirectional a2d mixed-net, the analog driver is modeled as a digital driver with the Verilog default drive strength of 6 or Strong.

• If the interface is a bidirectional mixed-net, the a2d events will be modeled as a digital driver whose drive strength is determined by the effective output resistance of the analog driver. The analog engine calculates that output resistance and uses it as an index "resistance map file" to get a corresponding drive strength for Verilog. Smaller output resistances lead to stronger Verilog drive strengths and larger output resistances lead to weaker Verilog drive strength (see the section Creating a Resistance Map File).

The "hiz_on" and "hiz_off" options for the mixed-signal command "a2d" can be used to change these default behaviors.

Note: Calculating a2d drive strength and estimating the output resistance for the a2d conversion is time consuming, which could noticeably slow down the simulation if there are too many ports requiring it. Therefore, it is recommended that the use of "inout" mixed-nets be limited to those interface nets that are functionally bidirectional. For those interface nets that have become bidirectional only because they were ports of a



single-view SPICE cell (with no Verilog view to determine port directions), it is recommended to use the "a2d" command with the "hiz_off" option to turn off a2d drive strength calculation.

■ Only resistive elements—equivalent channel resistance for MOS transistors and/or ideal resistors—that can be traced to the local power supply or to ground from a mixed net are used in the calculation of net output resistance, when such calculation is done.

■ The Verilog drive strength calculation in the a2d conversion for a mixed net ignores the effects of BJTs, diodes, or coupling capacitors connected to the ports inside the subcircuits.

The following WARNING message is generated by NanoSim-VCS when BJTs or coupling capacitors are connected to mixed nets:

WARNING:NanoSim:0x2070fe17: the element ‘top.I1.cl’ is not supported in mixed net driving strength calculation

Cases Where A/D and D/A Converters are Not InsertedThere are two cases in which A/D or D/A converters are not inserted on the path of a mixed net:

Case #1

When two SPICE ports are connected to each other via a Verilog wire in the parent Verilog cell

Case #2

When two Verilog ports are connected to each other via a SPICE net in the parent SPICE cell

In these two cases, the analog engine detects that the origin and destination of the mixed nets are from the same domain (SPICE or Verilog); as a result, No A/D or D/A converters are inserted on their paths.

Figure 5 on page 47 graphically demonstrates Case #1. Two SPICE blocks, blk-1 and blk-2, are instantiated under a Verilog parent, and a port of blk-1 is connected to a port of blk-2 via a Verilog wire.



Figure 5 SPICE is the Source and Destination

Because both the source and destination of that wire are analog, that wire is treated as an analog net and no A/D or D/A converters are inserted on this path from blk-1 to blk-2.

As a result, this mixed net is optimized as an analog net, despite its definition as a Verilog wire, and by default is captured only in the analog output file. (You can have a digital image of the signal dumped in the digital output file, which is explained in the following text).

Figure 6 on page 48 graphically demonstrates Case #2. Two Verilog cells, blk-1 and blk-2, are instantiated under a SPICE parent, and a port from blk-1 is connected to a port from blk-2 via a SPICE net.



Figure 6 Verilog is the Source and Destination

Because the tool detects that both the source and destination of the signal is digital, it does not insert A/D or D/A converters on the path from blk-1 to blk-2, and treats the SPICE net connecting the two digital ports as a digital net.

As a result, this mixed net is optimized as a digital wire, despite its definition as a SPICE net. By default, this mixed net is captured only in the digital output file. (You can have an analog image of the signal dumped in the analog output file, which is explained in the following text).

Such mixed nets—which cross the analog and digital boundary, yet do not incur the insertion of A/D or D/A components—are referred to interchangeably as through-nets or thru-nets.

The through-net in Case #1 that connects two analog blocks is referred to as an a2a through-net. The through-net in Case #2 that connects two digital blocks is referred to as a d2d through-net.

An a2a through-net is optimized as an analog node and, by default, is dumped only in the analog output file. You can use the print_thru_net mixed-signal control command to generate a digital image of the signal created and dumped



in the digital output file. In doing so, a redundant A/D converter is added to the optimized analog net to generate the digital image.

Note: No converter is inserted on the path from blk-1 to blk-2. The new a2d converter will be added from the analog net between blk-1 to blk-2 and the digital domain.

The same principle applies to d2d through-nets. By default, a d2d through-net is optimized as a digital node and is dumped only in the digital output file. You can use the print_thru_net mixed-signal control command to generate an analog image of the signal created and dumped in the analog output file. In doing so, a redundant D/A converter is added to the optimized digital net to generate the analog image.

Caution: These redundant A/D and D/A converters can create excess overhead for the mixed-signal simulation and degrade performance; therefore, these converters should be used with caution.

Also, when a dummy A/D or D/A converter is connected to an optimized net, that mixed net is no longer reported as a "through-net".

Signal Conversion from Verilog-to-SPICE and SPICE-to-VerilogNote that the term SPICE refers to all transistor-level netlist formats supported by the analog engine. See the following conversion sections:■ Converting Signal Values■ Converting Signal Strength■ Creating a Resistance Map File

Converting Signal ValuesIn the A/D or D/A conversion, mixed-signal simulation must translate both the signal value and the signal strength from one domain to the other.

The signal strength translation (in each direction) is implemented with the help of the resistance map file, which is described in the section Creating a Resistance Map File.



The rules governing D/A signal conversion are summarized in Table 3.

Signal value conversion in the a2d direction from the transistor level to Verilog is based on the analog voltage crossing high and low thresholds. By default, 50% of the local voltage supply is used for both high and low a2d thresholds. To change the threshold values for digital event generation, the mixed-signal control command a2d must be used. If the dynamic supply feature is enabled in the a2d command (seee the The a2d Command description). Then the high and low thresholds can be set as a percentage of the referenced VDD net.

The A/D signal value conversion rules are displayed in Table 4.

Table 3 Signal Value Conversion Rules for Digital-To-Analog Conversion

Verilog value Transistor-level value

0 ■ 0V (gnd) or, in case dynamic supply is enabled for d2a, a percentage of the voltage on the referenced VDD net.

■ Can be modified with the d2a mixed-signal control command.

1 ■ Local supply voltage value or, in case dynamic supply is enabled for d2a, a percentage of the voltage on the referenced VDD net.

■ Can be modified by the d2a mixed-signal control command.

Z ■ The analog node will not be driven by Verilog. The voltage of the node depends entirely on the analog circuitry.

X ■ 0V■ Can be modified by the d2a mixed-signal

command.

Table 4 Signal Value Conversion Rules for Analog-To-Digital Conversion

Transistor-level value Verilog value

■ Less than (<) or equal to (=) the low threshold voltage (default = 50% of local voltage supply)

■ Can be modified by the a2d command

0



No value is converted from transistor-level to X in Verilog.

The following example sets 0.35V as the low-thresh and 0.65V as the high-thresh for a2d conversion at interface net "top.dout". If the voltage on the top.dout interface node decreases to 0.35, a digital event is generated and the logic value changes to 0. If the voltage on the top.dout interface node increases to 0.65, a digital event is generated and the logic value changes from 0 to 1:

a2d loth=0.35 hith=0.65 node=top.dout;

Dynamic Supply in Mixed-SignalBy default the a2d and d2a conversions are based on the assumption that the analog supply voltage remains constant. But in many cases of low power designs the chip occasionally powers down and powers back up, or the supply voltage dynamically changes throughout the simulation. And as a result the a2d and d2a voltage levels must track the changes in supply dynamically to correctly represent the behavior of the circuit.

The dynamic supply feature addresses this requirement. If enabled, this feature forces the a2d and d2a levels to change in tandem with the voltage on a given supply net. The feature is enabled via mixed-signal commands a2d and d2a. For example:

a2d loth=20% hith=80% node=top.i1.clk vdd=top.i2.vdd;d2a hiv=100% lov=0% node=top.i1.rst vdd=top.i2.vdd;

Figure 7 demonstrates how, with the dynamic supply enabled, the a2d thresholds vary as the analog supply varies. Here, the variations on the supply net VDD causes the a2d thresholds to vary in tandem with it (assuming that both a2d thresholds are set to 50% of VDD).

■ Greater than (>) or equal to (=) the high threshold voltage (default = 50% of local voltage supply)

■ Can be modified by the a2d command

1

■ In case of bidir interface nets or if the drive strength calculation is enabled for a2d interface nets and the analog node is HiZ.

Z

Table 4 Signal Value Conversion Rules for Analog-To-Digital Conversion

Transistor-level value Verilog value



Figure 7 Thresholds Vary as the Analog Supply Varies

Figure 8 demonstrates how the d2a conversion is impacted by a varying analog supply voltage if dynamic supply is enabled. Here, the "logic" data is the input to the d2a converter and the "analog output" is the output from d2a. The analog output tracks the changes of VDD (assuming the default high and low d2a levels are set to 100% and 0% of VDD).



Figure 8 Conversion Impacted by a Varying Analog Supply Voltage

For details about how to enable the dynamic supply feature through the a2d and d2a commands, see The a2d Command and The d2a command.

Note: The dynamic supply feature is only supported in the CustomSim-VCS and FineSim-VCS tools.

Converting Signal StrengthThere are eight different drive strengths defined in the Verilog language—0 is the weakest and 7 is the strongest. The following list shows the eight Verilog drive strengths and the way logic 0 and 1 are represented for each level in Verilog:■ Level 0: highz0, highz1■ Level 1: small, small■ Level 2: medium, medium■ Level 3: weak0, weak1■ Level 4: large, large■ Level 5: pull0, pull1



■ Level 6: strong0, strong1 (default)■ Level 7: supply0, supply1

These drive strengths enable multiple drivers—with differing strengths—to drive the same net that can be modeled in Verilog. In case of a conflict between multiple drivers driving a net, the driver with the value from the strongest driver prevails and determines the net value. Unless explicitly stated in the Verilog code, the default drive strength for all Verilog nets is 6 (Strong0, Strong1).

For the A/D conversion, if the mixed net has inout direction, the tool calculates the effective analog output resistance of the mixed net to estimate an equivalent drive strength on the digital side.

By default all SPICE ports are assumed to be inout, unless the SPICE cell has a Verilog view where the direction of ports are explicitly declared. If the direction of a SPICE port connected to a mixed net is output, no drive strength mapping from Analog to Digital will take place during A/D conversion and the mixed net will always assume Level 6, the default drive strength (the strongest) in Verilog.

If the mixed net connects to a SPICE port of type inout (either because there is no Verilog view for the SPICE cell or the direction of the port in the Verilog view is defined as inout) then the tool calculates the effective output resistance for the analog output and maps it to a corresponding drive strength in Verilog. This can be a time-consuming task during simulation and it is recommended to avoid bidirectional mixed nets as much as possible.

For the D/A conversion, the Verilog drive strength is translated to a resistance value for the resistor which is placed in series with the voltage supply that models the Verilog driver in SPICE. This drive strength mapping in D/A conversion occurs for both unidirectional and bidirectional mixed nets. The following sections describe the rules governing these conversions:

Verilog-to-Transistor Level Conversion

Verilog strength is converted to an average resistance value. This value is calculated from a corresponding resistance range listed in theresistance map file. Each entry in the rmap file declares a range of resistance values. The midpoint in that range is used during D/A conversion to determine the value of the rmap resistor used on the analog side.

For example, consider a driver in Verilog driving with a drive strength of 6 and the entry for drive strength 6 in the rmap file looks like the following:

resistance_map 1.2–1000.1 6 ;



The resistance value of the series resistor used in the d2a interface will be

or 500.65 Ohms. The only exception will be when Verilog drives with HiZ (drive strength 0) for which no driver (no ideal supply or series resistor) will be applied on the analog side and the digital driver will act as an open circuit. In that case, the voltage of the analog node will depend entirely on the drivers in the analog circuit.

See Figure 9 for a visual representation.

Figure 9 Verilog-To-Transistor-Level Strength Conversion

Transistor Level-to-Verilog Conversion

Transistor-level resistance value is converted to the corresponding Verilog strength by a resistance map file. For example, resistance value 200 (ohm) for logic “1” and resistance value 450 (ohm) for logic “0” is converted to strength “6”. See Figure 10 for a visual representation.

1.2 1000.1+2

------------------------------



Figure 10 Transistor Level-To-Verilog Strength Conversion

Creating a Resistance Map FileThe rmapAD.init default resistance map file is available in the following location:

<analog_simulator_installed_directory>/include/rmapAD.init

The default resistance map file is used, unless you specify your own resistance map file using the rmap_file command in the mixed-signal simulation setup file (vcsAD.init, by default).

You can create a custom resistance map file using unidirectional mapping or bidirectional mapping. The unidirectional resistance map file is useful when you want different resistance mapping for either direction: from Verilog-to-transistor level, or from transistor level-to-Verilog.

Unidirectional Mapping

See the following syntax and description for strength (Verilog) to resistance (transistor-level) unidirectional mapping.



The unidirectional -from syntax is

resistance_map -from analog resistance_value_range -to verilog strength;

The unidirectional -to syntax is

resistance_map -to analog resistance_value_range -from verilog strength;

See the following example for a unidirectional file sample.

resistance_map -from analog 90000.2-1e32 -to verilog 0;resistance_map -from analog 70000.2-90000.1 -to verilog 1;resistance_map -from analog 50000.2-70000.1 -to verilog 2;resistance_map -from analog 5000.2-50000.1 -to verilog 3;resistance_map -from analog 4000.2-5000.1 -to verilog 4;resistance_map -from analog 3000.2-4000.1 -to verilog 5;resistance_map -from analog 1.2-3000.1 -to verilog 6;resistance_map -from analog 0-1.1 -to verilog 7;

resistance_map -to analog 2002.2-1e32 -from verilog 0;resistance_map -to analog 1500.2-2002.1 -from verilog 1;resistance_map -to analog 1000.2-1500.1 -from verilog 2;resistance_map -to analog 500.2-1000.1 -from verilog 3;resistance_map -to analog 400.2-500.1 -from verilog 4;resistance_map -to analog 300.2-400.1 -from verilog 5;resistance_map -to analog 1.2-300.1 -from verilog 6;resistance_map -to analog 0-1.1 -from verilog 7;

Note: Both direction definitions are required for unidirectional mapping.

Bidirectional Mapping

See the following syntax and description for strength (Verilog) to resistance (transistor-level) bidirectional mapping.

The bidirectional syntax is

resistance_map resistance_value_range strength;

See the following example for a bidirectional file sample.

resistance_map 90000.2-1e32 0;resistance_map 70000.2-90000.1 1;resistance_map 50000.2-70000.1 2;resistance_map 7000.2-50000.1 3;resistance_map 6000.2-7000.1 4;resistance_map 1000.2-6000.1 5;resistance_map 1.2-1000.1 6;resistance_map 0-1.1 7;


Chapter 3: Using Verilog-SPICE Mixed-Signal FeaturesPostlayout Simulation Through Back-annotation

Postlayout Simulation Through Back-annotation

Mixed-signal simulation supports back-annotation of analog nodes, including those at the analog/digital boundary, with DSPF/SPEF files. The Verilog modules instantiated inside the back-annotated analog blocks do not get back-annotated by DSPF/SPEF files—you must use the SDF files to back-annotate those Verilog modules separately.

Mixed-signal simulation also supports back-annotation of digital blocks with SDF files; mixed nets are not back-annotated (current limitation). The instantiated SPICE subcircuit is not affected by the SDF files— you must use the HSPF/HSPEF files to back-annotate those SPICE subcircuits.

To simulate donut-configured netlists with back-annotation, DSPF/SPEF or HSPF/HSPEF files must be used for the SPICE representations—depending on whether the SPICE block is the top level or at lower levels. Use the SDF files to back-annotate the Verilog modules.

Using the SDF FileUse the $sdf_annotate system task (function) to specify SDF files in a Verilog module. This usage model is identical to VCS. In the following example, the $sdf_annotate system task (function) is called inside the initial block in the my_back_annotation module. The ./dut.sdf SDF file is in the current directory. In this example, the path ./dut.sdf points to the location of the SDF file and module top identifies the Verilog block on which the SDF back-annotation must be applied.

module my_back_annotation();initial $sdf_annotate("./dut.sdf",top);endmodule

In the following example, the $sdf_annotate system task (function) is specified inside the initial block in the top module. In this case, you do not need to specify top in the task—the back-annotation applies on all instances of the module top.

module top ( );........initial $sdf_annotate (“./dut.sdf”);........endmodule


Chapter 3: Using Verilog-SPICE Mixed-Signal FeaturesKnown Limitations

Known Limitations

The following are current limitations:■ NanoSim set_sim_hierid command is ignored in the NanoSim-VCS/

VCS-MX flow. (At all times, use the default "." (period) hierarchical delimiter.)

The following features are not supported in the NanoSim-VCS/VCS-MX flow:■ HAR■ BDC■ .ALTER■ Bisection■ Selective BA (back-annotation)■ SDF annotation on the mixed-net

A mixed net can be back-annotated with an SDF file, but due to hierarchical net name optimization, the delay introduced by the SDF file might not be transferred to the analog side in the D2A direction, which could lead to incorrect results. But in the A2D direction, the delay introduced by the SDF file for the mixed net is accounted for. Because of this inconsistency and potentially incorrect results, the use of SDF back-annotation on mixed nets is strongly discouraged.

Known Problems

The following problems currently exist:■ SDF back-annotation to the library cells does not function properly. Use the

library cells as design modules, if possible.■ When a programming language interface (PLI) is used along with the g++

complier on the Linux platform, an error messages for multiple symbol definition... might be generated. To resolve the error, set the UNIX environmental variable as follows: setenv NO_STDPP 1


Chapter 3: Using Verilog-SPICE Mixed-Signal FeaturesKnown Problems


4

4Mixed-Signal Simulation in the Verilog-SPICEFlow

This chapter describes the required steps for preparing Verilog and SPICE netlists for mixed-signal simulations, and for generating a mixed-signal control file.

Overview

Before using any one of the mixed-signal flows, there are several tasks that should be completed. Verilog netlist files and/or SPICE netlist files may need some modification for a successful netlist compilation. Check these guidelines before simulating a design.

When running a mixed-signal simulation, note that the required mixed-signal simulation control file contains commands that are described in the Creating a Mixed-Signal Simulation Control File section of this chapter.

This chapter contains the following topics:■ Mixed-signal Setup Checklist■ Netlist-Related Issues

• Identical Module/Subcircuit Name

• Case Sensitivity

• Power Supplies

• Netlist Statements

• Simulation Time■ Port-Related Issues

• Port Mapping


Chapter 4: Mixed-Signal Simulation in the Verilog-SPICE FlowMixed-signal Setup Checklist

• Duplicate Ports■ Creating a Mixed-Signal Simulation Control File■ Mixed-Signal Control Commands■ The optimize_shadowfile Command■ Summary of Mixed-Signal Simulation Commands■ Known Limitations

Mixed-signal Setup Checklist

Table 5 is a checklist for the setup of the mixed-signal simulation. Each task that pertains specifically to Verilog, SPICE, or both, is checked and is detailed throughout this chapter.

Netlist-Related Issues

Each topic listed in Table 5 is described in the following sections:■ Identical Module/Subcircuit Name■ Case Sensitivity■ Power Supplies

Table 5 Mixed-signal Setup Checklist

Topic Task Verilog SPICE

Netlist-Related Issues Identical Module/Subcircuit Name

Case Sensitivity

Power Supplies

Netlist Statements

Simulation Time

x

x

x

x

x

x

x

x

x

Port-Related Issues Port Mapping

Duplicate Ports

x

x

x

x


Chapter 4: Mixed-Signal Simulation in the Verilog-SPICE FlowNetlist-Related Issues

■ Netlist Statements■ Simulation Time

Identical Module/Subcircuit NameFor a multi-view cell, the Verilog module name and the SPICE subcircuit names must be identical, as well as the number of ports and their names between the two views.

Case SensitivityFor a multi-view cell, the Verilog module name’s case and the SPICE subcircuit name’s case must be identical. The cases for port names must be identical between SPICE and Verilog views. Also, be aware that every name in HSPICE netlists is treated as lowercase (by default). Because Verilog is case-sensitive, and VCS processes everything as-is (by default), you must be aware of any possible case discrepancies between the two views that may arise.

Power SuppliesPower supplies must be passed to SPICE subcircuits to function properly. If the SPICE subcircuit is instantiated under Verilog, the supply nets can be passed to it by one of the following methods:■ Method #1■ Method #2■ Method #3

Method #1If neither the subcircuit definitions, nor their instantiations under Verilog, contain the supply pins (that is, VDD and VSS), then the supply pins must be propagated to the SPICE subcircuits via.global statements in SPICE.



Method #2If both the subcircuit definitions and their instantiations under Verilog contain the supply pins (that is,VDD and VSS) then there are two options for passing supplies to SPICE:■ Verilog can drive the powernets (e.g. drive VDD to 1'b1 and VSS to 1'b0).

The powernets are fed to SPICE through d2a elements at the boundary. All d2a interface elements include a series resistance map resistor which are undesirable for powernets. To remove the resistance map use the d2a command with powernet option for both VDD and VSS.

Example:

d2a powernet hiv=1.2 lov=0 node=top.vdd;d2a powernet hiv=1.2 lov=0 node=top.vss;

assuming that the power supply is 1.2V. The hierarchical paths to the powernets must be taken from the simv.msv/interface_element.rpt report file.

Note: If the Verilog nets that drive the SPICE supplies are defined as Verilog predefined "supply0" or "supply1" nets, the tool automatically treats those nets as if the d2a powernet command was applied to them. So no rmap resistor is placed at the d2a interface for those nets and they are treated as ideal voltage sources on the analog side.

■ A new two-port SPICE subcircuit must be created that has defined analog supplies. By instantiating this new subcircuit under Verilog, the two ports are connected to the supply pins for other SPICE cells under Verilog. In this way, the SPICE cell receives its supply.

Figure 11 shows an example of the SPICE definitions for Method #1, in which VDD and VSS pins do not appear in the subcircuit port list, and a .global statement is used instead to provide supply net connectivity:



Figure 11 SPICE Supply Pins Passed to a Subcircuit via a .global Statement

Figure 12 shows the Verilog instantiation of the subcircuit defined in Figure 11. Because the power supply nets are defined and passed to SPICE subcircuits as global nets, they do not need to appear in the SPICE instantiation under Verilog:

Figure 12 Instantiation of the Subcircuit Defined in Figure 11

Examples for Method #2 are displayed in Figure 13 and Figure 14. Supply nets are defined as subcircuit ports and are passed to SPICE cells at their instantiations under Verilog.



Figure 13 shows the subcircuit definitions. A two-port SPICE subcircuit is defined that contains analog supply sources:

Figure 13 SPICE Definitions for the Design Cell and a User-Defined Subcircuit

Figure 14 shows the instantiation of these cells under Verilog. Note that the two-port subcircuit containing the analog supplies must be instantiated under Verilog, to establish supply connections to SPICE cells.



Figure 14 Instantiation of SPICE Cell Containing Analog Supplies under Verilog to Establish Supply Connectivity

Method #3If the SPICE subcircuit instantiated under a Verilog (or VHDL) parent has power pins (for example, VDD, VSS) but those power pins are not used in the instantiation and as a result not hooked up, you can use the mixed-signal port_connect command to connect those ports to any analog net that is connected to an ideal supply. That way the SPICE supply pins get hooked up to the right source and allow the SPICE circuitry to function correctly. See The port_connect Command command description.



Netlist StatementsAny statements, keywords, or elements that are not supported by by the analog simulator in a stand-alone analog simulation are also not supported in mixed-signal either. For example, a y element in an Eldo format netlist is not supported in NanoSim and is therefore not supported in NanoSim-VCS.

All other options and/or statements that are required for correct analog simulation setup, such as .options scale=1e-6, must be included in the netlist for mixed-signal as well. The following example shows a SPICE netlist file sample.

.lib ‘models’ TT

.inc ‘cells.spi’

.options scale=1e-6

.temp 27

.global vdd gnd

.subckt test a b c dx1 a b n1 vdd cell1x2 c n1 d ref cell2vref ref gnd 2.0.endsvvdd vdd 0 dc 3.3vgnd gnd 0 dc 0.end

Simulation TimeIn mixed-signal simulation, the simulation time can be determined by either the analog domain (usually by the .tran statement) or in the digital domain (usually a $finish system task in the Verilog code).

In the case when different stop times are specified in analog and digital domains, the smaller of the two times determines the simulation stop time.

Note: For the CustomSim, FineSim, HSIM, or NanoSim tools to be able to report the completed percentage of simulation time, there must be a .tran statement in the SPICE code. The analog engine bases its percentage calculation on the run time given by the .tran statement.


Chapter 4: Mixed-Signal Simulation in the Verilog-SPICE FlowPort-Related Issues

Port-Related Issues

The section contains information about:■ Port Mapping■ Duplicate Ports

Port MappingBy default mixed-signal simulation assumes that a multi-view cell (for example, a cell with both Verilog and SPICE views) has the same number of ports and port names in both views. But if the number of ports or the names of the ports differ between the two views the compilation errors out. To resolve the port inconsistency problem between different views the port_map option of the use_spice, use_verilog or use_vhdl commands must be used.

Also, to handle discrepancy in the number of ports (for example if one view has extra ports), you can use the port_connect command. See Chapter 8, Mixed-Signal Simulation in the VHDL/Verilog-SPICE Flow for a description of these commands and options.

If there is no port mismatch between different views of a cell, ports from different views get mapped as described below.

For a SPICE parent instantiating a Verilog child, by default, ports are mapped by position. However, name-based port mapping can be achieved by creating a SPICE view for the Verilog cell (if one is not already there). The tool then automatically maps ports by name for the child Verilog cell, comparing the port order between the SPICE and Verilog views, and rearranging the Verilog port order to match the SPICE view.

In the case of a Verilog parent instantiating a SPICE child, either name-based or position-based port-mapping can be used. When using port-mapping by name, the Verilog module port name begins with a period character ( . ), and must be identical to the SPICE port name. The cases for port names at the instantiation must be identical to the case of ports in the subcircuit definition. Figure 15 demonstrates the Verilog syntax for name-based port mapping. Figure 16 is an example of port mapping by name.



Figure 15 Verilog Syntax for a nor Gate Instance

Figure 16 Port Mapping by Name

Port-mapping at the Verilog instantiation can also be implemented by the port position. Port count and positions must be identical between the Verilog instantiation and the SPICE subcircuit definition. In Figure 17, the port zn of the SPICE subcircuit nor1 is connected to the wire out1 at the instantiation of that subcircuit in Verilog. The port count must also be identical.

Figure 17 Port Mapping by Position

nor i2 (.a(in1));

instance port name

module port name

instance namemodule name

// Verilog instantiation

...

//name mapping

nor2 i2(.a(in1),

.b(in2), .zn(out2));

*SPICE subckt

.subckt nor2 zn a b

...

.ends


...

//position mapping

nor1 i1 (out1, in1, in2);

*SPICE subckt

.subckt nor1 zn a b

...

.ends



Port-mapping between Verilog and SPICE can also be achieved for bus ports. By default, mixed-signal simulation requires that the bus members be contiguous in the subcircuit definition (that is, no other port defined between any two members of the same bus port), and the ports must be sequentially numbered—ascending or descending. Failing to meet these two requirements leads to compilation failure. Additionally, the ascending or descending order of the bus members in SPICE must be identical to the order expected by the Verilog parent block; otherwise, the port connections are incorrect.

However, if the bus port definition in the SPICE subcircuit does not meet these requirements, the problem can be resolved by defining a Verilog view for the subcircuit and using the following mixed-signal command to set the port order in the SPICE subcircuits to that of their Verilog view:

spice_port_order_as_vlog;

Figure 18 shows an example of a SPICE subcircuit with bus ports and its instantiation in a Verilog parent block. In the SPICE subcircuit, the port names a[3], a[2], a[1] and a[0] are contiguous, and the sequencing of the bus members meets the expectation of the parent Verilog (both are descending).

As a result, compilation should be without problems related to the bus order in SPICE. In addition, the port connections for this bus are correct since both the bus port a in SPICE and the wire ai in Verilog are in a descending order.

By default, the tool assumes that the SPICE port names that connect to a mixed-net and contain closed bracket characters [ ] are members of a bus. If the bus notation in the SPICE subcircuit is a string different from [ ], use the mixed-signal bus_format command to override the default SPICE bus notation. For more information, see The bus_format Command section.

Figure 18 Port Mapping for the Verilog Vector Port and SPICE Scalar Port


...

addr i3(.a(ai[3:0]),

.b(bi[3:0]), .cin(ci),

.s(su[3:0]), .cout(co));

...

*SPICE subckt

.subckt addr a[3] a[2]

+a[1] a[0] b[3] b[2] b[1]

+b[0] cin s[3] s[2] s[1]

+s[0] cout

.ends


Chapter 4: Mixed-Signal Simulation in the Verilog-SPICE FlowCreating a Mixed-Signal Simulation Control File

Duplicate PortsDuplicate port names in the SPICE subcircuit cannot be used, except for power supply nodes.

Parameterized Bus PortsParameterized Verilog and VHDL bus ports at the analog/digital boundary are not supported in mixed-signal simulation. These are bus ports with a variable width, and usually a user-defined parameter determines the bus width for these ports.

The following Verilog example uses a parameterized bus width:

`define BUS_WIDTH 8...

module proc ( din, dout);input [ (`BUS_WIDTH-1) : 0 ] din;output [ (`BUS_WIDTH-1) : 0 ] dout;...

If the proc module is at the digital/analog boundary (for example, if this Verilog block is being replaced by its SPICE view with the use_spice command, or if this module is replacing its SPICE view with the use_verilog command) then the mixed-signal compilation creates an error. The size of the buses must be explicit for those digital cells that are located at the digital/analog boundary.

However, the use of a Verilog or VHDL cell with parameterized bus ports that is located elsewhere in the design (not touching the analog/digital boundary) is completely legal.

Creating a Mixed-Signal Simulation Control File

By default, VCS looks for vcsAD.init file as the mixed-signal simulation setup file if no file name is specified with the VCS switch -ad. You can specify a different file name with the -ad=<control_file_name> compile-time option. The mixed-signal simulation control file contains all the commands to configure mixed-signal simulation.

The mixed-signal simulation setup file must contain the choose command.


Chapter 4: Mixed-Signal Simulation in the Verilog-SPICE FlowCreating a Mixed-Signal Simulation Control File

Each of the following sections includes a mixed-signal control command description, the command’s syntax, and examples:■ The a2d Command■ The bus_format Command■ The choose Command■ The d2a command■ The duplicate_net_inst_name Command■ The e2r command■ The ie_activity_rpt Command■ The insert_cell Command■ The map_by_node Command■ The mview_vlog_noportswap Command■ The optimize_shadowfile Command■ The param_pass Command■ The port_connect Command■ The port_dir Command■ The print_ie_res Command■ The print_thru_net Command■ The r2e command■ The remove_d2a Command■ The rt_a2d Command■ The rt_d2a Command■ The rt_e2r Command■ The rt_r2e Command■ The rmap_file Command■ The shadow_file_dir Command■ The spice_port_order_as_vlog Command■ The spice_top Command


Chapter 4: Mixed-Signal Simulation in the Verilog-SPICE FlowMixed-Signal Control Commands

■ The use_spice Command■ The use_verilog Command

To use these commands, the following rules apply:■ All commands must be completed with a semi-colon (;)■ To create a comment line, insert the double forward-slash character (//)■ Commands can span more than one line with no line continuation character

needed. The Enter character at the end of each line serves as the line continuation character.

For example, the following command spread across two lines is considered one command line:

choose nanosim -nspice test.spi -C config –nvec test.vec -o output_files/nanosim ;

Mixed-Signal Control Commands

The following section describes the syntax and application of mixed-signal control commands.

Note: Starting from the 2009.06 release, the additional VCS switches (-ad_hsim and -ad_xa) which were previously required for HSIM and CustomSim mixed-signal simulations, are no longer needed.

The a2d CommandUse this command to control all aspects of the A2D interfaces in CustomSim/FineSim/HSIM/NanoSim-VCS and CustomSim/FineSim/HSIM/NanoSim-VCS-MX solutions. If you do not specify this command, by default all a2d events are triggered at 50% of the local VDD. Note that the dynamic supply option is only available in CustomSim-VCS and CustomSim-VCS-MX.



Syntax

a2d [ loth=lo_thrsh[V | %] ] [ hith=hi_thrsh[V | %] ] [ hiz_off | hiz_on ]<cell=cell_name port=port_name | node=hier_name> [ vdd=hier_name [minv=min_vdd_voltage] [minv_logic= [0 | 1 | X | Z ]][ceff=value]

Options Description

loth=lo_thrsh[V | %]hith=hi_thrsh[V | %]

These two options determine the low and high a2d threshold values. They can be expressed either as absolute values (1.1V, 2.2) or as a percentage of the supply (10%, 90%). For dynamic supply (when the vdd= option is specified) they can only be specified as a percentage of the supply voltage. That way, as the supply voltage changes during the simulation, so do the a2d thresholds.



hiz_off Turns off the a2d drive strength calculation. All a2d events are passed to digital with the Verilog default drive strength of 6 (strong).

The application of this option is for inout (bidirectional) interface nets. With this option enabled, the analog side always sends values across to the digital side with a "strong" drive strength (st0 or st1). This means that the interface signal as seen in the digital output never shows HiZ.

You can use this option to remove (mask) the HiZ glitches on bidirectional interface nets. The HiZ glitches are caused during the periods when neither the analog nor the digital circuits are driving the interface net. With this option enabled, the interface element always drives the digital side, with a st0 or st1, based on the voltage on the analog side and the a2d thresholds. This means that the digital net always has a non-HiZ driver and as a result no HiZ appears on the digital image of the interface net.

Caution: HiZ glitches usually reflect the correct behavior of the circuit. Removing them by using the hiz_off option can potentially mask a real phenomenon or problem in the circuit and is discouraged.

hiz_on Turns on the a2d drive strength calculation. For each a2d event, the analog engine calculates the analog output resistance and uses that value as an index to the resistance map file to get the corresponding Verilog drive strength to pass to Verilog.

With this option enabled, HiZ states are passed to digital if the analog engine identifies them.

This feature is enabled by default for bidirectional interface nets.

Options Description



cell=cell_name, port=port_name, node=hier_name

The command can be applied as cell-based, in which case the cell name and port name must be given.

Alternatively, the command can be instance based, in which case the hierarchical path to the instance port must be given.

Cell and port names can contain the asterisk (*) wildcard character. For example, node=top.i1.ad*, cell = *foo, port=*

vdd=hier_name This option enables the dynamic supply feature. Without this option, the a2d command behaves as if the reference supply voltage was constant. If you use this option, the a2d high and low thresholds change as the supply voltage identified by the “hier_name” changes during the simulation. With this option enabled, only the “%” format can be used to specify “loth” and “hith” parameters. The supply net identified by the “hier_name” could be either an internal analog node, a top-level analog net, a regular interface net (d2a, inout) or a “real” interface net.

minv=min_vdd_voltage This option determines the minimum voltage for VDD that turns off the a2d conversion. The purpose of the option is to disable a2d conversions when the analog supply is very low and it does not make sense to continue converting analog signals to logic values, giving the impression to the digital domain that the analog circuit is still functioning. When specified, if the VDD supply associated with the interface element goes below this value, the a2d conversion is turned off and a fixed logic value is passed to digital. The “minv_logic” option determines what that fixed logic value would be. By default, minv is set to 100mV.

minv_logic= [0 | 1 | X | Z ] This option determines what logic value is passed to the digital engine when the a2d conversion is disabled because of “minv” trigger. By default “Z” is passed to digital.

Options Description



Examples

The following example sets the a2d low and high thresholds for node top.i1.ctl to 0.2V and 1.7V respectively.

a2d loth=0.2 hith=1.7 node=top.i1.ctl;ora2d loth=0.2V hith=1.7V node=top.i1.ctl;

The following a2d command sets the a2d low and high thresholds for node top.i1.ctl to 20% and 80% of the local supply voltage.

a2d loth=20% hith=80% node=top.i1.ctl;

The following a2d command enables the dynamic supply feature and sets the a2d thresholds for node top.i1.ctl to 50% of the referenced VDD node. As the voltage of the VDD node changes, so do the a2d thresholds.

a2d loth=50% hith=50% node=top.i1.ctl vdd=top.vdd;

The following a2d command enables the dynamic supply feature and sets the a2d thresholds for node top.i1.ctl to 40% and 60% of the referenced VDD node. It also sets the minv value t0 500mV. As a result if the VDD voltage drops below that value, the a2d conversion would be shut off and HiZ is passed to the digital side instead.

a2d loth=40% hith=60% node=top.i1.ctl vdd=top.vdd minv=500mV;

The following a2d command enables the dynamic supply feature and sets the a2d thresholds for node top.i1.ctl to 40% and 60% of the referenced VDD node. It also sets the minv value to 500mV and specifies logic value "X" to be transferred to the digital side if the VDD voltage drops below the minv value.

a2d loth=40% hith=60% node=top.i1.ctl vdd=top.vdd minv=500mV minv_logic=x;

Note: If multiple a2d commands in the mixed-signal control file target the same node, the last command overrides all the others.

ceff=value Lets you model the loading effect of the digital blocks driven by the analog interface net. By default, there is no extra capacitance inserted at the a2d interface net. You can use this option to specify a loading capacitance to be inserted at the a2d interface net or nets. The unit of the value is Farady.

Options Description



The following example specifies top.n1 to be an a2d interface net and adds 1pF capacitance at the top.n1 node.

a2d node=top.n1 ceff=1p;

The following example specifies the ports in1 of cell blk1 to be a2d interface nets and adds 2pF capacitance at this port.

a2d cell=blk1 port=in1 ceff=2p;

The bus_format CommandThe bus_format command identifies the bus notation used in the SPICE netlist. This command causes the tool to treat multiple SPICE ports as members of a bus and group them together when making connections between SPICE and Verilog/VHDL buses at the analog/digital boundary. It allows more than one bus format to be identified as the SPICE bus notation. The [%d] notation is the default bus format for SPICE. The ports in a SPICE subcircuit that follow the [%d] notation, such as a[2] a[1] a[0], by default are considered members of a bus when connecting to Verilog.

Syntax

bus_format [open_char] %d [close_char] [[open_char] %d [close_char]... ] ;

Examples

The following example shows how to identify angle brackets (< >) as the bus notation used in the SPICE netlist:

bus_format <%d>;

*SPICE subckt .subckt addr4 a<3> a<2> a<1> a<0> +b<3> b<2> b<1> b<0> cin+s<3> s<2> s<1> s<0> cout.ends

In the following example, more than one bus format is defined for SPICE. Both ports inp and out are considered as busses when connecting to Verilog.

bus_format <%d> _%d ;*SPICE subckt definition.subckt data_blk inp<2> inp<1> inp<0> out 2 out_1 out_0....ends



The following example specifies that the underscore ( _) character is used as open_char in SPICE bus notation, and no character is used as close_char.

bus_format _%d;

*SPICE subckt .subckt addr4 a_3 a_2 a_1 a_0 +b_3 b_2 b_1 b_0 cin+s_3 s_2 s_1 s_0 cout.ends

Note: Mixed-signal simulation only supports the following bus format characters for SPICE: { } < > [ ] _

The choose CommandUse the choose command to point to the analog simulator (the CustomSim, FineSim, HSIM, or NanoSim tools) and pass command line options to it.

Syntax

choose xa xa_command_line_options;choose finesim finesim_command_line_options;choose hsim hsim_command_line_options;choose nanosim nanosim_command_line_options;

Mixed-signal simulation does not support all NanoSim command-line options. See Appendix C, “NanoSim-supported Command-line Options,” for the supported options.

The following example specifies that a SPICE netlist named net.spi must be read by the CustomSim tool. It also uses the -c command line option to pass CustomSim analog configuration commands stored in the xa.cmd file.

//This is a commentchoose xa -n net.spi -c xa.cmd;

For the FineSim tool:

//This is a commentchoose finesim net.spi -o out;

Specifies that FineSim Pro is the analog engine in the mixed-signal simulation and a SPICE netlist named net.spi must be passed to it. It also sets the prefix for output files to out.



Examples

The following example indicates that FineSim SPICE is the analog engine in the mixed-signal simulation and a SPICE netlist names net.spi must be passed to it. It also sets the prefix for output files to out;.

// This is commentchoose finesim -spice net.spi -o out;

The following example specifies that HSIM is the analog engine in the mixed-signal simulation and a SPICE netlist named net.spi must be passed to it.

//This is a commentchoose hsim -i net.spi;

The following NanoSim example specifies that a SPICE netlist named net.spi and an analog configuration file named cfg for the NanoSim simulation must be read. Note that the first line is a comment, which is preceded by a double-slash character (//).

//This is a commentchoose nanosim -n net.spi -C cfg;

The d2a commandUse this command to control all aspects of the D2A interfaces in the CustomSim/FineSim/HSIM/NanoSim-VCS and CustomSim/FineSim/HSIM/NanoSim-VCS-MX solutions. Note that the dynamic supply option is only available in CustomSim-VCS and CustomSim-VCS-MX.



Syntax

d2a [powernet] [rf_time=slope_time] | [rise_time=rise_time] [fall_time=fall_time] [delay=delay_time] [x2v=0|1|2|3|4] hiv=high_voltage [ V | % ] lov=low_voltage [V | % ] <cell=cell_name port=port_name | node=hier_name> [ vdd = hier_name ]

Options Description

powernet Identifies a d2a node as an ideal voltage source on the analog side without the resistance map resistor. This option must be used when Verilog drives analog power nets in order to remove the series resistance map resistors and to allow efficient partitioning of the analog circuit.

Note that If the Verilog wires driving the SPICE supply are defined as "supply1" or "supply0" types in the Verilog code, the tool treats the d2a interfaces connected to those wire types as if the d2a command with the powernet option was used. This means that no rmap resistors are inserted at the d2a interface and the supply nets are treated as ideal sources in analog.

rf_time=slope_time Specifies the analog rise and fall times. The default time unit is in seconds, so specify the sub-unit with the value rf_time=1.5n, for example. With this option, both rise and fall times are set to the same value.

rise_time=rise_time Specifies the analog rise time. The default time unit is in seconds, so specify the sub-unit with the value rise_time=1n rise_time=2n, for example.

fall_time=fall_time Specifies the analog fall time. The default time unit is in seconds, so specify the sub-unit with the value fall_time=1n fall_time=2n, for example.

delay=delay_time Specifies the delay before the analog transition starts. The default time unit is in seconds, so specify the sub-unit with the value delay=1.5n, for example.



x2v= Specified with a value of 0, 1, 2, 3 or 4. Sets the rule on how a logic X must be translated to a voltage level on the analog side:

Use this option to manage the translation of the X to a voltage level.■ 0: always set to the logic zero voltage (default)■ 1: always set to the logic one voltage■ 2: if node is in PWL, SMS, or analog mode, set

to (the logic one voltage + the logic zero voltage)/2; otherwise, set to low_voltage.

■ 3: set to previous voltage■ 4: if logic = 0, set to the logic one voltage else;

if logic = 1 set to the logic zero voltage else get previous voltage.

hiv=high_voltage By default the logic 1 voltage value is the voltage of the local supply. If the tool cannot trace the d2a net to an ideal supply, it assumes 3.3V. This option allows you to overwrite the default voltage for logic 1. It allows you to overwrite the default value by either expressing an absolute voltage value (for example, 1.2V or 1.2) or as a percentage of the supply voltage (fore example, 90%).

If the dynamic supply feature is enabled (by using the vdd= option) the values for hiv can only be specified as a percentage of the VDD net.

You must use this option combination with the lov= option.

lov=low_voltage By default the logic 0 voltage value is assumed to be 0V. This option allows you to overwrite that default value. The value can be expresses as an explicit voltage value (for example, 0.2V or 2.0) or as a percentage of the local supply (for example, 10%).

If the dynamic supply feature is enabled (by using the vdd= option) then the values for lov can only be specified as a percentage of the VDD net.

You must use this option in combination with the lov= option.

Options Description



Examples

The following d2a command sets the high and low d2a voltages to 1.8V and 0.1V

d2a hiv=1.8 lov=0.1 node=top.i1.ctl;

The following d2a command sets the high and low d2a voltages to 1.2V and 0V.

d2a hiv=1.2V lov=0V node=top.i1.ctl;

The following two commands define interface nets top.vdd and top.vss as ideal supplies while setting their high and low voltage values to 1.2V and 0V respectively.

d2a powernet hiv=1.2 lov=0 node=top.vdd;d2a powernet hiv=1.2 lov=0 node=top.vss;

The following command enables dynamic supply and defines the interface net top.i1.rst as a d2a interface for which high and low voltages track the


The option can be applied as cell-based, in which case the cell name and port name must be given.


Cell and Port names can contain the asterisk (*) wildcard character. For example, node=top.i1.ad*, cell = *foo, port=*

vdd=hier_name This option enables the dynamic supply feature. Without this option, the d2a behaves as if the reference supply voltage was constant. If you use this option, the d2a high and low voltages change as the supply voltage identified by the “hier_name” changes during the simulation.

With this option enabled, only the “%” format can be used to specify “lov” and “hiv” parameters. The supply net identified by the “hier_name” could be either an internal analog node, a top-level analog net, a regular interface net (d2a, inout) or a “real” interface net.

Options Description



changes on node top.i2.vdd. The high and low voltages are set to 90% and 10% of the voltage on the node top.i2.vdd.

d2a hiv=90% lov=10% node=top.i1.rst vdd=top.i2.vdd;

The following command enables dynamic supply for all d2a interface elements below the hierarchical level “top.i1”. All those d2a interfaces track the changes on supply net “top.i1.vdd” dynamically. The “hiv” and “lov” values are set to 100% and 0% of the voltage on node top.i1.vdd.

d2a hiv=100% lov=0% node=top.i1.* vdd=top.i1.vdd;

Note: If multiple d2a commands in the mixed-signal control file target the same node, the last command overrides all the others.

The duplicate_net_inst_name CommandThis command allows the same name to be used for both an instance and a net in SPICE.

Using the same name for a node and an instance is allowed in SPICE but it is illegal in Verilog and causes a compilation error.

Because mixed-signal simulation builds a Verilog shadow module for each instance of SPICE subcircuit by default, if the same name is used both as an instance and a net name anywhere in the SPICE netlist, the Verilog shadow modules inherits the same net and instance names which violate the Verilog rule and lead to a mixed-signal compilation error.

This command, if used with the enable option, resolves that problem by internally renaming the net name to "net_name_DUPLICTE_INST_n" in Verilog (not in SPICE, original duplicate names are preserved in SPICE) where "n" is a numerical index starting from 0 and going up if the duplicate name is used for more than one net.

Syntax

duplicate_net_inst_name enable | disable

One of the options (enable or disable) must be used with the command. The enable option allows identical names to be used for both SPICE net(s) and instance in mixed-signal by renaming the net name to net_name_DUPLICATE_INST_n in the Verilog shadow module created for the SPICE instance, where n is a numerical index.



If the command is used with the disable option (default behavior of mixed-signal simulation), duplicate names used for net(s) and an instance in SPICE causes a compilation error:

Examples

x_and1 a x_and1 y and2x2

Here the subcircuit and2x2 is instantiated with instance name x_and1 while at the same time one of the nodes connected to its ports is also called x_and1. This is allowed in SPICE, but illegal in Verilog, and causes an error during mixed-signal compilation.

To resolve it, use the following command inside the mixed-signal control file:

duplicate_net_inst_name enable;

By doing so, the net name is renamed to x_and1_DUPLICATE_INST_0 in Verilog to avoid the conflict, but the names remain intact in SPICE.

The e2r commandUse the e2r command to control the behavior of an e2r interface element. This command lets you set the threshold at which e2r events occur and also allows e2r to convert analog voltage values (default) or current values to digital.

Syntax

e2r [type=i] [fidelity=<value>] [gain=<value>] [res=<value>] node=hierarchical_node_name


type Determines if the e2r is converting voltage values to digital (default) or the current through a resistors (with type=i).

fidelity Determines the absolute voltage/current threshold value for e2r events in the engineering format. The default value is 1 % of the maximum voltage/current value.

gain Determines if the analog voltage/current needs to be multiplied by a multiplier when converted to digital. The multiplier could be a negative number as well. The default value is 1.



The following example shows an e2r interface element at hierarchical path top.i1.ictrl can be set to a current type. The current through the 10 Ohm resistor identified by the res=10 option is converted to digital real values.

Examples

e2r type=i node=top.i1.ictrl res=10;

The next example shows how the fidelity for the e2r interface located at test.pblk.clk is set to 1mV.

e2r fidelity=1e-3 node=top.pblk.clk;

The ie_activity_rpt CommandEnables dumping the interface activity statistics into the report file, simv.msv/interface_activity.rpt. By default the report file gets updated at time intervals equal to 10% of the simulation time specified by the .tran statement.

This file gets generated only in the Verilog-SPICE and VHDL/Verilog-SPICE flows, and only if the interface activity report is enabled with the ie_activity_rpt command. The report file has an entry for each interface element (a2d, d2a, e2r, or r2e) and displays how many events have occurred for each interface.

Syntax

ie_activity_rpt enable [-flush <flush percent>% | -flush <flush time>];

res Determines the value of the resistor, which is put between the interface net and ground to measure the current through it. This option is only applicable with type=i.

node Specifies the hierarchical path to the e2r interface. You can specify wildcard characters (*) in the path.

Options Description

enable Enables dumping of the interface_activity.rpt file in the simv.msv directory.




Examples

The following example shows how to enable dumping the interface activity report in the simv.msv/interface_activity.rpt file.

ie_activity_rpt enable;

The following example shows how to enable dumping the interface activity report and sets the intervals at which the file gets updated to 2ns.

ie_activity_rpt enable -flush 2ns;

The following example demonstrates how to enable creating the interface activity report and sets the refresh interval for the file to 5% of the .tran end time.

ie_activity_rpt enable -flush 5% ;

The insert_cell CommandUse this command to insert a 2-port SPICE netlist on the analog side of an interface net.

-flush <flush percent>%

Specifies the simulation time interval at which the report file gets updated. The interval is given as a percentage of the end time specified in the .tran statement. By default the interval is be 10% of the .tran end time. If there is no .tran statement in SPICE, this option is ignored.

-flush <flush time>

Specifies the absolute simulation time intervals at which the report file gets updated.

Options Description



Syntax

insert_cell [model= ADFMI_model_name [param=parameter_list] ] [subckt= subcircuit_name apin=port_name dpin=port_name ] <cell=cell_name port=port_name | node=hier_name> subckt= subcircuit_name apin=port_name dpin=port_name

Examples

To insert the 2-port SPICE subcircuit:

.subckt multiplier in out

...

.ends

At the interface net top.rst, the following command must be used:

insert_cell subckt=multiplier apin=in dpin=out node=top.rst;

Options Description

model= ADFMI_model_name [param=parameter_list]

Supported only in NanoSim-VCS, NanoSim-VCS-MX and Verilog-AMS-SPICE solutions: identifies the name of the ADFMI model to be inserted at the interface.

subckt= subcircuit_name apin=port_name dpin=port_name

Identifies a two-port subcircuit to be inserted on the analog side of the interface and determines which port faces the analog side and which the digital side.

The apin= and dpin= options are only needed if the the two ports of the inserted cell are not called the default names apin and dpin.


The command can be applied as cell-based, in which case the cell name and port name must be given.


Cell and port names can contain the asterisk (*) wildcard character. For example, node=top.i1.ad*, cell = *foo, port=*



To insert the 2-port SPICE subcircuit:

.subckt term apin dpin

...

.ends

At the interface net test.i1.d_in, the following command must be used:

insert_cell subckt=term node=top.i1.d_in;

The map_by_node CommandUse the map_by_node command if a specific resistance value is required for d2a conversion at an interface node, instead of the value calculated from the resistance map file. This command is only effective in the digital-to-analog direction.

Syntax

map_by_node r=resistance_value node=node_name(s);

Examples

In the following example, the 5 ohm resistance value is applied to the interface resistor connected to the top.n1 node.

map_by_node r=5 node=top.n1;

When multiple map_by_node commands are used for the same mixed-nets in the mixed-signal simulation setup file, the last command takes precedence.

The mview_vlog_noportswap CommandUse the mview_vlog_noportswap command to force mixed-signal simulation to use the SPICE port order. This command applies to multi-view Verilog blocks instantiated under SPICE. If the Verilog and SPICE views of the child block have different port orders, by default mixed-signal simulation rearranges the Verilog ports such that they match SPICE order so that the connectivity between Verilog ports and top-level SPICE nets take place correctly.

If for whatever reason this default behavior needs to be disabled, this command can be used to do so.



The optimize_shadowfile CommandUse the optimize_shadowfile command to optimize the shadow Verilog hierarchy generated for SPICE blocks. To save compile time, this command instructs the analog engine that it should not generate unnecessary Verilog dummy modules for blocks with the SPICE view. If references to nets in the transistor-level netlist (from the Verilog netlist) are made when this command is used, compilation errors related to the cross-module references (XMR) may occur. Be cautious when using this option with XMR.

Syntax

optimize_shadowfile;

In the following example, the CustomSim/FineSim/HSIM/NanoSim tools are instructed not to generate some of the Verilog dummy modules so the Verilog hierarchy under the SPICE view can be optimized.

optimize_shadowfile;

Note: Using this command prevents VCS from probing inside the SPICE hierarchy; this can prevent optimization of D2D through-nets, potentially increasing the number of interface nodes.

The param_pass CommandThis command enables parameter passing between Verilog/VHDL and SPICE. Use the param_pass command’s disable and enable options to change the default behavior.

Table 6 shows the default behavior for parameter passing in different flows. To change the default behavior, use the param_pass command with the proper switch: enable or disable.

Syntax

param_pass enable | disable

Table 6

Flow Default Description

Verilog-AMS-SPICE enable Parameter passing between Verilog and SPICE is enabled by default.



The port_connect CommandUse this command when a SPICE cell is instantiated under a Verilog or VHDL parent and it has extra ports (usually VDD and VSS) that are not connected in the instantiation. This command allows those extra ports to connect to a hierarchical net either in the analog or digital domain.

Note: If a hierarchical net is at the top level, you must define it as a global net. For example, if you specify:

port_connect -cell inv ( inv_vdd => vdd , inv_vss => vss );

And vdd and vss are not declared as global (there is no such line: .global vdd vss), then the connection is not made.

Syntax

port_connect <cell_name> spice_port_name => hierarchical_net, ... | spice_port_name => snps_open

Examples

Here the SPICE cell inv1 is instantiated under a Verilog-top testbench:

inv1 i1 (.y(y_wire), .a(a_wire) );

The SPICE cell has two extra ports called vdd, vss that are not present in the Verilog view of the cell and as a result are not connected in the instantiation above.

Verilog-SPICE disable Parameter passing between HDL and SPICE is disabled by default.

VHDL/Verilog-SPICE disable Parameter passing between HDL and SPICE is disabled by default.


hierarchical_net The hierarchical path to the net the extra port needs to be connected to.

Table 6

Flow Default Description



.subckt inv1 y a vdd vss….module inv1 (y, a);….

Assuming that in the body of SPICE there are two ideal supplies defined as following:

v3 vdd! 0 DC=3.0v2 vss! 0 DC=0

You can use the following mixed-signal command to connect the dangling SPICE ports vdd and vss to to the nets connected to the ideal supplies:

port_connect -cell inv1 ( vdd => vdd! , vss => vss! );

In the following example the SPICE cell inv1 instantiated under a Verilog-top testbench:

inv1 i1 (.y(y_wire), .a(a_wire) );has two extra ports called vdd, vss that are not present in the Verilog view of the cell:.subckt inv1 y a vdd vss….module inv1 (y, a);….

Assuming that two ideal supplies are defined in subcircuit at the hierarchical path top.i_power_blk as:

v1 vdd 0 DC=1.2v2 vss 0 DC=0

You can use the following mixed-signal command to connect the dangling SPICE ports vdd and vss to to the nets connected to the ideal supplies:

port_connect -cell inv1 ( vdd => top.i_power_blk.vdd , vss => top.i_power_blk.vss );

The port_dir CommandDeclares port directions for SPICE subcircuit ports that cannot be derived from an equivalent multiple verilog or vhdl view port direction.



Syntax

port_dir <cell_name> [input|output|inout] <spice_port_name>, <spice_port_name>;

Examples

port_dir -cell invs1 (input a;output y);port_dir –cell invs1 (input a,b; output y);

The print_ie_res CommandPrints out analog output resistance values for mixed-signal interface elements for which the driver strength calculation is enabled.

Syntax

print_ie_res [limit=yyy] node = hier_node_name | cell=cell_name port=port_name;


cell_name Specifies the cell name.

input|output|inout Specifies the port direction.

spice_port_name Specfies the spice port name.


limit=yyy Specifies the upper limit for the resistance to be graphed in the output waveform file. The value can be expressed as plain numerical (such as 1000), metric (such as 1k or 1M or 250m), or scientific notation (such as 1e3). The default upper limit is 1MOhms.

node = hier_node_name

Specifies the hierarchical path to the interface element. The hierarchical path is taken from the simv.msv/interface_element.rpt file. You can specify a wildcard character ("*") in the node name.



DescriptionBidirectional interface elements are common in mixed-signal designs. These interface elements usually model I/O elements that can assume one of the following two states during the circuit operation:■ Transmitter (driver)■ Receiver (high Impedance (HiZ) input)

Two or more of such I/O elements are connected together to allow data exchange between multiple transmitters and receivers. Usually at each given time only one of the I/O elements is in transmission mode and the rest of the I/Os are in HiZ receiver mode. For this data exchange to occur, it is imperative that all the receivers stay in HiZ mode and do not drive the interface. Otherwise they would interfere with the transmitter (active driver).

Note: If you use a2d hiz_off, the print_ie_res is ignored for that interface element. If you use a2d without hiz_on, and the net is not bidirectional, the print_ie_res command is ignored for that interface element.

In a mixed-signal simulation, it is possible that one of the I/O elements is modeled in SPICE and another in RTL. In that case it is important that when in the receiver mode, the SPICE I/O (blue device in Figure 19) needs to be in an HiZ state and does not drive, and potentially corrupt, the value driven by the digital driver (red device in Figure 19). Usually for that to happen, the resistance map for the bidirectional interface element (see Figure 19) for the SPICE I/O must be adjusted such that when the SPICE I/O is in the receiver mode, its output resistance satisfies the minimum resistance requirement for HiZ. You use The rmap_file Command to specify the resistance map file.

For example, if the output resistance of the SPICE I/O is 1.2 kOhms when in receiver mode, the resistance map for this interface element must be modified such that the HiZ threshold is brought down from the default 90 kOhms to, for example, 1kOhms. That way when the SPICE I/O is in the receiver mode it exhibits an output resistance larger than the HiZ resistance threshold and the interface element goes into HiZ (not driving the interface net).

cell=cell_name port=port_name

Specifies the cell name and port name. You must specify both names, in which you can use wildcard characters ("*").




Figure 19 Bidirectional I/O Buffers Connecting to the Same Net

In this process, knowing the value of the output resistance exhibited by the SPICE I/O element, especially during the receiver mode, is crucial to proper adjustment of the resistance map for the interface element, as shown in Figure 20.

The capability to view the output resistance of the analog drivers at the analog/digital boundary in the analog waveform file and decide how or whether to adjust the resistance map for that interface element is only applicable to interface elements for which analog drive strength calculations take place, which are:■ inout interface elements■ a2d interface elements for which drive strength calculation is enabled with

the hiz_on option of the a2d command

ctrlctrl ctrl

TX

RX

TX

RX



Figure 20 Output Resistance of the Analog Driver is used for Drive Strength Calculation of the Interface Element

ExamplesThe following command enables dumping the output resistance for interface net top.i1.ckgen.rst:

print_ie_res node = top.i1.ckgen.rst ;

The output resistances bigger than 1MOhms is capped and displayed as 1MOhms:

ctrlctrl ctrl

TX

RX

TX

RX

SPICE Digital

ctrlctrlctrl

ie

Output resistance



The following command enables dumping the output resistance for interface net at port vbc of cell bandgap and limits the display of output resistances bigger than 10kOhms:

print_ie_res limit=10k cell=bandgap port=vbc ;

The output resistances bigger than 10kOhms is capped and displayed as 10kOhms:

1MEG

Res(rst)

10K

Res(ctl)



The print_thru_net CommandUse the print_thru_net command to force the CustomSim/FineSim/HSIM/NanoSim tools to instantiate a dummy A/D or D/A converter at the given mixed-net to make an image of through-nets visible in the other domain. By default, a2a through-nets are only dumped from the analog domain, and d2d through-nets are only dumped from the digital domain.

Syntax

print_thru_net a2a|d2d|all;

Important: When the print_thru_net command is added, extra A/D or D/A converters are inserted, which could potentially result in a slower simulation.

The r2e commandUse the r2e command to control the behavior of an r2e interface element. This command lets you set the threshold at which r2e events occur and also allows defining r2e as a voltage source (default) or a current source on the analog side of the interface.

Syntax

r2e [type=i] [fidelity=<value>] [gain=<value>] node=hierarchical_node_name [rf_rate=<value>]


a2a Prints the digital image of all a2a through-nets in the digital output file

d2d Prints the analog image of all d2a through-nets in the analog output file

all Combines both the a2a and d2d arguments


type Determines if the r2e is modeled as a voltage source (default) or as a current source (with type=i).



The following example shows an r2e interface element at hierarchical path top.i1.ictrl can be set to a current type:

Examples

r2e type=i node=top.i1.ictrl;

The next example shows how the fidelity for the r2e interface located at test.pblk.clk is set to 1mV.

r2e fidelity=1e-3 node=top.pblk.clk;

The remove_d2a CommandUse the remove_d2a command to remove a D2A (digital-to- analog) mixed-net from the digital-analog boundary, and apply a constant DC voltage on the analog side source with a value defined by the dc= argument. The node= argument takes a mixed-net. The node= argument cannot take the asterisk wild card character ( * ), such as node=* . However, a partial node search using the asterisk character is legal; for example, node = top.din* matches all signals with names starting with the top.din string.

Syntax

remove_2da [dc=dc_voltage_source_value] node=node_name;

fidelity Determines the absolute voltage/current threshold value for r2e events in the engineering format. The default value is 1% of the maximum voltage/current value.

gain Determines if the analog voltage/current needs to be multiplied by a multiplier. The multiplier could be a negative number as well. The default value is 1.

node Specifies the hierarchical path to the r2e interface. You can specify wildcard characters (*) in the path.

rf_rate The rf_rate has a unit of second/volt, with the default set to 10ps/V. This value indicates how fast the voltage changes from the current value to the target value. It is recommended to avoid too fast changes in voltage values that might create unwanted current peaks.




Examples

The following example shows that top.VVDH is no longer a mixed-net node. The constant dc voltage source value is 1.8V. , and is applied to that net in the transistor-level netlist.

remove_d2a dc=1.8 node=top.VVDH;

The following example shows that all net names starting with top.V are no longer considered mixed-nets. In addition, the constant dc voltage source with a value of 2.5V is applied to those nets in the transistor-level netlist.

remove_d2a dc=2.5 node=top.V* ;

Note: When multiple remove_d2a commands are used for the same mixed-net(s) in the mixed-signal simulation setup file, the last command takes precedence.

The rt_a2d CommandControls all aspects of any runtime a2d interfaces created in the CustomSim-VCS-MX solutions. If this command is not specified, then by default all a2d events are triggered at 50% of the local VDD.

Syntax

rt_a2d [ loth=lo_thrsh[V | %] ] [ hith=hi_thrsh[V | %] ] node=hier_name;


loth=lo_thrsh[V | %]hith=hi_thrsh[V | %]

These two options determine the low and high a2d threshold values. They can be expressed either as absolute values (1.1V, 2.2) or as a percentage of the supply (10%, 90%).

node=hier_name Because rt_a2d is instance based, you must specify the hierarchical path to the instance port. For example, node=top.i1.y;.



The rt_d2a CommandControls all aspects of any runtime d2a interfaces created in the CustomSim-VCS-MX solutions. The drive strength for rt_d2a defaults to the "supply" strength.

Syntax

rt_d2a [rf_time=slope_time] | [rise_time=rise_time] [fall_time=fall_time] [x2v=0|1|2|3|4] hiv=high_voltage [ V | % ] lov=low_voltage [V | % ] node=hier_name;


rf_time=slope_time Specifies the analog rise and fall times. The default time unit is in seconds, so specify the sub-unit with a value such as rf_time=1.5n, for example. With this option, both rise and fall times are set to the same value.

rise_time=rise_time Specifies the analog rise time. The default time unit is in seconds, so specify the sub-unit with a value such as fall_time=1n rise_time =2n, for example.

fall_time=fall_time Specifies the analog fall time. The default time unit is in seconds, so specify the sub-unit with a value such as fall_time=1n rise_time=2n, for example.

x2v=0|1|2|3|4 Sets the rule on how a logic X must be translated to a voltage level on the analog side: Use this option to manage the translation of the X to a voltage level with one of the following values.■ 0 to always set to the logic zero voltage (default).■ 1 to always set to the logic one voltage.■ 2 to set to (the logic one voltage + the logic zero

voltage)/2.■ 3 to set to previous voltage.■ 4 to set to the logic one voltage else; if logic = 1 set

to the logic zero voltage else get previous voltage.



The rt_e2r CommandControls the behavior of a runtime e2r interface element. This command lets you set the threshold at which e2r events occur and also allows e2r to convert analog voltage values (default) or current values to digital.

Syntax

rt_e2r [type=i] [fidelity=<value>] [gain=<value>] [res=<value>] node=hierarchical_node_name;

hiv=high_voltage [ V | % ]

By default, the logic 1 voltage value is the voltage of the local supply. If the tool cannot trace the rt_d2a net to an ideal supply, it assumes the same default value as the rmap d2a. This option allows you to overwrite the default voltage for logic1. It allows you to overwrite the default value by either expressing an absolute voltage value (for example, 1.2V or 1.2) or as a percentage of the supply voltage (for example, 90%).You must use this option combination with the lov= option.

lov=low_voltage [V | % ]

By default, the logic 0 voltage value is assumed to be 0V. This option allows you to overwrite that default value. The value can be expresses as an explicit voltage value (for example, 0.2V or 2.0) or as a percentage of the local supply (for example, 10%).

node=hier_name Because rt_d2a is instance based, you must specify the hierarchical path to the instance port. For example: node=top.i1.y;


type=i Determines if the e2r is converting voltage values to digital (default) or the current through a resistors (with type=i).

fidelity=<value> Determines the absolute voltage/current threshold value for e2r events in the engineering format. The default value is 1% of the maximum voltage/current value.




The rt_r2e CommandControls the behavior of a runtime r2e interface element. This command lets you set the threshold at which r2e events occur and also allows defining r2e as a voltage source (default) or a current source on the analog side of the interface.

Syntax

rt_r2e [type=i] [fidelity=<value>] [gain=<value>] node=hierarchical_node_name;

gain=<value> Determines if the analog voltage/current needs to be multiplied by a multiplier when converted to digital. The multiplier can be a negative number as well. The default value is 1.

res=<value> Determines the value of the resistor put between the interface net and ground to measure the current through it. This option is only applicable with type=i.

node=hierarchical_node_name

Specifies the hierarchical path to the r2e interface. You can specify wildcard characters (*) in the path.


type=i Determines if the r2e is modeled as a voltage source (default) or as a current source (with type=i).

fidelity=<value> Determines the absolute voltage/current threshold value for r2e events in the engineering format. The default value is 1% of the maximum voltage/current value.

gain=<value> Determines if the analog voltage/current needs to be multiplied by a multiplier. The multiplier can be a negative number as well. The default value is 1.

node=hierarchical_node_name

Specifies the hierarchical path to the r2e interface. You can specify wildcard characters (*) in the path.




The rmap_file CommandUse the rmap_file command to specify the resistance map file or the path to where the resistance map file is located. If the command is not specified, the default rmapAD.init resistance map file from the CustomSim/FineSim/HSIM/NanoSim installation is used.

Syntax

rmap_file resistance_map_file_name [options];

The node, instance and subcircuit options are mutually exclusive, and cannot be used with each other in the same command. However, these options can be used in separate rmap_file commands.

When more than one rmap_file command is used, the last command overrides the settings of the previous one(s).

See Table 7 for the four rmap_file command option categories.

Examples

In the following example, resis_comp.map is the resistance map file in the current directory.

rmap_file resis_comp.map;

In the following example, resis.map is the resistance map file in the /home/john/work directory.

rmap_file /home/john/work/resis.map;

Table 7 rmap_file command option categories

Category Command option

file Custom resistance map file name.

node node=nodename(s)

instance inst=instance_names(s)

inst=instance_name port=port_name(s)

subcircuit subckt=subckt_name(s)

subckt=subckt_name port=port_name(s)



In In the following example, r2.map is the resistance map file that is applied to the top.i1.wen and top.i2.ren nodes. The default resistance map file is applied to the remaining mixed-nets.

rmap_file r2.map node=top.i1.wen top.i2.ren;

In In the following example, r3.map is the resistance map file that is applied to all mixed-nets connected to the top.i1.abc and top.i2.xyz instances. The default resistance map file is applied to the remaining mixed-nets.

rmap_file r3.map inst=top.i1.abc top.i2.xyz;

In the following example, r3.map is the resistance map file that is applied to the mixed-net connected to port Z located at the top.i1 instance. The default resistance map file is applied to the remaining mixed-nets.

rmap_file r3.map inst=top.i1.abc port=Z;

In the following example, r4.map is the resistance map file that is applied to all mixed-nets connected to the pad subcircuit. The default resistance map file is applied to the remaining mixed-nets.

rmap_file r4.map subckt=pad;

In the following example, r4.map is the resistance map file that is applied to the mixed-net connected to the IN port located at the pad subcircuit. The default resistance map file is applied to the remaining mixed-nets.

rmap_file r4.map subckt=pad port=IN;

In the following example, r5.map is the resistance map file that is applied to the top.i1.clk, top.i2.addr[0], top.i2.addr[1] and top.i2.addr[2] mixed-nets. The default resistance map file is applied to the remaining mixed-nets.

rmap_file r5.map nodefile=n1.txt;

The following example shows the content of the n1.txt file.

top.i1.clktop.i2.addr[0]top.i2.addr[1]top.i2.addr[2]

In the following example, r6.map is the resistance map file that is applied to the mixed-nets connected to the top.i1, top.i2, top.i3.abc and



top.i4.xyz instances. The default resistance map file is applied to the remaining mixed-nets.

rmap_file r6.map instfile=inst1.txt;

The following example shows the content of the inst1.txt file.

top.i1top.i2top.i3.abctop.i4.xyz

In the following example, r7.map is the resistance map file that is applied to the mixed-nets connected to the pad, abc and xyz subcircuits. The default resistance map file is applied to the remaining mixed-nets.

rmap_file r7.map subcktfile=s1.txt;

The following example shows the content of the s1.txt subcircuit file.

padabcxyz

In the following example, r8.map is the resistance map file that is applied to all mixed-nets matched by the *addr* string. The default resistance map file is applied to the remaining mixed-nets.

rmap_file r8.map node=*addr*;

In the following example, the r1.map resistance map file is ignored because the second rmap_file command also encompasses the signal identified by the first command. When two or more rmap_file commands encompass the same signals, the last command always prevails—file rmap r2.map is applied to node top.i1.addr.n1. The default resistance map file is applied to the remaining mixed-nets that are not covered by these commands.

rmap_file r1.map node=top.i1.addr.n1;rmap_file r2.map node=top.*addr*;

The following example is illegal. The options are mutually exclusive. The node and inst options cannot be used together in the same command. An additional rmap_file command must be used, such that one command contains the inst= option and the other command contains the node= option:.

rmap_file r1.map node=top.i1.addr inst=top.i1.abc;

In the following example, r2.map is the resistance map file that is applied to the mixed-nets connected to the top.i1.abc instance. The r1.map file is



applied to the top.i1.addr.n1 node. The default resistance map file is applied to the remaining mixed-nets.

rmap_file r1.map node=top.i1.addr.n1;rmap_file r2.map inst=top.i1.abc;

If multiple rmap_file commands target the same mixed-nets, and each one of the commands uses one of the node, instance or subcircuit options, use the options with the rmap_file command in the following order: (1) subcircuit-based, (2) instance-based, and (3) node-based.

The wild card (*) character can be used in the port, node, instance, or subcircuit name.

The period (.) character is the required hierarchical separator. The string length must not exceed 4,096 characters.

Note: When multiple rmap_file commands are used for the same mixed-net(s) in the mixed-signal simulation setup file, the last command takes precedence.

The shadow_file_dir CommandUse the shadow_file_dir command to specify the simv.daidir directory in which user-modified Verilog dummy module files reside.

In Verilog-SPICE and VHDL/Verilog-SPICE flows, mixed-signal simulation automatically generates Verilog dummy module files (called shadow modules) for all SPICE subcircuits in the design. These files are placed in the simv.daidir directory or, if the VCS switch -o unique_name is used, in the unique_name.daidir directory.

VCS then reads these files to construct the design hierarchy. If there are any problems in the Verilog dummy modules (usually caused by differences in the number of ports or their names between Verilog and SPICE views) VCS fails in the compilation phase.



This command allows you to work around such netlist disparity problems by following these steps:

1. Copy the simv.daidir directory (or unique_name.daidir if VCS option -o unique_name is used) to a new location.

2. Hand-edit the shadow module files to resolve the Verilog/SPICE netlist disparity issues.

3. Run the compile again with shadow_file_dir command in the mixed-signal control file pointing to the new location.

Syntax

shadow_file_dir directory_path;

Examples

The following example shows how to have the shadow_file_dir command point to the /home/john/work/wrapper_dir directory, which contains the modified versions of simv.daidir files.

shadow_file_dir /home/john/work/wrapper_dir;

The spice_port_order_as_vlog CommandUse the spice_port_order_as_vlog command to force mixed-signal simulation to use the Verilog bus order at the instantiation of the SPICE view. This command applies to multi-view SPICE blocks instantiated under Verilog. If the SPICE instance has bus ports and the bus order in SPICE is different from the one in Verilog (for example, the bus order is descending in SPICE and ascending in Verilog), this command can be used to force SPICE adopt the Verilog bus order. That way the connectivity between the top level Verilog nets and SPICE bus ports is done correctly.

The spice_top CommandUse the spice_top command to indicate that the top-level of the design is described in SPICE. This command is required for simulating a SPICE-top design.

Syntax

spice_top [name=unique_name];



Examples

The unique_name option assigns a name (of your choice) to the top-level dummy module instance—see the following example. Specifying a unique_name option is useful when you want the name of the top-level block in design be something other than the default SPICE-top name snps_sptop.

spice_top name=my_top;

The use_spice CommandUse the use_spice command to explicitly instruct the tool to use the SPICE view of a multi-view cell for a child cell under a Verilog or VHDL parent. By default mixed-signal simulation chooses the view for the child cell that is the same as the parent cell view. So if the parent of a multi-view cell has a Verilog view, by default the same Verilog view is picked for the child cell. Use this command to override the default view selection and explicitly select the SPICE view for a given cell or instance of a cell.

Syntax

use_spice -cell subcircuit_name [-inst instance_name ] [ port_map (port_map_list) ] ;


-cell subcircuit_name Identifies the cell name to be substituted with SPICE. The substitution is done on a cell basis for all instances of the cell. The "*" (asterisk) wildcard character can be used as part of the subcircuit name.

-inst instance_name If this option is used, only the specified instances is instantiated in SPICE. The full hierarchical path to the instance is required.

If you use the VCS -adopt wildcard command line switch, then the instance name can also contain a "*" wildcard character. Note that the use of the VCS -adopt wildcard switch and "*" in the instance name increases the compilation time by forcing the tool to elaborate the design once so all the hierarchical instance names in the design are known, and then applies the use_spice command with the "*" in the instance name and elaborates the design for a second time.



port_map (port_map_list)

When the ports in the SPICE view of a multi-view cell have a different name compared to their Verilog or VHDL view, you can use this option to map the Verilog/VHDL port name to SPICE. The port_map_list can have one or more of the following mappings, each separated by a ",":

verilog/vhdl_port_name => spice_port_name

A Verilog/VHDL port name is mapped to a SPICE port name. The port name could be a bus identifier as well. For single dimensional buses, you can specify the dimension of the SPICE bus could be specified as well:

verilog/vhdl_port_name => spice_port_name[range]

If you do not specify a range, the members with the same index number get mapped together:

verilog/vhdl_port_name[0] => spice_port_name[0]

verilog/vhld_port_name[1] => spice_port_name[1]

...

But if you specify the SPICE bus range, the left-most member of the Verilog/Vhdl bus gets mapped to the left-most member of the SPICE port, and so on. You can specify the range for SPICE bus to, for example, flip the bus order in SPICE so that SPICE MSB maps to Verilog/VHDL LSB and vice versa.

verilog/vhdl_port_name => snps_open

A Verilog/VHDL port is declared as not having a SPICE counterpart and as a result the top-level Verilog/VHDL net connected to that port remain open/dangling.

* => snps_by_position

Maps all Verilog/VHDL ports (or all remaining Verilog/VHDL ports that have not been mapped yet) to SPICE ports by position. As a result the first port declared in Verilog/VHDL is mapped to the first port declared in the SPICE subcircuit and so on and so forth.

*=> snps_by_name

Maps all Verilog/VHDL ports (or all remaining Verilog/VHDL ports that have not been mapped yet) to SPICE ports by name. As a result ports that have the same name in SPICE and Verilog/VHDL are mapped together.

* => snps_open



All Verilog/VHDL ports (or all remaining Verilog/VHDL ports that have not been mapped yet) stay open, meaning that the top-level Verilog/VHDL nets connecting to those Verilog ports stay open/dangling when the Verilog/VHDL view of the cell is substituted with the SPICE view.


Examples

The following shows how to use the SPICE view for all instances of the cell memory. This command can be used when both the memory Verilog module and the memory SPICE subcircuit are available.

use_spice -cell memory;

The following example is an instance-based substitution for specific instances of the cells inv2 top.i1.u1 and top.i2.u5.inv5.

use_spice -cell inv2 -inst top.i1.u1 top.i2.u5.inv5 ;

The following example shows how to replace the Verilog view of a multi-view cell with its SPICE counterpart and how to map Verilog ports to SPICE ports when they have different names.

module inv1 (y, a);…..subckt inv1 i o….use_spice -cell inv1 port_map ( y => o, a => i );

The following example demonstrates how to map Verilog ports to SPICE ports when a few of the ports have different names in Verilog and SPICE but the rest have identical names in both views and can be mapped by name.

module inv1 (z, n, a, b, c);…..subckt inv1 y m a b c….use_spice –cell inv1 port_map ( z => y, n =>m, * => snps_by_name);

The following example shows how to map Verilog ports to SPICE ports when there are a few Verilog ports that don't have a counterpart in SPICE, a few of the ports have different names in Verilog and SPICE, and the rest have identical names.

module inv1 (z, n, a, b, c);…..subckt inv1 y a b c….use_spice –cell inv1 port_map ( z => y, n =>snps_open, * => snps_by_name);

The following example shows how to map a Verilog bus to its SPICE counterpart when there is a mismatch between the Verilog and SPICE bus port names:



module data_path (data, ...);input [2:0] data;...

.subckt data_path d_2 d_1 d_0 ...

...

use_spice -cell data_path port_map ( data => {d_2, d_1, d_0}, *=> snps_by_name);

Another way to map the bus ports would is:

use_spice -cell data_path port_map (data => d, *=> snps_by_name);

Here the bus identifiers have been used to map ports. Another option would be to use SPICE bus order as shown in the following examples:

use_spice -cell data_path port_map (data => d[2:0], *=> snps_by_name);

Going from left to right, maps the leftmost member of data to the leftmost member of d and so on:

data[2] => d[2]data[1] => d[1]data[0] => d[0]

or

use_spice -cell data_path port_map (data => d[0:2], *=> snps_by_name);

Which maps to:

data[2] => d[0]data[1] => d[1]data[0] => d[2]

The following example demonstrates how the "*" wildcard character can be used as part of the instance name in the use_spice command:

use_spice -cell ph_det -inst test.i1.*.u1;use_spice -cell serdes -inst test.idata1.i_s*;use_spice -cell div -inst test.i3.u2.*;

The "*" character in the instance name is only supported if the -adopt wildcard switch is added to the VCS command line:

vcs -ad -adopt wildcard ...



Note that all ports must be mapped. That is why the "*" in " *=> snps_by_name" is required to map any port that is not explicitly mapped.

Note that the instance name (under the SPICE view) begins with the letter X. To ensure that you are using the correct hierarchical path to the instance, use the hierarchical names listed in the interface_element.rpt file under the simv.msv directory as a guide. The interface_element.rpt file is explained in Chapter 15, Mixed-Signal Report Files.

The use_verilog CommandUse the use_verilog command to explicitly instruct the tool to use the Verilog view of a multi-view cell for a child cell under a SPICE parent. By default mixed-signal simulation chooses the view for the child cell that is the same as the parent cell view. So if the parent of a multi-view cell has a SPICE view, by default the same SPICE view is picked for the child cell. Use this command to override the default behavior and explicitly select the Verilog view for the given cell or instance of a cell.

Syntax

use_verilog | use_vcs -module module_name [ -inst instance_name] [port_map (port_list)] ;

The use_vcs command can be used as an alias for the use_verilog command.


-module module_name Identifies the module name to be substituted with Verilog. The module name cannot contain a wildcard (asterisk "*" character).

-inst instance_name If this option is used, only the specified instances is instantiated in SPICE. The full hierarchical path to the instance is required.



Examples

The following example shows how to use the Verilog view for all instances of the cell memory. This command can be used when both the memory Verilog module and the memory SPICE subcircuit are available.

use_verilog -module memory;(use_vcs -module memory;)

port_map (port_map_list)

When the ports in the Verilog view of a multi-view cell have a different name compared to their SPICE view, you can use this option to map the SPICE name to the Verilog name. The port_map_list can have one or more of the following mappings, each separated by a ",":

spice_port_name => verilog_port_name

A SPICE port name is mapped to a Verilog port name.

spice_port_name => snps_open

A SPICE port is declared as not having a Verilog counterpart and as a result the top-level SPICE net connected to that port remains open/dangling.


Maps all SPICE ports (or all remaining SPICE ports that have not been mapped yet) to Verilog ports by position. As a result the first port declared in the subckt definition is mapped to the first port declared in Verilog module definition, and so forth.

*=> snps_by_name

Maps all SPICE ports (or all remaining SPICE ports that have not been mapped yet) to Verilog ports by name. As a result ports that have the same name in SPICE and Verilog are mapped together.

* => snps_open

All SPICE ports (or all remaining SPICE ports that have not been mapped yet) stay open, meaning that the top-level SPICE nets connecting to those SPICE ports stay open/dangling when the SPICE view of the cell is substituted with the Verilog view.




The following example shows an instance-based Verilog substitution for specific Instances of the cell inv2 xi1.xu1 and xi2.xu5.xinv5.

use_verilog -module inv2 -inst xi1.xu1 xi2.xu5.xinv5 ;

The following example shows how to map SPICE ports to Verilog ports when they have different names.

.subckt inv1 i o….module inv1 (y, a);….use_verilog -module inv1 port_map ( o => y, i => a );

The following example demonstrates how to map SPICE ports to Verilog ports when a few of the ports have different names in Verilog and SPICE but the rest have identical names in both views and can be mapped by name.

.subckt inv1 y m a b c….module inv1 (z, n, a, b, c);….use_verilog –module inv1 port_map ( y => z, m =>n, * => snps_by_name);

Note that all ports must be mapped. That is why the "*" in " *=> snps_by_name" is required to map any port that is not explicitly mapped.

The following example shows how to map SPICE ports to Verilog ports when there are a few SPICE ports that don't have a counterpart in Verilog, a few of the ports have different names in Verilog and SPICE, and the rest have identical names.

.subckt inv1 y n a b c….module inv1 (z, a, b, c);….use_verilog –module inv1 port_map ( y => z, n =>snps_open, * => snps_by_name);



Summary of Mixed-Signal Simulation CommandsA summary of the mixed-signal simulation setup file commands is shown in Table 8.

Table 8 Mixed-signal Simulation Commands

Command Use Definition

choose analog_engine_name command-line options;

required Specifies the CustomSim, FineSim, HSIM, or NanoSim tools as the analog engine and its command-line options.

bus_format open_char %d close_char;

optional Specifies bus format used in the SPICE netlist.

set interface_opt [option] node=node_name(s);

optional Models the digital-to-analog interface.

mview_vlog_noportswap; optional Applies to multi-view Verilog blocks instantiated under SPICE. This command forces the use of the original SPICE port order instead of the default Verilog port order.

optimize_shadowfile; optional Optimizes Verilog dummy modules and hierarchy under the SPICE view.

print_thru_net [a2a | d2d | all]; optional Instructs the CustomSim/FineSim/HSIM/NanoSim tools to instantiate dummy A/D or D/A inverters to generate the digital image of an a2a through-net and/or the analog image of a d2d through-net.

remove_d2a [dc=dc_voltage_source_value] node=node_name;

optional Specifies a d2a mixed-net to be removed from the Verilog and transistor-level boundary.



rmap_by_node r= resistance_value node=node_name(s);

optional Applies the resistance value to the interface resistor connected to the node at the digital-to-analog interface.

rmap_file resistance_map_file_name

OR

rmap_file resistance_map_file_path_name [option];

optional Specifies the resistance map file to be used.

spice_port_order_as_vlog; optional Applies to multi-view SPICE blocks instantiated under Verilog. It forces mixed-signal simulation to apply the port order in the Verilog view of the cell to the SPICE instantiation.

shadow_file_dir directory_path; optional Specifies the directory where mixed-signal intermediate files are stored.

spice_top [name=unique_name]; optional Specifies that the top level of the design is SPICE

use_spice -cell subcircuit_names -C cfg_file_name;

OR

use_spice instance_names -C cfg_file_name;

optional Specifies cells or instances to be modeled and simulated in analog. The -C option can only be used in NanoSim-VCS and NanoSim-VCS-MX.

use_verilog -module module_name;

OR

use_verilog instance_name;

optional Specifies cells or instances to be modeled and simulated in digital.

Table 8 Mixed-signal Simulation Commands

Command Use Definition



Known LimitationsThe following are known limitations:■ Bidirectional pass switches and registered nets (tran, rtran, tranif1,

rtranif1, tranif0, and rtranif0) that are connected to mixed-nets are not supported—the results could be incorrect.

■ Jumper ports that are connected to the mixed-nets are not supported—the results are incorrect.

The following example shows a sample jumper port.

module jumper (a, a);inout a;...endmodule




5

5Running a Mixed-Signal Simulation in the Verilog-SPICE Flow

This chapter provides information for the mixed-signal simulation with CustomSim-VCS/FineSim-VCS/HSIM-VCS, and NanoSim-VCS, including interactive and postlayout parasitic back-annotation.

Overview

Information about compiling and simulating the design is described in Chapter 3, “Using Verilog-SPICE Mixed-Signal Features.”

This chapter contains the following topics:■ Setting Up the Simulation Environment for the Verilog-SPICE Flow

• Version Compatibility Between Analog and Digital Engines

• Licenses

• Required UNIX Paths and Variable Settings

• Using the 64-bit Binaries■ Required Input Files■ Compiling the Design■ Running the Simulation in the Verilog-SPICE Flow

• Invoking the Interactive Mode with the UCLI Debugging Feature with Verilog-SPICE

■ DC Initialization■ Recompiling the Design


Chapter 5: Running a Mixed-Signal Simulation in the Verilog-SPICE FlowSetting Up the Simulation Environment for the Verilog-SPICE Flow

Setting Up the Simulation Environment for the Verilog-SPICE Flow

To set up the simulation environment, be aware of:■ Version Compatibility Between Analog and Digital Engines■ Required UNIX Paths and Variable Settings

Version Compatibility Between Analog and Digital EnginesTo successfully run a simulation in the Verilog-SPICE flow, ensure that the versions of the analog engine (the CustomSim/FineSim/HSIM/NanoSim tools) and VCS are compatible; otherwise, the compilation might fail. Also ensure that the Operating System utilities (such as cc, gcc and ld) used during the VCS compilation meet the mixed-signal simulation version requirements.

All the version compatibility requirements for the CustomSim/FineSim/HSIM/NanoSim tools and VCS, as well as the correct versions for compile utilities, are provided in the compatibility table available in the Release Notes on SolvNet.

LicensesTo run a mixed-signal simulation, the following license keys are required:■ Regular license keys for the CustomSim, FineSim, HSIM, or NanoSim tools

(depending on which analog engine is being used)■ Regular license keys for VCS■ Mixed-Signal keys for the CustomSim, FineSim, HSIM, or NanoSim tools

(depending on which one of them are used)

Either LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE can be used to specify the license file location.

setenv LM_LICENSE_FILE Location_of_License_File

or

setenv SNPSLMD_LICENSE_FILE Location_of_License_File

By default, if any one of the required licenses for the analog or digital engines is missing, the simulation will not compile or execute.


Chapter 5: Running a Mixed-Signal Simulation in the Verilog-SPICE FlowSetting Up the Simulation Environment for the Verilog-SPICE Flow

To enable queuing for license keys, so that the compilation/simulation waits for the required license key to become available, do the following:■ For the CustomSim tool:

setenv XA_WAIT_LICENSE

■ For the FineSim tool:

setenv FINESIM_LICENSE_WAIT_TIMEOUT 3600

This command forces FineSim to wait for an hour (3600 seconds) for a FineSim license key to become available. If after an hour still no license is available the simulation exits.

■ For the HSIM tool:

setenv HSIM_WAIT_LICENSE

■ For NanoSim tool:

setenv EPIC_WAIT_LICENSE

■ For VCS:

Use the +vcs+lic+wait switch at compile time.

vcs +vcs+lic+wait ...

Required UNIX Paths and Variable SettingsTo set the paths for the CustomSim/FineSim/HSIM/NanoSim tools and VCS, do the following:■ For the CustomSim tool:

source XA_installation_directory/CSHRC_xa


setenv install_directory the_correct_install_dirsource finesim_install_dir/finesim.cshrc


set path = (HSIM_installation_directory/hsimplus/bin $path)

■ For the NanoSim tool:

source NanoSim_installation_directory/CSHRC_ns

■ For VCS:


Chapter 5: Running a Mixed-Signal Simulation in the Verilog-SPICE FlowRequired Input Files

setenv VCS_HOME VCS_installation_directoryset path = ($VCS_HOME/bin $path)

For example

setenv VCS_HOME /usr/synopsys/VCS/vcsmx_2010.06set path = ($VCS_HOME/bin $path)source /usr/synopsys/Nanosim/2010.06/CSHRC_ns

Using the 64-bit Binaries

Currently, mixed-signal supports Solaris, Suse, and Linux (AMD) 64-bit platforms. The binaries must be either 32-bit or 64-bit for both the analog and the digital engines. It is not permitted to have a 32-bit binary for one engine and a 64-bit binary for the other; such a combination would result in incompatibility between the binaries and a compilation error.

Note: Starting with the J-2014.09 release the CustomSim and FineSim tools are only be available in the 64-bit mode. Running a mixed-signal simulation in the 32-bit mode causes an error, so use the VCS switch -full64 at all times when running a mixed-signal simulation:

vcs -ad -full64 ...

This tells VCS to use 64-bit binaries and also instructs the analog engine (the CustomSim, FineSim, HSIM, or NanoSim tools) to use 64-bit binaries as well (assuming that the 64-bit binaries for the analog engine are installed and the environment variables for the analog engine are set as described above).


Before using the Verilog-SPICE flow, the following files must be in place:■ Verilog netlist files■ Verilog-A module files, if used■ SPICE netlist files (including device model libraries)■ Mixed-signal simulation control file■ Command file


Chapter 5: Running a Mixed-Signal Simulation in the Verilog-SPICE FlowCompiling the Design

One of the following, depending on which analog engine is being used:

• CustomSim/HSIM/NanoSim config file

• HSIM hsim.ini command file

• CustomSim command file

Compiling the Design

To compile the design, invoke the vcs command:

vcs verilog_design_file(s) -ad [=mixed-signal_control_file] [vcs options]

The following example shows that vcs compiles the design.v file with the -ad VCS compile time option. It reads the default vcsAD.init file as the mixed-signal control file. The simv simulation executable is created (if no errors occur during the compilation).

vcs design.v -ad

The following example shows that vcs compiles the design files listed in the my_list.txt file with the -ad VCS compile time option. It reads the my_setup.init file as the mixed-signal simulation control file. A simulation executable, my_simv, is created, instead of the default simv executable.

vcs -f my_list.txt -ad=my_setup.init -o my_simv

The following example is identical to the previous example, except for the-full64 option. This option generates 64-bit simv executable instead of the default 32-bit.

vcs design.v -ad -full64

After simv is generated, the simulation can be run using the following syntax:

simv [vcs run-time options]

The following example shows how to instruct VCS to generate a run time log file called simv.log.

simv -l simv.log


Chapter 5: Running a Mixed-Signal Simulation in the Verilog-SPICE FlowRunning the Simulation in the Verilog-SPICE Flow

Running the Simulation in the Verilog-SPICE Flow

To synchronize the digital and analog events, ideally, both the analog and digital engines should have the same time resolution value, where time resolution is the smallest timestep the simulator is allowed to take. ■ By default, in the case of NanoSim and HSIM, the analog engine assumes

the smaller of the analog and digital time resolution. For example, if VCS time resolution is 10ps and NanoSim/HSIM time resolution is 1ps, NanoSim/HSIM will run with 1ps time resolution and VCS with 10ps time resolution.

In a situation in which the VCS time resolution is extremely small (sfor example, 100fS), which would unnecessarily slow down analog performance, the best solution would be to override the VCS timescale and set it to a larger value that satisfies both analog accuracy and performance objectives. To override the VCS timescale, use the -override_timescale switch at compile time.

In the following example the VCS timescale/timeresolution is being overwritten with a 1ns/10ps.

vcs -ad -override_timescale=1ns/10ps

■ The CustomSim tool does not have a predetermined time resolution. In the CustomSim tool the time resolution is constantly optimized and adjusted for accuracy and performance during simulation.

As a general rule the analog time resolution cannot be greater than the digital time resolution, because a loss of synchronization could happen at run time causing a run time error. ■ In CustomSim-VCS, such a violation cannot occur, because of the

adjustable time resolution mechanism in the CustomSim tool.■ In HSIM-VCS, such a violation will result in a compliation error and a

warning that the analog time resolution value cannot be smaller than the digital time resolution value.

■ In NanoSim-VCS, if the digital time resolution value is smaller than the analog time resolution value, then NanoSim automatically overrides its own time resolution with the smaller digital value so as not to violate the above rule.

Table 9 shows a few examples for NanoSim/HSIM and VCS time resolution settings and the final values that are eventually used for analog and digital time


Chapter 5: Running a Mixed-Signal Simulation in the Verilog-SPICE FlowInvoking the Interactive Mode with the UCLI Debugging Feature with Verilog-SPICE

resolutions. The CustomSim tool is not mentioned in this table because it does not have the notion of a predetermined time resolution.

Limitation: All timestep values for NanoSim, HSIM, and VCS must be set to a value that is a power of 10; for example 1ns, 10ps, 100ps.

Invoking the Interactive Mode with the UCLI Debugging Feature with Verilog-SPICE

To enable the interactive mode during a mixed-signal simulation, you must enable the VCS UCLI (Unified Command Line Interface) debugging feature.

To invoke the UCLI interactive mode, first use the -debug or-debug_all VCS compile option:

vcs -debug_all ...

Next, invoke the simv binary file by passing the -ucli option to it:

% simv -ucli

Table 9 Timestep Synchronization Behavior Overview

NanoSim/HSIM VCS Time Resolutions

10 ps 10 ps The analog and digital engines both use 10 ps time resolution.

10 ps 1 ps ■ In the case of NanoSim-VCS, the VCS timestep overrides the NS timestep so that both use 1 ps as atimestep value.

■ In the case of HSIM-VCS a compilation error occurswarning that the analog timestep cannot be smaller than the digital timestep.

1 ps 10 ps NS/HSIM and VCS use their own time resolution valuesindependently ■ NS/HSIM uses 1 ps■ VCS uses 10 ps


Chapter 5: Running a Mixed-Signal Simulation in the Verilog-SPICE FlowInvoking the Interactive Mode with the UCLI Debugging Feature with Verilog-SPICE

This switch stops the mixed-signal simulation at simulation time 0, and generates the UCLI prompt:

ucli%

Alternatively, you can stop the simulation any time during the simulation by pressing Ctrl+C, provided that the UCLI was enabled through "-debug" or "-debug_all" at compile time and simv was run with the -ucli switch.

All UCLI commands can be used at this prompt, such as

ucli % run 10

which runs the simulation for 10 (VCS) units of time.

The VCS time unit is usually defined by the `timescale directive in the Verilog code.

The following command prints all the digital sources that drive the given node_name with the file and line numbers locating the contributing Verilog code

ucli% drivers -full hier_node_name

The ucli% ace Analog Interactive CommandsYou can use analog interactive commands at the UCLI prompt if they are preceded by the ace command. The following example shows how the CustomSim interactive command iprint_time can be used at the UCLI interactive prompt.

ucli% ace iprint_time

For a complete list of the UCLI commands, see the VCS Unified Command Line Interface User Guide.

Note: The analog simulation time cannot be advanced using the UCLI command. The analog simulation time can only be advanced by advancing the digital simulation time in UCLI. (See the VCS User Guide for more information.)

To use the FineSim interactive command exi to report devices with excessive current:

ucli% ace exi

For the HSIM tool:


Chapter 5: Running a Mixed-Signal Simulation in the Verilog-SPICE FlowDC Initialization

ucli% ace ni hier_node_name

For the NanoSim tool:

ucli% ace pnc hier_node_name

DC Initialization

When you replace existing SPICE subcircuits with Verilog modules, the analog DC initialization in mixed-signal simulation may not be identical to the stand-alone analog simulation. For DC initialization condition-sensitive circuits, it may be necessary to apply specific DC initialization condition values at certain nodes to get expected simulation behaviors.

Recompiling the Design

In the current standalone version of VCS, the -Mupdate option is on by default. As mixed-signal requires both the compile-time phase and run-time phase to work seamlessly, do not compile incrementally.

When you modify any design files (Verilog, Verilog-A, or SPICE) or the mixed-signal control file:■ Remove all of the intermediate files/directories generated by the previous

mixed-signal simulation by removing the simv.daidir and csrc directories.

■ Restart the compilation.

Also, if you use the analog configuration commands to change the case sensitivity in SPICE netlists, then you must recompile the design before those changes can take effect.


Chapter 5: Running a Mixed-Signal Simulation in the Verilog-SPICE FlowRecompiling the Design


6

6Mixed-Signal Simulation Output and Display inVerilog-SPICE

This chapter describes how to generate separate digital and analog waveforms or a unified output file in Verilog-SPICE and how to view them.

Overview

In Verilog-SPICE, simulation results can be ■ Generated separately for analog and digital signals.■ Viewed with Signal Explorer, CosmosScope, or nWave.

Alternatively, the output can be■ Generated as a single output file in VPD (VCD Plus Dump) format.

This chapter contains the following topics:■ Capturing Analog and Digital Signals in the Output File(s)

• Generating an Analog Output File

• Generating a Digital Output File■ Generating a Unified Output

Capturing Analog and Digital Signals in the Output File(s)

To capture digital and analog signals in the output file(s), use two sets of commands: one set for analog signals and another set for digital signals.


Chapter 6: Mixed-Signal Simulation Output and Display in Verilog-SPICECapturing Analog and Digital Signals in the Output File(s)

Generating an Analog Output FileAny method of printing analog signals that is used in stand-alone analog simulations for the CustomSim, HSIM, or NanoSim tools can also be used in the Verilog-SPICE flow, such as:■ The CustomSim probe_waveform_voltage * -port 1 -limit 99

and probe_waveform_current * -port -limit 99 to dump all analog nodes throughout the hierarchy in the output file.

■ The CustomSim probe_waveform_va *.* -limit 99 config command to capture Verilog-A variables in the output

■ The HSIM ".param hsimvaprintvar=1" parameter to capture Verilog-A variables in the output

■ The NanoSim print_node_v and print_node_i config commands■ The NanoSim print_veriloga_var config command to capture Verilog-

A variables in the output■ The $display, $strobe and $write functions within the Verilog-A code

to dump Verilog-A variables or voltage and current values on the screen■ SPICE-specific print commands, such as the HSPICE .print and

.probe commands

The format of the analog output file can be any one of the formats supported by the analog engine, including .vpd, .fsdb and ASCII .out.

The following configuration commands must be used to set the output format for analog signals:■ For the CustomSim tool:

Use the set_waveform_option –format fsdb|wdf|wdb|out|vpd command inside the CustomSim command file. See the CustomSim User Guide for more details.


Use the SPICE parameter .param HSIMOUTPUT=vpd to have HSIM generate a VPD output. By default HSIM generates an fsdb file. See the HSIM Simulation Reference Manual for more details.


Use the set_print_format for=vpd | fsdb ... command inside the NanoSim config file. See the NanoSim User Guide for more details.



By default, the hierarchical nets that appear in multiple levels of the SPICE hierarchy with different names (aliases) appear only once under their top-level alias.

This makes the size of the analog output file more compact but could make chasing signals through the hierarchy difficult. The following configuration commands enable printing of all analog hierarchical aliases:■ For the CustomSim tool use the "-port 1" option of the "probe_waveform_xx"

commands. For example:

probe_waveform_voltage * -port 1


.OPTION POST PROBE

.probe v(*) i(*)

To probe voltages and currents for all analog nodes.■ For the HSIM tool use "matchport=1" option along with ".probe/

.print v(*)" or ".probe/.print i(*)" commands:

.probe v(*) matchport=1

.print i(*) matchport=1

■ For the NanoSim tool use the "shorted_alias=1 hier_alias_level=<nn>" options of the "set_print_format" command. For example:

set_print_format shorted_alias=1 hier_alias_level=99

Generating a Digital Output FileTo capture and dump digital signals in the design, the recommended format of the digital output file is VPD (also called VCD+). Storing digital signals in VPD also provides the option of merging the digital and analog signals into a merged output file.

Here are the steps to generate a VPD output for digital signals:



1. Use the -PP or -debug_pp compile time options with VCS to enable VPD generation by VCS-MX, as follows:

vcs -ad top_entity_name -PPorvcs -ad top_entity_name –debug_pp

2. Use the simv run time options -ucli -i ucli_command_file_name to pass UCLI commands to dump a VPD file to VCS. The command file must contain a dump command to create a VPD file. It can also contain an optional command to specify the name of the output VPD file. The example below shows how the UCLI command file is read at run time:

simv -ucli -i ucli_command_file

Where the content of the command file is:

dump -file output.vpddump -add / -depth 99run 50000quit

In which the -depth option specifies that all signals—at and below the hierarchical path /foo—are dumped in the VPD file. If foo is the name of the top entity, every digital signal in the design is saved in the VPD file. The -o option specifies the VPD file name, and in this example, the file name is foo.vpd. For a complete list of all options for the UCLI dump command, refer to the VCS Unified Command Line Interface User Guide.

Generating a Unified OutputYou can use the following method to generate a Unified Output file that contains both analog and digital waveforms:■ Merged VPD Output

Note: FineSim does not support VPD output format and as a result FineSim-VCS cannot produce a merged VPD file.

Merged VPD OutputVPD is a binary waveform format that allows compact and efficient storage of output data.



To generate a merged VPD file the following steps must be taken:

1. VCS must generate a VPD output

2. The CustomSim/HSIM/NanoSim tools must be instructed to generate an analog output in the VPD format and then merge it with the digital VPD file. Use the following commands to merge a VPD file containing both analog and digital signals:

• For the CustomSim tool:

Use the set_waveform_option –format vpd –file merge config command.

• For the FineSim tool:

The FineSim tool does not support VPD format.

• For the HSIM tool:

Use the param HSIMOUTPUT=vpd file=merge SPICE command.

• For the NanoSim tool:

Use the set_print_format for=vpd file=merge config command.

The merged VPD file takes the name determined by VCS, which can be either of the following: ■ The VCS default name■ The file name specified by the $vcdplusfile() system task in Verilog

For more information on VPD file generation in VCS, see the VCS/VCSi User Guide.




Part 2: VHDL/Verilog-SPICE Mixed-Signal Simulation



7

7Using the VHDL/Verilog-SPICE Flow

This chapter provides the basic information needed to start simulation in the VHDL/Verilog-SPICE flow—including installation and setup.

Overview

The VHDL/Verilog-SPICE flow provides a mixed-signal, mixed-HDL language verification solution. VHDL/Verilog-SPICE enables simulating a design described in SPICE (or other transistor-level description language that the analog engine supports), Verilog-HDL (“Verilog”), and VHDL.

You must be familiar with the SPICE, Verilog, and VHDL languages, as well as the CustomSim, FineSim, HSIM, or NanoSim tools (depending on which analog engine is being used) as well as VCS_MX. See the respective manuals for more information.

This chapter contains the following sections:■ VHDL/Verilog-SPICE Flow Highlights■ Known Limitations

VHDL/Verilog-SPICE Flow Highlights

In VHDL/Verilog-SPICE simulation, different parts of the design can be simulated in SPICE, Verilog, or VHDL models.

VHDL/Verilog-SPICE supports both Verilog-top and VHDL-top flows. SPICE-top is also supported.


Chapter 7: Using the VHDL/Verilog-SPICE FlowVHDL/Verilog-SPICE Flow Highlights

The following features are described in detail in this section:■ Donut Configurations■ Multiple Views

• View Selection for Cells Under a VHDL Parent

• View Selection for Cells Under a Verilog Parent

• View Selection for Cells Under a SPICE Parent■ Real Port Support at the Analog/Digital Boundary■ Interface A/D and D/A Conversion■ Generating a Merged Output file for Analog and Digital Signals

Donut ConfigurationsCustomSim-VCS-MX/FineSim-VCS-MX/HSIM-VCS-MX, and NanoSim-VCS-MX support VHDL-top, Verilog-top, and SPICE-top design configurations.

There is no restriction on donut configurations. VHDL, Verilog or SPICE blocks can each instantiate blocks of the other two formats without restriction. The only requirement is for SPICE instantiations under VHDL; those SPICE cells must also have a Verilog view available in order for the instantiation under VHDL to take place.

Multiple ViewsThe blocks in the design can contain more than one view (for example, SPICE and VHDL).

By default, VHDL/Verilog-SPICE selects the view for the multi-view cell that is identical to the parent block view. If that view is not available, VHDL/Verilog-SPICE selects the next-available view.

A particular view of a multi-view cell can also be selected explicitly. The method of explicit view selection for a child cell depends on the view of the parent cell.



View Selection for Cells Under a VHDL ParentFor a VHDL parent, a Verilog or VHDL view for a child cell can be selected by pointing to the design library that contains that view. This can be done in a number of ways. ■ By placing the VHDL use lib_name.cell_name constructs inside the

VHDL code that explicitly points to a particular cell in a particular library■ By VHDL configurations that determine which "architecture" from what

"library" must be used for which instance or instances■ During the elaboration of the design where a library name can be specified

from where the cells must be selected. The elaboration stage of design compilation is described later in more detail.

For more details on VHDL and Verilog view selections, see the VCS-MX User Guide.

To select the SPICE view for a child cell,

1. VHDL code must use one of the three methods described above to select the Verilog wrapper, since SPICE cells instantiated under VHDL require a Verilog view of the SPICE cell.

2. The use_spice mixed-signal command must be used to indicate that the SPICE view of the cell will replace the Verilog wrapper.

View Selection for Cells Under a Verilog ParentFor a Verilog parent, a Verilog or VHDL view for a child cell can be selected during design elaboration by specifying the design library name that contains the desired view of the child. The elaboration stage of design compilation is described later in more detail. For more details on VHDL and Verilog view selections, please refer to the VCS-MX User Guide.

To select the SPICE view for a child cell, use the use_spice mixed-signal command.

View Selection for Cells Under a SPICE Parent For a SPICE parent, a Verilog view for a child cell can be selected by the use_verilog mixed-signal command.

To select the VHDL view, use the use_vhdl mixed-signal command.

For details about the syntax of the use_spice and use_verilog mixed-signal commands, see Mixed-Signal Control Commands. For details about the



syntax of the use_vhdl mixed-signal command, see Creating a Mixed-signal Simulation Control File for VHDL/Verilog-SPICE.

Real Port Support at the Analog/Digital BoundarySPICE ports can be of type real at the boundary between SPICE and Verilog or SPICE and VHDL. In such a case, instead of the conventional a2d and d2a interfaces, an e2r (electrical to real) or r2e (real to electrical) interface element is inserted by the tool.

For an e2r interface, changes to the analog voltage translate to an e2r event generation in which the new analog voltage is passed to the digital side as a real value.

For the r2e interface, changes to the digital real value translate to an r2e event generation in which the new real value is passed to the analog side as a voltage.

A SPICE real port at the analog/digital boundary can be generated in one of the following ways:■ SPICE port connecting to a Verilog "real" variable

A Verilog variable can connect to a SPICE port of type input or output, which creates an r2e or e2r interface element respectively. To allow that connectivity to happen, the following steps must be taken:

• The SPICE block must have a Verilog view defined and in that Verilog view, the real port must be defined as type "wreal", or if SystemVerilog is used, the port must be defined as type "real".

• The VCS command line switch "-realport" must be used to enable the SPICE real port. For example, here is a top-level Verilog testbench instantiating SPICE block "addr4" which has a real port called "cin":

module top;real cin_real;…addr4 dut (.cin(cin_real), … );…

The SPICE block "addr4" must have a Verilog view defined in which the port "cin" is defined as "wreal":



module top;real cin_real;…addr4 dut (.cin(cin_real), … );…

.module addr4 (cin, … );input cin,wreal cin;…

Or if SystemVerilog is enabled (by adding the VCS switch "-sverilog" to the vcs command line), the Verilog view of the SPICE cell can have the port "cin" defined as SystemVerilog type "real":

.module addr4 (cin, … );input cin,real cin;…

And to compile this design, the VCS switch "-realport" must be used:

% vcs -ad=vcsAD.init -realport ….

■ SPICE port connecting a VHDL "real" signal

A VHDL net type of "real" can connect to a SPICE port of type input or output which would create an r2e or e2r interface element respectively. To allow that connectivity to happen, the following steps must be taken:

• The SPICE block must have a Verilog view defined and in that Verilog view, the real port must be defined as type "wreal", or if SystemVerilog is used, the port must be defined as type "real".

• The switch "-realport" must be used in "vlogan" and "vcs" command line to enable the SPICE real port. For example, here is a top-level VHDL testbench instantiates SPICE block "addr4" which has a real port called "cin":

architecture bhv of testbench is… component addr4 port ( cin : in real; … ) …… signal cin_real : real;…I0 : addr4 port map ( cin => cin_real, … );…



The SPICE block "addr4" must have a Verilog view defined in which the port "cin" is defined as "wreal":

.module addr4 (cin, … );input cin,wreal cin;…

Or if SystemVerilog is enabled (by adding the VCS switch "-sverilog" to the vcs command line), the Verilog view of the SPICE cell can have the port "cin" defined as SystemVerilog type "real":

.module addr4 (cin, … );input cin,real cin;

And to compile this design, the VCS switch "-realport" must be used:

% vlogan -realport addr4.v% vcs -ad=vcsAD.init -realport ….

In both cases above note that in SystemVerilog or VHDL a port of type "real" can only connect to other ports/signals of type "real" as the signal traverses up or down the digital hierarchy. So if a port is defined as "real" and it also connects to ports of other cells at lower or higher levels of the hierarchy, all those ports also need to be defined as "real".

Interface A/D and D/A ConversionIn VHDL/Verilog-SPICE, the A/D and D/A conversions between SPICE and Verilog follow the same rules as in the Verilog-SPICE flow. However, through net optimization and drive strength conversion only take place for interface nets between SPICE and Verilog, not for those between SPICE and VHDL.

Each time a signal crosses the SPICE-VHDL boundary, an A/D or D/A component is instantiated.

The "a2d" and "d2a" commands that control A/D and D/A conversions (and their thresholds) are the same as in the Verilog-SPICE flow.

Refer to the Interface A/D and D/A Signal Conversions in Chapter 3, Using Verilog-SPICE Mixed-Signal Features, for more details.


Chapter 7: Using the VHDL/Verilog-SPICE FlowKnown Limitations

Generating a Merged Output file for Analog and Digital SignalsVHDL/Verilog-SPICE can create merged VPD files. Refer to Chapter 11, Mixed Simulation Output and Display in VHDL/Verilog-SPICE for further details.

Known Limitations

Some limitations exist in VHDL/Verilog-SPICE, due to the existing limitations in the VCS-MX flow. See the VCS-MX User Guide for more details.

The known VHDL/Verilog-SPICE limitations are:■ Verilog wrappers are required for instantiations of SPICE under VHDL

(Please refer to "Using a Verilog Wrapper" section below for further details).

However, donuts of Verilog and SPICE blocks, or SPICE instantiating VHDL, do not require a Verilog wrapper.

■ The NanoSim set_sim_hierid configuration command is ignored. ■ Thru-net optimization is not supported for SPICE ports connecting through

a top-level Verilog/VHDL net. But Verilog/VHDL ports connecting through a top-level SPICE net are subject to thru-net optimization.

Note: As an alternative, real type connections in VHDL can be used to generate unidirectional connections of SPICE ports via VHDL.


Chapter 7: Using the VHDL/Verilog-SPICE FlowKnown Limitations


8

8Mixed-Signal Simulation in the VHDL/Verilog-SPICE Flow

This chapter provides the instructions on how to prepare the files (input data) to run a mixed-signal simulation with CustomSim-VCS-MX/FineSim-VCS-MX, HSIM-VCS-MX, or NanoSim-VCS-MX.

Overview

Some of the issues that require attention for VHDL/Verilog-SPICE mixed-signal simulation are identical to those for the Verilog-SPICE.

Those issues are:■ Netlist-related■ Port-related

For a description of the steps to take to ensure that these issues are addressed, refer to the Netlist-Related Issues and Port-Related Issues sections in Chapter 4, Mixed-Signal Simulation in the Verilog-SPICE Flow.

Figure 21 shows the recommended steps to take to prepare files for CustomSim/FineSim/HSIM/NanoSim-VCS-MX mixed-signal simulation.


Chapter 8: Mixed-Signal Simulation in the VHDL/Verilog-SPICE FlowInput Netlist Files

Figure 21 Flow for Preparing A Mixed-Signal Simulation

This chapter contains the following sections:■ Input Netlist Files

• VHDL and Verilog Descriptions■ Using a VHDL Setup File■ Using a Verilog Wrapper■ Creating a Mixed-signal Simulation Control File for VHDL/Verilog-SPICE

• The use_vhdl Command

• The use_verilog Command

Input Netlist Files

Ensure that all the netlist files that model each block in the design are present.


Chapter 8: Mixed-Signal Simulation in the VHDL/Verilog-SPICE FlowInput Netlist Files

The required files for analog models and blocks in the design are:■ Transistor-level descriptions (or SPICE netlists)■ Device model libraries (can be included inside the SPICE netlist)

Note: The CustomSim/FineSim/HSIM/NanoSim configuration commands for specific analog parts of the design are not required, but often used.

The required files for the digital components of the design are■ VHDL and/or Verilog descriptions of the digital blocks■ Dummy Verilog wrappers for SPICE blocks instantiated under VHDL■ VHDL setup file■ Mixed-signal simulation control file

VHDL and Verilog DescriptionsHere are the issues to consider regarding the VHDL and Verilog netlists:■ A VHDL block can contain a real data type port, as long as that port is meant

for data exchange between two VHDL blocks, or a VHDL and SPICE block.■ In the case of VHDL instantiating SPICE, where a Verilog wrapper is

required for SPICE, the Verilog port that corresponds with the VHDL real port must be defined as wreal.

■ The VHDL real ports and the Verilog wrapper wreal ports cannot have the direction inout. These ports must have an input or output direction.

■ Cross-module reference (XMR) across digital/analog boundary is only supported between Verilog and SPICE as explained in the Verilog-SPICE section of this document. Cross referencing an analog node from inside VHDL is not supported.

■ A mixed-net cannot connect to Verilog ports that are connected to bidirectional pass switches (tran, rtran, tranif0, rtranif0, tranif1, and rtranif1)

■ A mixed-net cannot connect to Verilog jumper ports (see the following example)


Chapter 8: Mixed-Signal Simulation in the VHDL/Verilog-SPICE FlowUsing a VHDL Setup File

module jumper (a, a);inout a;. . .endmodule

Transistor-level DescriptionsFor the SPICE netlists, keep the following points in mind:■ HSPICE and VHDL netlist formats are case-insensitive, but Verilog is case-

sensitive.

So the best practice is to create all subcircuit, port, and signal names consistently, in either lowercase or uppercase, across all SPICE, Verilog and VHDL files.

■ Unused ports must be removed from the subcircuits that are going to be instantiated under VHDL, and a Verilog wrapper is generated for them.

NanoSim removes those ports by default. The corresponding ports in the Verilog wrapper modules must also be removed. You will see a WARNING and ERROR message when NanoSim removes the port:

WARNING: mixed node “net10” not found.ERROR: Unable to find nanosim id for net ‘net10’ interface signal mismatch

Using a VHDL Setup File

VCS-MX uses a VHDL setup file named synopsys_sim.setup to set up and configure the environment for VHDL and mixed-HDL designs. Multiple copies of this setup file can be located in the VCS-MX installation directory, in your home directory, or in your run directory. VCS-MX searches these locations—in that order—and the last file found overrides any previously found file.

This setup file maps VHDL logical library names to physical directories, set search paths, set the VHDL simulation time base and time resolution, and assign values to some simulation control variables.

One of the most frequent uses of the VHDL setup file is to map logical VHDL libraries to physical host directories.

In VHDL, design blocks can be analyzed and stored in one or more logical libraries. This capability offers great flexibility in maintaining multiple versions of a VHDL block by analyzing each version into a different library.


Chapter 8: Mixed-Signal Simulation in the VHDL/Verilog-SPICE FlowUsing a Verilog Wrapper

The VHDL setup file allows defining multiple logical library names and mapping them to their actual physical location.

By default, all VHDL blocks are analyzed and stored in the WORK logical library. The default physical directory for this library is ./WORK

For more information on the VCS-MX setup file, please refer to the VCS-MX User Guide.

The following example shows a sample synopsys_sim.setup file. Here, rtl_lib and gate_lib (two logical libraries) and their physical locations are defined. Also, the WORK default logical library is mapped to the rtl_lib library.

WORK > rtl_librtl_lib: ./rtl_librarygate_lib: ./gate_library

TIMEBASE=nsTIME_RESOLUTION=10ps

Using a Verilog Wrapper

If in the design there is a SPICE block instantiated under VHDL, a dummy Verilog wrapper for the SPICE block must be generated.

This dummy module must have the same name, number of ports and port names as the SPICE cell. The body of the dummy module can be empty, as VHDL/Verilog-SPICE does not read the body of that module if it is used as a dummy wrapper for SPICE.

A dummy Verilog wrapper is not required for any type of Verilog or SPICE donuts, nor for SPICE instantiating VHDL.

If a Verilog description already exists for the SPICE block, use the existing Verilog module as the Verilog wrapper. If not, the wrapper can be created either manually or by using the autowrapper utility (which is shipped with NanoSim) —see section Using the Autowrapper Utility in Chapter 10, “Creating Verilog Wrappers in VHDL/Verilog-SPICE,” for the autowrapper usage.

If real ports are used in the VHDL description, ensure that a wreal declaration is made for the same ports in the Verilog wrapper module (also include the -realport switch when calling vlogan and vcs, which is discussed later in this document). When using a wreal declaration, only input and output ports are allowed—inout ports are not supported.


Chapter 8: Mixed-Signal Simulation in the VHDL/Verilog-SPICE FlowUsing a Verilog Wrapper

The following example shows a wreal declaration file sample.

//Verilog wrapper for using real portsmodule test (a, b);input a;wreal a;output b;wreal b;/* in addition to module name, port name, and directions,wreal declaration is also required */end module

Note: Using real ports can result in a simulation performance penalty; specifically, real values passed from the analog engine to VHDL. Be aware that this, when combined with smaller time resolution values, can cause slower simulation runs.

The following example shows a SPICE subcircuit, its instance in the VHDL description, and the required corresponding Verilog wrapper.

*.subckt chargepump_com + com_inv<3> com_inv<2> com_inv<1> com_inv<0>+ com_rsh<3> com_rsh<2> com_rsh<1> com_rsh <0>+ clk* we skip the subckt description.ends

The following example shows the instantiation of the SPICE block described in example 53 in the VHDL description. The sig_inv, sig_rsh and sig_clk signals are defined in the VHDL block and connect to the chargepump ports.

I3 : chargepump_comport map (com_inv=> sig_inv(3 downto 0),com_rsh=> sig_rsh(3 downto 0),clk => sig_clk);


Chapter 8: Mixed-Signal Simulation in the VHDL/Verilog-SPICE FlowCreating a Mixed-signal Simulation Control File for VHDL/Verilog-SPICE

The following example shows a Verilog wrapper that must be generated to allow the instantiation of the SPICE cell under VHDL.

'timescale 1ns/10psmodule chargepump_com(com_inv, com_rsh, clk);input [3:0] com_inv, com_rsh;input clk;// The body of the Verilog wrapper can// be empty. And if it is not, its content// will be completely ignored.endmodule

Creating a Mixed-signal Simulation Control File for VHDL/Verilog-SPICE

In VHDL/Verilog-SPICE, as in Verilog-SPICE, a mixed-signal control file must be created. This file, called by -ad=setup_file_name at compile time, contains mixed-signal control commands which, among other things, controls the view selection of multi-view cells and A/D and D/A conversions.

All the mixed-signal simulation commands supported by Verilog-SPICE (as described in Creating a Mixed-Signal Simulation Control File in Chapter 8, “,”) are also supported in the VHDL/Verilog-SPICE flow—with the following exceptions:■ The use_vhdl command (view-selection command), is applicable in VHDL/

Verilog-SPICE. Use this command to select the VHDL view of a multi-view cell instantiated under SPICE.

■ Use the use_verilog command to select the Verilog view of a multi-view cell instantiated under SPICE.

■ Use the use_spice command to select the SPICE view of a multi-view cell instantiated under Verilog. This command alone is not sufficient to select a SPICE view for a cell instantiated under VHDL. The conventional VHDL methods such as configuration files or explicit "use lib.cell_name" must be used to select the Verilog wrapper for the SPICE block in addition to using the "use_spice" command.

Instance-based view selection is possible:

• For SPICE cells under Verilog, by enabling the instanced-based partitioning of the use_spice command.



• For cells instantiated under VHDL, when VHDL native methods are used (through use lib_name.cell_name in VHDL code or by using VHDL configurations).

The following example is a sample mixed-signal control file for the CustomSim-VCS-MX file.

use_spice -cell chargepump;use_verilog –module counter;use_vhdl –cell d_flop;use_vhdl –cell rtl_lib.mux_1;

choose xa -n spice_cells.spi -c cfg;bus_format <%d>;

The mixed-signal control file for FineSim, HSIM and NanoSim will look the same except that the choose nanosim line must be replaced with choose finesim or choose hsim or choose nanosim.

The use_vhdl CommandThe use_vhdl command selects the VHDL view of a multi-view cell instantiated in a SPICE block.

See the following syntax, arguments, and description:

use_vhdl –cell entity [-inst instance_name] [ port_map (port_map_list)

See Table 10 for the use_vhdl argument descriptions.

Table 10 use_vhdl Arguments


-cell entity Identifies the subcircuit to be substituted with a VHDL cell. The entity name cannot contain a wildcard (asterisk "*" character).

-inst instance_name If this option is used, only the specified instances aree instantiated in VHDL. The full hierarchical path to the instance is required.



The following example shows an instance-based VHDL substitution for specific Instances of the cell "inv2" "xi1.xu1" and "xi2.xu5.xinv5".

use_vhdl -cell inv2 -inst xi1.xu1 xi2.xu5.xinv5 ;

port_map (port_map_list) When the ports in the VHDL view of a multi-view cell have a different name compared to its SPICE view, this option can be used to map the SPICE name to the VHDL name. The port_map_list can have one or more of the following mappings, each separated by a ",":

spice_port_name => vhdl_port_name

A SPICE port name is mapped to a VHDL port name.

spice_port_name => snps_open

A SPICE port is declared as not having a VHDL counterpart and as a result the top-level SPICE net connected to that port remains open/dangling.


Maps all SPICE ports (or all remaining SPICE ports that have not been mapped yet) to VHDL ports by position. As a result the first port declared in the subcircuit definition is mapped to the first port declared in the VHDL entity definition and so on and so forth.

* => snps_open

All SPICE ports (or all remaining SPICE ports that have not been mapped yet) stay open, which means that the top-level SPICE nets connecting to those SPICE ports stay open/dangling when the SPICE view of the cell is substituted with the VHDL view.

Table 10 use_vhdl Arguments




The following example shows how to map SPICE ports to VHDL ports when they have different names.

.subckt inv1 i o….entity inv1 is port (y, a : out STD_LOGIC);….use_vhdl -cell inv1 port_map ( o => y, i => a );

The following example demonstrates how to map SPICE ports to VHDL ports when a few of the ports have different names in VHDL and SPICE but the rest have identical names in both views and can be mapped by name:

.subckt inv1 y m a b c….entity inv1 is port (z, n, a, b, c : out STD_LOGIC);….use_vhdl –cell inv1 port_map ( y => z, m =>n, * => snps_by_name);

Note that all ports must be mapped, which is why the "*" in " *=> snps_by_name" is required to map any port that is not explicitly mapped.

The following example shows how to map SPICE ports to VHDL ports when there are a few SPICE ports that don't have a counterpart in VHDL, a few of the ports have different names in VHDL and SPICE, and the rest have identical names:

.subckt inv1 y n a b c….entity inv1 is port (z, a, b, c : out STD_LOGIC);….use_vhdl –cell inv1 port_map ( y => z, n =>snps_open, * => snps_by_name);

The use_verilog CommandThe syntax for the use_verilog command is the same as in Verilog-SPICE. For more information, refer to the use_verilog description in the Verilog-SPICE section of this manual.

The use_spice CommandThe syntax for the use_spice command is the same as in Verilog-SPICE. For more information, see The use_spice Command description.


9

9Running a Mixed-Signal Simulation in VHDL/Verilog-SPICE

This chapter provides information for running an CustomSim-VCS-MX, FineSim-VCS-MX, HSIM-VCS-MX, or NanoSim-VCS-MX mixed-signal simulation.

Overview

To run a VHDL/Verilog-SPICE mixed-signal simulation, you must first be familiar with stand-alone VCS-MX and CustomSim/FineSim/HSIM/NanoSim simulations.

This chapter contains the following sections:■ Installation Requirements■ Setting up the Simulation Environment for the VHDL/Verilog-SPICE flow■ Required Input Files■ Compiling the Netlists

• The Design Analysis Stage

• The Design Elaboration Stage■ Running the Simulation in VHDL/Verilog-SPICE

• Simulation Time Resolution in VHDL/Verilog-SPICE

• Interactive Simulation with UCLI using VCS-MX■ Back-Annotation


Chapter 9: Running a Mixed-Signal Simulation in VHDL/Verilog-SPICEInstallation Requirements

Installation Requirements

In order to use VHDL/Verilog-SPICE, both the analog engine (the CustomSim, FineSim, HSIM or NanoSim tools) and VCS-MX must be installed.

Check the respective release notes for the compatibility table showing the compatible versions of the CustomSim/FineSim/HSIM/NanoSim tools and VCS-MX. The compatibility table also specifies the utilities (such as "cc", "gcc" and "ld") and the versions that are required for each release.

Generally, only one version of the CustomSim/FineSim/HSIM/NanoSim tools and one version of VCS-MX are certified for each VHDL/Verilog-SPICE release. (Non-recommended versions are not guaranteed to be compatible with each other. Refer to the Installation Requirements section of each manual for installation specifications.

Setting up the Simulation Environment for the VHDL/Verilog-SPICE flow

Running a mixed-signal simulation requires setting up paths and environment variables for both the CustomSim/FineSim/HSIM/NanoSim tools and VCS-MX.

Here is how to set the paths:■ For the CustomSim tool:

source XA_installation_directory/CSHRC_xa


setenv install_directory the_correct_install_dirsource finesim_install_dir/finesim.cshrc


set path = (HSIM_installation_directory/hsimplus/bin $path)


source NanoSim_installation_directory/CSHRC_ns

■ For VCS-MX

setenv VCS_HOME VCS-MX_installation_directoryset path = ($VCS_HOME/bin $path)


Chapter 9: Running a Mixed-Signal Simulation in VHDL/Verilog-SPICERequired Input Files

LicenseBoth LM_LICENSE_FILE and SNPSLMD_LICENSE_FILE can be used to specify the license file location.

setenv LM_LICENSE_FILE Location_of_License_File

or

setenv SNPSLMD_LICENSE_FILE Location_of_License_File

See the following example to set up the environment to run NanoSim-VCS-MX on the linux platform:

setenv VCS_HOME /usr/synopsys/VCS-MXset path = ($VCS_HOME/bin $path)source /usr/synopsys/Nanosim/CSHRC_linuxsetenv LM_LICENSE_FILE 26585@synopsys:$LM_LICENSE_FILE


Here are the required files for a VHDL/Verilog-SPICE simulation:■ All netlist files

• VHDL, Verilog, SPICE, Verilog-A, etc.■ VCS-MX setup and run-time files

• synopsys_sim.setup (optional), run-time command file (optional)■ Mixed-signal simulation control file

Compiling the Netlists

In the VHDL/Verilog-SPICE flow, simulation is performed in three steps. The compilation comprises the first two steps.

1. Design Analysis

2. Design Elaboration

3. Design Simulation


Chapter 9: Running a Mixed-Signal Simulation in VHDL/Verilog-SPICECompiling the Netlists

During Design Analysis, the syntax of Verilog and VHDL files are verified and intermediary files are generated that are used during Design Elaboration. Any syntax errors in Verilog or VHDL netlists are flagged during this step.

During Design Elaboration, the design hierarchy is built based on the information obtained during the Design Analysis step. At this stage, incorrect port connectivity or missing definitions for instantiated blocks in Verilog, VHDL or SPICE are identified and flagged.

Figure 22 demonstrates the two stages and the commands required for each stage.

Figure 22 Netlist Compilation Stages

The Design Analysis StageThe first step in the design compilation is the analysis of the Verilog and VHDL netlists. To analyze Verilog and VHDL files, the vlogan and vhdlan utilities are used, respectively. It is recommended that the analysis of the Verilog files be completed before the VHDL files.



Analyzing Verilog Files Using the vlogan UtilityTo analyze Verilog files, the vlogan command must be used. The syntax of the command follows:

vlogan [options] verilog_file(s)


-f verilog_list_file_name

Specifies a file that contains a list of paths to Verilog source files and compile-time options

-help Displays a succinct description of the most commonly used options

-l log_file Specifies a log file where VCS-MX records compilation messages

-q Suppresses compiler messages

-realport Use this option if among the Verilog files passed to vlogan there is one or more Verilog wrappers for SPICE that contains a wreal port. Such wreal ports must be defined in the wrapper when a SPICE port connects to a VHDL signal of type real. This option must also be used when SystemVerilog real type nets/ports connect to SPICE ports/nets.

-sverilog This option must be used if one or more files being analyzed contains SystemVerilog code or a SystemVerilog specific type such as a port of type "real".

-timescale=time_unit/time_precision

Enables you to specify the timescale for the source files that do not contain the ‘timescale compiler directive, and precedes the source files that do contain the ‘timescale compiler directive.

-v library_file Specifies a Verilog library file to search for module definitions.

-y library_directory +libext+ext

Specifies a Verilog library directory to search for module definitions.



For a complete list of the command-line options for vlogan, refer to the VCS® MX/VCS MXi User Guide.

The following example shows the calling of vlogan, where the two Verilog netlist files cell1.v and cell2.v are passed for analysis.

% vlogan cell1.v cell2.v

Because the –work option is not given, the intermediary files generated during analysis are stored in the logical WORK directory—the physical location of which is determined in the synopsys_sim.setup file.

The following example shows that instead of passing the names of individual Verilog files, option -f passes the file_list file to vlogan, which includes the names of the Verilog files to be analyzed. The intermediary files are also generated during the analysis of the Verilog files and are written into the vlog_lib logical library. The physical location of this logical library must be defined in the synopsys_sim.setup file.

% vlogan –f file_list -work vlog_lib

The following example shows how to analyze a Verilog wrapper file that contains one or more wreal ports with the -realport option.

% vlogan –realport wrapper1.v

-work logical_library Specifies the logical library where the intermediate files are written into. The physical location of logical libraries are defined inside the synopsys_sim.setup file. If not given, by default the intermediate files are stored in the logical WORK directory.

+incdir+directory Specifies the search directories to search for files specified with the ‘include compiler directive. You can specify more than one directory, separating each path name with the plus (+) character.

+v2k Enables the use of new Verilog constructs in the 1364-2001 standard.




Here, vlogan is called to analyze the verilog file wrapper1.v. Also the option -realport is used so that the ports defined as wreal in the wrapper1.v file can be handled by vlogan; otherwise, analysis fails and an error message is generated.

If there are no wreal ports defined in the Verilog files passed to vlogan, using the -realport option has no impact on the analysis.

The following example shows how to analyze a Verilog file that contains one or more SystemVerilog real ports with the -realport option.

% vlogan -sverilog -realport real_port_file.v

Here, vlogan analyzes the Verilog file real_port_file.v, which contains one or more ports of type real. The option -sverilog allows the ports to be real and the option -realport allows those ports to connect to SPICE. If there are no real ports in the Verilog file or if they do not conenct to SPICE, the option -wreal has no impact on the analysis. Note that if the -sverilog option is used to analyze one or more of the Verilog files, the -sverilog option must also be used with vcs at elaboration.

Analyzing VHDL Files Using the vhdlan UtilityTo analyze VHDL files, the vhdlan command must be used. The syntax of the command follows:

vhdlan [options] vhdl_file(s)


-f optionsfile Specifies an optionsfile that expands vhdlan command-line options.

-help Displays a succinct description of the most commonly used options.

-version Prints the version number of vhdlan and exits without running analysis.

-work logical_library Specifies the logical library where the intermediate files are written into. The physical location of logical libraries is defined inside the synopsys_sim.setup file. If not given, by default the intermediate files are stored in the logical WORK directory.



For a complete list of the command-line options for vhdlan, refer to the VCS® MX/VCS MXi User Guide.

The following example shows the calling of vhdlan, where the test1.vhd and test2.vhd files are passed for analysis:

% vhdlan test1.vhd test2.vhd

Because the -work option is not used, the intermediary files generated during analysis are stored in the WORK logical library, the physical location of which is determined in the synopsys_sim.setup file.

The following example shows the file testbench.vhd is analyzed and the intermediary files are stored in the vhd_lib logical library. The physical location of vhd_lib must be defined inside the synopsys_sim.setup file.

% vhdlan –work vhd_lib testbench.vhd

The Design Elaboration Stage Once all the VHDL and Verilog blocks in the design (including the Verilog wrappers) are analyzed, the next step is to elaborate those blocks, as well as the SPICE cells, as the final stage of the compilation.

To elaborate the design, the vcs command is used with the following syntax:

vcs -ad[=initFile] topConfig | topModule| topEntity ElabOptions

-output outfile Redirects standard output from VCS-MX analysis (that usually goes to the screen) to the file you specify as outfile.


-ad [=initFile] Enables the mixed-signal feature. If -ad is used alone, the mixed-signal control file name is assumed to be vcsAD.init. If the file name is different, it must be given with the =initFileoption.




topConfig | topModule| topEntity

Defines the top-level cell in the design. The top-level cell can be defined in one of three ways:

topConfig Defined by the VHDL configuration name that is defined for the top-level cell, if the design is VHDL-top.

topModule Defined by the name of the top-level module, if the design is Verilog-top.

topEntity Defined by the name of the top-level entity, if the design is VHDL-top.

ElabOptions Some of the useful VCS options that can be used during elaboration are listed as follows. For a complete list of all VCS options, refer to the VCS® MX/VCS MXi User Guide. Some of the commonly used options are listed below

-debug Enables DVE and UCLI debugging. This option does not enable line-stepping.

-debug_PP Enables both VPD generation and UCLI/DVE debugging.

-debug_all Enables all debug features, including VPD generation, UCLI/DVE debugging and line stepping.

-PP Enables VPD generation.

One of these two options (-debug_pp or -PP) are needed in combination with a $vcspluson system task embedded in the Verilog code to generate a unified VPD output file for both Verilog and VHDL signals.

-o executable_name Enables you to give the executable a different name.

By default, simv is the name of the executable generated by VCS.




The following example shows a sample compilation script for CustomSim-VCS-MX containing analysis and elaboration commands for a design with VHDL, Verilog and SPICE components. The design is assumed to be VHDL-top, and the tb.vhd and blk_1.vhd files contain all of the VHDL definitions, the blk_2.v and blk_3.v files contain all of the Verilog definitions, and the all_spice.spi file contains the SPICE definitions.

vlogan blk_2.v blk_3.vvhdlan tb.vhd blk1.vhdvcs -ad=setup.init testbench -ad_xa

testbench is the name of the top-level entity.

Because the -work option is not present, the default logical WORK library is used to analyze the digital blocks into. The mixed-signal control file "setup.init" file can look like the previous example:

choose xa –n all_spice.spi –c xa.cmd;use_spice –cell counter ddr_flop;bus_format <%d>;

Because counter and ddr_flop are multi-view cells, the "use_spice" command has been used to explicitly specify that the SPICE view of those cells must be used.

-R Runs the simulation immediately when the compilation is successfully completed.

-realport This switch must be used when a VHDL or SystemVerilog net of type "real" connects to a SPICE port. Or, alternately, a SPICE net connects to a VHDL or SystemVerilog port of type "real".

-sverilog This option must be used if one or more files being analyzed contain SystemVerilog code.

-ucli Enables UCLI debugging and forces the simulation to start in UCLI mode at run time.



Chapter 9: Running a Mixed-Signal Simulation in VHDL/Verilog-SPICERunning the Simulation in VHDL/Verilog-SPICE

Running the Simulation in VHDL/Verilog-SPICE

To run the mixed-signal simulation, the executable generated during the compilation must be run. By default, simv is the executable, unless the default name is overridden by the VCS -o option. The syntax for running simv follows:

% simv [runtime options]

In the following example, simv generates a simv.log run-time log file.

% simv –l simv.log

In the following example, the -ucli option starts the simulation in the UCLI interactive mode (assuming that the -debug or -debug_all option was also used during VCS compilation).

%simv -ucli

In the following example, a command file is passed to simv at run time.

% simv –include command.txt

The command.txt file can appear as follows:

run 1000echo “Simulation run for 1000 time-units”quit


-include [VCS-MX command file_name]

Specifies a file that contains VCS-MX commands to be run during run-time.

-l [log_file_name] Generates a run-time log file.

-ucli Starts the simulation in the UCLI interactive mode. The UCLI feature must have been enabled at compile time by passing the -ucli option to VCS.

-version Prints the version of the VCS-MX used in compilation.


Chapter 9: Running a Mixed-Signal Simulation in VHDL/Verilog-SPICEBack-Annotation

Simulation Time Resolution in VHDL/Verilog-SPICEThe time resolution rules and requirements for in VHDL/Verilog-SPICE simulation are identical to those for Verilog-SPICE simulation. Refer to the section Running the Simulation in the Verilog-SPICE Flow in Chapter 5, Running a Mixed-Signal Simulation in the Verilog-SPICE Flow.

Interactive Simulation with UCLI using VCS-MXThe simulation with UCLI rules and requirements for VCS-MX are identical to those for an VCS simulation. Refer to the section Invoking the Interactive Mode with the UCLI Debugging Feature with Verilog-SPICE in Chapter 5, Running a Mixed-Signal Simulation in the Verilog-SPICE Flow.

Back-Annotation

The same rules governing back-annotation in Verilog-SPICE apply in VHDL/Verilog-SPICE as well.


10

10Creating Verilog Wrappers in VHDL/Verilog-SPICE

This chapter describes how to use the autowrapper utility, which can generate Verilog wrappers for SPICE subcircuits instantiated under VHDL.

Overview

The autowrapper generates an empty Verilog module for a given SPICE subcircuit.

This chapter contains the following sections:■ The VHDL/Verilog-SPICE Autowrapper Utility

• Using the Autowrapper Utility

The VHDL/Verilog-SPICE Autowrapper Utility

As described in the previous chapters, a SPICE subcircuit cannot be directly instantiated in a VHDL or a Verilog block. A Verilog wrapper corresponding to the subcircuit must be initially created. The wrapper can be manually created or automatically created using the autowrapper utility.

After the wrapper has been created, you have to change the port direction in the wrapper.v file. Port direction does not pertain to a SPICE subcircuit, as all ports are considered inout. The autowrapper utility specifies all ports with inout direction. You must change the port direction in the wrapper.v file to assign the actual direction to each port (such as input, output, or inout). Although designating the directions of all ports as inout works, it could hinder


Chapter 10: Creating Verilog Wrappers in VHDL/Verilog-SPICEThe VHDL/Verilog-SPICE Autowrapper Utility

(slow) the run time because inout mixed-nets can lead to many successive back-and-forth D/A and A/D conversions.

The autowrapper utility creates wrapper.v and wrapper.log files (by default). The wrapper.v file contains all Verilog wrapper modules corresponding to all subcircuits that are defined in the SPICE file. For instance, if there are four subcircuits specified in the SPICE file, this utility creates four Verilog wrapper modules in the wrapper.v file. The syntax for the autowrapper utility is:

autowrapper -n[fmt] netlist_file(s)_name[-bus_fm bus_format][-cell subckt_name(s)][-xcell subckt_name(s)] [-file netlist_file_name][-o output_file_name][-case s|S|l|L|u|U]

For example, if a SPICE file contains the following subcircuit:

*spice sub circuit definition example.subckt inv a znm1 zn a vdd vdd p 1 0.35m2 zn a gnd gnd n 2 0.35.ends

The autowrapper utility creates a Verilog wrapper:

//generated verilog wrapper examplemodule inv (a, zn);inout a;inout zn;

endmodule

All ports are defined as inout in module inv. You must change port directions; for example, a as input and zn as output.

For a description of the autowrapper utility options, see Table 11.

Table 11 autowrapper Utility Description

Utility option Description

-n[fmt] netlist_file(s)_name

Specifies the file name (in any NanoSim- supported format) to be read-in. (Required option)

-bus_fm bus_format Enables the recognition of bus signals (with a specified bus format) for the input netlist file. The default bus format is [%d], but it can be set to any valid node name symbols. See Table 12 .



-cell subckt_name(s) Specifies the subcircuits, in the netlist file, that must be converted into Verilog wrapper modules. (All other subcircuits are ignored.) The module name uses the same case-sensitivity as the subckt_name.

If the defined subcircuit is not detected in the file, the following WARNING message is displayed:There is no subckt .... in nanosim_netlist_name.

-xcell subckt_name(s)

Specifies the subcircuits that must NOT be converted into Verilog wrapper modules. (All other subcircuits are converted into Verilog wrapper modules.) This option excludes specified subcircuits, and is case-insensitive.

If the defined subcircuit is not detected in the file, the following WARNING message is displayed:There is no subckt .... in nanosim_netlist_name.

-file netlist_file_name

Defines a list of subcircuits that must be converted into Verilog wrapper modules. These subcircuits are defined in the netlist_file. The netlist_file must have one subcircuit name per line. You can define the excluded subcircuit(s) commenting out the subcircuit names with a semicolon (;), as in the following example:File:name.txt ;inv;xor ;f_add adder

Table 11 autowrapper Utility Description (Continued)




For example, the _%d bus format directs the autowrapper utility to recognize bus signals defined as A_1, A_2 ..., A_n.

-o output_file_name Defines the name of the output file name where the Verilog wrappers are written, and sets the .log file prefix.

If the same file exists in the output directory, it is overwritten without a WARNING message.

-case s|S|l|L|u|U -case s or -case S maintains case-sensitivity for the port names

-case l or -case L generates lowercase port names (default)

-case u or -case U generates uppercase port names

Table 12 -bus_fm bus_format options

bus signal bus format

A[0] [%d]

B_1 _%d

C<2> <%d>

D_3_ _%d_

E{4} {%d}

F5 %d

G6_ %d_

Table 11 autowrapper Utility Description (Continued)




Using the Autowrapper UtilitySee the following guidelines about using the Autowrapper utility:■ If an inout port is connected to the register type net, VCS generates an

error message and stops compilation. In Verilog, a register type net should be connected to an input port—not an inout port. The autowrapper utility only generates inout ports, since direction does not exist in SPICE netlists. Therefore, before compiling, edit the wrapper.v file and specify the correct port direction.

■ The autowrapper utility generates one Verilog wrapper module per subcircuit; therefore, it can generate unnecessary Verilog wrappers. Some of these modules might be using the same module name as other Verilog modules in the original Verilog code. If this occurs, VCS generates an error message and stops compilation. Therefore, before compiling, check the module names in the Verilog wrapper file. If the name is used elsewhere in the Verilog description, and the generated Verilog wrapper is not needed, remove the module from the Verilog wrapper file. The following example displays the SPICE definition for subcircuits adder4 and inv, and how a Verilog wrapper can be generated.

.subckt adder4 a[3] a[2] a[1] a[0] b[3] b[2] b[1] b[0]+ clk cin cout xinv1 clk clkn inv….ends

.subckt inv a znm1 zn a vdd vdd p 1 0.35m2 zn a gnd gnd n 2 0.35.ends

You run the following:

autowrapper -nspi netlist -o net.v

The content of file net.v is shown in the following example:



module adder4 (a, b, clk, cin, cout);inout [3:0] a;inout [3:0] b;inout clk;inout cin;inout cout;endmodule

module inv (a, zn);inout a;inout zn;endmodule

The inv module is unnecessary here and can create confusion if another inv module exists in the original Verilog code. You must remove the inv module description from the net.v file.

■ Verilog is case-sensitive. SPICE is not case-sensitive. The autowrapper utility maintains case-sensitivity for module names; but, you must use the -case option if you want to maintain case-sensitivity for port names.

■ No timescale information in the wrapper file is generated by the autowrapper utility. Therefore, the wrapper file must be placed at the end of the Verilog file’s compilation input:

vcs -ad a.v c.v d.v wrapper.v

■ If the signal in the SPICE netlist is bus- or array-type, it must be expanded.

The autowrapper utility automatically generates bus- or array-type signals in the Verilog wrapper file (original SPICE subcircuit), as shown in the following example. Refer to Table 11 for details.

.subckt mem DATA[3], DATA[2], DATA[1], DATA[0],+ WL[0], WL[1], WL[2], WL[3],+ WL[4], WL[5], WL[6], WL[7],+ R_WB, RAM_ENB.ends



The autowrapper utility automatically forms bus- or array-type signals in the Verilog wrapper file, as shown in the following example. Refer to Table 11 for details.

module mem (data, wl, r_wb, ram_enb);inout [3:0] data;inout [0:7] wl;inout r_wb;inout ram_enb;

endmodule

■ If special characters and Verilog-specific keywords are used for the signal or subcircuit name, the name is assigned a backslash ( \ ) leading character.

In addition, a space is inserted at the end of the name in the Verilog wrapper file, as shown in the following example.

module \inverter.test ( \if , \1 , \2 );inout \if ;inout \1 ;inout \2 ;

endmodule

module vsources (\0 , \B#1 , B, \CE# , CLK, DECOUT, \Q^ , XDPD, \b#2 );

inout \0 ;inout \B#1 ;inout [5:5] B;inout \CE# ;inout CLK;inout [7:7] DECOUT;inout \Q^ ;inout [7:7] XDPD;inout \b#2 ;

endmodule

■ If subcircuit ports in a bus are randomly ordered in the transistor netlist, the autowrapper utility cannot function properly.



See the following example for a sample (unsupported) file.

.subckt p7ibptacddecwr clk wlw0[0] wlw0[10] wlw0[11] wlw0[12]+wlw0[13] wlw0[14] wlw0[15] wlw0[1] wlw0[2]+wlw0[3] wlw0[4] wlw0[5] wlw0[6] wlw0[7]+wlw0[8] wlw0[9] wlw1[0] wlw1[10] wlw1[11]+wlw1[12] wlw1[13] wlw1[14] wlw1[15] wlw1[1]+wlw1[2] wlw1[3] wlw1[4] wlw1[5] wlw1[6]+wlw1[7] wlw1[8] wlw1[9] writeadd[0] writeadd[1]+writeadd[2] writeadd[3] writeen[0] writeen[1].ends

■ Nested subcircuits in the SPICE netlist are supported. A module is generated for the nested subcircuit; the module name is made of the nested subcircuit name preceded by the parent subcircuit name, itself preceded by a backslash character (\).

A nested subcircuit sample is shown in the following example.

.subckt s in out

.subckt inv13 in out

.ends inv13

.ends s

An automatically generated Verilog wrapper module sample is shown in the following example.

module s (in, out)inout out;inout in;

endmodule

module \s.inv13 (in, out);inout out;inout in;

endmodule


11

11Mixed Simulation Output and Display in VHDL/Verilog-SPICE

This chapter describes the ways analog and digital waveforms can be generated and saved in CustomSim-VCS-MX, FineSim-VCS-MX, HSIM-VCS-MX, and NanoSim-VCS-MX simulations.

Overview

The output of VHDL/Verilog-SPICE mixed-signal simulation can either be saved into two separate files—one file for VCS-MX results (.vpd format) and another for analog results (for example,.vpd or .fsdb format)—or the simulation can generate a unified single output (in a merged .vpd format) that contains both digital and analog waveforms.

This chapter contains the following sections:■ Generating an Analog Output File■ Generating a Digital Output File■ Generating a Merged VPD Output File

Generating an Analog Output File

The same methods described in the Verilog-SPICE chapter earlier in this document are applicable in VHDL/Verilog-SPICE as well (see Generating an Analog Output File on page 132).


Chapter 11: Mixed Simulation Output and Display in VHDL/Verilog-SPICEGenerating a Digital Output File

Generating a Digital Output File

To capture both VHDL and Verilog signals in the design, the format of the digital output file must be VPD (also called VCD+). Storing digital signals in VPD also provides the option of merging the digital and analog signals into a unified output file.

The recommended method for generating a VPD file for digital signals is by using the UCLI "dump" command. Here are the steps:

1. Use the -PP or -debug_pp compile time options with VCS to enable VPD generation by VCS-MX, as follows:

vcs -ad top_entity_name -PPorvcs -ad top_entity_name –debug_pp

2. Use the simv run time options "-ucli -i ucli_command_file_name" to pass UCLI commands to dump a VPD file to VCS_MX. The command file must contain a dump command to create a VPD file. It can also contain an optional command to specify the name of the output VPD file. The example below shows how the UCLI command file is read at run time:

simv -ucli -i ucli_command_file

where the content of the command file looks like:

dump -file output.vpddump -add /foo -depth 99run 50000quit

in which the -depth option specifies that all signals—at and below the hierarchical path /foo—are dumped in the VPD file. If foo is the name of the top entity, every digital signal in the design is saved in the VPD file.

The -o option specifies the VPD file name, and in this example, the file name is foo.vpd. For a complete list of all options for the UCLI dump command, refer to the VCS Unified Command Line Interface User Guide.


Chapter 11: Mixed Simulation Output and Display in VHDL/Verilog-SPICEGenerating a Merged VPD Output File

Generating a Merged VPD Output File

In VHDL/Verilog-SPICE, a merged output file in VPD format can be created.

Note: FineSim does not support VPD format and as a result FineSim-VCS cannot generate a merged VPD output.

To generate a merged VPD file, the following conditions must be met:■ The analog signals must be saved in .vpd format and the CustomSim/

HSIM/NanoSim tools must be instructed to merge the analog VPD output with the one generated by VCS through the following configuration commands:

• For the CustomSim tool:

config command:

set_waveform_option –format vpd –file merge

• For the HSIM tool:

SPICE command:

.param HSIMOUTPUT=vpd file=merge

• For the NanoSim tool:

config command:

set_print_format for=vpd file=merge

■ The digital signals must be saved in .vpd format

The name of the merged VPD file will be the one determined by VCS.


Chapter 11: Mixed Simulation Output and Display in VHDL/Verilog-SPICEGenerating a Merged VPD Output File


Part 3: Verilog-AMS-SPICE Mixed-Signal Simulation



12

12Mixed-Signal Simulation in the Verilog-AMS-SPICE Flow

This chapter provides an overview of the Verilog-AMS-SPICE flow.

Overview

The Verilog-AMS-SPICE flow is only supported in the CustomSim-VCS AMS and NanoSim-VCS AMS solutions (mixed-signal solutions with the FineSim and HSIM tools do not currently support Verilog-AMS). This flow supports Verilog-AMS, as described in the Verilog-AMS LRM (with some exceptions and limitations described in this section).

The Verilog-AMS-SPICE flow supports many of the same features as those in Verilog-SPICE, described in Chapter 4, Mixed-Signal Simulation in the Verilog-SPICE Flow.

Some of the concepts in the Verilog-AMS language that must be considered when using the Verilog-AMS-SPICE flow are:■ Analog and digital blocks in Verilog-AMS■ Connect rules and connect modules■ Continuous and discrete domains ■ Nets and disciplines

This chapter contains the following topics:■ Analog and Digital Domains■ Understanding Analog and Digital Blocks in Verilog-AMS■ Nets and Disciplines


Chapter 12: Mixed-Signal Simulation in the Verilog-AMS-SPICE FlowAnalog and Digital Domains

Analog and Digital Domains

Depending on the computational methods used to calculate the values of a signals or variable, the signal or variable can belong to the analog domain (also known as continuous domain) or digital domain (also known as discrete domain).

Voltage and current values are calculated in the analog domain, while the contents of registers and states of gate primitives are calculated in the digital domain. Integer and real variables can belong to either the analog or digital domain, depending on how their values are assigned.

If a value is assigned in an analog block, the domain is considered analog. If a value is assigned in a digital block, the domain is considered digital. The assignment to real and integer variables can occur only in one domain.

Values calculated in the digital domain change values in a discrete and non-continuous manner. As a result, the derivative—with respect to the time of a digital value—is always zero (0). Values calculated in the analog domain, however, vary continuously and their derivative—with respect to the time—varies (as the value varies).

Understanding Analog and Digital Blocks in Verilog-AMS

Verilog-AMS supports the definition of analog and digital blocks within the same module, and for the digital block to access nets in the analog block (and vice-versa).

The following example shows Verilog-AMS code with both digital and analog blocks (highlighted). The port in is defined as a net of discipline logic, while port out is declared as a net of discipline electrical.


Chapter 12: Mixed-Signal Simulation in the Verilog-AMS-SPICE FlowNets and Disciplines

ìnclude "constants.vams"ìnclude "disciplines.vams"

module foo ( in, out);input in;output out;logic in;electrical out;

reg clk; (Digital block)initial begin clk = 0; forever #5 clk = ~clk;end

analog begin (Analog block) if (in == clk) V(out) <+ 1.8; else V(out) <+ 0.0;end

endmodule

A Verilog-AMS module can contain many digital blocks, but it can only contain one analog block as defined in the Verilog-AMS LRM (Language Reference Manual).

An analog block is identified by the keyword analog. All other blocks inside a module definition are considered digital blocks (e.g., initial and always blocks).

Since Verilog-AMS is a superset of the Verilog-A and digital Verilog-HDL languages, a module that only contains digital blocks (conventional digital Verilog HDL) or a module that only contains an analog block (conventional Verilog-A) is also viewed and treated as Verilog-AMS code by the simulator.

Nets and Disciplines

In Verilog-AMS, the term net refers to nodes inside a module that provide connections between two or more submodules. Every port of an instantiated module provides a connection between two nets.

A net can belong to a digital or analog domain. The way to declare the domain for a net is by associating it with a predefined discipline in Verilog-AMS. Two of



the most common disciplines in Verilog-AMS are electrical—for analog nets, and logic—for digital nets.

The discipline declaration for each net can be made explicitly in the code, or the simulator can resolve it, based on the discipline resolution algorithm. However, the discipline of all nets in a Verilog-AMS code must be determined before the simulation can start.

The following example shows an example of a module in which internal nets n1, n2 and n3 are defined to make connections between submodules.


module test;

// no disciplines declared for nets "n1", "n2" and "n3"

blka i1 (.a( n1), .b(n2), .z(n3) );blkb i2 (.out(n1) );blkc i3 (.a(n3), .out(n2) );

endmodule

Note: No explicit disciplines are declared for these nets, and the simulator can use the discipline resolution method to assign the proper discipline.

In the digital Verilog-HDL language, no explicit discipline declaration is made for wire, reg or port, so the compilation of the Verilog-HDL files can fail when they are used in the Verilog-AMS-SPICE flow.

To resolve this problem, a default discipline can be declared for all nets without an explicit discipline declaration. This can be achieved by either placing the `default_discipline directive inside the Verilog code, or by using the -ams_discipline VCS compile switch.

The following example shows where the `default_discipline directive in Verilog code is used to define the discipline logic as the default discipline. In this example, ports a and b of module foo have no explicit discipline



declaration. However, because of the `default_discipline logic statement, the logic discipline is assigned.


`default_discipline logicmodule foo ( a , b);input a;output b;…endmodule

The following example shows the -ams_discipline VCS switch defines a default discipline.

vcs testbench.v -R -ad -ams_discipline logic

Unlike nets, disciplines are not explicitly declared for variables.. The domain of a variable is determined by the context in which the assignment is made. If the variable is assigned a value in an analog context (i.e., in an analog block), the variable is considered analog. If, however, the assignment is made in a digital context (i.e., in a digital block), the variable is considered digital. A variable can only be assigned a value in one domain, but it can be accessed for reading from any domain.

The following example shows shows a digital domain variable. The real variable v is assigned a value in the digital domain (inside the initial block), and as a result is considered a digital variable.


module foo;real v;

initial begin v=1.5;end…endmodule



The following example shows a variable definition in Verilog-AMS code. The variable is assigned a value in the analog domain, and is treated as an analog variable.


module foo;real v;

analog begin …

v = 1.5; …end…endmodule


13

13Using Multiple Views, Donut Partitioning andConnect Modules with Verilog-AMS-SPICE

This chapter describes using multiple views, donut partitioning, and connect modules in Verilog-AMS-SPICE.

Overview

The following topics are described in this section:■ Selecting Multiple Views■ Understanding Hierarchical Layering of SPICE and Verilog-AMS in a Design■ Unsupported Features in Verilog-AMS-SPICE■ Resolving Keyword Conflicts between SystemVerilog and Verilog-AMS■ Converting Signals with Interface A/D and D/A Connect Modules

• Identifying the Correct Connect Module

• Understanding Connect Rules

Selecting Multiple Views

In the Verilog-AMS-SPICE flow, multi-view cells can exist, meaning that the cells can have both a SPICE subcircuit and a Verilog module definition. The desired view can be selected by using The use_spice Command or The use_verilog Command (mixed-signal control commands). Both of these commands—just as in Verilog-AMS-SPICE—support instance-based, as well as cell-based, view selection.


Chapter 13: Using Multiple Views, Donut Partitioning and Connect Modules with Verilog-AMS-SPICEUnderstanding Hierarchical Layering of SPICE and Verilog-AMS in a Design

Note: In the Verilog-AMS-SPICE flow, there is no distinction between Verilog-A, digital Verilog-HDL or Verilog-AMS code. Verilog-A and digital Verilog-HDL are both viewed as subsets of Verilog-AMS. Legacy digital Verilog-HDL code or legacy Verilog-A code are both considered Verilog-AMS code in the Verilog-AMS-SPICE flow.

In the Verilog-AMS-SPICE flow, a cell can only have one module definition. Regardless of the type of Verilog language used, the definition is viewed as Verilog-AMS and can be selected by using the use_verilog command.

The following example shows a mixed-signal control file where both instance-based and cell-based view selection commands are used.

choose xa -nspice spice_files.spi -c cfg;

use_verilog -module mux; // cell based use_veriloguse_spice -cell inverter; // cell based use_spice

use_verilog -module mux -inst top.i1.i2; // instance based use_veriloguse_spice -cell inverter -inst top.i1.i3; // instance based use_spice

Note: In the Verilog-AMS-SPICE flow, all Verilog files are passed to VCS at compile time. In the Verilog-SPICE flow, Verilog-A files are passed to fastSPICE, using the `hdl command. Although this feature is also supported in the Verilog-AMS-SPICE flow, it is recommended that, in the Verilog-AMS-SPICE flow, all Verilog files, including legacy Verilog-A, be passed to VCS at compile time.

Understanding Hierarchical Layering of SPICE and Verilog-AMS in a Design

Verilog-AMS-SPICE supports both SPICE-top and Verilog-top flows. It also supports any donut configuration with arbitrary layering of SPICE and Verilog-AMS in the design hierarchy.

By default, Verilog-AMS-SPICE assumes that the design is Verilog-top, unless the spice_top command is placed in the mixed-signal control file. The support of the SPICE-top and Verilog-top flows in Verilog-AMS-SPICE is


Chapter 13: Using Multiple Views, Donut Partitioning and Connect Modules with Verilog-AMS-SPICE

Unsupported Features in Verilog-AMS-SPICE

consistent with their support in Verilog-SPICE. For further information, please refer to the section Three Mixed-Signal Simulation Flows in Chapter 1, Getting Started with Mixed-Signal Simulation.

Unsupported Features in Verilog-AMS-SPICE

The following Verilog-AMS 2.2 features are not currently supported in the Verilog-AMS-SPICE flow:■ Analog voltage or current contribution from Verilog using cross-Module

Referencing (XMR) across the analog/digital boundary

Note: You can use XMR from inside Verilog to only probe (read) an analog voltage or current.

■ abstol parameter in ddt() (LRM chapter 4.4.4)■ aliasparam (LRM chapter 3.2)■ ddx() (LRM chapter 4.4.7 )■ detail discipline resolution (LRM chapter 8.4.4.2)■ driver access functions, $driver_xxx (LRM chapter 8.10)■ hierarchical net discipline coercion (LRM chapter 8.4.4.3)■ hierarchical system parameters (LRM chapter 7.2.6)■ last_crossing (LRM chapter 4.4.11)■ localparam (LRM chapter 3.2)■ parameterized-width analog buses■ parameter arrays (LRM chapter 3.2.4)■ paramsets (LRM chapter 7.3 )■ $param_given() (LRM chapter 10.11)■ $port_connected() (LRM chapter 10.11)■ predefined macros (LRM chapter 11.7)■ $rdist_xxx functions (LRM chapter 10.3)■ $simparam() (LRM chapter 10.1)■ VPI routines (LRM chapter 13)


Chapter 13: Using Multiple Views, Donut Partitioning and Connect Modules with Verilog-AMS-SPICEResolving Keyword Conflicts between SystemVerilog and Verilog-AMS

Resolving Keyword Conflicts between SystemVerilog and Verilog-AMS

There are certain function names and keywords in Verilog-AMS that cannot be used in SystemVerilog (for example "analog", "max", "sin") and vice versa (for example "interface", "logic").

To avoid such conflicts it is preferable that SystemVerilog and Verilog-AMS code each get parsed separately using their own language parsers. One way to achieve that is to give Verilog-AMS and SystemVerilog files distinct extensions. For example "*.vams" can be used for Verilog-AMS files and "*.v", ".sv", or "*.svh" for SystemVerilog. And then the following VCS switches can be used to identify those file extensions as the differentiation between SystemVerilog and Verilog-AMS contexts:

vcs -ams -ad +verilogamsext+vams +systemverilogext+sv+v+svh ...

This way the language context for SystemVerilog and Verilog-AMS would be kept separate at compilation time and the potential conflict between keywrods/function names can be avoided.

Converting Signals with Interface A/D and D/A Connect Modules

In Verilog-AMS, the conversion of signals between the analog and digital domains is done by interface blocks called connect modules. Connect modules are inserted automatically by the simulator at the interface between analog and digital nets, but they can also be inserted manually.

A connect module is a predefined Verilog-AMS module with two ports—one analog and one digital. The following example shows a sample connect module with the arbitrary name of snps_cm_a2d that takes an input of type




electrical and produces an output of type logic.

connectmodule snps_cm_a2d (ain, dout);output dout;input ain;logic dout;electrical ain;

… // The body of the connect-module … // will be defined here

endmodule

Identifying the Correct Connect ModuleThe process of identifying and applying the appropriate connect module for each interface requires the following steps:

1. The simulator ensures that every net in a module has a defined discipline. If a net does not have an explicit discipline definition, the discipline resolution algorithm is called to resolve and assign a discipline based on the discipline of other nets connected to it.

2. Once the disciplines for all nets are determined, the simulator identifies connections between nets of digital and analog disciplines

3. connect modules with matching disciplines are then inserted between the analog and digital nets. Direction of the ports are also accounted for.

Note: These steps occur at compilation time. If any steps are unsuccessful, the compile exits with an error message.

Verilog-AMS enables associating a particular connect module, based on the disciplines and port directions of the two nets connected, by defining a connect rule that is passed to the simulator.

Connect modules of this type are commonly called a2d connect modules. Connect modules that take a digital input and deliver an analog output are usually called d2a connect modules. The connect modules with bidirectional analog and digital ports are called bidi connect modules.


Chapter 13: Using Multiple Views, Donut Partitioning and Connect Modules with Verilog-AMS-SPICEConverting Signals with Interface A/D and D/A Connect Modules

Understanding Connect RulesThe following example shows a connect rule where two connect module associations are made. The first rule defines the connect module to be used in case an a2d interface must be inserted between two nets. The second rule defines the connect module to be used as a d2a interface between two nets.

connectrules snps_crules; connect snps_cm_a2d input electrical, output logic ; connect snps_cm_d2a input logic, output electrical ;endconnectrules

A connect rule may contain many more associations; for example, to define interfaces between other types of digital and analog disciplines, or to define bidi connect modules.

Note: Connect rules and connect modules are only deployed by the simulator if there is a connection between a digital and an analog net. If no direct connection exists throughout the netlist, connect rules and connect modules are not used.

In Verilog-AMS-SPICE, all conversions of signals between digital and analog are done by-way-of connect modules, as opposed to the resistance mapping used in NanoSim-VCS.




The following example displays an example in which no connect module is required.

module foo ( dig_in, dig_out, an_in, an_out);input dig_in, an_in;output dig_out, an_out;reg dig_out;

logic dig_in, dig_out;electrical an_in, an_out;

…

always @ (above(V(an_in), +1) // analog signal accessed in digital domain dig_out = 1b'1;

…

analog begin if (dig_in == 1b'1) // digital signal accessed in analog domain V(an_out) <+ 1.8;end

…

endmodule

Figure 23 shows an example of a circuit, a simple inverter chain, where connect modules are used because of a direct connection of analog and digital nets.



Figure 23 Cells of an inverter Chain Modeled in SPICE, Verilog-D, Verilog-A and Verilog-AMS

The circuit in this example contains four inverters:■ The first inverter is modeled in Verilog-D

The inverter is defined by a module that contains only digital block(s)■ The second inverter is modeled in SPICE

All ports of a SPICE cell assume electrical discipline in Verilog-AMS-SPICE

■ The third inverter is modeled in Verilog-AMS with logic input and electrical output

The inverter is defined by a module that contains both an analog block and digital block(s)

■ The fourth inverter is modeled in Verilog-A

The inverter is defined by a module that contains only an analog block

Note: In the Verilog-AMS-SPICE flow, all "Verilog" modules, regardless of whether they contain an analog or digital block, or both, are considered Verilog-AMS code. The examples of Verilog-A and Verilog-D referenced in Figure 23 are only used for clarification.

Figure 24 shows where the simulator inserts connect modules. There are two inserted connect modules: d2a and a2d.

Verilog-D SPICE Verilog-AMS Verilog-A

electrical electrical logic electrical electrical electrical logic logic




Figure 24 Inserted Connect Modules when Two Nets Of Different Disciplines come into Contact

Verilog-D SPICE Verilog-AMS Verilog-A

d2a a2d

electrical electrical logic electrical logic logic electrical electrical




14

14Preparing a Mixed-Signal Simulation with Verilog-AMS-SPICE

This chapter describes the special requirements for compiling netlists for an Verilog-AMS-SPICE simulation.

Overview

Before compiling netlists for an Verilog-AMS-SPICE simulation, special requirements must be met. For example, identical subcircuit and module names for multi-view cells, port name matching between SPICE and Verilog views, etc.

The following topics are described in this section:■ Preparing a Mixed-Signal Simulation in Verilog-AMS-SPICE■ Files Containing Connect Rule and Connect Module Definitions

Preparing a Mixed-Signal Simulation in Verilog-AMS-SPICE

In addition to the tasks required for using the NanoSim-VCS flow, which are mentioned in Table 5 in Chapter 4, Mixed-Signal Simulation in the Verilog-SPICE Flow, the following steps must be taken to prepare a mixed-signal


Chapter 14: Preparing a Mixed-Signal Simulation with Verilog-AMS-SPICEPreparing a Mixed-Signal Simulation in Verilog-AMS-SPICE

simulation in Verilog-AMS-SPICE:

1. Define proper connect modules and connect rules, if needed.

2. Use/modify the default connect rule and connect module files that come with the CustomSim™ and NanoSim installations.

3. Include the following two lines at the top of the first Verilog file passed to the simulator:

• ìnclude "constants.vams"

• ìnclude "disciplines.vams"

Note: Connect rules and connect modules are not used if direct connection(s) between analog and digital nets do not exist. This occurs if the interactions between analog and digital nets are implemented by-way-of the analog/digital cross-boundary sampling within a Verilog-AMS module—not through port connections—as shown in Figure 24 in Chapter 13, Using Multiple Views, Donut Partitioning and Connect Modules with Verilog-AMS-SPICE.

However, if there are direct connections between analog and digital nets (e.g., nets of electrical and logic disciplines), the definitions for connect rules and connect modules must be passed to the simulator at compile time.

CustomSim and NanoSim installations come with default connect rules and connect modules. They are located at:

XA_install_dir/include/connect_modules

NanoSim_install_dir/platform_type/ns/interfaces/vcsace

where platform_type is the name of the platform (e.g., linux, amd64, sparcOS5 etc.). For example, the default connect rules and connect modules for NanoSim on a Linux platform are located at:

NanoSim_install_dir/linux/ns/interfaces/vcsace


Chapter 14: Preparing a Mixed-Signal Simulation with Verilog-AMS-SPICEFiles Containing Connect Rule and Connect Module Definitions

Files Containing Connect Rule and Connect Module Definitions

The files that contain default definitions for connect rules and connect modules are:■ snps_cm_a2d_1.vams and snps_cm_d2a_1.vams (connect module)

These files contain the default a2d and d2a connect module definitions. The connect modules contain many parameters that define their behavior, such as parameters to define the analog supply voltage, high and low thresholds for a2d or d2a conversions, delay times, etc.

These parameters have default values that can be overwritten when the modules are referenced in the connect rule files.

■ snps_crules_1_xx.vams (connect rule)

Specific xx strings signify specific connect rule definitions for specific analog supply voltages. For example, the default connect rule file for a 1.8V supply is:

snps_crules_1_18.vams

If the design has specific characteristics (e.g., an analog supply voltage of 1.6V) that do not match any of the default connect rule files, define a connect rule file by copying one of the default files to a new file and change the parameters for the connect module referenced inside of it.


Chapter 14: Preparing a Mixed-Signal Simulation with Verilog-AMS-SPICEFiles Containing Connect Rule and Connect Module Definitions


Part 4: Appendices



A

AMixed-Signal Commands

This appendix lists the old and new Mixed-signal commands.

Overview

Starting from 2009.06 a new set of mixed-signal commands is introduced which will replace, and in some cases add to, the old command set.

Table 13 maps the new commands to the old ones. The table also identifies the old, obsolete commands and new commands that do not have a counterpart in the old command set.

Both sets of commands will be supported in the 2010.12 release, but the old commands will be phased out in later releases.

Table 13 Old and New Mixed-Signal Commands

Old Mixed-Signal Commands

(to be phased out)

New Mixed-Signal Commands

(starting from 2009.06)

choose choose

set bus_format bus_format

N/A duplicate_net_inst_name (new in 2010.03)

N/A a2d (replaces NanoSim config command "set_node_thresh" and the use of HSIM ".hsimvcs_intfparam" command for a2d interface elements)


Appendix A: Mixed-Signal CommandsOverview

set interface_opt d2a (also replaces the use of HSIM ".hsimvcs_intfparam" command for d2a interface nets)

N/A insert_cell (new in 2009.06)

set irmap (obsolete, replaced by XMR system tasks in 2009.06)

N/A

set mview_vlog_noportswap mview_vlog_noport_swap

set opt_shadowfile optimize_shadowfile

set print_thru_net print_thru_net

N/A param_pass (new in 2009.06)

set remove_interface remove_d2a

set res_by_node rmap_by_node

set spice_port_order_as_vlog spice_port_order_as_vlog

set wrapper_dir shadow_file_dir

spice_top spice_top

use_spice use_spice

use_verilog use_verilog

use_vhdl use_vhdl

Table 13 Old and New Mixed-Signal Commands (Continued)

Old Mixed-Signal Commands

(to be phased out)

New Mixed-Signal Commands

(starting from 2009.06)


B

BReserved Keywords

This appendix describes the reserved keywords. When using the Verilog-SPICE, VHDL/Verilog-SPICE or Verilog-AMS-SPICE flows, or Verilog-AMS-SPICE, these terms are treated as keywords in the Verilog modules. If any of the following keywords are used as net names, port names, instance names or module names in the Verilog (D) modules, you must rename these keywords to avoid compilation errors.

Overview

This appendix contains the following items:■ Reserved Keywords for Verilog-SPICE and VHDL/Verilog-SPICE■ Reserved Keywords for Verilog-AMS-SPICE

Reserved Keywords for Verilog-SPICE and VHDL/Verilog-SPICE

See Table 14 for an alphabetical listing of the reserved keywords for NanoSim-VCS and NanoSim-VCS-MX:

Table 14 Reserved Keywords for Verilog-SPICE and VHDL/Verilog-SPICE

abs absdelay abstol access

acos acosh ac_stim always


Appendix B: Reserved KeywordsReserved Keywords for Verilog-SPICE and VHDL/Verilog-SPICE

analog analysis and asin

asinh assign atan atan2

atanh begin branch buf

bufif0 bufif1 capacitor case

casex casez ceil cmos

connect connectrules continuous cos

cosh cross ddt ddt_nature

deassign default defparam disable

discipline discrete domain driver_update

edge else end enddiscipline

endcase endconnectrules endmodule endfunction

endnature endprimitive endspecify endtable

endtask event exclude exp

final_step flicker_noise floor flow

for force forever fork

from function generate genvar

ground highz0 highz1 hypot

inductor idt idtmod idt_nature

iexp ipulse ipwl isine

if ifnone inf initial

intial_step inout input integer



Appendix B: Reserved KeywordsReserved Keywords for Verilog-SPICE and VHDL/Verilog-SPICE

join laplace_nd laplace_np laplace_zd

laplace_zp large last_crossing limexp

ln log macromodule max

medium merged min module

nand nature negedge net_resolution

nmos noise_table nor not

notif0 notif1 or output

parameter pmos posedge potential

pow primitive pull0 pull1

pullup pulldown rcmos real

realtime reg release repeat

resolveto resistor rnmos rpmos

rtran rtranif0 rtranif1 scalared

sin sinh slew small

specify specparam split sqrt

strong0 strong1 supply0 supply1

table tan tanh task

time timer tline tran

tranif0 tranif1 transition tri

tri0 tri1 triand trior

trireg units vcvs vccs



Appendix B: Reserved KeywordsReserved Keywords for Verilog-AMS-SPICE

Reserved Keywords for Verilog-AMS-SPICE

See Table 15 for an alphabetical listing of the reserved keywords for Verilog-AMS-SPICE:

vectored vexp vpulse vpwl

vsine wait wand weak0

weak1 while white_noise wire

wor wreal xnor xor

zi_nd zi_np zi_zd zi_zp

Table 15 Reserved Keywords for Verilog-AMS-SPICE

above abs absdelay acos

acosh ac_stim aliasparam always

analog analysis and asin

asinh assign atan atan2

atanh begin branch buf

bufif0 bufif1 case casex

casez ceil cmos connectrules

cos cosh cross ddt

ddx deassign default defparam

disable discipline driver_update edge




else end enddiscipline endcase

endconnectrules endmodule endfunction endnature

endparamset endprimitive endspecify endtable

endtask event exclude exp

final_step flicker_noise floor flow

for force forever fork

from function generate genvar

ground highz0 highz1 hypot

idt idtmod if ifnone

inf initial intial_step inout

input integer join laplace_nd

laplace_np laplace_zd laplace_zp large

last_crossing limexp ln localparam

log macromodule max medium

min module nand nature

negedge net_resolution nmos noise_table

nor not notif0 notif1

or output parameter paramset

pmos posedge potential pow

primitive pull0 pull1 pullup

pulldown rcmos real realtime

Table 15 Reserved Keywords for Verilog-AMS-SPICE (Continued)



reg release repeat rnmos

rpmos rtran rtranif0 rtranif1

scalared sin sinh slew

small specify specparam sqrt

string strong0 strong1 supply0

supply1 table tan tanh

task time timer tran

tranif0 tranif1 transition tri

tri0 tri1 triand trior

trireg vectored wait wand

weak0 weak1 while white_noise

wire wor wreal xnor

xor zi_nd zi_np zi_zd

Table 15 Reserved Keywords for Verilog-AMS-SPICE (Continued)


C

CVerilog/VHDL/HSIM VPI Mixed-Signal Simulation

Provides information on the Verilog/VHDL/HSIM VPI mixed-signal simulation works.

This chapter presents a solution to Verilog/VHDL/HSIM VPI mixed-signal simulation. The chapter is structured in the following order:■ System environment variable setup■ Analog/digital partitioning flows and examples■ Configuration commands ■ Setup and partitioning guidelines

Verilog/VHDL/HSIM mixed-signal simulation allows a design to be partitioned into digital and analog blocks and simulated as one. The digital partition is in Verilog/VHDL and simulated by a Verilog/VHDL simulator. HSIM simulates the analog partitions with SPICE netlist format. The mixed-signal simulation interfaces synchronize both the Verilog/VHDL simulator and HSIM as well as passing and translating signal values back and forth between these two simulators.

The Synopsys Verilog/VHDL/HSIM mixed-signal simulation offers three analog/digital partitioning flows to fit into different design and verification methodologies:■ Verilog/VHDL netlist on top with leaf instances assigned to SPICE.■ SPICE netlist on top with leaf instances assigned to Verilog or VHDL.■ Integration with Virtuoso® Analog Design Environment with analog and

digital netlists generated by SPECTRE/Verilog mixed-signal simulation.

Cadence® NC-Verilog®/VHDL[1] and Mentor Graphics ModelSim® are supported. Cadence Verilog-XL[2] also works with mixed-signal simulation, but


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationSetting Up System Environment Variables for Mixed-Signal Simulation

it is not fully tested. Other PLI 2.0 compliant Verilog/VHDL simulators may also work with HSIM mixed-signal simulation but have not been fully tested.

Mixed-signal simulation uses Verilog Procedural Interface (VPI) or Programming Language Interface (PLI) 2.0, to interact with ncsim, NC-Verilog/VHDL simulator. The mixed-signal simulation executable is a shared library including VPI code and the HSIM engine. Mixed-signal simulation starts with ncsim as the master simulator which dynamically links with the mixed-signal simulation library and invokes the HSIM engine. The single process combines the ncsim, mixed-signal simulation interface, and HSIM engine. The interactions between ncsim and HSIM go through VPI function calls. This approach does not need any communication backplane and interprocess communication (IPC). Thus, best performance can be achieved.

Setting Up System Environment Variables for Mixed-Signal Simulation

Before running mixed-signal simulation, the system must be set up using the following steps.

1. Set the NC-Verilog/VHDL executables path as shown in the following example:

set path=($path /usr/local/vendors/cadence/ldv40/tools/bin)

2. Add the NC-Verilog/VHDL library path to the LD_LIBRARY_PATH environment variable as shown in the following syntax example:

setenv LD_LIBRARY_PATH ${LD_LIBRARY_PATH}/bin:/usr/local/vendors/cadence/ldv40/tools/inca/lib:/usr/local/vendors/cadence/ldv40/tools/lib

3. Add the directory containing libvpihsim.so to LD_LIBRARY_PATH. libvpihsim.so is the VPI shared library shipped to Synopsys customers.

4. Add a directory containing the Tool Command Language (TCL) shared library and output the shared library, such as libFSDB.so, to LD_LIBRARY_PATH. Shared libraries are provided in the tool installation.

Note: For the HP-UX platform, the library path environment variable is SHLIB_PATH and the VPI shared library is libvpihsim.sl.


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationMixed-Signal Simulation with Verilog as the Top Instance

Note: To run mixed-signal simulation with VCS and Verilog-XL, set the TCL_LIBRARY environment variable to the HSIM tool installation directory containing the init.tcl file.

Mixed-Signal Simulation with Verilog as the Top Instance

High-Level Mixed-Signal Simulation InstructionsHigh-level mixed-signal simulation provides the steps necessary to run Verilog/HSIM mixed-signal simulation without using the cell view approach.

Note: Syntax Convention: A backslash character (\) in syntax examples marks a line continuation. Where there is no space before the \, the line continues unbroken. If a there is a space prior to the \, a space exists in the syntax.

To perform high-level mixed-signal simulation without using the cell view approach, do the following:

1. For those Verilog modules to be simulated by HSIM, replace their module body with only one line as shown in the following syntax example:

initial $nsda_module();

2. Provide a SPICE netlist for Verilog modules that have the same module/subcircuit and port names.

3. Recompile the Verilog source code using ncvlog. Proper hdl.var and cds.lib are required for ncvlog.

4. Insert ncelab with an additional command line option where libvpihsim.so is the VPI share library shipped to Synopsys customers as shown in the following syntax example:

-loadvpi libvpihsim.so:nsda_vpi_startup

5. Specify HSIM parameters such as the netlist file name in the cosim.cfg file.

6. Run ncsim with additional command line option as shown in the following syntax example:

-loadvpi libvpihsim.so:nsda_vpi_startup +nsda+”cosim.cfg”



Detailed Mixed-Signal Simulation InstructionsThe information contained in this section provides details on running Verilog/HSIM mixed-signal simulation using the cell view approach.

To perform detailed mixed-signal simulation using the cell view approach, do the following:

1. Create new Verilog source files for the modules to be simulated in HSIM. It is not necessary to modify the original Verilog source code. The modules should have the same module name and port name as the original Verilog modules. The module body contains only the following syntax line:


Use a new file name extension, such as .cs, to compile the new files into a new view such as cosim view.

2. Modify hdl.var to define a new view as shown in the following syntax example:

DEFINE VIEW_MAP (.cs => cosim)

3. The selected view described in the previous syntax is cell based. For an instance based view selection, insert the following compilation directive before the instance in the original Verilog source code as shown in the following syntax:

ùselib lib=cosim_lib view=cosim

4. Create a SPICE netlist for the Verilog modules. Make sure to have the same subcircuit name as the Verilog module name and port names as well.

Note: If a subcircuit name is different from the module name, use map_subckt_name to associate them.

5. Compile the new Verilog files into a new view as specified in hdl.var.

6. Prepare mixed-signal simulation configuration file, e.g. cosim.cfg, with HSIM parameters and mixed-signal simulation parameters.

7. Run the NC-Verilog command with additional -loadvpi command option. NC-Verilog is a Cadence product that requires three steps to run a simulation: compilation, elaboration, and simulation. The related commands are:

• Compilation—Use the ncvlog command. The syntax is :



% ncvlog top.v gate.cs

• Elaboration—Use the ncelab command. The syntax is:

% ncelab -loadvpi libvpihsim.so:nsda_vpi_startup -access \+rwc -LIBNAME cosim_lib cosim_lib.top -snapshot \cosim_lib.top:cosim

• Simulation—Use the ncsim command. The syntax is:

% ncsim -loadvpi libvpihsim.so:nsda_vpi_startup \+nsda+”cosim.cfg” cosim_lib.top:cosim

where libvpihsim.so is the VPI share library are shipped with the product.

Note: The ncsim command line option +nsda+ is used to pass the cosim.cfg configuration file name to mixed-signal simulation. If the +nsda+ option is not specified, the default configuration file is cosim.cfg.

The following example illustrates a simple inverter chain with five inverters of which two are in analog and three in digital. The inv module is shown in both the top.v and gate.cs files. Since hdl.var defines the .cs file as cosim view with a higher precedence over the default module view, the inv module is simulated in HSIM. Its equivalent subcircuit is defined in the inv.spi file.

Sample files for the example include the following:■ top.v

Verilog source code that contains the default inv module. This file is compiled into the default module view.

■ gate.cs

Verilog source code containing an inv module to be simulated by HSIM. This file is compiled into the cosim view.

■ hdl.var

Verilog configuration file that specifies a cosim view, asks the compiler to compile *.cs source files into cosim view, and asks elaborator to pick cells with cosim view whenever available.

■ cds.lib

Verilog configuration file that defines design libraries. The physical directory for a design library must pre-exist. Refer to the Cadence NC-Verilog User Manual for details.



■ inv.spi and test.spi

SPICE netlist with inv subcircuit simulated by HSIM.■ cosim.cfg

Mixed-signalsimulation configuration file that specifies both HSIM and mixed-signal simulation parameters such as the SPICE netlist file name.



======== top.v ========// Top cell with 5 chain inverters, but pushing thru // one more level of hierarchy by my_buf`timescale 1ns / 10ps

module top;wire z1, z2, z3;testbench tb(z1, z2, z3, a);chain main(a, z1, z2, z3);

endmodule

module testbench(z1, z2, z3, a0);input z1, z2, z3;output a0;reg a0;always #25 a0=~a0;initial begin

a0=1'b1;$monitor($time,, a0,, z1,, z2,, z3);#200;$finish;

endendmodule

module chain (a, z1, z2, z3);input a;output z1, z2, z3;my_buf x1 (a, z1);my_inv x2 (z1, z2);my_buf x3 (z2, z3);

endmodulemodule inv (a, z);

input a;output z;assign z=~a;

endmodule

module my_inv (a, z);input a;output z;assign z=~a;

endmodule

module my_buf (a, z);input a;output z;wire t;my_inv IV1(a, t);


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationInstance Based Instantiation with Verilog Configuration

inv IV2(t, z);endmodule

======= gate.cs =======module inv (a, z);

input a;output z;initial $nsda_module();

endmodule

====== inv.spi ======.subckt inv a zm1 z a vdd vdd p l=0.5u w=5u as=1.0e-10 ad=1.0e-10 ps=0+ pd=0m2 z a 0 0 n l=0.5u w=3u as=1.0e-10 ad=1.0e-10 ps=0 pd=0.ends

====== test.spi =====.param VDDVAL=3v* global nodes.global vdd vss gnd* suppliesvvdd vdd 0 dc VDDVALvgnd gnd 0 dc 0v.inc models.inc inv.spi.print v(*).end

======== cosim.cfg ========set_args test.spi

======== hdl.var =========DEFINE WORK cosim_libDEFINE VIEW_MAP (.cs => cosim)

======== cds.lib =========DEFINE cosim_lib ./cosim_lib

Instance Based Instantiation with Verilog Configuration

NC-Verilog 5.1 supports instance based instantiation by using Verilog configurations in accordance with the IEEE standard, IEEE 1364-2001. A library map file contains the binding rules. This feature is invoked using ncvlog and ncelab with the -libmap command line option to specify the library map file.


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationInstance Based Instantiation with Verilog Configuration

Multiple implementations of the same module can be compiled into different design libraries. Using Verilog configurations, ncelab searches design libraries to bind instances as shown in the following example.

====== File: top.v ======module top();

chain a1(...);chain a2(...);

endmodule

module chain(...);inv i1(...);inv i2(...);

endmodule

module inv(in, out);input in;output out;assign out = ~in;

endmodule

====== File: inv.cs ======module inv(in, out);

input in;output out;initial $nsda_module();

endmodule

====== Library map file: lib.map ======library rtlLib top.v;library cosimLib inv.cs;

config cfg;design rtlLib.top;default liblist rtlLib cosimLib;instance top.a2.i1 liblist cosimLib;

endconfig

To compile the design units, invoke ncvlog using the following syntax:

% ncvlog -libmap lib.map top.v inv.cs

This compiles the design units into the appropriate libraries as follows:

Design Units Library

top rtlLib


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationMixed-Signal Simulation with VHDL as the Top Instance

In the lib.map (library map) file, the Verilog configuration cfg specifies an instance based instantiation for instance top.a2.i1. To elaborate the top design, use the following command:

% ncelab -libmap lib.map cfg -loadvpi \ libvpihsim.so:nsda_vpi_startup -access +rwc

The instance top.a2.i1 is bound to the design unit inv in cosimLib while the remaining three inv instances are bound to the design unit inv in rtlLib. During mixed-signal simulation, the instance top.a2.i1 is partitioned to the analog simulator and the others are simulated by Verilog simulator. With the Verilog configuration, analog/digital partitioning for mixed-signal simulation can be accomplished in an instance based fashion.

Refer to the NC-Verilog User Manual and IEEE 1364-2001 standard for further details on instance based instantiation.

Mixed-Signal Simulation with VHDL as the Top Instance

The Cadence ncsim is able to simulate pure Verilog, pure VHDL, and mixed Verilog/VHDL designs. This Synopsys mixed-signal simulation uses VPI to interact with ncsim. However, VPI can only access Verilog objects. In order to simulate with VHDL, HSIM needs Verilog as the media to interact with VHDL indirectly. Therefore, a Verilog wrapper is required.

Use the following steps to run mixed-signal simulation with VHDL designs.

1. Create a Verilog module with the same port definition as the VHDL entity to be partitioned to SPICE. This Verilog module contains only one statement as the module body and functions as a wrapper around the SPICE block as shown below:


chain rtlLib

inv (from inv.cs) cosimLib

inv (from top.v) rtlLib

Design Units Library



2. Modify the original VHDL code to instantiate the new Verilog module.

3. Compile the VHDL code with ncvhdl as shown in the following syntax:

% ncvhdl top.vhd

4. Compile the Verilog code with ncvlog as shown in the following syntax:

% ncvlog gate.cs

5. Elaborate the design with ncelab as shown in the following syntax:

% ncelab -loadvpi libvpihsim.so:nsda_vpi_startup -access +rwc top:a

6. Prepare SPICE netlist for the SPICE block.

7. Setup mixed-signal simulation configuration file.

8. Run mixed-signal simulation with ncsim as shown in the following syntax:

% ncsim -loadvpi libvpihsim.so:nsda_vpi_startup +nsda+cosim.cfg top

Note: Bi-directional port in VHDL/HSIM mixed-signal simulation is not supported.

The following example shows a VHDL on top design of a inverter chain with two leaf inverters assigned to SPICE. The VHDL entity inv is replaced by a SPICE subcircuit inv for mixed-signal simulation. A Verilog module inv is created as the wrapper of the SPICE subcircuit.

The following sample files are used are:■ top.vhd: The VHDL design■ gate.cs: The Verilog wrapper for SPICE subcircuit inv.■ test.spi: SPICE netlist■ inv_sub.spi: SPICE netlist■ cosim.cfg: Mixed-Signal simulation configuration file■ hdl.var: NC-Verilog configuration file■ cds.lib: NC-Verilog configuration file



========== File: top.vhd ===========library ieee;use ieee.std_logic_1164.all;library std;use std.textio.all;entity top isend top;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_textio.all;library std;use std.textio.all;architecture A of top is component

testbench port (z1, z2, z3: in std_logic; a: out std_logic); end component; component

cut port (a: in std_logic; z1, z2, z3: out std_logic); end component; signal a, z1, z2, z3: std_logic;begin tb: testbench PORT MAP (z1, z2, z3, a); main: cut PORT MAP (a, z1, z2, z3); process (a, z1, z2, z3) VARIABLE I: LINE; begin

write( I, now, left, 15); write( I, a , right, 3); write( I, z1, right, 3 ); write( I, z2 , right, 3); write( I, z3 , right, 3); writeline(output, I);

end process;end;library ieee;use ieee.std_logic_1164.all;entity testbench is port (z1, z2, z3: in std_logic;

a: out std_logic);end testbench;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_textio.all;library std;use std.textio.all;architecture behav of testbench is



signal tick: std_logic;begin process variable i: std_logic := '0'; variable initial: integer := 0; begin a <= i; tick <= i after 3 ns;

if (now >= 250 ns) then wait;end if;

wait for 25 ns; i := NOT i; end process; process(tick) variable error: STRING (1 to 7) := "ERROR: "; VARIABLE I: LINE; begin if (now > 0 ns) then if (tick /= z1) or (tick = z2 ) or (tick = z3 ) then write( I, error, left, 7); write( I, now, left, 15); write( I, tick, right, 3); write( I, z1, right, 3); write( I, z2, right, 3); write( I, z3, right, 3); writeline(output, I); end if; end if; end process;end behav;library ieee;use ieee.std_logic_1164.all;entity cut is port (a: in std_logic;

z1, z2, z3: out std_logic);end cut;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_textio.all;library std;use std.textio.all;architecture gate of cut is component

my_buf port (a: in std_logic; z: out std_logic); end component;



componentmy_inv port(a: in std_logic;

z: out std_logic); end component; signal m1, m2, m3: std_logic;begin x1: my_buf PORT MAP (a, m1); x2: my_inv PORT MAP (m1, m2); x3: my_buf PORT MAP (m2, m3); z1 <= m1; z2 <= m2; z3 <= m3;-- process (a, m1, m2, m3)-- VARIABLE I: LINE;-- begin-- write( I, now, left, 15);-- write( I, a , right, 3);-- write( I, m1, right, 3 );-- write( I, m2 , right, 3);-- write( I, m3 , right, 3);-- writeline(output, I);-- end process;end;library ieee;use ieee.std_logic_1164.all;entity my_inv is port(a: in std_logic;

z: out std_logic);end my_inv;library ieee;use ieee.std_logic_1164.all;architecture behav of my_inv isbegin-- z <= NOT a after 1 ns; z <= NOT a;end;--library ieee;--use ieee.std_logic_1164.all;--entity inv is-- port(a: in std_logic;-- z: out std_logic);--end inv;--library ieee;--use ieee.std_logic_1164.all;--architecture behav of inv is--begin-- z <= NOT a after 1 ns;-- z <= NOT a;



--end;library ieee;use ieee.std_logic_1164.all;entity my_buf is port (a: in std_logic;

z: out std_logic);end my_buf;library work;use work.all;architecture gate of my_buf is component

my_inv port(a: in std_logic; z: out std_logic); end component; component

inv port(a: in std_logic; z: out std_logic); end component; signal t: std_logic;begin IV1: my_inv PORT MAP (a, t); IV2: inv PORT MAP (t, z);end gate;

========== File: gate.cs ===========module inv (a, z); input a; output z; initial $nsda_module();endmodule========== File: test.spi ===========.param VDDVAL=3v* global nodes.global vdd vss gnd * suppliesvvdd vdd 0 dc VDDVALvgnd gnd 0 dc 0v.inc models.inc inv_sub.spi.print v(*).end========== File: inv_sub.spi ===========.subckt inv a zm1 z a vdd vdd p l=0.5u w=5u as=1.0e-10 ad=1.0e-10 ps=0 pd=0 m2 z a 0 0 n l=0.5u w=3u as=1.0e-10 ad=1.0e-10 ps=0 pd=0 .ends.subckt invs a z vccm1 z A vdd vdd p l=0.35u w=400u as=1.0e-10 ad=1.0e-10 ps=0 pd=0


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationMixed-Signal Simulation with SPICE as the Top Instance

m2 z a 0 0 n l=0.35u w=200u as=1.0e-10 ad=1.0e-10 ps=0 pd=0 .ends========== File: cosim.cfg ===========set_argsspice/test.spi========== File: hdl.var ===========DEFINE WORKcosim_lib DEFINE VIEW_MAP( .cs => cosim, .vhd => vhd, .v => module )========== File: cds.lib ===========INCLUDE /rmnt/tools/cadence/LDV51QSR1/tools/inca/files/cds.libDEFINE cosim_lib ./cosim_lib

Mixed-Signal Simulation with SPICE as the Top Instance

In this design flow, the SPICE netlist is the design top instance. Verilog instances are instantiated from the SPICE netlist. In general, circuit designers have the whole SPICE netlist and would like to replace certain digital blocks with Verilog instances.

To run mixed-signal simulation, the cosim.v Verilog interface file is automatically generated by executing HSIM command against the original SPICE netlist. The cosim.v file contains the Verilog top module instaitiating Verilog instances to replace SPICE subcircuits. Then mixed-signal simulation is conducted against cosim.v, other Verilog source files for digital instances, and the original SPICE netlist.

The procedure to run mixed-signal simulation for this design flow is described as follows:

1. Create a configuration file such as cosim.cfg for both HSIM and mixed-signal simulation containing the following commands:

• set_args: Used with HSIM command line options including the SPICE netlist to run HSIM.

• digital_cell or digital_cell_inst: Specifies the Verilog instances in the SPICE netlist.

• verilog_file: Specifies the Verilog file containing the Verilog module definitions.

Here is an example of a cosim.cfg file:



set_args spice/test.spidigital_cell invdverilog_file verilog/invd.v

In this example, invd.v defines the Verilog inverter, and digital_cell defines the digital partitions instantiated in cosim.v which is generated by HSIM.

2. Run HSIM with the configuration file. HSIM stops simulation after generating cosim.v as shown in the following example:

% hsim -cscfg cosim.cfg

Once cosim.v is generated, Step 2 can be skipped in future mixed-signal simulation runs if analog/digital partitioning and the Verilog port analog/digital interface definitions remain unchanged.

3. Use the Verilog compiler to compile cosim.v together with other Verilog source files.

4. Start mixed-signal simulation from the top Verilog module defined in cosim.v and the SPICE netlist. HSIM will skip simulating the SPICE subcircuits specified in digital_cell or digital_cell_inst commands.

The following example presents a simple inverter chain with a SPICE netlist on top and two leaf inverters partitioned to Verilog. Sample files for include the following:■ cosim.v: Verilog top module that instantiates two Verilog inverters. This

digital interface file is automatically generated by HSIM.■ test.spi: SPICE top netlist of an inverter chain.■ inv.spi: SPICE netlist for an inverter.■ invd.spi: SPICE netlist of the inverter to be partitioned to Verilog.■ buf.spi: A SPICE inverter chain.■ invd.v: A Verilog inverter module.



====================== File: cosim.v ======================‘timescale 1ns / 10psmodule top;

wire w1; // x1.n1wire \x1.n1 = w1;wire w2; // out1wire \out1 = w2;wire w3; // x3.n1wire \x3.n1 = w3;wire w4; // outwire \out = w4;// Instance sectioninvd \x1.x2 (w1, w2);invd \x3.x2 (w3, w4);// interface nodesinitial begin

$nsda_a2d_node(w1, "x1.n1");$nsda_d2a_node(w2, "out1");$nsda_a2d_node(w3, "x3.n1");$nsda_d2a_node(w4, "out");

endinitial $nsda_module(1);// By default, spiceflow mixed-signal simulation

will use .tran time // for the simulation time// To specify simulation time from verilog, please

add// command "spice_finish 0"// in the cosim config file// initial begin// #100 $finish;// end

endmodule====================== File: test.spi ======================*.param VDDVAL=3v* global nodes.global vdd vss gnd* suppliesvvdd vdd 0 dc VDDVALvgnd gnd 0 dc 0v* top level netlistx1 in out1 bufx2 out1 out2 invx3 out2 out bufx4 out dummy inv.inc models


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationSpectre/Verilog Mixed-Signal Simulation Running Under the Virtuoso Analog Design Environment

.inc inv.spi

.inc invd.spi

.inc buf.spivin in 0 pwl 0n 0v 1n 0v 1.1n 3v 6n 3v 6.2n 0v r.print v(*).tran 0.1n 100n.end=========== File: inv.spi =============.subckt inv a zm1 z a vdd vdd p l=0.5u w=5u as=1.0e-10 ad=1.0e-10 ps=0 pd=0m2 z a 0 0 n l=0.5u w=3u as=1.0e-10 ad=1.0e-10 ps=0 pd=0.ends=========== File: invd.spi ============.subckt invd a zm1 z a vdd vdd p l=0.5u w=5u as=1.0e-10 ad=1.0e-10 ps=0 pd=0m2 z a 0 0 n l=0.5u w=3u as=1.0e-10 ad=1.0e-10 ps=0 pd=0.ends=========== File buf.spi ==============.subckt buf in outx1 in n1 invx2 n1 out invd.ends buf============ File: invd.v ============`timescale 1ns/10psmodule invd (a, z);

input a;output z;assign z =~a;

endmodule

Note: To simulate a VHDL block in SPICE on the top flow, create a Verilog wrapper for the VHDL entity with the same port definition. In the new Verilog module, instantiate the VHDL entity.

Spectre/Verilog Mixed-Signal Simulation Running Under the Virtuoso Analog Design Environment

The Virtuoso Analog Design Environment provides the mixed-signal simulation capability for Spectre® and Verilog®. The HSIM and NC-Verilog mixed-signal simulation are integrated into the Virtuoso Analog Design Environment GUI based on the Spectre and Verilog netlists generated by Virtuoso.


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationDonut Partitioning with Verilog as the Top Instance (V-S-V)

The procedure to run batch mode in HSIM and NC-Verilog mixed-signal simulation with netlists generated by Virtuoso Analog Design Environment is as follows:

1. Generate Spectre and Verilog netlists: In the Analog Artist window, select spectreVerilog as the simulator. Select design and then generate netlists.

2. Run spectreVerilog mixed-signal simulation to generate the vmx run script, runSimulation, in the project directory. Stop spectreVerilog mixed-signal simulation after runSimulation is created.

3. From the project directory, run HSIM mixed-signal simulation by using runnsdavmx command with the vmx run script as an input argument as shown in the following syntax example:

% runnsdavmx runSimulation [options]

runnsdavmx options include:

• -include <hsim_netlist_file>

• -config <cosim_config_file>

• -prefix <hsim_prefix>: (default) hsim.

• -outdir <output_directory>: (default) spectre -raw option.

• -vsrcd2a <0|1>: (default is 0) This option is used to set the D2A input as a voltage source.

• -xl: This option is used to invoke Verilog-XL for mixed-signal simulation.

• -help

Donut Partitioning with Verilog as the Top Instance (V-S-V)

Using Verilog-on-Top PartitioningIn the V-S-V partitioning flow, the top instance is in Verilog and some modules will be simulated in HSIM. Within the modules to be simulated in HSIM, submodules can be partitioned to Verilog.



To use donut partition with Verilog on top, perform the following steps.

1. Use the analog_cell statements specify analog/digital partitioning. The syntax for analog_cell is:

analog_cell <cell name> -vmod <verilog module name>...

where <cell name> specifies the module to be simulated in HSIM and -vmod <verilog module name> specifies the module under <cell name> that remains in Verilog.

Any number of module names can be specified by adding additional -vmod <verilog module name> parameters. Refer to analog_cell on page 244 for additional information.

2. Run the simulation as normal Verilog netlist-on-top flow. The first run will exit before simulation time 0, generating a .cs and file for each donut cell.

3. Include the .cs files in Verilog compilation and run the simulation. The modules will be partitioned and simulated as specified in the analog_cell command.

Note: The cosim view file extension (.cs) is optional and can be specified in the analog_cell command.

Figure 25 and Example show donut partitioning with a Verilog top. The mixed-signal simulation configuration file should contain the analog_cell command.



Figure 25 Verilog Top Mixed-Signal Simulation Working in Donut Partitioning

============= cosim.cfg =============set_args spice/test.spianalog_cell -ext cs -dir . hsimmod -vmod invd -vmod invd3analog_cell -ext cs -dir . hsimmod_2 -vmod invd2 -vmod invd3analog_cell -ext cs -dir . pure_hsimmod

In the configuration file shown in Figure 25 the syntax is as follows:■ hsimmod, hsimmod_2, and pure_hsimmod: Modules simulated in HSIM.■ invd, invd2, and invd3: Submodules simulated in Verilog.■ -vmod: A global option. For example, if -vmod invd3 is present only in the

hsimmod command line, all instances of invd3 will be in Verilog, including those in hsimmod_2.

inv invinvd3invd invd inv invd3

inv invd3invd2 inv invd3

invdinv inv

·

·

hsimmod

hsimmod_2

pure_hsimmod vlogmod

bufferbuffer

buffer buffer

Verilog Top



First Run Example% ncvlog verilog/top.v verilog/invd.v % ncelab -loadvpi libvpihsim.so:nsda_vpi_startup -access \ +rwc -LIBNAME cosim_lib cosim_lib.top -snapshot \ cosim_lib.top:cosim% ncsim -loadvpi libvpihsim.so:nsda_vpi_startup \ +nsda+”cosim.cfg” cosim_lib.top:cosim

After first run, the following files are generated in the specified “.” output directory. In this example, it is the current directory:■ hsimmod.cs■ hsimmod_2.cs■ pure_hsimmod.cs

Second Run Example% ncvlog verilog/top.v verilog/invd.v hsimmod.cs \ hsimmod_2.cs pure_hsimmod.cs% ncelab -loadvpi libvpihsim.so:nsda_vpi_startup -access \ +rwc -LIBNAME cosim_lib cosim_lib.top -SNAPSHOT \ cosim_lib.top:cosim% ncsim -loadvpi libvpihsim.so:nsda_vpi_startup \ +nsda+”cosim.cfg” cosim_lib.top:cosim



Verilog and SPICE Files:============= top.v =============`timescale 1ns/10psmodule top;

reg vlog_drv;wire h_in_1;wire h_out_1;wire h_out_2;wire h_out_3;wire v_out;

invd inv_vtop(vlog_drv, h_in_1);hsimmod h_mod_1(h_in_1, h_out_1);hsimmod_2 h_mod_2(h_out_1, h_out_2);pure_hsimmod h_mod_3(h_out_2, h_out_3);vlogmod v_mod(h_out_3, v_out);

initial begin#0 vlog_drv = 1'bz;#10 vlog_drv = 1'b1;#10 vlog_drv = 1'b0;#10 vlog_drv = 1'b1;#10 vlog_drv = 1'b0;#10 $finish;end

endmodule

module vlogmod (vmod_in, vmod_out);input vmod_in;output vmod_out;invd inverter(vmod_in, vmod_out);

endmodule

module hsimmod (in, out);input in;output out;wire out0, out1, out2;invd inst_invd(in, out0);buffer inst_buf1(out0, out1);inv nst_inv(out1, out2);buffer inst_buf2(out2, out);

endmodule

module hsimmod_2 (in, out);input in;output out;wire out0, out1;invd2 inst_invd2(in, out0);



buffer inst_buf1(out0, out1);buffer inst_buf2(out1, out);

endmodule

module pure_hsimmod (in, out);input in;output out;

endmodule

============= invd.v =============`timescale 1ns/10ps

module invd (a, z);input a;output z;

assign z =~a;always @(a)$display(“%t invd : z = %v”, $time, z);

endmodule

module invd2 (a, z);input a;output z;

assign z =~a;always @(a)$display”%t invd2: z = %v”, $time, z);

endmodule

module invd3 (a, z);input a;output z;

assign z =~a;always @(a)$display(“%t invd3: z = %v”, $time, z);

endmodule

module inv (a, z);input a;output z;

assign z =~a;always @(a)v$display(“%t inv : z = %v”, $time, z);

endmodule

module buffer (in, out);input in;output out;wire n1;



inv inst_inv(in, n1);invd3 inst_invd(n1, out);

endmodule

============= test.spi =============.param VDDVAL=3v

* global nodes.global vdd vss gnd

* suppliesvvdd vdd 0 dc VDDVALvgnd gnd 0 dc 0v

.inc models

.inc inv.spi

.inc invd.spi

.inc buf.spi

.subckt hsimmod in outx0 in out0 invdx1 out0 out1 bufferx2 out1 out2 invx3 out2 out buffer.ends

.subckt hsimmod_2 in outx0 in out0 invd2x1 out0 out1 bufferx3 out1 out buffer.ends

.subckt pure_hsimmod in outx4 in out0 invx5 out0 out inv.ends

vin in 0 pwl 0n 0v 1n 0v 1.1n 3v 6n 3v 6.2n 0v .print v(*).tran 0.1n 10n

.end

============= inv.spi =============.subckt inv a zm1 z a vdd vdd p l=0.5u w=5u as=1.0e-10 ad=1.0e-10 ps=0 pd=0 m2 z a 0 0 n l=0.5u w=3u as=1.0e-10 ad=1.0e-10 ps=0 pd=0


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationDonut Partitioning with SPICE as the Top Instance (S-V-S)

.ends

============= invd.spi =============.subckt invd a zm1 z a vdd vdd p l=0.5u w=5u as=1.0e-10 ad=1.0e-10 ps=0 pd=0 m2 z a 0 0 n l=0.5u w=3u as=1.0e-10 ad=1.0e-10 ps=0 pd=0 .ends

.subckt invd2 a zm1 z a vdd vdd p l=1.0u w=10u as=1.0e-10 ad=1.0e-10 ps=0 pd=0m2 z a 0 0 n l=1.0u w=6u as=1.0e-10 ad=1.0e-10 ps=0 pd=0.ends

.subckt invd3 a zm1 z a vdd vdd p l=1.0u w=10u as=1.0e-10 ad=1.0e-10 ps=0 pd=0m2 z a 0 0 n l=1.0u w=6u as=1.0e-10 ad=1.0e-10 ps=0 pd=0.ends

============= buf.spi =============.subckt buffer in outx1 in n1 invx2 n1 out invd3.ends buffer

Donut Partitioning with SPICE as the Top Instance (S-V-S)

Using SPICE-on-Top PartitioningIn the S-V-S partitioning flow, the top instance is in SPICE and Verilog instances are instantiated from the SPICE netlist. This is similar to the normal SPICE netlist-on-top flow. Within the Verilog module, sub blocks can be simulated in HSIM. The Verilog module containing analog cells is similar to the top Verilog module in the normal standalone Verilog netlist-on-top flow.

To use SPICE-on-top donut partitioning, perform the following steps:

1. Specify the cosim view of the sub block in the Verilog module to be simulated in HSIM. This is similar to the Verilog netlist-on-top flow where the hdl.var file should contain the following syntax specifying cosim view:

DEFINE VIEW_MAP (.cs => cosim )



2. Replace the module body of the sub block in the Verilog module to be simulated in HSIM with the following syntax line:


3. Specify the following in the mixed-signal simulation config file:

set_args spice/test.spidigital_cell bufferverilog_file verilog/buf.v

where buffer is the Verilog module name, and verilog/buf.v is the Verilog file name.

4. Run HSIM with the configuration file. HSIM stops simulation after generating cosim.v as shown in the following example:

% hsim -cscfg cosim.cfg

Note: Once cosim.v is generated, Step 3 can be skipped in future mixed-signal simulation runs if analog/digital partitioning and the Verilog port analog/digital interface definitions remain unchanged.

5. The Verilog compiler is used to compile cosim.v together with other Verilog source files.

6. Start mixed-signal simulation from the top Verilog module defined in cosim.v and the SPICE netlist. HSIM will skip simulating the SPICE subcircuits specified in digital_cell commands while partitioning the sub-block specified in Step 2 into HSIM.

Figure 26 is an example of donut partitioning with a SPICE top. Within the SPICE top, the buffer is partitioned to Verilog while one of its sub blocks, inva, is partitioned to be simulated in HSIM.

Figure 26 SPICE Top Mixed-Signal Simulation Working in Donut Partitioning

SPICE top

buffer

invainvd· ·



First Run Example% hsim -cscfg cosim.cfg

Second Run Example% ncvlog verilog/cosim.v verilog/buf.v verilog/gate.cs

% ncelab -loadvpi libvpihsim.so:nsda_vpi_startup -access \ +rwc -LIBNAME cosim_lib cosim_lib.top -SNAPSHOT \ cosim_lib.top:cosim

% ncsim -loadvpi libvpihsim.so:nsda_vpi_startup \ +nsda+”cosim.cfg” cosim_lib.top:cosim



Verilog and SPICE Files============= test.spi =============.param VDDVAL=3v

* global nodes.global vdd vss gnd

* suppliesvvdd vdd 0 dc VDDVALvgnd gnd 0 dc 0v

* top level netlistx1 in out1 buffer

.inc models

.inc inva.spi

.inc invd.spi

.inc buf.spi

vin in 0 pwl 0n 0v 1n 0v 1.1n 3v 6n 3v 6.2n 0v.print v(*).tran 0.1n 10n

.end

============= inva.spi =============.subckt inva a zm1 z a vdd vdd p l=0.5u w=5u as=1.0e-10 ad=1.0e-10 ps=0 pd=0m2 z a 0 0 n l=0.5u w=3u as=1.0e-10 ad=1.0e-10 ps=0 pd=0.ends

============= invd.spi =============.subckt invd d_a d_zm1 d_z d_a vdd vdd p l=0.5u w=5u as=1.0e-10 ad=1.0e-10 ps=0 pd=0m2 d_z d_a 0 0 n l=0.5u w=3u as=1.0e-10 ad=1.0e-10 ps=0 pd=0.ends

============= buf.spi =============.subckt buffer in outx1 in n invdx2 n out inva.ends buffer

============= buf.v =============`timescale 1ns/10ps

module buffer (in, out);input in;


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationSave-Restart in Mixed-Signal Simulation

output out;wire n;

invd inst_invd (in, n);inva inst_inva(n, out);endmodule

module invd (d_a, d_z);input d_a;output d_z;

assign d_z = ~d_a;always @ (d_a) $display(“%t invd : d_z = %v”, $time, d_z);

endmodule

============= gate.cs =============`timescale 1ns/10ps

module inva (a, z);input a;output z;

endmodule

Save-Restart in Mixed-Signal Simulation

Mixed-Signal simulation allows you to save the complete simulation state. Simulation can be restarted at a later time by loading the simulation state and continued from where it was saved. The simulation state is saved to a Verilog snapshot and an HSIM save file, hsim.iic.<time>. You can restart the simulation by invoking the Verilog snapshot.

To save a simulation state, you can get into ncsim interactive mode and apply the save command as shown in the following example:

ncsim> run -cleanncsim> save <snapshot name>

To restart the simulation, use ncsim command with the saved snapshot as shown in the following example:

% ncsim <snapshot name>

Restart from within ncsim interactive mode is not supported.


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationConfiguration File Commands

Appending a Waveform in Mixed-Signal SimulationMixed-signal simulation allows waveforms to be appended to fsdb or wdf files using the appropriate syntax as follows:

ncsim +restart+"<-fsdb fsdb_filename>" <snapshot name>ncsim +restart+"<-wdf wdf_filename>" <snapshot name>

In the following command example, a new waveform will be appended to hsim_save.fsdb:

ncsim +restart+"-fsdb hsim_save.fsdb" <snapshot name>

Configuration File Commands

This section lists the configuration file commands used in Verilog/VHDL/HSIM mixed-signal simulation.

The value sets of some common configuration command arguments are as follows:

<bool>

0, 1

<positive number>

1, 2, 3, etc.

<double>

Floating point number

<time>

Floating point number plus time unit. For example, 100p and 1n stand for 100 pico seconds and 1 nano second, respectively.

<file>

File name

analog_cellGenerates Verilog module templates containing the $nsda_module() statement for analog partitions in the Verilog as the top instance flow.



Syntaxanalog_cell [-ext <file name extension>] [-dir <directory>]

<cell 1> <cell 2> -vmod <verilog sub-module name>...

Arguments-ext

Specifies file name extension for the generated Verilog module templates. The default file name extension is cs.

-dir

Specifies the directory to put the generated Verilog module template. The default directory is the current working directory.

cell name

Can be a wildcard.

-vmod

Specifies the submodule that remains in Verilog. Do not use wild cards.

Note: When using the -vmod option, only one cell within an analog_cell command may be used.

DescriptionThe analog_cell command generates Verilog module templates containing the $nsda_module() statement for analog partitions in the Verilog as the top instance flow. If the design module of an analog partition does not exist in the design library, mixed-signal simulation stops after the template is generated. Then this new file must be compiled in order to start mixed-signal simulation. If the design module of an analog partition already exists in the design library, analog_cell will not generate the module template.

auto_vsrc_warningIssues warning message if conflict exists between automatically detected voltage level and voltage level set by set_port_prop command.

Syntaxauto_vrsc_warning <bool>

DescriptionDefault for <bool> is 0. When set to 1, a warning message is issued if a conflict between an automatically detected voltage level and a voltage level set



by the set_port_prop configuration command occurs. Refer to Automatic Voltage Level Detection on page 259 for information regarding the rules for setting automatic voltage detection levels.

correct_netlistSyntaxcorrect_netlist <bool>

DescriptionDefault for <bool> is 1. If this option is on, and:■ Verilog module has more ports than subcircuit ports, it will drop port a

connection which is found as a global node, i.e. vdd, vss.■ Subcircuit has more ports than inst module ports, it will create dummy node

to let simulation go on.

define_print_variableDefines a print variable used as a reference voltage in the set_port_prop command.

Syntaxdefine_print_variable <print variable name> = <expression>

DescriptionThis command defines a print variable used as a reference voltage in the set_port_prop command. The print variable will be added to nsda_cosim.sp netlist file with SPICE .print statement.

Note: The syntax for the print variable in define_print_variable is identical to the .print statement syntax.

define_strengthDefines a strength table with resistances mapped to Verilog seven strength levels.



Syntaxdefine_strength <strength table name> [<double>] [-<strength

option> <double>] [-<strength option> <double>] ...

DescriptionThis command defines a strength table with resistances mapped to Verilog seven strength levels.

Each -<strength option> is used to map to the corresponding Verilog strength level and can be any of the following:■ -supply■ -strong■ -pull■ -weak■ -large■ -medium■ -small

The value inserted after -<strength option> is a strength resistor’s resistance. If a value does not have an associated -<strength option>, it will be set as the default value for the remaining strength levels not specified using the -<strength option>.

<strength table name> is used in the -strength port property of the set_port_prop command for strength resolution at inout ports. Verilog inputs will be applied through the resistor with respect to the Verilog strength level and HSIM resolves contributions of both the Verilog- and SPICE-sides in order to obtain the final bi-directional net value.

digital_cellSpecifies the SPICE subcircuit to be partitioned to Verilog.

Syntaxdigital_cell <sub-circuit name>

DescriptionIn SPICE flow, specifies the SPICE subcircuit to be partitioned to Verilog.



digital_cell_instSpecifies the SPICE instance to be partitioned to Verilog.

Syntaxdigital_cell_inst <SPICE instance name>

DescriptionIn SPICE flow, specifies the SPICE instance to be partitioned to Verilog.

dump_interfaceProduces a report file showing the mapping result between analog and digital ports.

Syntaxdump_interface [0|1|2]

Arguments0

Do not dump the .csintf file.

1

Generates the .csintf that lists all interface nodes and properties.

2

(Default) Generates the .csintf at the end of mixed-signal simulation that lists all interface nodes, properties, and the number of interface events for each interface node.

DescriptionThis command produces a report file showing the mapping result between analog and digital ports.

ExampleHere is a .csintf file example.

-------------------------------------------a2d main.out2 xmain.out2 node=out2 vhi=2.1 vlo=0.9d2a main.out1 xmain.out1 node=out1 logichv=3 logiclv=0 rise=1000 fall=1000 rm_glitch=1000-------------------------------------------



■ Column two lists the verilog ports.■ Column three lists the HSIM ports.

dump_port_propDumps port properties associated with matching ports.

Syntaxdump_port_prop <file>

DescriptionDumps out what port properties have been associated with the matching ports.

dump_settingDumps configuration command settings to HSIM log file.

Syntaxdump_setting <bool>

DescriptionDumps configuration command settings to the HSIM log file. Default for <bool> is 0.

keep_iface_fileSpecifies whether to deletes nsda_cosim.sp interface file automatically after completing simulation.

Syntaxkeep_iface_file <bool>

DescriptionMixed-signal -simulation engine generates the nsda_cosim.sp interface file for the analog blocks in analog view, and it serves as the interface media between Verilog and HSIM simulators. Turning off this flag deletes this file automatically after simulation is complete. Default for <bool> is 1.



map_subckt_nameMaps module name to correct subcircuit definition in SPICE instantiation.

Syntaxmap_subckt_name <module_name> <subckt_name>

DescriptionIf module name is different than the subcircuit name, this command will map it to the correct subcircuit definition in SPICE instantiation.

map_unfound_portMaps unfound port to the specified SPICE node name.

Syntaxmap_unfound_port [-cell <pattern>] <map_node>

<unfound_port> …

DescriptionWhen writing the interface netlist file, if a subcircuit has more ports than inst module ports, this command will map the unfound port to the specified SPICE node name.

The search priority is in a top-down order as follow:■ Exact cell name.■ Match cell pattern.■ Match unfound port list for rules without -cell argument.

report_logic_delayReports delayed logic output when the signal voltage crosses logic threshold voltage.

Syntaxreport_logic_delay <time>

Description[default] 2 ns



This command reports delayed logic output when the signal voltage crosses the logic threshold voltage, if the delayed logic output is greater than a specified time.

report_port_resistanceGenerates a report of path resistances in the hsim.csres file.

Syntaxreport_port_resistance {0|1|2}

Arguments0

no report (default)

1

Report for inout ports only.

2

Report for all interface ports.

DescriptionThis command generates a report of path resistances in the hsim.csres file. The report contains statistics of resistances of paths from interface nodes to voltage sources. The resistance values can be used as a reference to set up strength tables to map Verilog seven strength levels to resistors.

set_argsPasses the regular HSIM command line argument to HSIM.

Syntaxset_args <nsda_args> …

DescriptionThis command passes the regular HSIM command line argument to HSIM. For example: set_args test.spi asks HSIM to accept test.spi as an input netlist.



set_intr_modeSets the interactive mode.

Syntaxset_intr_mode <bool>

DescriptionBy default, Ctrl-C stops simulation in the Verilog simulator’s interactive mode. To move between the interactive modes of the Verilog simulator and HSIM, use the following commands:■ call nsda_intr_mode: Leaves the Verilog simulator’s interactive mode

and enters the HSIM interactive mode. ■ quit: Leaves the HSIM interactive mode and returns to the Verilog

simulator’s interactive mode.

If set_intr_mode is set to 1, Ctrl-C stops the simulation in HSIM’s interactive mode instead of Verilog simulator's interactive mode. HSIM interactive commands can be applied to debug the simulation. In this case, Verilog’s interactive mode can not be entered by users. Default for <bool> is 0.

set_fall_stepSpecifies the number of stop times to update signal voltages when a rising/falling slope occurs.

Syntaxset_fall_step <positive number>

DescriptionThis command specifies the number of stop times to update signal voltages when a rising/falling slope occurs. Default for <positive number> is 10.

set_port_propApplies specified properties to matched cells or instances and their ports.

Syntaxset_port_prop [-cell <pattern>|-inst <pattern>] [-port

<pattern>] <-port property1> <value1> <-port property2> <value2> … [-follow_ov_param] [-no_a2d <bool>] [-no_d2a



<bool>][-cap capacitance_value] [-res resistance_value] [-linear <bool>] [-csrc <bool>]

DescriptionThe port properties apply to the matched cells or instances and their ports.■ -cell is used for cell based port properties.■ -inst is used for instance based port properties.■ Port names match Verilog port definitions that are case sensitive.■ This specified value overrides any default value.■ If more than one rule is found for a particular property, the last rule is used.■ Without any cell or port pattern specified, the default value is used.

The options for port properties are listed below:

-alloweddv <double>

[default] HSIMALLOWEDDV

Set HSIMALLOWEDDV at the interface node.

-logichv <double> | <output variable>

[default] HSIMLOGICHV

Set port logic1 voltage.

Its value can be a double number or an output variable which is a string identifier starting with an alphabetic letter.

The output variable is defined with a .print statement to represent a voltage expression. For example:

.print logichv=par('0.7 * v(vdd)')

where logichv is the output variable and '0.7 * v(vdd)' is the voltage expression.

-logiclv <double>|<output variable>

[default] HSIMLOGICLV

Set port logic0 voltage.


-logicxv <double>|<output variable>

[default] HSIMLOGIGLV



Set port logic X voltage.


-vhi <double>|<output variable>

[default] HSIMVHTH if specified, otherwise use the following:(logichv - logiclv) * 0.7

Set port logic1 threshold voltage.


-vlo <double> <output variable>

[default] HSIMVLTH if specified, otherwise use the following:(logichv - logiclv) * 0.3

Set port logic0 threshold voltage.


-timex <time>

[default] No state X report.

Report X when the output port voltage stays between -vlo and -vhi longer than the timex time.

-slope <time>

HSIMSLOPE

Set port rising & falling time.

-rise <time>

HSIMRISE if specified, otherwise use HSIMSLOPE

Set port rising time.

-fall <time>

HSIMFALL if specified, otherwise use HSIMSLOPE.

Set port falling time.

-delay <time>

[default] 0

Set port delay. This delays the signal output to Verilog.



Only allow positive delay.

-delay1 <time>

[default] 0

Apply port delay to the rising edge only.

-delay0 <time>

[default] 0

Apply port delay to the falling edge only.

-delay_hz2st <time>

[default] 0

Apply port delay to signal changes from a Hi-Z state to a strong state.

-rm_glitch <time>

[default] -slope value

Remove glitches within <time> after Verilog input changes.

Apply to inout port.

-strength <strength name>

[default] no strength

<strength name> is a string identifier defined in define_strength.

Apply to inout port for strength resolution with the resistor specified in <strength name>.

-vsrc <bool>

[default] 0

Model input as a voltage source. It will be partitioned into a smaller block and results in a faster simulation runtime.

Only inputs without Hi-Z can use this option, otherwise the simulation may be incorrect.

-vprint <bool>

[default] 0

Insert .print statement to print voltage value.

-lprint <bool>

[default] 0



Insert .lprint statement to print voltage logic.

-follow_ov_param

Allows a user-defined expression to be dynamically evaluated along two digital-to-analog (d2a) events (as opposed to being evaluated at the final value). Because this option allows a dynamic change on the logic values of d2a converters, you can model complex voltage-controlled voltage sources, ideal level shifters, dc-dc converters, and modulated voltage sources.

-no_a2d <bool>

[default] 0

Skips the a2d interface element insertion on the specified interface node.

-no_d2a< bool>

[default] 0

Skips the d2a interface element insertion on the specified interface node.

-cap capacitance_value

[default] 0

Adds node capacitance value to the interface node. The capacitance value is in double precision and has the unit of Farad.

-res resistance_value

[default] 1

Adds node resistance value to the interface node. The resistance value is in double precision and has the unit of Ohm. This value is used only when '-linear' option is '0'.

-linear <bool>

[default] 1

Generates a linear slope for d2a interface.

-csrc <bool>

[default] 0

Model interface as constant vsrc.

set_port_prop_warningSpecifies the number of warning messages allowed before simulation stops.



Syntaxset_port_prop_warning <number> [-stop]

DescriptionWarning messages are issued when set_prop_prop command specifies mismatched ports. This command specifies the number of warning messages allowed before simulation stops. If -stop option is specified, simulation stops whenever there is any mismatched port. The default is 250 warning messages with -stop option.

set_print_progressSpecifies the time interval to output mixed-signal simulation progress.

Syntaxset_print_progress <time>

DescriptionThis command specifies the time interval to output mixed-signal simulation progress.

set_rise_stepSpecifies the number of stop times to update signal voltages when a rising/falling slope occurs.

Syntaxset_rise_step <positive number>


set_slope_stepSpecifies the number of stop times to update signal voltages when a rising/falling slope occurs.

Syntaxset_slope_step <positive number>




set_verboseSets the level of detail for output messages.

Syntaxset_verbose <level>

DescriptionThis command sets the level of detail for output messages. <level> can be none, low, high, or detail; default is high.

none

Suppresses any messages generated by the mixed-signal simulation interface except error message.

low

Writes information messages generated by the mixed-signal simulation interface.

high

Writes warning messages generated by the mixed-signal simulation interface.

detail

Writes suggestion on which D-to-A input should be defined as VSRC to speedup the simulation time and other messages.

set_verilog_supply1Defines voltage level for Verilog supply1.

Syntaxset_verilog_supply1 <double>

DescriptionThis command defines voltage level for Verilog supply1.


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationAutomatic Voltage Level Detection

set_verilog_supply0Defines voltage level for Verilog supply0.

Syntaxset_verilog_supply0 <double>

DescriptionThis command defines voltage level for Verilog supply0.

verilog_fileSpecifies Verilog source file containing Verilog module definitions for digital_cell or digital_cell_inst.

Syntaxverilog_file <Verilog source file name>

DescriptionIn SPICE flow, this command specifies Verilog source file containing Verilog module definitions for digital_cell or digital_cell_inst. verilog_file can be applied multiple time for different verilog sources.

set_args hsim_top.spset_rise_step10set_fall_step6set_port_prop-cell top -port outport1 outport2 \

outport3 -vhi 2.64 -vlo 0.66set_port_prop-cell top -port inport* \

-logichv 3.3 -logiclv 0 -slope 100ps

Automatic Voltage Level Detection

Mixed-signal simulation is able to automatically identify voltage levels at interface nodes thereby reducing the need for user intervention. The rules described in the Voltage Setting Rules section have the following precedence: Rule 1, Rule 2, and Rule 3.


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationMixed-Signal Simulation Interactive Mode

Voltage Setting Rules

Rule 1The set_port_prop configuration command provides the flexibility to over write both default and automatically detected voltages.

Rule 2Search through channel connected voltage sources. The voltage levels of the voltage sources will be applied to the interface nodes. Warning messages are given if there is any conflict between detected voltage sources and configuration commands. By default, Warning messages are suppressed. They can be turned on using the auto_vsrc_warning configuration command. A Warning message is given if the interface node is not connected to any voltage source and HSIMVDD is applied.

Rule 3HSIMVDD is used as the default voltage if Rule 1 and Rule 2 do not apply. If any channel connected voltage source is detected with a different voltage than HSIMVDD, a Warning message is issued and the detected voltage is applied.

Mixed-Signal Simulation Interactive Mode

The mixed-signal simulation interactive commands add to the command set described in the HSIM Simulation Reference Manual: Interactive Mode Debugging. The mixed-signal simulation interactive mode allows information to be obtained on both interface elements and interface activity history. It also permits watch points to be set on interface node activities to catch a specific event in the interactive debugging mode.

Mixed-signal simulation interactive commands are used with HSIM>, the HSIM interactive mode prompt. The HSIM Simulation Reference Manual: Interactive Mode Debugging provides information on how to get into the HSIM interactive mode.

To get into HSIM interactive mode from the ncsim>, the NC-Verilog interactive prompt, use the following command:

call nsda_intr_mode



To continue simulation in NC-Verilog, issue the command cont from the HSIM interactive mode prompt HSIM> and simulation will continue. If you are prompted with ncsim> after issuing the cont command at HSIM>, type run and NC-Verilog will continue.

Note: Currently only NC-Verilog is supported in mixed-signal simulation interactive debugging.

Table 16 on page 261 lists the commands used in mixed-signal simulation interactive debugging.

List Interface Nodes

cslicsli <pattern> <-a2d|-d2a|-biput>

Table 16 Mixed-Signal Simulation Interactive Mode Commands

Command Function

csli List Interface Nodes

csh Print Global Interface History in Time

csnh Print Interface Node History by Node Name

csinh Print Interface Node History by Node Index

csnph Set the Number of Entries Printed by csnh and csinh

csnw Set Watchpoint to Interface Node by Node Name

csinw Set Watchpoint to Interface Node by Node Index

csdnw Delete Watchpoint by Node Name

csdinw Delete Watchpoint by Node Index



csli lists all mixed-signal simulation interface nodes if no option is specified. A pattern can be used to search for certain names. You can choose to list a certain type of interface node by specifying -a2d, -d2a or -biput.

A typical result of csli command is shown in the following example. Note that <=> denotes bi-directional ports:

Table 17 List Interface Nodes: csli Syntax Descriptions

Parameter Description

pattern Pattern used to search for certain interface node names. Pattern matching is based on the Tool Command Language (TCL) API.

-a2d Lists only a2d (HSIM to Verilog) interface nodes.

-d2a Lists only d2a (Verilog to HSIM) interface nodes.

-biput Lists only bi-directional interface nodes.

Table 18 HSIM Example

HSIM > csli Prints all interface nodes.

HSIM > csli *addr* -d2a Prints d2a interface nodes with names matching the pattern *addr*.



HSIM > cslicosim interface nodes:---------------------------------id type node---------------------------------7 <=>a2d b[3]6 <=>a2d db[2]5 <=>a2d db[1]4 <=>a2d db[0]10 d2a pch212 d2a rd215 d2a wr27 <=>d2a db[3]3 d2a addr[2]6 <=>d2a db[2]2 d2a addr[1]5 <=>d2a db[1]1 d2a addr[0]4 <=>d2a db[0]8 d2a en2---------------------------------

Note: In this example, the bi-directional ports have both a2d and d2a interface nodes: 7 <=>a2d db[3] and 7 <=>d2a db[3].

Print Global Interface History in Time

cshcsh <number of entries (default is 10)>

csh prints the global interface activity history in chronological order. If no argument is specified, csh prints the maximum number of entries available up to a maximum of 10 entries. If the number of entries is specified, csh prints up to the specified number of entires. The maximum number of global history entries is set to 10000 by default and can be changed by the max_history command in mixed-signal simulation configuration file as follows:

max_history <max # of global history entires>


HSIM > csh Prints 10 global interface activity history entries.

HSIM > csh 20 Prints 20 global interface activity history entries.



Print Interface Node History

csnh, csinhcsnh <name>csinh <id>

csnh and csinh print the activity of a specified interface node if available. Entries for the specified node stored in the history buffer are printed in chronological order. Both a2d and d2a history will be printed if available. The maximum number of entries printed each time by csnh and csinh can be set by the command csnph. The default is 10.

The id corresponds to the id field in the output of the csli command. This id can also be used in other HSIM interactive commands.

Set the Number of Entries Printed By csnh and csinh

csnphcsnph <number of entries>

csnph reports the current setting if no argument is given. If an argument is specified, the number of entries to be printed by csnh and csinh commands are set. The number is limited between max_history and 0.


HSIM > csnh db[3] Prints activity history of interface node on db[3].

HSIM > csinh 10 Prints activity history of interface node with index 10.


HSIM > csnph Prints current csnph setting.

HSIM > csnph 20 Sets the max number of entries to be printed in each csnh and csinh call to 20.



Set Watchpoint to Interface Node

csnw, csinwcsnw <name> <-a2d|-d2a|-hz>csinw <id> <-a2d|-d2a|-hz>

csnw and csinw set a watch point to the specified interface node. If no additional option is given, any activity on the interface node will trigger the watch point and you will enter the HSIM> prompt. Use -a2d|-d2a|-hz to catch a specific type of interface activity. If no argument is given to csnw and csinw, a list of current watch points is printed. Previous watch point settings are overridden by the new setting.

Table 22 Set watch point to interface node: csnw csinw Syntax Descriptions

Parameter Description

name Interface node name to which the watchpoint is set.

id Interface node id to which the watchpoint is set.

-a2d Watch for a2d (HSIM to Verilog) activity only.

-d2a Watch for d2a (Verilog to HSIM) activity only.

-hz Watch for Hi-Z event only.


HSIM > csnw Prints the list of currently set watchpoints.

HSIM > csnw addr[2] Sets watchpoint on interface node addr[2].

HSIM > csinw 5 -hz Sets watchpoint on interface node with id 5 to watch for high-z events.

HSIM > csnw db[0] -d2a Sets watchpoint on d2a part of interface node db[0].


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationVerilog System Tasks for Mixed-Signal Simulation

Delete Watchpointcsdnw and csdinw delete the watchpoint specified by name or id, or delete all watchpoints if -a or -all option is used. If no argument is given, csdnw and csdinw print the list of currently set watchpoints.

csdnw, csdinwcsdnw <name|-a|-all>csdinw <id|-a|-all>

Verilog System Tasks for Mixed-Signal Simulation

The following system tasks are available for interactions between Verilog and SPICE. They are incorporated into Verilog source code to pass data to or retrieve data from analog blocks. System tasks should be put into the initial block of a Verilog module.

$nsda_a2d_node (net, “SPICE node name”)

Creates an A-to-D interface element between the Verilog net and SPICE node. This system task behaves like a continuous assignment from a SPICE internal node to the Verilog net.

$nsda_add_cap (net, variable)

This system task adds capacitance to the SPICE node connecting to the interface net. It requires two arguments, one Verilog net and one Verilog variable, constant, or parameter of real type. The Verilog net has to be an interface connecting to a SPICE node. The second argument specifies capacitance in Farad and represents the lumped sum capacitance of Verilog side components connecting to the SPICE node.


HSIM > csdinw Prints the list of currently set watchpoints.

HSIM > csdnw db[1] Deletes the watchpoint on db[1].

HSIM > csdinw 4 Deletes the watchpoint on node with id 4.


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationVerilog System Tasks for Mixed-Signal Simulation

$nsda_d2a_node(net, “SPICE node name”)

Creates a D-to-A interface element between the Verilog net and SPICE node. This allows Verilog to connect the net directly to a SPICE internal node, instead of going through port mapping. For example,

• initial $nsda_d2a_node (test, “xi1.xi2.sync”);

• where test is a Verilog net in the module containing this system task and xi1.xi2.sync is the hierarchical path name to identify a SPICE node.

$nsda_get_volt (net, variable)

Requires two arguments, one Verilog net and one Verilog variable of real type. The Verilog net has to be an interface connecting to a SPICE node. This system task retrieves the analog voltage of the SPICE node at current time and assigns the voltage to the variable.

$nsda_inout_node (net, "SPICE node name")

Creates one D-to-A interface element and one A-to-D interface element between the Verilog net and SPICE node. This is equivalent to one $nsda_d2a_node() and one $nsda_a2d_node() combined.

$nsda_module()

Designates the current module to be partitioned into an SPICE subcircuit. The module body should contain nothing but only one initial block of this system task.

$nsda_save_waveform(obj1 [, level1], obj2 [, level2], ...)

Allows Verilog object waveforms to be saved to the HSIM waveform file. The Verilog objects can be net, register, net bit, register bit, and module instance. The optional level argument is valid only for module instance objects and specifies all nets under the design hierarchy level. Its default value is 1. A 0 level means full hierarchy of the given instance.

$nsda_set_volt (net, variable)

Requires two arguments, one Verilog net and one Verilog variable, constant, or parameter of real type. The Verilog net has to be an interface connecting to a SPICE node. This system task assigns the value of the second argument to the SPICE node as an analog voltage at current time.


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationMixed-Signal Simulation Setup Guidelines

Mixed-Signal Simulation Setup Guidelines

There are several areas that require special attention during mixed-signal simulation setup in order to help simulation performance and avoid common mistakes.

Map Correct Port VoltagesThis is especially true for logicxv: Verilog assigns logic X value to the nets which are not initialized. For input ports from Verilog to HSIM, HSIM takes port voltages for DC initialization and simulation. It is important to map a correct analog voltage for logic X value at input ports. Some circuits require logic X to have the same analog voltage as logic0, while some circuits require it to be the middle voltage between logic1 and 0.

Define Clear Port DirectionIf a port direction is known to be unidirectional for the SPICE block, its corresponding mixed-signal simulation view Verilog module should clearly define an input or output port rather than an inout port. This will reduce the number of interface elements and improve simulation performance.

Set Input Ports As Voltage Sources If PossibleIf the input from Verilog to HSIM will never become HiZ, this input can be treated as a voltage source to the SPICE block. This will improve HSIM simulation. Use the -vsrc option of set_port_prop configuration command to set ports as voltage sources.

Define SPICE Netlist Bus NotationUsually, Verilog defines vector nets at ports. The SPICE netlist only has bit level port definition. A bus notation is required to map each individual bit level port back to Verilog vector ports. The default bus notation for SPICE netlist is square brackets []. Other bus notations can be set by using HSIMBUSDELIMITER command in the SPICE netlist as shown in the following example:


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationPartitioning Guidelines

.param HSIMBUSDELIMITER=<>

.param HSIMBUSDELIMITER=_

Handle Bi-Directional PortsIf the analog partition presents Hi-Z states to interface ports, use .param HSIMHZ=1 in the SPICE deck.

If strength fighting occurs at bi-directional interface ports, use the -strength option for set_port_prop and define_strength to map verilog strengths to the proper resistance values.

Partitioning Guidelines

Partition Boundary with Clear Digital BehaviorIn mixed-signal simulation, digital and analog signals are presented on two sides of a partition boundary. In order to reduce the loss of accuracy and to maintain correct functionality, the boundary signals should have clear digital behavior and should not be voltage sensitive.

Avoid Partitioning at Timing Sensitive SignalsThe signal conversion from analog to digital depends on high and low threshold voltages. If the circuit design is timing sensitive at the interface signals, functionality errors may occur due to timing shift by a slight change in threshold voltages. There should be certain timing error margin for the interface signals. Also, the timing representation in Verilog may not match the exact timing in SPICE. It is recommended not to partition at timing sensitive signals.

Avoid Reach-in Signals in Analog PartitionsVerilog elaboration will fail when the Verilog netlist contains a reach-in signal partitioned into an analog partition whose internal objects are not visible to Verilog elaborator.


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationStrength Table Setup Guidelines

Reach-in signals can be replaced with a new Verilog net using either of the following system tasks; depending on the direction of the original reach-in signal.

$nsda_a2d_node()$nsda_d2a_node(),

The system task associates the new Verilog net to the SPICE node that is equivalent to the original reach-in signal.

Avoid Partitioning at Bi-directional Signals Involved Strength Fighting and Pass SwitchesBi-directional interface signals are supported. However, the signal value set by VPI at one terminal of a pass switch (the primitive gate tranif0 and tranif1) cannot be propagated to the other end. A Verilog n-MOSFET gate is added in between the pass switch and the interface signal to allow signal value passing through the pass switch. If the bi-directional interface signals involve strength fighting, the final signal value is resolved by HSIM. A resistor is added to incorporate the contribution of the digital signal in resolving the final value. Special attention is required to map the resistance value, specified by set_port_prop configuration command, to its corresponding digital strength.

Avoid Fine Grain PartitioningFine granularity partitioning creates many small analog and digital blocks and introduces many interface signals which decrease mixed-signal simulation performance. Frequent and unnecessary analog/digital signal conversion may also introduce functionality errors.

Strength Table Setup Guidelines

Multiple drivers can drive the same net using different values. The final value of the net depends on the strengths of the drivers. Strength fighting may occur at bi-directional nets or inout ports of digital/analog partitions. Verilog defines seven strength levels and rules to resolve strength fights. HSIM models Verilog strength as a resistor. The Verilog signal input is applied through the resistor



and HSIM resolves both Verilog and SPICE contributions to obtain the final values of the bi-directional nets.

A strength table defines a set of resistance strength values that are mapped to Verilog seven strength levels for use in strength resolution at inout ports. If Verilog-side signals always win during strength fighting or there is no strength fighting at inout ports, it is not necessary to introduce strength resistors.

The define_strength configuration command specifies the resistances of strength resistors to map to the Verilog seven strength levels. The syntax is shown in the following example.

define_strength strength_tbl -supply 10 -strong 100 \-pull 1000 -large 10000 -weak 100000 \-medium 1000000 -small 10000000

The resistance presents a Verilog strength relative to a lumped sum SPICE impedance at the bi-directional net. The SPICE impedance depends on the transistor model, technology, and process used in the design. Therefore, a default strength table will not satisfy the requirement because the relative resistances are both design-dependent and port-dependent.

Data flow direction must be available in order to select proper resistances. If the Verilog-side signal wins the strength fight, the strength resistor’s resistance must be significantly smaller than SPICE-side impedance. Conversely, if the SPICE-side signal wins the strength fight, the resistance of the strength resistor must be significantly larger than the SPICE-side impedance. The following two examples show how this works:

ExamplesAssume the following for this example:■ Strength fighting occurs at port Y■ Simulation time is 10 ns■ The Verilog-side presents a weak logic0■ The SPICE-side has 3V and logic1 before strength resolution■ Data flows from the SPICE- to the Verilog-side at the 10 ns mark indicating

that the SPICE-side driving strength is stronger.

In this example, the final value at port Y should be logic1.

If the impedance at the SPICE-side is 1000 Ohms, then the proper resistance of the strength resistor can be 10000 Ohms; in which case HSIM does the following:



■ Resolves that the voltage at port Y to be 2.8V ■ Sets port Y to logic1

In this case, the weak Verilog strength is mapped to a 1000 Ohm strength resistor. ■ Later, at simulation time 20 ns:■ The Verilog-side presents a strong logic0 at port Y■ SPICE-side voltage is 3V with a driving impedance of 1000 Ohms before

strength resolution■ Data flows from the Verilog- to SPICE-side■ The final value at port Y should be logic0

The proper resistance of the strength resistor may be 100 Ohms for HSIM to resolve the strength fight and produce a final value of 0.5V and a logic0. Therefore, strong Verilog strength is mapped to a 100 Ohm strength resistor.

The above two examples show why it is important to know the data flow direction in order to select proper resistance values. Designers specify strength resolution as follows:■ Full Verilog netlist: Data flow direction is specified by setting different verilog

strength levels that drive the same net. ■ Full SPICE netlist: Data flow direction is determined by different size

transistors connecting to the same net.■ Mixed-signal Simulation netlist: Data flow information is not available. Signal

strength tables are constructed from information provided by designers to determine data flow directions.

The report_port_resistance configuration command creates a report that details the SPICE-side resistance or impedance from interface nodes to voltage sources. Strength tables can be constructed from the data flow directions in a circuit design and the SPICE-side path resistance.

Note: The resistance difference between two consecutive Verilog strength levels can be one (1) order of magnitude such that if 100 Ohms is described a strong level then the pull level can be 1,000 Ohms.


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationMixed-Signal Simulation with ModelSim

Mixed-Signal Simulation with ModelSim

Verilog/VHDL is used with HSIM to simulate mixed Verilog/VHDL and SPICE-based designs that contain both digital and analog partitions. This is accomplished by using the Verilog/VHDL simulator to simulate the digital netlist; while HSIM simulates the analog SPICE netlist. When complete, analog and/or digital simulation results are available for designers to verify their designs.

In addition to Cadence NCSIM, mixed-signal simulation with Mentor Graphics ModelSim is now supported.

ModelSim/HSIM IntegrationThe libvpihsim.so mixed-signal simulation library supports ModelSim integration with either of the following:■ Stand-alone ModelSim■ In the ADMS environment

In both Verilog and SPICE design partitioning flows, most mixed-signal simulation features and limitations for NC-Verilog/VHDL are applicable to ModelSim. Since the cell view and Verilog configurations for instance based instantiation are not available in ModelSim, users need to modify the original Verilog source files to add the $nsda_module() system task in order to designate analog partitions.

Note: save-restart is not supported in ModelSim/HSIM mixed-signal simulation.

Running ModelSim/HSIM Mixed-Signal Simulation with Stand-alone ModelSimUse the ModelSim commands shown in the following steps to run ModelSim in a stand-alone ModelSim environment.

1. Create a design library using the following syntax. In this example, the design library will be named work.

% vlib work


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationHSIM Features Not Supported by Mixed-Signal Simulation

2. Compile the Verilog source code using the following syntax:

% vlog top.v

3. Use the -pli command line option to link libvpihsim.so into ModelSim for simulation using the following syntax. In this example, top is the name of the top design module.

% vsim -c -pli libvpihsim.so +nsda+cosim.cfg top

To enter HSIM interactive mode from ModelSim, press "Ctrl-C" during simulation to pause at ModelSim interactive prompt, and use the command:

% vsim(paused) nsda_intr_mode

Running ModelSim/HSIM Mixed-Signal Simulation Under the ADMS EnvironmentUse the ADMS commands shown the following steps to run ModelSim/HSIM mixed-signal simulation under the ADMS environment.

1. Create a design library using the following syntax. In this example, the design library will be named work.

% valib work

2. Compile the Verilog source code using the following ModelSim syntax. In this example, -ms invokes the ModelSim compiler:

% valog top.v -ms

3. Invoke ModelSim to run the simulation using the following syntax. In this example, top is the name of the top design module.

% vasim top -ms -pli libvpihsim.so

Note: The -c command line option does not work for mixed-signal simulation in batch mode.

HSIM Features Not Supported by Mixed-Signal Simulation

Mixed-signal simulation is designed for transient analysis. The following HSIM features and parameters are not supported:


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationHSIM Features Not Supported by Mixed-Signal Simulation

■ DC Analysis■ AC Analysis■ Monte Carlo Analysis■ Parameter Sweeping Analysis


Appendix C: Verilog/VHDL/HSIM VPI Mixed-Signal SimulationReferences

References

[1] NC-Verilog/VHDL is a functional verification tool from Cadence Design Systems, Inc.

[2] Verilog-XL is functional verification tool from Cadence Design Systems, Inc.


D

DMixed-Signal Simulation for Three-DimensionalIntegrated Circuits (3D-IC)

The 3D-IC methodology allows the integration of different chips in a mixed-signal flow with different technologies, in the same netlist, without modifying the netlist, models, or parameters of the individual chips.

Introduction to the 3D-IC Mixed-Signal Flow

The 3D-IC methodology lets you:■ Keep separate scopes for the different chips.■ Have devices, models and parameters with same names in different chips.■ Define global nets and environmental parameters locally for each chip.■ Maintain separate corners and parametric controls for different chips.

How 3D-IC Works in the Standalone CustomSim Tool

For details about how the 3D-IC technology works, see the CustomSim User Guide.

Basic Mixed-Signal 3D-IC Implementation

A netlist containing a 3D-IC can be included in a Verilog-Top mixed-signal simulation as long as the interface between HDL and SPICE does not cross the 3D-IC domain boundary. For example, in Figure 27, the instantiation in Verilog


Appendix D: Mixed-Signal Simulation for Three-Dimensional Integrated Circuits (3D-IC)Enhanced Mixed-Signal 3D-IC Implementation

is made for the myspice subcircuit, which is defined outside of the scope of the 3D-IC module.

Figure 27 SPICE Subcircuit Instantiated in Verilog

Enhanced Mixed-Signal 3D-IC Implementation

The enhanced mixed-signal 3D-IC implementation allows:■ Including SPICE cells with a 3D-IC scope in a mixed-signal simulation

without modification of the netlist.■ Cell based references to be distinguishable for their 3D-IC scope using

mixed-signal commands.

For this implementation, replacements involving 3D-IC scope require the cell name, 3D-IC scope, and instance.



Specifying a Verilog-Top with SPICE LeafFigure 28 show a Verilog-Top design with SPICE leaf instantiations.

Figure 28 Verilog-top with SPICE Leaf Instantiations

You can select a SPICE subcircuit with a 3D-IC scope using the use_spice command. To use this command to instantiate a 3D-IC SPICE cell, you must specify the cell, icmodule, and instance. The replacement is instance-based. For example:

use_spice -cell core -icmodule cpumod -inst top.x1;

You can replace any cell with a SPICE view with a 3D-IC scope:

use_spice -cell and_gt -icmodule cpumod -inst top.x4.x5.x1;use_spice -cell dram -icmodule memmod -inst top.x2;use_spice -cell dram -icmodule memmod2 -inst top.x3;



Cell-Based Mixed-Signal Commands Affected by 3D-IC ScopeThe a2d, d2a, e2r, and r2e commands at the interface to a 3D-IC module can be applied by node. For example:

d2a node=top.il.n1

Port-related commands port_dir and port_connect require that all cells that have the same name, but different 3D-IC scope, and must also have the same port list. Port-related commands affect all cells of that name without distinction. For example:

port_dir -cell cellname (input a; output y);port_connect cellname (vdd => top.vdd);

If two cells with the same name and different 3D-IC scope have different number of ports or different port names, an error is generated because this distinction is not yet supported.

Support for Verilog-AVerilog-A instantiated by .hdl within the SPICE block is supported.

Wildcard SupportInstance based wildcards that refer to blocks inside a 3D-IC module are allowed. For example: top.x1.ou*.

Standalone 3D-IC Global SuppliesAs in standalone 3D-IC, global supplies may be defined independently through an instance based connection. See Figure 29.



Figure 29 Standalone Global Supplies Example

Direct Supply Connections Through the Mixed-signal Interface Figure 30 shows direct supply connections.



Figure 30 Direct Supply Connections

Node based connections from Verilog are supported, allowing for separate supplies:

D2A powernet … node=top.vdd1 vih=1.0D2A powernet … node=top.vdd2 vih=1.2

If a cell/port based reference is made, it is applied to all cells of that name, regardless of 3D-IC scope. For example:

D2A powernet -cell cellname -port n1


E

EResolving Inconsistencies Between Digital andAnalog Hierarchical Paths

This appendix describes a technique to reuse a single testbench with multiple design hierarchies.

Reusing a Single Testbench for Multiple Design Hierarchies

Verilog or VHDL HDL testbenches that instantiate mixed-language HDL and SPICE design hierarchies, including duplicate module or entity and subcircuit cell views, are interchanged frequently during the design verification process. The HDL testbenches need to be consistent during the process.

A single testbench that can be re-used for multiple design hierarchies is required.

You can use a new mixed-signal command, resolve_x_inst_prefix, so that HDL testbenches do not need to be changed when multiple cell views are changed, and HDL testbenches using cross-module references for digital targets as well as UCLI commands for digital targets remain consistent if the hierarchical paths change to ones that contain SPICE "X" prefixes.

PrerequisitesDesign hierarchies instantiated in an HDL testbench can be of different formats, such as mixed SPICE/HDL, but the hierarchies must be consistent using the same module/entity or SPICE instances and cell names.


Appendix E: Resolving Inconsistencies Between Digital and Analog Hierarchical PathsReusing a Single Testbench for Multiple Design Hierarchies

Recommended Steps1. Develop an HDL testbench that contains a cross-module reference to a

digital target for a complete HDL, digital only, design hierarchy.

2. Ensure that the testbench and the cross module reference are functional.

3. Change the design cell view from HDL to SPICE.

4. Ensure that the HDL testbench cross-module reference is no longer functional, since the SPICE instances in the design are prefixed with "X".

5. Use the new mixed-signal command resolve_x_prefix in the mixed-signal control file (vcsAD.init) to resolve the SPICE X prefixes.

6. Ensure that the testbench is consistent and the cross-module reference is again functional.

ExampleMixed Language - Verilog/VHDL

Verilog Testbench, instantiating a Verilog dut (Device under Test), the dut instantiating VHDL components.

Three VHDL inverters inv1, inv2 and inv3, instances g1, g2 and g3 are instantiated in the Verilog Module dut:

// verilog dutmodule dut (out,clk);output out;input clk;

inv1 g1 (net1,clk); // VHDL inv2 g2 (net2,net1); // VHDLinv3 g3 (out,net2); // VHDL

endmodule

This example also has a "multiple cell view", or duplicate SPICE view, dut with the same hierarchy and instances, but with the dut now described in SPICE format, the HSPICE format to be specific:

/* SPICE dut.subckt dut out clk

xg1 net1 clk inv1 * VHDLxg2 net2 net1 inv2 * VHDLxg3 out net2 inv3 * VHDL

.ends



Note: All VHDL instances in the SPICE dut are now prefixed with "x". This is required for HSPICE and Eldo® SPICE formats (not required for Spectre® format).

The same three VHDL inverters inv1, inv2 and inv3, instances xg1, xg2 and xg3 are instantiated in the SPICE subcircuit dut as in the Verilog dut.

The Verilog testbench top instantiates the dut with an $hdl_xmr referencing a specific VHDL/instance port: top.g1.g2.Y:

module top(out);output out;reg clk, xmr;

// device under testdut g1 (out,clk);

initial begin$hdl_xmr("top.g1.g2.Y","xmr",1);$monitor ($time,,"clk=%b,out=%b,xmr=%b",clk,out,xmr);#0 clk = 1'b0;#101 $finish;endalways begin #10 clk = ~clk;endendmodule

This testbench performs the following operations:

1. First the design is configured all Verilog/VHDL.

The $hdl_xmr is functional with no problems.

2. Second the design is reconfigured with the Verilog dut replaced by the SPICE dut, in the mixed-signal control file (vcsAD.int), the cell view, the dut, is changed to use_spice: use_spice -cell dut;

The same Verilog testbench and $hdl_xmr is used.

The $hdl_xmr is no longer functional.

Warnings are output from the simulation engine.

The hierarchical path for the VHDL instance g2, port Y, is no longer correct.

Testbench -> hierarchical path for $hdl_xmr => top.g1.g2.Y.



Warning-[HXSSI] Hdl_xmr: Source signal invalid verilog/testbench.v, 11Instance path: topSource signal 'top.g1.g2.Y' could not be found in the design. Hence the connection with its destination signal is not established.Please use a valid source signal.

To resolve this problem, the testbench could have been re-configured, manually, adding an "X" prefix in the Verilog testbench for the $hdl_xmras shown below:

initial begin $hdl_xmr( "top.g1.xg2.Y", "xmr",1);i.e. add an "x" prefix for the instance "xg2"

Then the $hdl_xmr is again functional, with no problems.

But if the design is re-configured again back to a Verilog/VHDL only simulation, the testbench must be re-configured again, because the testbench is not consistent:

initial begin $hdl_xmr("top.g1.g2.Y","xmr",1);

i.e. remove the "x" prefix for the instance "g2"

However the $hdl_xmr is again functional, with no problems.

Reconfiguring the testbench and hdl_xmr each time a cell view is changed is time consuming and error prone.

SolutionA new mixed-signal control command is introduced:

resolve_x_inst_prefix enable;

When this command is applied, the same testbench for designs re-configured with changes of multiple cell views can be re-used. For the test case shown above, the same testbench and $hdl_xmr can be used for the design configured with either the Verilog or SPICE dut cell views.

initial begin $hdl_xmr("top.g1.g2.Y","xmr",1);

The testbench can be "re-used" independent of the design configuration.



Note: The resolve_x_prefix enable; command is not required for the Spectre SPICE format since Spectre instances do not require an "X" prefix.




GlossaryGL

A2A through-netA net that is used only for port connections between two SPICE subcircuits in a Verilog view.

A2DAn analog-to-digital converter.

ADFMI viewIn a given design, at a particular hierarchy, if an ADFMI module is available and is used to simulate a particular block, it is considered an ADFMI view for that block.

BA (back-annotation)Back-annotation (BA) is a process of stitching the parasitic RCs back to the design netlist through connectivity information (net name, instance name, pin name) inside the parasitic file.

bidirectional switchA device that conducts in both directions. In such cases, signals on either side of the device can be the driver signal. A bidirectional switch is typically used to enable isolation between buses or signals.

D2AA digital-to-analog converter.

D2D through-netA net that is only used for port connections between two Verilog modules in a SPICE view.

donut configurationA description of the design using different views across different levels of hierarchy. For example: Verilog-SPICE-Verilog or SPICE-VHDL-SPICE are considered donut configurations.

DSPFA detailed standard parasitic format (DSPF) output netlist format is generated by an extraction tool, and describes interconnect information. Actual net parasitic resistance and capacitance component information is contained in this format.


Glossary

GUIA graphical user interface (GUI) for NanoSim.

HARHierarchical array reduction (HAR) in NanoSim that speeds-up the simulation for memory designs (DRAM and SRAM).

instantiationThe process of creating an instance from a module definition or simulator primitive, and defining the connectivity and parameters of that instance.

mixed-netA net that connects the discrete domain (digital) to the continuous domain (analog). All nodes that exist at the boundary between VCS and NanoSim are considered mixed-nets.

mixed-signalA circuit containing analog- and digital-style components.

multiple viewIn a given design, at a particular hierarchy, if more than one representation is available for simulation (from the choices of Verilog, SPICE, ADFMI, and Verilog-A), it is considered a multiple view.

NanoSimThe Synopsys fast-SPICE transistor-level simulator.

PLIA programming language interface (PLI) of Verilog HDL is a mechanism for interfacing Verilog programs with programs written in the C language. PLI also provides a mechanism for accessing internal databases of the simulator from the C program.

real data typeThe Verilog or VHDL data type defined in IEEE Std 1264-1996 and Std 1364-2001.

resistance map fileAn ASCII file that equates MOSFET "on" resistance to Verilog drive strength; the resistance map file contains the signal conversion data between a SPICE analog value to a Verilog digital value, and a Verilog digital value to a SPICE analog value.


Glossary

SDFA standard delay format (SDF) file stores the timing data generated by EDA tools for use in any stage of a design process. The data in the SDF file is represented in a tool-independent way and includes the following information: delay, timing check, timing constraint, incremental and absolute delay.

simvA Verilog simulator command.

single viewIn a given design, at a particular hierarchy, if there is only one view available for simulation (from the choices of Verilog, SPICE, ADFMI, and Verilog-A), it is considered a single view. A single view is automatically selected for simulation as it is the only view available.

SPEFA standard parasitic extraction format (SPEF) file is an IEEE standard format. This file provides a standard median to pass parasitic information between EDA tools during any stage in the design process. This format contains actual net parasitic resistance and capacitance components.

SPICE netlistIn the present context, the term SPICE netlist is used in place of transistor-level netlist.

SPICE-topThe top level of the design hierarchy is described in a transistor-level netlist format.

SPICE viewIn a given design, at a particular hierarchy, if a SPICE module is available and is used to simulate a particular block, it is considered a SPICE view for that block.

VCSA Synopsys Verilog hardware description language (HDL) simulator.

VCS-MXA Synopsys simulator for Verilog, VHDL, and mixed-HDL design descriptions.

Verilog dummy moduleA module that is the Verilog place holder for a transistor block. A dummy module is an empty module containing only the module declaration and port declarations.


Glossary

Verilog-topThe top level of the design hierarchy is described in Verilog RTL or gate-level netlist format.

Verilog viewIn a given design, at a particular hierarchy, if a Verilog module is available and is used to simulate a particular block, it is considered a Verilog view for that block.

Verilog wrapperA Verilog netlist comprising an empty module. Only the module name and port description are in the wrapper.

VHDLVHSIC HDL

vhdlanA VHDL analyzer command.

vloganA Verilog analyzer command.

VPDAn output format for VCS-MX. VPD uses the VCD+ (value change dump) format.

wreal data typeA Verilog-AMS wire of type "real" which allows modules to exchange "real" values through ports. Also a real net data type used in a Verilog wrapper module in the VHDL/Verilog-SPICE flow to interface a real VHDL port to a top-level SPICE net or connect a SPICE port to a top-level VHDL real net.

XMRA feature that is extensively used in Verilog testbenches, and is referred to as a cross-module reference or Verilog hierarchical referencing. This feature enables simple probing into, or monitoring of, buried signals without requiring the signals to be routed to the top of the design for observation. No declaration of global signals in a package is required for this feature, nor is any modification of the original monitored code.


Index

Symbols$monitor 219

Aa2d command 74A-D signal conversion 269ADMS commands

% valib work 274ADMS environment 273analog blocks 213, 270analog/digital partitioning flows 213appending waveforms 244array-type signal, Verilog wrapper 175array-type signals, Verilog wrapper 174, 175A-to-D interface element 266, 267auto_vsrc_warning 245autowrapper utility 169

Bback-annotation 58back-annotation simulation 58bi-directional interface nodes 262bi-directional interface signals 270bidirectional mapping 57bi-directional net value 247bi-directional nets 270bi-directional port 223, 262bit level port definition 268boundary signals 269bus notation 268bus-type signal, Verilog wrapper 175bus-type signals, Verilog wrapper 174, 175

CCadence

Virtuoso Analog Design Environment 213, 231Cadence NCSIM 273Cadence ncsim 222

Cadence NC-Verilog 216cell name 250cell pattern 250channel connected voltage sources 260choose command 80circuit timing sensitivity 269commands

a2d 74choose 80d2a 81rmap_by_node 90set spice_port_order_as_vlog 109spice_top 109use_spice 110use_verilog 114

compilingdesigns 125netlists 8

creating a resistance map file 56cross module referencing (XMR) 37

Dd2a command 81data flow direction 271DC initialization 129default strength table 271delayed logic output 250, 251digital blocks 213, 270digital/analog partitions 270donut configuration 4donut partition with Verilog on top 233donut partitioning with a Verilog top 233donut partitioning with SPICE top 240D-to-A interface element 267dummy Verilog modules 35dump configuration command 249

Ffarad 266

293

IndexG

fine granularity partitioning 270floating point number 244flow

verilog-spice 3vhdl/verilog-spice 3

flowsmixed-signal 3

functionality errors 270

Gglitches 255global interface activity history 263

Hhigh-level mixed-signal simulation 215history buffer 264HiZ 268HSIM interactive mode 252, 260, 261HSIM waveform file 267HSIMFALL 254HSIMLOGICHV 253HSIMLOGICLV 253HSIMLOGIGLV 253HSIMRISE 254HSIMSLOPE 254HSIMVHTH 254HSIMVLTH 254

IIEEE Standard, IEEE 1364-2001 220inout ports 270Input files 124instance based instantiation 220interactive debugging 261interactive debugging mode 260interface activity history 260interface elements 268interface netlist file 250interface node activity history 264interface nodes 262interface signal timing error margin 269interface signals 269, 270inter-process communication (IPC) 214inverter chain 229

IPC (inter-process communication) 214

Kkeywords, reserved 207, 210

Lleaf inverter 229licenses 122

Mmapping

bidirectional 57unidirectional 56

Mentor Graphics ModelSim 213, 273mismatched port 257Mixed Signal Simulation Interactive Mode

Commandcsnh 264

mixed-signal control file commands, summary 117mixed-signal simuation

digital and analog partitions 273mixed-signal simulation 61, 62

Verilog/VHDL and SPICE-based designs 273Mixed-Signal Simulation Configuration Commands

set_fall_step 252analog_cell 245auto_vrsc_warning 245correct_netlist 246define_strength 246, 247digital_cell 247digital_cell_inst 248dump_interface 248dump_port_prop 249dump_setting 249keep_iface_file 249map_subckt_name 250map_unfound_port 250report_logic_delay 250report_port_resistance 251set_args 251set_intr_mode 252set_port_prop 252

-alloweddv 253-delay 254-delay_hz2st 255-delay0 255

294

IndexN

-delay1 255-fall 254-logichv 253-logiclv 253-logicxv 253-lprint 255, 256-rise 254-rm_glitch 255-slope 254-strength 255-timex 254-vhi 254-vlo 254-vprint 255-vsrc 255

set_port_prop_warning 257set_print_progress 257set_rise_step 257set_slope_step 257set_verbose 258set_verilog_supply0 259set_verilog_supply1 258verilog_file 259

mixed-signal simulation engine 249Mixed-Signal Simulation Interactive Mode

Commandcsdinw 266csdnw 266csh 263csinh 264csinw 265csli 262csnph 264csnw 265

mixed-signal simulation interface nodes 262mixed-signal simulation setup 268

spice_top 109mixed-signal simulation setup file 72mixed-signal simulation system variable setup 213Mixed-Singal Simulation Configuration Commands

analog_cell 244ModelSim command

% valog top.v -ms 274% vasim top -ms -pli libvpihsim.so 274% vlib work 273% vlog top.v 274% vsim -c -pli libvpihsim.so +nsda+cosim.cfg top

274

Nncsim interactive mode 243NC-Verilog 213, 260, 261NC-Verilog 5.1 220NC-Verilog library 214NC-Verilog/VHDL executables path 214netlist

compiling 8SPICE 61Verilog 61

nsda_cosim.sp interface file 249

Ooptimize_shadowfile command 91

Ppartition boundary 269partitioning commands

set rmap 154pass switch 270path resistance report 251port delay 255port falling time 254port mapping 267port rising & falling time 254port rising time 254port-mapping 70positive delay 255primitive gate 270print voltage logic 256print voltage value 255programming language interface (PLI) 214

Rreach-in signal 269reach-in signals 270real type Verilog variable 267remove_d2a command 100reserved keywords 207, 210resistance map file 56resistance map file, creating 56resistance value 270rmap_by_node command 90rmap_file command 105

295

IndexS

SSDF files 58set mview_vlog_nosportswap command 90set spice_port_order_as_vlog command 109setting up environment 158setup file, creating 72shadow_file_dir 108shadow_file_dir command 108simulation

preparing 4setup file 7

simv executable 125SPICE impedance 271SPICE internal node 267SPICE netlist

array-type signal 174bus-type signal 174

SPICE node 267SPICE sub-circuit 267spice_top 109spice_top command 34, 109SPICE-on-top donut partitioning 239stop times 252, 257, 258strength fighting 270strength levels 271strength resistors 271strength resolution 271strength table 271strength tables 251string identifier 253, 254, 255strong state 255S-V-S partitioning 239

TTCL (tool command language) 214threshold voltages 269timing shift 269tool command language (TCL) 214translating signal values 213

Uunfound port list 250unidirectional mapping 56unidirectional port direction 268

use_spice command 110use_verilog command 114

Vvector nets 268Verilog elaboration 269Verilog elaborator 269Verilog interactive mode 252Verilog interface file 228Verilog module 222Verilog module definition file 259Verilog net 270Verilog object waveforms 267Verilog Procedural Interface 214Verilog strength map 251Verilog vector ports 268Verilog voltage level specification 259Verilog wrapper 231Verilog wrapper file, bus/array-type signals 174,

175Verilog/SPICE system tasks

$nsda_a2d_node 266$nsda_add_cap 266$nsda_d2a_node 267$nsda_get_volt 267$nsda_inout_node 267$nsda_module 267$nsda_save_waveform 267$nsda_set_volt 267

Verilog/VHDL/HSIM mixed-signal simulationconfiguration commands 213partitioning guidelines 213

Verilog/VHDL/HSIM mixe-signal simulation 213Verilog-side signals 271Verilog-XL 213, 215, 232VHDL design library 150VHDL on top mixed-signal simulation 223Virtuoso Analog Design Environment 213, 231vmx run script 232voltage expression 253voltage sensitivity 269VPI 270VPI (Verilog Procedural Interface) 214VPI code 214VPI function call 214

296

IndexW

VPI shared library 214VSRC 258V-S-V partitioning 232

Wwatchpoint 265, 266

watchpoints 260waveform appending 244

XXMR (cross module referencing) 37

297

IndexX

298

Documents

Mixed-Signal Simulation User Guide