MIT Lincoln Laboratory TIPP 2011 p1 14 June 2011 ckc SOI-Enabled 3D Integrated Circuit Technology TIPP 2011 14 June 2011 C.K. Chen, B Wheeler, D.R.W. Yost,

MIT Lincoln LaboratoryTIPP 2011 p1

14 June 2011 ckc

SOI-Enabled3D Integrated Circuit Technology

TIPP 201114 June 2011

C.K. Chen, B Wheeler, D.R.W. Yost, J.M. Knecht, and C.L. KeastMIT Lincoln Laboratory

*This work was sponsored by the Defense Advanced Research Projects Agency under Air Force contract #FA8721-05-C0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government .


14 June 2011 ckc

Why 3D?

Mixed Material IntegrationCompound Semiconductors

Advanced Focal Plane Imagers100% Fill Factor

3DIC Cross Section

Exploiting Different Process Technologies

High Performance -Processors

Density, Speed, & Power


14 June 2011 ckc

Improve Density by Chip Stacking

ChipPAC, Inc. Tessera, Inc.

Stacked Chip-Scale PackagesStacked-Die Wire Bonding

1 mm


14 June 2011 ckc

Approaches to High-Density 3D Integration(Photos Shown with Same Scale)

Micro bump bond for flip-chip interconnecting

two circuit layersTSMC 40-m pitch, 2010 IEDM

MITLL SOI-based 3D vias for interconnecting

three circuit layers

Thru silicon via (TSV) for interconnecting circuit layers through thinned

bulk Si layersTSMC 30-m pitch, 2010 IEDM

10 m

3D-Vias

Tier-1

Tier-3

Tier-2

10 m10 m

3D-Vias


14 June 2011 ckc

Outline

• Motivation

• Lincoln’s 3D Integrated Circuit Process

• 3D Circuit Demonstrations

• Summary


14 June 2011 ckc

2D versus 3D Circuits

3D Integrated Circuit Cross-Section

2D Integrated Circuit Cross-Section

Handle Silicon

Single CircuitLayer

Circuit Layers

Tier 1

Tier 2

Tier 3

Handle Silicon

3D Vias

Silicon

Buried Oxide

Deposited Oxide

Metal


14 June 2011 ckc

3D Integrated Circuit Process Flow

• Fabricate circuits on Silicon-on-Insulator (SOI) wafers (active Si layer is separated from a handle bulk Si substrate by an insulating buried oxide)

• Assemble circuit layers into a 3D stack

Handle Silicon

Buried Oxide

Tier-1

Handle Silicon

Buried Oxide

Tier-2

Handle Silicon

Buried Oxide

Tier-3

Tier-1 can be either Bulk or SOI

Silicon

Buried Oxide

Deposited Oxide

Metal


14 June 2011 ckc

Tier2-to-Tier1 Alignment and Bonding

Handle Silicon

Buried Oxide

Tier-1

Handle Silicon

Buried Oxide

Tier-2

Silicon

Buried Oxide

Deposited Oxide

Metal


14 June 2011 ckc

Tier2 Substrate Removal andElectrical Connection to Tier1

Handle Silicon

Buried Oxide

Tier-1Handle Silicon

Buried Oxide

Tier-2

Silicon

Buried Oxide

Deposited Oxide

Metal

Tungsten


14 June 2011 ckc

Tier3 Bonding and Alignment

Handle Silicon

Buried Oxide

Tier-1

Handle Silicon

Buried Oxide

Tier-3

Silicon

Buried Oxide

Deposited Oxide

Metal

Tungsten


14 June 2011 ckc

Handle Silicon

Buried Oxide

Tier-3

Tier3 Substrate Removal andElectrical Connection to Tier1-Tier2

Handle Silicon

Buried Oxide

Tier-1

150-mm-diameter three-tier wafer

Silicon

Buried Oxide

Deposited Oxide

Metal

Tungsten• SOI enables elimination of tier2 & tier3 handle Si wafer

• Thru Si via (TSV) becomes thru oxide via (TOV)

• TOV offers many advantages vs. TSV – more compact, higher density, oxide isolation, reduced parasitics


14 June 2011 ckc

3D Enabling Technologies

• Precision wafer aligner-bonder– Designed and built at MITLL– Incorporates IR cameras– Demonstrated 0.25-m wafer-to-wafer

alignment capability

• Low temperature oxide-oxide bonding– Allows use of standard IC processing to

complete 3D integration – Room temperature bond followed by a

175C post-bond anneal

• Concentric 3D via– Formed by high-density-plasma oxide etch– Interconnect formed by CVD tungsten

deposition

3D Via ChainSEM cross section


14 June 2011 ckc

Design Rule 3D Vias(SEM Images Shown at Same Scale with Drawn 3D Via Size)

10um

epoxy bond

~15 m2000

2 m2004

1.75 m2005

1.25 m2008

oxidebond

1024×1024, 8-μm pixel visible image sensor

64 x 64, 12-μm active-pixel sensor

64 x 64, 50-m pixel LADAR

3rd 3D multi project run

• Key 3D Via Developments– Replaced epoxy with oxide bond allowing use of standard silicon

integrated circuit processing– Developed concentric 3D vias, allowing much higher density– Reduced 3D via size– Reduced active area exclusion

1.00 mcurrent

InP detector array


14 June 2011 ckc

3-Tier 3DIC Cross-SectionDARPA 3DM3 Multiproject Run

Three FDSOI CMOS Tiers

3DIC Process Highlights 11 metal interconnect levels 1.25-m 3D via tier interconnect Stacked 3D vias allowed

Tier-3 RF tungsten gate shunt Tier-3 2-m-thick RF back metal

Oxide Bond Interface

Tier-2

Tier-3 3DVia

3DVia

Transistor Layers

Tier-1 Transistor Layer 20 m

RF Back Metal

Tier-1


14 June 2011 ckc

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Vgate (V)

Idra

in (

A)

pMOS

tier 3

nMOS

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Vgate (V)

Idra

in (

A)

pMOS

tier 2

nMOS

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Vgate (V)

Idra

in (

A)

pMOS

tier 1

nMOS

Transistor CharacteristicsBefore and After 3D Integration

Tier 1

Tier 2

Tier 3

• Ids-Vgs plots

Width/Length = 8/0.15 m

Vdd = +/-1.5V for p/nMOS

Before ( ) & after ( ) 3D integration

• No significant change before and after 3D integration

+ ▬


14 June 2011 ckc

Outline

• Motivation

• Lincoln’s 3D Integrated Circuit Process


• Summary


14 June 2011 ckc

3D Circuit Demonstrations

• Advanced Focal Plane Imager (ISSCC 2005 & 2009)

– Photoactive and readout circuit layers– 100% fill factor– 1024 x 1024 pixel array– 8-m pixel pitch

• 3-Tier Laser Radar Focal Plane (ISSCC 2006)

– 3D Integration of three different process technologies

1.5 V FDSOI CMOS counter circuit layer 3.3 V APD drive-sense circuit layer 30 V avalanche photodiode layer

• High Speed 10Gb/s Tier-to-Tier Interconnect (Frank Chang, UCLA, ISSCC 2007 )

Image from 3D ChipImage from 3D Chip

3-Tier Pixel Layout3-Tier Pixel Layout

Input

Output

10ps/div

100mV/div

500ps/divInput

Output

10ps/div

100mV/div

500ps/div

RFI Test @ 12.5 GHz Output Eye diagram


14 June 2011 ckc

Mixed Material 3D IntegrationInGaAs Diode Array with SOI CMOS Readout

150 mm

3D Integrated SOI / InP Wafer SEM Cross Section of Pixel Array

• Established 3D Si-compatible III-V process

• Demonstrated 6-m-pixel SWIR focal plane

InGaAs

p InP

n InP

M3

M2

FET

3D

TO

V

Top metal

6 m

InP

SO

I

Oxide


14 June 2011 ckc

• Funded by DARPA to explore new 3D circuit applications

• Engage government, academic, and industry design groups in a Multiproject run, using a proven 3D integration process

• Provided 3D process design kit based on a decade of fabrication experience over ten different designs

• Third 3D Multiproject statistics:– 38 design proposals received– Requested area: 760 mm2

– Available area: 484 mm2

Enabling 3D Design Multiproject Fabrication Runs

3D Multiproject Floorplan

Cornell U Pitt UMN JHU

UFL RPI DOD

MITLL

Eutecus

PSU

ASU

NCSU

UNH JHU

UNH

U Idaho

MITLL

MITLL

ASU

Vanderbilt

Rochester

NCSU

Sensing Mach

NRL-Cornell

Wash StL

Fermi Lab

Yale

PSU

UNH-MIT


14 June 2011 ckc

Third 3D IC Multiproject Run (3DM3)(Three Tiers of 150-nm 1.5-volt FDSOI CMOS)

ASUCornellDoDEutecusFermi Nat’l LabIBMJohns HopkinsMIT (Campus)MIT Lincoln Lab

NCSUNRLPenn StateRPISensing Mach.SUNYUNHU Idaho

U FloridaU MinnesotaU PittsburghU RochesterU TennVanderbiltWash U StLYale

3DM3 Participants (Industry, Universities, Laboratories)

3D Circuits Secure ID/Anti-tamper, Stacked SRAM & DRAM,

Stacked microprocessor, Hi-speed transmit/ receive, One-chip GPS, Network-on-chip, Reconfigurable neural network, SAR processor elements, RF-switching power converter, Power management for 3DIC’s, Integrated RF MEMS, Implantable biosensors, Bio lab-on-chip

3D Imaging Applications ILC pixel readout, low-power pattern recognition

3D vision chip, Multi-core processor with image recognition, Focal plane image processor, Sub--sized pixel imaging array

3D Technology Characterization 3D radiation test structures, Jitter-clock skew-

propagation delay, Hi-speed I/O, RF building blocks, Meta-material inductor, Stacked MOSFET

Completed 3DM3 Die photo

22 m

m

• First 3D Multiproject run 3DL1chips delivered April 2006

• Second 3D Multiproject run 3DM2chips delivered Nov 2007

• Third 3D Multiproject run 3DM3chips delivered Aug 2010


14 June 2011 ckc

3D Integrated Foundry Wafers

22 mm

Foundry Wafer Die Photo

150 mm

• Demonstrated bonding and 3D integration of metal-only Jazz wafers

• Achieved 100% yield of design-rule 10K 3D via chains

3D integrated Jazz wafers


14 June 2011 ckc

Summary

• SOI-Enabled 3DIC Process

• Process characterization

• TOV (thru oxide via) vs. TSV (thru silicon via) smaller, higher density, reduced parasitics


– Advanced Focal Planes (100% fill factor)

– 3D LADAR Chip (mixed technologies)

– High Speed 10 Gbps Interconnect

– InP-Si Integration (mixed materials)

– 3D Multiproject Designs

• 3D Integration of Foundry Wafers


14 June 2011 ckc

Supplemental Slides


14 June 2011 ckc

BV BV

BM1 BM1

M1

BV

BM1

M1

BV

BM1

CON CON

Back Metal-to-Transistor Contact Use of Back Via Improves Design Flexibility

NominalNominal Cross Section

Experimental BVExperimental BV Cross Section• ExperimentalExperimental back via-transistor layout

– Required layers – back via (BV) & back metal (BM1)

– More compact layout reduces transistor footprint by ~40%

– Allows back metal use as local interconnect routing layer

Transistor

Transistor

• NominalNominal design rule transistor layout

• Required layers -- contact (CON), metal-1 (M1), back via (BV), & back metal (BM1)


14 June 2011 ckc

0.0E+00

1.0E-03

2.0E-03

3.0E-03

4.0E-03

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

+Vdrain (V)

Idra

in (

A)

nMOS

0.0E+00

5.0E-04

1.0E-03

1.5E-03

2.0E-03

2.5E-03

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

-Vdrain (V)

Idra

in (

A)

pMOS

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Vgate (V)

Idra

in (

A)

pMOS nMOS

tier 3

Transistor CharacteristicsExperimental Back Via vs. Nominal Layout

• Ids-Vgs and Ids-Vds plots

Width/Length = 8/0.15 m

Vdd = +/-1.5V for p/nMOS

Tier 3

Vg = 0 to 1.5 V in 0.25 V steps

Vg = 0 to -1.5 V in 0.25 V steps

Nominal Layout

Experimental Back-Via Layout

+

▬

Documents

MIT Lincoln Laboratory TIPP 2011 p1 14 June 2011 ckc SOI-Enabled 3D Integrated Circuit Technology TIPP 2011 14 June 2011 C.K. Chen, B Wheeler, D.R.W. Yost,