Minimum System Requirements

Clock GeneratorMemory Interfacing

System Block Diagram

System bus (data, address & control signals)

Memory

Interrupt circuitrySerial I/OParallel I/O

Timing CPU

P + associated logic circuitry:

•Bus controller

•Bus drivers

•Coprocessor

• ROM (Read Only Memory) (start-up program)

• RAM (Random Access Memory)• DRAM (Dynamic RAM) - high capacity,

refresh needed• SRAM (Static RAM) - low power, fast,

easy to interface

•Crystal oscillator•Timing circuitry(counters dividing to lower frequencies)

At external unexpected events, P has to interrupt the main program execution, service the interrupt request (obviously a short subroutine) and retake the main program from the point where it was interrupt.

Simple (only two wires + ground) but slow.•Printer (low resolution)•Modem•Operator’s console•Mainframe•Personal computer

Many wires, fast.•Printer (high resolution)•External memory

• Floppy Disk • Hard Disk• Compact Disk

•Other high speed devices

Required Circuits in Minimum-mode and Maximum-mode

GNDAD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0NMIINTRCLKGND

VCCAD15A16/S3A17/S4A18/S5A19/S6

RQ/GT0RQ/GT1

QS0

READYRESET

BHE/S7MN/MXRD

LOCKS2S1S0

QS1TEST

1234567891011121314151617181920

3130292827262524232221

4039383736353433328086

Max Mode

GNDAD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0NMIINTRCLKGND

VCCAD15A16/S3A17/S4A18/S5A19/S6

HOLDHLDA

ALE

READYRESET

BHE/S7MN/MXRD

WRM/IODT/RDEN

INTATEST

1234567891011121314151617181920

3130292827262524232221

4039383736353433328086

Min Mode

Vcc GND

Basic Requirements: Power Clock Reset Circuit Memory ( ROM – RAM)

8284 Clock Generator for 8086

an 18-pin chip• specially designed to be used with 8088/86 microprocessors,• It provides the clock and synchronization for the microprocessor,• also provides the READY signal for the insertion of wait states into the CPU bus cycle.

Block Diagram

Memory Interfacing

TimingMemories

IO/M DT/R SSO CHARACTERISTICS

0 0 0 Code Access0 0 1 Read Memory0 1 0 Write Memory0 1 1 Passive1 0 0 Interrupt Acknowledge1 0 1 Read I/O port1 1 0 Write I/O port1 1 1 Halt

Read Write Control Signals

Read Cycle

Min mode Pins: ALE – M/IO – DT/R - DEN

23

Write Cycle in 8088/8086 Minmode

Address Bus Latches and Buffers

Address Latch Circuit

Data Bus Transceivers

Data bus Transceiver Circuit

Bank Write and Bank Read Control Logic

Bank Write Control Logic Bank Read Control Logic

Address Decoders

Allmost all systems contain two main types of memory :

Read-Only Memory (ROM) system software and permanent system data Random Access Memory (RAM) or read/write memory Temporary data and application software

Memory Devices

• Types of Memory :– read-only memory (ROM)– flash memory (EEPROM)– static random access memory (SRAM)– dynamic random access memory (DRAM)

• All memory devices have :– Bidirectional Data– address inputs – a pin for selection (CE – CS – EN )– one or more pins that control the operation of the

memory (RD – WR – R/W – OE )

Maximum Mode Interface

• Used in a multiprocessor environment

• 8288 Bus Controller is used for bus control

• WR, IO/M, DT/R, DEN, ALE, INTA signals are not readily available

33

8088 System

34

Fully buffered 8088

35

8086 System

36

Fully Buffered 8086

37

8086 Max Mode Interface

38

Max Mode Memory Interface

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOEWE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOEWE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOEWE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOEWE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOEWE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOEWE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOEWE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOEWE

D0 - D7

D8 - D15A1-A16

A1-A16

Y0Y1Y2Y3Y4Y5Y6Y7

A0A1A2

G1 G2

A17A18A19

A0DEN

Y0Y1Y2Y3Y4Y5Y6Y7

A0A1A2

G1 G2

A17A18A19

BHEDEN

RD RD

RD

RD

RD

RD

RDRD

WR

WR

WR

WRWR

WRWR

WR

SRAMs

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOE

A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15

D0D1D2D3D4D5D6D7

CSOE

D0 - D7

D8 - D15A1-A16

A1-A16

Y0Y1Y2Y3Y4Y5Y6Y7

A0A1A2

G1 G2

A17A18A19

A0DEN

Y0Y1Y2Y3Y4Y5Y6Y7

A0A1A2

G1 G2

A17A18A19

BHEDEN

RD RD

RD

RD

RD

RD

RDRD

EPROMs