MIL-STD-883: MIL-STD-202 · 2018. 11. 24. · NDO2 CML Output Input Non-Inverting / Inverting Data, internal differential termination at 100 Ω E2/F2 DO3 / NDO3 CML Output Input Non-Inverting

Copyright © 2018 – Reflex Photonics Inc.SpaceABLE 4TRx Data Sheet – 970-00323_REV03 Page 1 (of 33)

Document Number: 970-00323_REV03

Radiation Hardened - SpaceABLE™ 4TRx Parallel Optical Engine

Photo 01: SpaceABLE 4TRx SMT and pluggable Parallel Optical Engine

Product Summary

The Reflex Photonics RADIATION RESISTANT SpaceABLE™ 4TRx Surface-Mount Technology (SMT) or Pluggable Transceiver includes 4 optical transmit channels and 4 optical receive channels. The electrical interfaces are based on CML logic levels and support data rates per channel of up to 12.5-Gbps (a total bandwidth over 50-Gbps full duplex).

The module integrates an industry standard 1x12 MT optical interface using the QSFP compatible (4-Tx/4-n.c./4-Rx) channel configuration. The module can be offered as SMT version with a 10X10 BGA (Ball Grid Array) interface or as a pluggable version with an Amphenol/FCI 10X10 MegArray® mezzanine connector. The SMT version is reflowable according to standard solder reflow processes while the pluggable version plugs into a mating connector on the Host board. The SpaceABLE™ 4TRx optical engines operate from a single +3.3V power supply. A two-wire serial interface is available to send and receive control signals and to obtain digital diagnostic information.

Qualification Radiation test:

Heavy ion

Cobalt 60 – electron source

Proton bombardment

MIL-STD-883:

Vibration tests. Method 2007.3

Mech., shock tests, Method 2002.4

Thermal shock tests, Method 1011.9

Thermal cycling tests, Method 1010.8

MIL-STD-202:

Damp heat tests, Method 103B

MIL-STD-810:

Cold storage tests, Method 502.5

Summary Specifications

Industrial Temp. -40°C to 100°C Sensitivity of -9dBm Up to 12.5 Gbps per channel Short-Reach 850-nm VCSELs Standard 1x12 MT optical interface 4 Differential CML Inputs 4 Differential CML Outputs 10X10 SMT BGA or pluggable versions Link Distance up to 100-m (OM3 fiber) 2-wire (I2C) Serial Control Interface Asynchronous channel operation Data protocol agnostic, balanced code

Application The SpaceABLE™ 4TRX applications:

LEO, GEO satellites

Data Sheet



1. SpaceABLE™ Pluggable/Surface Mount 50G SR4 Optical Engine Overview The Reflex Photonics 50G SpaceABLE™ 4TRx optical engines offer 4 transmitters and 4 receiver asynchronous channels operating at up to 12.5 Gbps per channel. These optical engines are designed for short reach applications (up to 100m) on parallel multimode fiber.

The SpaceABLE™ 4TRx module’s transmitter section consists of an array of four 850 nm VCSELs (Vertical Cavity Surface Emitting Lasers) and associated circuitry, which convert four parallel electrical data inputs to four parallel optical data output signals. The SpaceABLE™ 4TRx module’s receiver section consists of an array of four high-speed photodiodes and associated amplifier circuitry, which convert four parallel optical data inputs to four parallel electrical data output signals.

An industry standard optical fiber ribbon with an MT-terminated compatible connector at one end plugs into the SpaceABLE(tm) 4TRx receptacle with the MicroClip™ to hold it in place. The MicroClip™ is shown in Figure 1.

Figure 1 – SpaceABLE™ 4TRx pluggable transceiver with MicroClip™ and connecting ribbon fiber.

The SpaceABLE™ 4TRx optical engines operate from a single +3.3V power supply. A two-wire serial interface is available to send and receive control signals and to obtain digital diagnostic information. Alarm interrupt (NINT) and hardware laser disable pin (LDIS) is also provided. External power supply filtering and bypass capacitors can easily be placed on the host board near the SpaceABLE™.

The diagnostic information includes RSSI (receiver signal strength indicator) and temperature readout that can be obtained from an analog signal pin. Details on the diagnostic information and the procedure to access that information from the SpaceABLE™ can be found in the document TBD. Each parallel module is supplied with a dust-plug for the protection of the optical interface during re-flow.



1.1 Suggested Application The Reflex SpaceABLE™ 4TRx optical engines can be attached directly onto a Host PCB via surface mountable BGA or a high speed electrical socket. An example application scenario is shown below.

Figure 2 – Application example of AMC (advanced mezzanine card) connection using SpaceABLE™ 4TRx optical engines



2. Absolute Maximum Ratings Absolute maximum ratings indicate values beyond which damage may occur.

Table 1 – Absolute Maximum Ratings for SpaceABLE™ 4TRx module

Parameter Symbol Min. Max. Unit Remarks

Industrial Storage Temperature TST -57 125 °C 1

Commercial Storage Temperature TST -57 125 °C 1

Industrial Operating Temperature TC -55 100 °C 1

Commercial Operating Temperature TC -55 100 °C 1

Supply Voltage Vcc -0.3 4.5 V

Singled Ended Input Swing ΔVIN 1.4 V 2

Peak Input Voltage VPEAK -0.3 Vcc+0.3 V 3

ESD Resistance VESD 2 kV 4

Relative Humidity RH 5 95 % 5

Bit rate B 0.05 12.5 Gbps

1. Temperature is measured at the SpaceABLE 4TRx case (Tcase). 2. Maximum voltage that can be applied across the differential data inputs without damaging the device. 3. Peak Input Voltage for control lines only 4. Human body model 5. Non-condensing

3. Recommended Operating Conditions Recommended operating conditions indicate values at which performance and reliability is intended. Device functionality is not implied beyond the recommended operating conditions.

Table 2 – Recommended Operating Conditions for SpaceABLE™SR4 module

Parameter Symbol Min. Max. Unit Remarks

Supply Voltage Vcc 3.2 3.4 V

Industrial Operating Temperature TC -40 100 °C 1

Bit rate B 1 12.5 Gbps 2

Differential Input Voltage Swing ΔVINp-p 200 1600 mV

1. Temperature is measured at the SpaceABLE 4TRx case (Tcase). 2. Assumes a balanced bit stream. Maximum data rate varies with part number



4. SpaceABLE™ 4TRx Specifications

4.1 Transmitter and Receiver Functional Description The SpaceABLE™ 4TRx module’s transmitter converts 4 parallel electrical input signals via a laser driver and a Vertical Cavity Surface Emitting Laser (VCSEL) array into parallel optical output signals. The transmitter module accepts electrical input signals which are voltage compatible with Current Mode Logic (CML) levels. All input data signals are differential and are internally terminated. The SpaceABLE 4TRx module’s receiver converts 4 parallel optical input signals via a photodiode and trans-impedance/limiting amplifier array into parallel electrical output signals. The receiver module outputs electrical data signals which are voltage compatible with Current Mode Logic (CML) levels. All output data signals are differential and are internally terminated. All data signals can support a data rate of up to 12.5 Gbps per channel (depending on part number). Figure 3 presents a detailed functional block diagram of the SpaceABLE 4TRx module with corresponding external connection pins. A single power voltage of 3.3V is required to power up the SpaceABLE 4TRx. All control signals are CMOS (Complementary Metal Oxide Semiconductor) compatible. A two-wire serial interface is available to communicate with the controller through two control pins: SCL (Clock) and SDA (Serial Data). As there is no module select pin on the SpaceABLE, all modules must be located on separate two-wire serial buses since all SpaceABLE share the same two-wire serial address. Device in default mode: Internal registers are used to control and monitor individual channel settings when the device is in the default mode (See table down below for the available mode). These registers are cleared during power-up/power-down of the module. Therefore, the module registers must be reloaded with the proper settings by the host system’s controller in order to enable operation of the module each time the power supply is cycled. The host controller will use the two-wire serial bus to access the registers (see section 5.1 for register memory map). A setting file with recommended parameters is provided with the part. Radiation resistant mode: (Hardwired) Internal registers are set to fixed values. I2C port can be used to monitor value only. In all the mode, the module offers a status signal called NINT (Global alarms interrupt). Refer to the memory map for an explanation of how to configure and interpret the NINT alarm signal. The diagnostic information includes RSSI (receiver signal strength indicator) and temperature readout that can be obtained from the analog signal pin A6. Details on the diagnostic information and the procedure to access that information from the SpaceABLE can be found in the document # TBD. The LDIS pin disables the TX laser output. Device configuration signal on boot up description is below. We recommend passing through the reset mode when switching between configurations of device when the device is powered on but this is not mandatory. Default mode gives full tunability over all parameters and is not fully radiation resistant. The standalone mode 0 and standalone mode 2 operates under fixed parameters and gives a fully radiation resistant mode.

TXC1 TXC2 Description 0 0 Standalone mode 0, no I2C access 0 1 Reset Mode 1 0 Standalone mode 2, no I2C access 1 1 Default mode. Module is I2C controlled



RXC1 RXC2 Description 0 0 Standalone mode 1, Squelch OFF 0 1 Standalone mode 3, Squelch ON 1 0 Reset Mode 1 1 Default mode. Module is I2C controlled

The SpaceABLE™ 4TRX module is a full transceiver with 4 transmits channels and 4 receive channels. The electrical inputs and outputs use standard CML or LVDS signaling levels and the transmitter outputs follow the extinction ratios and eye-mask requirements of the IEEE Std. 802.3ba for short-reach optical interconnects. In figure 03, a functional block diagram of the SpaceABLE™ 4TRX module is provided with all corresponding external connection pins.

Figure 3 – Reflex SpaceABLE 4TRx transceiver functional block diagram.



4.3 SpaceABLE™ 4TRx Electrical Connection Description

Table 3 – Electrical Pin Assignment and Description.

PIN Symbol

Type IO Description

K9/J9 DI1 / NDI1

CML Input Input Non-Inverting / Inverting Data, internal differential termination at 100 Ω

G10/H10 DI2 / NDI2


E9/F9 DI3 / NDI3


K6/K7 DI4 / NDI4


K2/J2 DO1 / NDO1

CML Output Input Non-Inverting / Inverting Data, internal differential termination at 100 Ω

G1/H1 DO2 / NDO2


E2/F2 DO3 / NDO3


K5/K4 DO4 / NDO4


B7 NINT CMOS Output Fault indicator, Logic Low indicates fault

C7 LDIS CMOS Input Laser Output Disable, Logic High disables laser

C6 SDA CMOS In/Out Serial data Input and Output for 2-wire (I2C) interface. Requires an external pull-up.

C4 SCL CMOS Input Clock for 2-wire (I2C) interface

A6 IMON RSSI

Analog Current

Output Analog Current Readout proportional to temperature or Received Signal Strength Indicator. Configurable via two-wire interface and memory map register programming. See memory map document (section 5)

B4 TXC1 CMOS Input Device configuration signal on boot up

B6 TXC2 CMOS Input Device configuration signal on boot up

B5 RXC1 CMOS Input Device configuration signal on boot up

A7 RXC2 CMOS Input Device configuration signal on boot up

A2 A4 A5 A9 B2 B9 C1 C5 C8 C10 D1 D10

DNC - - Do not connect (16 pins are assign as DNC)

B1 B10 C3 D3 D4 D5 D6 D7 D8 E4 E5 E6 E7

F1 F10 G3 G4 H3 J1 J10

VCC Supply Input +3.3 V Supply Voltage (20 pins are assign for VCC)

A1 A3 A8 A10 B3 B8 C2 C9 D2 D9 E1 E3 E8 E10 F3 F4 F5 F6 F7 F8 G2 G5 G6 G7 G8 G9 H2 H4 H5 H6 H7 H8

H9 J3 J4 J5 J6 J7 J8 K1 K3 K8 K10

GND Supply Input Ground, connected to signal ground plane (43 pins are assign for GND)



Note: Polarity of differential signals could be easily inverted via code. Programming registers 0x43, 0x42, 0x41 and 0x40 allows inverting each channel separately. Inverting or no-invert polarity is set via bit 0 of related registers.

Figure 4 SpaceABLE 4TRx simplified representation of inputs/outputs signals

RX

TX

Electrical inputs to module 4 pairs of differential high speed electrical inputs

Electrical outputs from module 4 pairs of differential high speed electrical outputs

Optical output from module 4 high speed optical outputs

Optical input to module 4 high speed optical inputs

Electrical low frequency communication & control inputs signals

Electrical low frequency communication & control outputs signals

K9/J9 G10/H10 E9/F9 K6/K7

K2/J2 G1/H1 E2/F2 K5/K4

B7 NINT C6 SDA A6 IMON /RSSI

C7 LDIS C6 SDA C4 SCL B4 TXC1 B6 TXC2 B5 RXC1 A7 RXC2





Figure 5 – SpaceABLE™ 4TRx pins indicators

A1 A10

K1 K10



4.4 Electrical Characteristics

Table 4 – Electrical Specifications (Room T = 25°C, VCC =3.3V +/- 0.1 V)

Parameter Symbol Min. Typ. Max. Unit Remarks

Power Dissipation PDIS 0.92 W 1

Supply Current ICC 284 mA 1

LDIS pull-down, NINT pull-up current IINT 10 20 50 uA

LDIS Input Voltage, High VIH 2 VCC V

LDIS Input Voltage, Low VIL 0.8 V

NINT Output Voltage, High VOH 2.4 VCC V

NINT Output Voltage, Low VOL 0.4 V

SDA, SCL Input Voltage, High VIH 2 VCC V

SDA, SCL Input Voltage, Low VIL 0.8 V

SDA sink current at 0.4V ISINK 4.5 mA

Transmitter Data Single Ended Input Impedance ZOUT 45 50 55 Ω

Transmitter Data Differential Input Voltage VD 0.2 1.6 Vp-p

Transmitter Data Absolute Voltage VDI 1.5 Vcc-0.2 V

RSSI Current output linear range/ch IRSSI 0.03 2 mA

Receiver Single Ended Output Impedance ZOUT 45 50 55 Ω

Receiver Differential Output Voltage VDO 550 mVp-p 1

Slope of Thermal current (IMON) Itherm/T 1.35 uA/°C

1. Based on recommended register settings for I2C mode



4.5 Transmitter Section Optical Characteristics

Table 5 – Transmitter Optical Specifications (See note 2)


Maximum bit rate BR 1 12.5 Gbps

Average Optical Power (per channel) POUT -1.5 +3.5 dBm 1,3,4

Average Optical Power– Disabled POFF -30 dBm

Extinction Ratio ER 4 5 dB 1

Center Wavelength λC 840 850 860 nm

RMS Spectral Width λ 0.5 0.65 nm

Total Jitter (p-p) TJ 35 ps 1

1. Based on recommended register settings for I2C mode 2. Specifications are based on measurement done at the following conditions: Data rate = 10.3125Gbps, VDD = 3.3V +/- 0.1 V, Case Temperature of -40°C

to 100°C for industrial grade modules.

3. Maximum power specification from 85°C to 100°C is 2.5 dBm. 4. Minimum power specification from 85°C to 100°C is -2.5 dBm.

4.6 Receiver Section Optical Characteristics

Table 6 – Receiver Optical Specifications (See note 3)


Standard Sensitivity option (per channel) with BER E-12

PIN MIN -9.0 dBm 1,2,3,4

Optical Power Saturation (per channel) PIN MAX +4 dBm

Center Wavelength λC 840 850 860 nm

1. Defined as the average optical power necessary to produce a BER of 10-12 at the center of the baud interval using a 10.3125 Gbps PRBS of length 231-1 or equivalent. Input power is provided as an ideal source and all receiver channels are operating.

2. Worst case over temperature range 3. Specifications are based on measurement done at the following conditions: Data rate = 10.3125Gbps, VDD = 3.3V +/- 0.1 V, Case Temperature of -40°C to 85°C

for industrial grade modules

4. Based on recommended register settings for I2C mode



4.9 Thermal Management Although the power dissipation of the Reflex 50 Gbps SpaceABLE™ Pluggable/Surface Mount 4TRx is low, the small form factor of the optical engine makes careful thermal design necessary. The combination of a good thermal path off the top and off the bottom of the device is recommended. Adequate airflow should be provided to ensure that the engine does not go above the rated maximum temperature. Theta JC measured for SpaceABLE™ Pluggable/Surface Mount 4TRx with maximum power used is 9 °C/W (+/- 15%).

4.10 AC Coupling The optical engine is designed to be AC coupled to the host ASIC/FPGA. To use AC coupling, place DC blocking capacitors on the CML high speed RF.

Figure 6 – Application diagram example



5. Two-Wire Monitoring and Control Interface

The two-wire serial interface is accessed via the following pins:

Table 7 – Two-Wire Serial Interface Pin Definitions

Pin Symbol Type IO Description

C6 SDA CMOS In/Out Serial data Input and Output for two-wire interface. Requires an external pull-up.

C4 SCL CMOS Input Clock for two-wire interface

The two-wire serial address for the TX’s is (0x6B) and for RX’s is (0x4C) Control and monitoring of the SpaceABLE™ Pluggable/Surface Mount 4TRx optical engines is via registers. Both TX and RX

have registers which are unique to each. Two-wire communication is I2C compatible with transfer speed up to 400 kHz. A

setting file with the parameters is provided with the module.

• The two-wire serial address of TX is (0x6B)

• The two-wire serial address of RX is (0x4C)

There are only read register and write register transactions. Auto increment is set by default and execute on successive transactions. Auto increment could be disabled via registers. The wrap around occurs at address 0xFF. A setting file with the parameters is provided with the module.

5.1 Memory Map (Recommended register values can be found in application note # TBD.) Different settings are required for different operating temperature ranges to maintain the TX laser performance over the full industrial operating temperature of -40°C to +85°C. Please note the SpaceABLE™ includes a thermal sensor that monitors junction temperature. There is approximately 8°C difference between junction and case temperature. Therefore, one can use the SpaceABLE™ thermal sensor to determine settings that should be loaded into the registers for a particular operating temperature range. The following figure shows the blue temperature range and the orange temperature range for which the operation parameter must be changed. Proper register values can be found in the following document # TBD.

Figure 7 – Codes overlap representation

Code for -40 to -25°C

Code for -30 to +85°C

-40°C -30°C -25°C +85°C

Use recommended registers value for

case temp -25°C or lower

Use recommended registers value for

case temp -30°C or higher



Bits type description: R/W Readable / Writeable bits R Readable bits only R/E Readable / Erasable bits. All the R/E bits represent latched values. A latched value is set to 1 when an

interrupt source is triggered.

Table 8 – TX register definition Address Register description

0x00 Bit 7...0 Reserved Do not change recommended values

0x01

The Global Digital Power Down Bit 7…2 Reserved. Do not change recommended values Bit 1 Auto Laser Disable. When bit is set and when a channel VVH threshold is violated, the channel output is disabled without intervention. Bit 0 Global Digital Powers Down. It should not be used for emergency laser disable function since it does not meet eye safety requirements for shutdown in the presence of a single fault.



0x04

IMON output disable/enable Bit 7...4 Reserved Do not change recommended values Bit 3 Select bit determines if current proportional to temperature is added to the IMON output. When this bit is set, the current is output on the IMON pin. By default it is disabled. Bit 2...0 Reserved

0x05 Bit 7...0 Reserved

0x06 Disable lasers Bit 7 Disable lasers via two-wire interface. When set all lasers are disabled. Bit 6…0 Reserved

0x07

Polarity invert / Auto Increment Bit 7 The Interrupt Output Invert bit control the polarity of the NINT pin. When the bit is set, the NINT pin is active high. When the bit is cleared, NINT is active low. Bit 6...5 Reserved Do not change recommended values Bit 4 When the bit is set, the I2C register address pointer is incremented automatically. When it is cleared, the register address pointer will not auto increment. Bit 3...0 Reserved.


0x09

Peaking Enable / Duration Register Bit 7…6 Reserved. Bit 5 The Peaking Enable / Disable bit Bit 4...0 The Peaking Duration bits controls the width of the peaking pulse. MSB is bit 4. The Peaking Duration is only valid when The Peaking Enable bit is set (bit 5).

0x0A Bit 7...0 Reserved Do not change recommended values

0x0B 0x0C

Bit 7...0 Reserved Do not change recommended values

0x0D

Bit 7...6 Reserved Bit 5...0 Channel Average Current bits. Do not change recommended values When a value is set into the value is also copied to all R/W bit with the same name. It allowed populate all channels at the same time by writing one register

0x0E

Bit 7...6 Reserved Bit 5...0 Channel Modulation Current bits. Do not change recommended values When a value is set into the value is also copied to all R/W bit with the same name. It allowed populate all channels at the same time by writing one register

0x0F

Bit 7...6 Reserved Bit 5...0 Channel Peaking Control bits. Do not change recommended values When a value is set into the value is also copied to all R/W bit with the same name. It allowed populate all channels at the same time by writing one register

0x19 0x16 0x13 0x10

Channel Average Current Registers Bit 7...6 Reserved Bit 5...0 Channel Average Current bits. MSB is bit 5. Addresses 0x19, 0x16, 0x13 and 0x10 control channels 1 through 4 respectively. Do not change recommended values

0x1A 0x17

Channel Modulation Current Registers Bit 7...6 Reserved



0x14 0x11

Bit 5...0 Channel Modulation Current bits. MSB is bit 5. Addresses 0x1A, 0x17, 0x14 and 0x11 control channels 1 through 4 respectively. Do not change recommended values

0x1B 0x18 0x15 0x12

Channel Peaking Control Registers Bit 7...6 Reserved Bit 5...0 Channel Peaking Control bits. MSB is bit 5. Addresses 0x1B, 0x18, 0x15 and 0x12 control channels 1 through 4 respectively. Do not change recommended values

0x1C till

0x3E Bit 7...0 Reserved Do not change recommended values

0x3F

Bit 7...4 Pulse Width Adjust. Do not change recommended values Bit 3 Power down channel Bit 2 Reserved Bit 1 The squelch enable bit enables the squelch function at the input. When cleared, the squelch function is disabled. Bit 0 The bit causes the channel to be inverting when the bit is set. When cleared, the channel is non-inverting When a value is set into the value is also copied to all R/W bit with the same name. It allowed populate all channels at the same time by writing one register

0x43 0x42 0x41 0x40

Channel Configuration Registers Bit 7...4 Pulse Width Adjust. Do not change recommended values Bit 3 Power down channel Bit 2 Reserved Bit 1 The squelch enable bit enables the squelch function at the input. When cleared, the squelch function is disabled. Bit 0 The bit causes the channel to be inverting when the bit is set. When cleared, the channel is non-inverting Addresses 0x43, 0x42, 0x41 and 0x40 control channels 1 through 4 respectively.

0x44 till


0x4F Bit 7...0 Reserved Do not change recommended values

0x53 0x52 0x51 0x50

Channel Interrupt Registers Bit 7 The Signal Detect bit. Bit 6 The Loss of Signal bit Bit 5…4 Reserved Bit 3 Latched The Signal Detect bit Bit 2 Latched The Loss of Signal bit Bit 1…0 Reserved Addresses 0x53, 0x52, 0x51 and 0x50 control channels 1 through 4 respectively.

0x54 till



0x60 0x61 0x62 0x63

Channel Interrupt Mask Registers Bit 7 The Signal Detect Mask bit. Bit 6 The Loss of Signal Mask bit Bit 5..4 Reserved Do not change recommended values Bit 3 Latched Signal Detect Mask bit Bit 2 Latched Loss of Signal Mask bit Bit 1..0 Reserved Do not change recommended values Addresses 0x63, 0x62, 0x61 and 0x60 control channels 1 through 4 respectively. When a bit of the Channel Interrupt Status Register is masked (bit is set to 1), the corresponding status bit register will not cause an alert and therefore will not affect the NINT pin.

0x64 till



0x70 0x71 0x72 0x73




0x74 till



0x80 0x81 0x82 0x83


0x84 till



0x90 0x91 0x92 0x93


0x94 till



0xA0 0xA1 0xA2 0xA3


0xA4 till

0xAE Bit 7...0 Reserved Do not change recommended values

0xAF Bit 7...0 Reserved Do not change recommended values

0xB0 0xB1 0xB2 0xB3


0xB4 till

0xDF Bit 7...0 Reserved Do not change recommended values

0xE0 Bit 7...0 Reserved

0xE1 Bit 7...0 Reserved

0xE2 till

0xEF Bit 7...0 Reserved Do not change recommended values

0xF0 Channel interrupt Bit 7 NINT bit Bit 6...0 Reserved

0xF1

Channel interrupt Bit 7...4 Reserved Bit 3 NINT bit is clear when any of the interrupt sources for channel 1 is present Bit 2 NINT bit is clear when any of the interrupt sources for channel 2 is present Bit 1 NINT bit is clear when any of the interrupt sources for channel 3 is present Bit 0 NINT bit is clear when any of the interrupt sources for channel 4 is present

0xF2 Bit 7...0 Reserved Do not change recommended values





Table 9– RX register definition Address Register description


0x01

The Pre-emphasis Enable/ Duration bits. Monitor currents bit (RSSI and Temperature) Bit 7...5 Pre-emphasis duration bits control. MSB is bit 7. Do not change recommended values Bit 4 Pre-emphasis Enable bit. Do not change recommended values Bit 3...1 Reserved Do not change recommended values Bit 0 when ‘0’ than RSSI current is directed to IMON pin, when ‘1’ temperature proportional current is directed to IMON pin. Please be aware if you select both RSSI and temperature, the two currents will be added.

0x02

The Global Digital Power Down / Enable signal detect function Bit 7...4 Reserved Do not change recommended values Bit 3 Power down all channels when bit is set Bit 2 Reserved Do not change recommended values Bit 1 Enable the signal detect function when bit is set Bit 0 Reserved Do not change recommended values

0x03

Interrupt invert / Auto increment Bit 7 The Interrupt Output Invert bit (NINT) when the bit is set, NINT pin is active high. Bit 6...4 Reserved Do not change recommended values Bit 3 When set, Auto increment register pointer is incremented automatically. Bit 2…0 Reserved Do not change recommended values

0x04 The Swing size bits control Bit 7…3 Reserved Do not change recommended values Bit 2…0 The swing size bits. MSB is bit 2. Do not change recommended values



0x07 Interrupt Bit 7...1 Reserved Bit 0 Interrupt bit

0x08 till

0x3E Bit 7...0 Reserved. Do not change recommended values

0x3F

Pre-emphasis, enable/disable channel , RSSI, power down, invert bit Registers Bit 7...4 Pre-emphasis Do not change recommended values Bit 3 Enable / Disable channel Bit 2 The Received Signal Strength Indicator. When the bit is set, a copy of proportional current of chosen channel is send to IMON pin. Bit 1 The digital Power Down control Bit 0 The bit causes the channel to be inverting when the bit is set. When cleared, the channel is non-inverting When a value is set into the value is also copied to all R/W bit with the same name. It allowed populate all channels at the same time by writing one register.

0x43 0x42 0x41 0x40

Pre-emphasis, enable/disable channel , RSSI, power down, invert bit Registers Bit 7...4 Pre-emphasis Do not change recommended values Bit 3 Enable / Disable channel Bit 2 The Received Signal Strength Indicator. When the bit is set, a copy of proportional current of chosen channel is send to IMON pin. Bit 1 The digital Power Down control Bit 0 The bit causes the channel to be inverting when the bit is set. When cleared, the channel is non-inverting Addresses 0x43, 0x42, 0x41 and 0x40 control channels 1 through 4 respectively.

0x44 till



0x53 0x52 0x51 0x50

Channel Interrupt Registers Bit 7 Signal Detect state Bit 6 Loss of Signal state Bit 5…4 Reserved Bit 3 Latch Signal Detect state Bit 2 Latch Loss of Signal state Bit 1…0 Reserved Addresses 0x53, 0x52, 0x51 and 0x50 control channels 1 through 4 respectively.



0x54 till


0x5F Bit 7...0 Reserved. Do not change recommended values

0x63 0x62 0x61 0x60

Channel interrupt Mask Registers Bit 7 Signal Detect Mask Bit 6 Loss of Signal Mask Bit 5…4 Reserved Bit 3 Latch Signal Detect Mask Bit 2 Latch Loss of Signal Mask Bit 1…0 Reserved Addresses 0x63, 0x62, 0x61 and 0x60 control channels 1 through 4 respectively. When a bit of the Channel Interrupt Status Register is masked (bit is set to 1), the corresponding status bit register will not cause an alert and therefore will not affect the NINT pin.

0x64 till



0x90 till


0x94 till



0xA3 0xA2 0xA1 0xA0

Squelch enable Bit 7...1 Reserved. Do not change recommended values Bit 0 Squelch enable / disable bit Addresses 0xA3, 0xA2, 0xA1 and 0xA0 control channels 1 through 4 respectively.

0xA4 till

0xDF Bit 7...0 Reserved. Do not change recommended values

0xE0 Bit 7...0 Reserved. Do not change recommended values

0xE1 Bit 7...0 Reserved. Do not change recommended values

0xE2 till

0xF0 Bit 7...0 Reserved. Do not change recommended values

0xF1

Channel Interrupt Bit 7...4 Reserved Bit 3 NINT bit is clear when any of the interrupt sources for channel 1 is present Bit 2 NINT bit is clear when any of the interrupt sources for channel 2 is present Bit 1 NINT bit is clear when any of the interrupt sources for channel 3 is present Bit 0 NINT bit is clear when any of the interrupt sources for channel 4 is present

0xF2

Global Signal detect / Global Loss of Signal Bit 7 The Global Signal Detect bit is cleared when any of the channels indicates that a signal is detected and the event is unmasked. Bit 6 The Global Loss of Signal bit is cleared when any of the channels declares a loss of signal event and the event is unmasked. Bit 5...4 Reserved. Bit 3 The Global Latched Signal Detect bit is cleared when any of the channels indicates that a latched signal detect event is present and the event is unmasked. Bit 2 The Global Latched Loss of Signal bit is cleared when any of the channels declares a latched loss of signal event and the event is unmasked. Bit 1...0 Reserved.



For more detailed information and recommended register values request application note 970-00223.



Example of two wire communications:

Figure 8 – Two-wire random readout from TX example

Figure 9 – Two-wire random write to RX example

Two-wire random readout from TX example

S

T

A

R

T

M

S

B

W

R

I

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M

S

B

L

S

B

R

E

S

T

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R

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M

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B

R

E

A

D

N

A

C

K

S

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O

P

1 1 0 1 0 1 1 0 0 x x x x x x x 1 1 1 0 1 1 1 1 x x x x x x x x 1

0 0 0

Transceiver = 0x6B

Receiver = 0x4C

M

S

B

L

S

B

Data from Device

I2C address Memory Address I2C address

H

O

S

T

DEV

ICE

AC

K

AC

K

AC

K

Two-wire random write to RX example

S

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S

B

M

S

B

L

S

B

S

T

O

P

1 0 0 1 1 0 0 0 0 x x x x x x x x x x x x x x x

0 0 0

Transceiver = 0x6B

Receiver = 0x4C

H

O

S

T

DEV

ICE

AC

K

AC

K

AC

K

I2C address Memory Address Data



6. Mechanical and Layout Considerations The following section provides the dimensions of the 4 x 12.5 Gbps SpaceABLE™ Pluggable/Surface 4TRs optical engines and the recommended footprint on the host board. The FCI MegArray system consist of a Plug connector, see Table 9) mounted on the host board and a Receptacle connector mounted on module which mate with each other. The mechanical dimensions are shown in Figure 10 (pluggable) and Figure 11 (surface mount).

Figure 10 – Mechanical outline - pluggable.

Notes: 1. Unless otherwise specified, all dimensions are in millimeters. 2. All tolerances, unless otherwise specified are +/- 0.1mm. 3. To convert millimeters to inches use 25.4mm = 1 inch. 4. Mechanical properties are the same for Transmitters and Receivers.



Figure 11 – Mechanical outline – surface mount.

Notes: 1. Unless otherwise specified, all dimensions are in millimeters. 2. All tolerances, unless otherwise specified are +/- 0.1mm. 3. To convert millimeters to inches use 25.4mm = 1 inch. 4. Mechanical properties are the same for Transmitters and Receivers.



MT/MPO Fiber #

Lane Assignment

MT/MPO Fiber #

Lane Assignment

1 RX1 7 Unused

2 RX2 8 Unused

3 RX3 9 TX4

4 RX4 10 TX3

5 Unused 11 TX2

6 Unused 12 TX1

Figure 12 – SpaceABLE™ 4TRx Pluggable with MT to MT fiber link connection

Fiber 12 Fiber 1

Guide pins



The optical engine is mounted to the Host PCB using a MegArray™ pluggable connector. Figure 13 shows the recommended pad layout of the Host PCB.

Figure 13 - PCB pad layout (looking down onto host PCB from top)

Electronic CAD models are available upon request.



Dimensions for the MicroClip™ which attaches a standard 12-fiber MT-terminated multimode ribbon fiber to the Reflex SpaceABLE™ Pluggable/Surface Mount SR4 optical engine are shown in Figure 14.

Figure 14 - MicroClip™ dimensions. Part # 322-00020

Figure 15 – Dust Cap dimensions. Part # 314-00054

Dimensions are in mm

Dimensions are in mm



7. Mounting Instructions 7.1 Optical Fiber Interface

MT/MPO to MT/MPO contact force is 2 lb. +/- 0.2 lb.

7.2 SpaceABLE™ Pluggable SR4 The FCI MegArray connector comes in Plug (e.g. part number: 600-00023 (Tin-Lead version) or 600-0006 (RoHS version), see Table 9, the pins on this connector are a single blade) and Receptacle (the pins on this connector are a split blade) formats which mate with each other. The Receptacle is already on the SpaceABLE™ Pluggable 4TRx module and as such the customer must attach a Plug to their board.

7.3 SpaceABLE™ Surface Mount SR4 Baking for 12h at 125 °C is required for the surface mount version of SpaceABLE 4TRx before assembly.

• Module must be reflowed within 48 hrs.

• Module may be stored in Dry Atmosphere Cabinet to extend time after pre-bake (up to 90 days @ <5% RH) The Reflex SpaceABLE™ optical engines can be placed onto the Host PCB like any other surface mount component. After re-flow, the dust cap (Figure 15) is removed and the MT-terminated ribbon fiber can be attached making the optical engine ready for use.

CAUTION: High Temperature Sensitive Device. Do not use a “rework machine” to assemble SpaceABLE™ parts without first contacting Reflex Photonics Inc. These

machines can heat the part beyond its acceptable solder reflow temperatures and cause damage. NOTE:

Dust cap must be present during re-flow process as it serves to insulate and protect the product. DO NOT REMOVE until assembly process is complete. REMOVE just prior to cleaning and mating of cable using Reflex approved dowel pins and retaining MicroClip™.

NOTE:

SpaceABLE™ engines should be reflowed once. The SpaceABLE 4TRx solder-ball attachment uses Tin/Lead solder balls (63Sn/37Pb 0.76mm +/- 0.015 mm) The recommended reflow profile for Tin/Lead solder (SN63) is below (Figure 16). Reflex SpaceABLE 4TRx engines are shipped in pre-baked tolerant trays which are JEDEC flow compliant. SpaceABLE 4TRx has non-solder mask defined and pad opening is 24 mils. Disclaimer: Presented profiles may vary depending upon PCB board design, reflow oven and solder paste selected. Please use compatible solder paste with SpaceABLE solder-balls. For details please see application note 970-00264.



Figure 16 – Tin/Lead Solder (SN63) solder reflow profile.

NOTE: For reference only, actual profile depends on PCB assembly.

Lead-free Soldering (SN96.5)

Tpeak

Tmp

Tc

Tsmax

Tsmin

Tem

per

atu

re [ C

]

Time [sec]

Troom

Rp

RpRc

t(max)

t(soak) t(rpeak)

t(reflow)

Reflow

ParametersMin Typical Max

Troom 25 °C

Tsmin 150 °C

Tsmax 150 °C

Tmp 187 °C

Tc 207 °C

Tpeak 213 °C 218 °C 223 °C

t(max) 480 sec

t(soak) 60 sec 100 sec 180 sec

t(reflow) 60 sec 100 sec 150 sec

t(rpeak) 25 sec 30 sec

Rp 2.5 °C/sec 3 °C/sec

Rc 4 °C/sec 6 °C/sec



8. Brief Application Information

8.1 Handling and Cleaning The optical interface for the SpaceABLE™ modules should be kept clean to prevent interference with the operation of the device. In the absence of an optical cable, place the dust cover onto the MT/MPO optical port. The pluggable module is mated by aligning the small notch of the Meg-Array® connector while pressing down and leading into the large notch of Meg-Array, as shown in Figure 17. To remove the SpaceABLE™ from the socket hold on to the housing and rock the module upwards from the large notch to the small notch. DO NOT PULL ON THE MT OPTICAL CONNECTOR.

Figure 17 – Mating or un-mating of the connector

8.2 ESD Discharge The SpaceABLE™ modules are shipped in Electrostatic Discharge ESD protective packaging. Once removed, normal handling precautions to prevent ESD are required. Workbenches should be grounded and the use of grounding wrist straps and floor mats are recommended.

8.3 Electrical Signals Reflex Photonics SpaceABLE™ modules use CML, a differential logic interface, for their electrical high-speed inputs and outputs. The CML lines should be AC coupled on the PCB. This feature provides the module with common-mode tolerance, fault protection and supply independency. The transmission traces on the host board which connect to the modules should be designed to have an individual impedance of 50 Ω in order to match the input impedance of the ICs.

8.4 Power Supply and Grounding Power supply filtering is highly recommended. See application diagram (filtering is not shown on the application diagram)

TO TO



8.5 Eye Safety Although the average optical power should be sufficiently low, EXTREME CARE should be taken not to look into the transmitter module with the naked eye and especially not with an optical instrument such as a microscope. Module is designed to be a Class 1M laser product, do not view directly with optical instruments.

9. Evaluation Kit The SpaceABLE™ evaluation boards designed for high-speed testing are available. SMA connectors are used to provide the connections to the transmitter / receiver high-speed channels. Switches control the discrete pins and a header is available to connect to the two-wire controls. The evaluation boards require a single 3.3V power supply. The evaluation kit comes with a user manual to facilitate the evaluation process. In-house applications and design engineers are available to assist product evaluations and to support integration. Please contact Reflex Photonics for more information on evaluation boards and kits.



10. Ordering Information

Table 8 – Part Numbers

Part Number Description

SMX04P518332101 SpaceABLE ™ SM 4TRx 4+4 channel Transmit/Receive module, 10.3125-Gbps/ch., Sens: -9.0 dBm, BER E-12, RoHS Pluggable, MT interface, w/o microcontroller, Industrial Temp -40 to 100 °C

SMX04P518432101 SpaceABLE ™ SM 4TRx 4+4 channel Transmit/Receive module, 10.3125-Gbps/ch., Leaded Pluggable, MT interface, w/o microcontroller, BER E-12, Sens: -9.0 dBm, Industrial Temp -40 to 100 °C

SMX04P518232101 SpaceABLE ™ SM 4TRx 4+4 channel Transmit/Receive module, 10.3125-Gbps/ch., Sens: -9.0 dBm, BER E-12, Leaded SMT, MT interface, w/o microcontroller, Industrial Temp -40 to 100 °C

Module is designed to be a Class 1M laser product, do not view directly with optical instruments.

Note: Custom variants may be available. For other transmitter power levels, engine traffic speed, mechanical samples or evaluation board please contact Reflex Photonics Inc.



Figure 18 – Product Code



Table 9 – Additional Part Numbers

Part Number Description

322-00020 MicroClip™ / Offered for free with a SpaceABLE ™

706-00003 Dowel Pins / Included with the SpaceABLE ™.

500-00002 1.2m MT-MT Multimode Fiber

500-00007 1.8m MT to MPO Multimode Fiber / MPO Optical Fiber Ribbon cable

314-00054 MT Dust Cap / Included with the SpaceABLE ™

600-00006 FCI MegArray mate connector for RoHS pluggable version

600-00023 FCI MegArray mate connector for Tin-Lead pluggable version

Note: For other type of fibers cables contact Reflex Photonics Inc.

For more information on this or other products:

Contact sales at 1-514-842-5179 or 1-408-715-1781 or via email at [email protected]

Copyright © 2018, Reflex Photonics Inc. “This document is the property of Reflex Photonics Inc. (“Reflex”) and contents Reflex’s confidential and proprietary information. The holder of this document shall neither use, copy, reproduce, disclose or otherwise deal with the information contained herein except in accordance with the provisions of a non-disclosure agreement executed between Reflex and the holder or in accordance with Reflex’s written instructions.” Disclaimer: Information furnished by Reflex Photonics is believed to be accurate and reliable. However, no responsibility is assumed for its use. Reflex Photonics makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

mailto:[email protected]



Table 10. Document revision history

REV # Date Description

1 First release January 2018

2 Changed LightSPACE and for SpaceABLE name. Clean up document changed the product tree at page 30 to reflect the SMX04 part number instead of the SMT12 part number; I took out the 11.5 Gbps SMX04P512 products from the product ordering information.

May 2018

3

Corrected pin diagram that now shows pin f1 as VCC. Removed LightSPACE and replace SpaceABLE name on the product tree diagram on page 31. Added the default mode and hardwired mode description on page 5. Added the note on the recommendation to pass through the reset mode when switching mode.

October 2018

Documents

MIL-STD-883: MIL-STD-202 · 2018. 11. 24. · NDO2 CML Output Input Non-Inverting / Inverting Data, internal differential termination at 100 Ω E2/F2 DO3 / NDO3 CML Output Input Non-Inverting