Microprocessor Programmable Universal Active Filters · PDF fileorder universal switched-capacitor active filters allow microprocessor control of precise filter functions. No ... An

General DescriptionThe MAX260/MAX261/MAX262 CMOS dual second-order universal switched-capacitor active filters allowmicroprocessor control of precise filter functions. Noexternal components are required for a variety of band-pass, lowpass, highpass, notch, and allpass configura-tions. Each device contains two second-order filtersections that place center frequency, Q, and filter oper-ating mode under programmed control.

An input clock, along with a 6-bit f0 program input,determine the filter's center or corner frequency withoutaffecting other filter parameters. The filter Q is also pro-grammed independently. Separate clock inputs foreach filter section operate with either a crystal, RC net-work, or external clock generator.

The MAX260 has offset and DC specifications superiorto the MAX261 and MAX262 and a center frequency(f0) range of 7.5kHz. The MAX261 handles center fre-quencies to 57kHz, while the MAX262 extends the cen-ter frequency range to 140kHz by employing lowerclock-to-f0 ratios. All devices are available in 24-pin DIPand small outline packages in commercial, extended,and military temperature ranges.

ApplicationsµP-Tuned Filters

Anti-Aliasing Filters

Digital Signal Processing

Adaptive Filters

Signal Analysis

Phase-Locked Loops

Features Filter Design Software Available

Microprocessor Interface

64-Step Center Frequency Control

128-Step Q Control

Independent Q and f0 Programming

Guaranteed Clock to f0 Ratio-1% (A grade)

75kHz f0 Range (MAX262)

Single +5V and ±5V Operation

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Microprocessor ProgrammableUniversal Active Filters

________________________________________________________________ Maxim Integrated Products 1

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

LPA

INB

LPB

BPBN.C.

HPA

N.C.

BPA

TOP VIEW

D0

OSC OUT

GND

V-CLK OUT

A3

D1

INA

16

15

14

13

9

10

11

12

WR

A0

HPB

A1CLKB

CLKA

A2

V+

MAX260

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

LPA

INB

LPB

BPBOP IN

HPA

OP OUT

BPA

HPB

D0

OSC OUT

V-

CLK OUT

A3

D1

INA

16

15

14

13

9

10

11

12

WR

GND

A0

A1CLKB

CLKA

A2

V+

MAX261MAX262

Pin Configurations

Ordering Information

OUTPUT

BPHPLPINBPHPLPIN

INPUT

+5V V+

GND

-5V V-

CLKA OSC CLKOUT CLKB

PROGRAMINPUTS

CRYSTALFOURTH-ORDER BANDPASS FILTER

MAX260MAX261MAX262

FILTERA

FILTERB

Functional Diagram

19-0352; Rev 2; 7/02

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PACKAGE A C C U R A C Y

MAX260ACNG 0°C to +70°C Plastic DIP 1%

MAX260BCNG 0°C to +70°C Plastic DIP 2%

MAX260AENG -40°C to +85°C Plastic DIP 1%

MAX260BENG -40°C to +85°C Plastic DIP 2%

MAX260ACWG 0°C to +70°C Wide SO 1%

MAX260BCWG 0°C to +70°C Wide SO 2%

MAX260AMRG -55°C to +125°C CERDIP 1%

MAX260BMRG -55°C to +125°C CERDIP 2%

*All devices—24-pin packages 0.3in-wide packages

Ordering Information continued at end of data sheet.

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ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

Total Supply Voltage (V+ to V-) .............................................15VInput Voltage, any pin ..........................(V- - 0.3V) to (V+ + 0.3V)Input Current, any pin ......................................................±50mAPower Dissipation

Plastic DIP (derate 8.33mW/°C above 70°C) ...............660mWCERDIP (derate 12.5mW/°C above 70°C) .................1000mWWide SO (derate 11.8mW/°C above 70°C) ..................944mW

Operating Temperature RangesMAX260/MAX261/MAX262XCXG .......................0°C to +70°CMAX260/MAX261/MAX262XEXG .....................-40°C to +85°CMAX260/MAX261/MAX262XMXG ..................-55°C to +125°C

Storage Temperature Range .............................-65°C to +160°CLead Temperature (Soldering, 10s) ................................+300°C

ELECTRICAL CHARACTERISTICS(V+ = +5V, V- = -5V, CLKA = CLKB = ±5V 350kHz for the MAX260 and 1.5MHz for the MAX261/MAX262, fCLK/f0 = 199.49 forMAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA = +25°C, unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

f0 Center Frequency Range See Table 1

Maximum Clock Frequency See Table 1

MAX260A ±0.2 ±1.0

MAX260B ±0.2 ±2.0

MAX261/MAX262A ±0.2 ±1.0fCLK/f0 Ratio Error (Note 1) TA = TMIN to TMAX

MAX261/MAX262B ±0.2 ±2.0

%

f0 Temperature Coefficient -5 ppm/°C

Q = 8 MAX260A ±1 ±6

Q = 8 MAX260B ±1 ±10

Q = 32 MAX260A ±2 ±10

Q = 32 MAX260B ±2 ±15

Q = 64 MAX260A ±4 ±20

Q = 64 MAX260B ±4 ±25

Q = 8 MAX261/MAX262A ±1 ±6

Q = 8 MAX261/MAX262B ±1 ±10

Q = 32 MAX261/MAX262A ±2 ±10

Q = 32 MAX261/MAX262B ±2 ±15

Q = 64 MAX261/MAX262A ±4 ±20

Q Accuracy (deviation from idealcontinuous filter) (Note 2)

TA = TMIN toTMAX

Q = 64 MAX261/MAX262B ±4 ±25

%

Q Temperature Coefficient ±20 ppm/°C

MAX260 ±0.1 ±0.3DC Lowpass Gain Accuracy

MAX261/MAX262 ±0.1 ±0.5dB

MAX260 -5

MAX261/MAX262 -5Gain Temperature CoefficientLowpass (at D.C.)Bandpass (at f0)

MAX260/MAX261/MAX262 +20ppm/°C

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ELECTRICAL CHARACTERISTICS (continued)(V+ = +5V, V- = -5V, CLKA = CLKB = ±5V 350kHz for the MAX260 and 1.5MHz for the MAX261/MAX262, fCLK/f0 = 199.49 forMAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA = +25°C, unless otherwise noted.)


MAX260A ±0.05 ±0.25

MAX260B ±0.15 ±0.45

MAX261A ±0.40 ±1.00

MAX261B ±0.80 ±1.60

MAX262A ±0.40 ±1.20

TA = TMIN to TMAX, Q = 4Mode 1

MAX262B ±0.80 ±1.60

MAX260A ±0.075 ±0.30

MAX260B ±0.075 ±0.50

MAX261A ±0.50 ±1.10

MAX261B ±0.90 ±1.60

MAX262A ±0.50 ±1.30

Offset Voltage At FilterOutputs—LP, BP, HP (Note 3)

Mode 3

MAX262B ±0.90 ±1.60

V

Offset Voltage TemperatureCoefficient

fCLK/f0 = 100.53, Q = 4TA = TMIN to TMAX

±0.75 mV/°C

Clock Feedthrough ±4 mV

Crosstalk -70 dB

Q = 1, 2nd-Order, LP/BP See Typ. Oper. Char.

4th-Order LP (Figure 26) 90Wideband Noise

4th-Order BP (Figure 24) (Note 4) 100µVRMS

Harmonic Distortion at f0 Q = 4, VIN = 1.5VP-P -67 dB

Supply Voltage Range TA = TMIN to TMAX ±2.37 ±5 ±6.3 V

MAX260 15 20

MAX261 16 20Power Supply Current (Note 5)TA = TMIN to TMAXCMOS Level Logic Inputs

MAX262 16 20mA

Shutdown Supply CurrentQ0A - Q6A = all 0,CMOS Level Logic Inputs (Note 5)

1.5 mA

INTERNAL AMPLIFIERS

Output Signal Swing TA = TMIN to TMAX, 10kΩ load (Note 6) ±4.75 V

Source 50Output Signal Circuit Current

Sink 2mA

Power Supply Rejection Ratio 0Hz to 10kHz -70 dB

Gain Bandwidth Product 2.5 MHz

Slew Rate 6 V/µs

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ELECTRICAL CHARACTERISTICS (for V± = ±2.5V ±5%)(V+ = +2.37V, V- = -2.37V, CLKA = CLKB = ±2.5V 250kHz for the MAX260 and 1MHz for the MAX261/MAX262, fCLK/f0 = 199.49 forMAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA = +25°C, unless otherwise noted.)


f0 Center Frequency Range (Note 7)

Maximum Clock Frequency (Note 7)

MAX26XA ±0.1 1fCLK/f0 Ratio Error(Notes 1, 8)

Q = 8MAX26XB ±0.1 2

%

MAX260A ±2 ±6Q = 8fCLK/f0 = 199.49 MAX260B ±2 ±10

MAX261A ±2 ±6fCLK/f0 = 199.49

MAX261B ±2 ±10

MAX262A ±2 ±6

Q Accuracy (deviation from idealcontinuous filter)(Notes 2, 8)

fCLK/f0 = 139.80MAX262B ±2 ±10

%

Output Signal Swing All Outputs (Note 6) ±2 V

Power Supply Current CMOS Level Logic Inputs (Note 5) 7 mA

Shutdown Current CMOS Level Logic Inputs (Note 5) 0.35 mA

Note 1: fCLK/f0 accuracy is tested at 199.49 on the MAX260/MAX261, and at 139.8 on the MAX262.Note 2: Q accuracy tested at Q = 8, 32, and 64. Q of 32 and 64 tested at 1/2 stated clock frequency.Note 3: The offset voltage is specified for the entire filter. Offset is virtually independent of Q and fCLK/f0 ratio setting. The test clock

frequency for mode 3 is 175kHz for the MAX260 and 750kHz for the MAX261/MAX262.Note 4: Output noise is measured with an RC output smoothing filter at 4 f0 to remove clock feedthrough.Note 5: TTL logic levels are: HIGH = 2.4V, LOW = 0.8V. CMOS logic levels are: HIGH = 5V, LOW = 0V. Power supply current is typi-

cally 4mA higher with TTL logic and clock input levels.Note 6: On the MAX260 only, the HP output signal swing is typically 0.75V less than the LP or BP outputs.Note 7: At ±2.5V supplies, the f0 range and maximum clock frequency are typically 75% of values listed in Table 1.Note 8: fCLK/f0 and Q accuracy are a function of the accuracy of internal capacitor ratios. No increase in error is expected at ±2.5V

as compared to ±5V; however, these parameters are only tested to the extent indicated by the MIN or MAX limits.

INTERFACE SPECIFICATIONS (Note 9)(V+ = +5V, V+ = -5V, TA = +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

WR Pulse Width tWR 250 150 ns

Address Setup tAS 25 ns

Address Hold tAH 0 ns

Data Setup tDS 100 50 ns

Data Hold tDH 10 0 ns

Logic Input High VIHWR, D0, D1, A0–A3, CLKA, CLKBTA =TMIN to TMAX

2.4 V

Logic Input Low VILWR, D0, D1, A0–A3, CLKA, CLKBTA =TMIN to TMAX

0.8 V

10

60Input Leakage Current IINWR, D0, D1, A0–A3, CLKBCLKATA =TMIN to TMAX

6 µA

Input Capacitance CIN WR, D0, D1, A0–A3, CLKA, CLKB 15 pF

Note 9: Interface timing specifications are guaranteed by design and are not subject to test.

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Pin Description

PIN

MAX260MAX261/MAX262

NAME FUNCTION

9 9 V+ Positive supply voltage

17 16 V- Negative supply voltage

18 17 GND

Analog Ground. Connectto the system ground fordual supply operation ormid-supply for single sup-ply operation. GND shouldbe well bypassed in singlesupply applications.

11 11 CLKA

Input to the oscillator andclock input to section A.This clock is internallydivided by 2.

12 12 CLKB

Clock input to filter B. Thisclock is internally dividedby 2.

8 8 CLK OUTC l ock outp ut for cr ystal and R- C osci l l ator op er ati on

19 18 OSC OUTConnects to crystal or R-Cfor self-clocked operation

PIN

MAX260MAX261/MAX262

NAME FUNCTION

5, 23 5, 23 INA, INB Filter inputs

1, 21 1, 21 BPA, BPB Bandpass outputs

24, 22 24, 22 LPA, LPB Lowpass outputs

3, 14 3, 20 HPA, HPBHighpass/notch/allpassoutputs

16 15 WR Write enable input

15, 13,10, 7

14, 13,10, 7

A0, A1,A2, A3

Address inputs for f0 andQ input data locations

20, 6 19, 6 D0, D1Data inputs for f0 and Qprogramming

2 OP OUT

Outp ut of uncom m i tted op am p on M AX 261/M AX 262 onl y. P i n 2 i s a no- connect on the M AX 260.

4 OP IN

Inver ti ng i np ut of uncom - m i tted op am p on M AX 261/M AX 262 onl y ( noni nver ti ng i np ut i s i nter nal l y connected to g r ound ) . P i n 4 i s a no- connect on the M AX 260.

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Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)

-20

-10

10

0

20

30

0.2 0.60.4 0.8 1.0 1.2 1.4

Q ERROR vs. CLOCK FREQUENCYMAX260

MAX

260/

61/6

2 to

c01

CLOCK FREQUENCY (MHz)

Q ER

ROR

(%)

MODE 4±5V25°CQ = 8fCLK/f0 N = 0

MODES 2 & 3

MODE 1

5

10

15

20

25IDD vs. POWER SUPPLY VOLTAGE

MAX

260/

61/6

2 to

c02

V+ TO V- (V)

I DD

(mA)

5 8 96 7 10 11 12

CLK FREQ = 500KHz25°CCONTROL PINS (5V, 0V)

CLOCKS (5V, 0V)

CLOCKS (5V, -5V)

13

15

14

17

16

19

18

20

0.5 1.5 2.5 3.5

IDD vs. CLOCK FREQUENCY

MAX

260/

61/6

2 to

c03


I DD

(mA)

CLOCK (2.4V, 0.8V)

CLOCK (5V, 0V)

±5VCONTROL PINS (5V, 0V)25°C

CLOCK (5V, -5V)

-4

0

4

8

12

16

20

0.5 1.51.0 2.0 2.5 3.0 3.5

Q ERROR vs. CLOCK FREQUENCYMAX261/MAX262

MAX

260/

61/6

2 to

c04


Q ER

ROR

(%)

MODE 3

MODE 2

MODES 1, 4

±5VQ = 8TA = 25°C

N = 0fCLKf0

-1.2

-1.0

-0.8

-0.6

-0.4

-0.2

0

0.2

1.0 1.5 2.0 2.5 3.0 3.5

FCLK/F0 ERROR vs. CLOCK FREQUENCYMAX261/MAX262

MAX

260/

61/6

2 to

c05


F CLK

/F0 E

RROR

(%)

MODES 2, 3

MODES 1, 4±5VQ = 8TA = 25°C

fCLKf0

N = 0

0

2

1

4

3

7

6

5

8

0.2 1.00.6 1.4 1.8 2.2 2.8 3.0

OUTPUT SIGNAL SWINGvs. CLOCK FREQUENCY

MAX

260/

61/6

2 to

c06


PEAK

TO

PEAK

, OUT

PUT

SWIN

G (V

)

MAX261/MAX262 ALL MODES

MAX260 MODE 4

±5V25°CQ = 8fCLK/f0 N = 0

MAX260 MODES 1, 2, 3

Q = 1 Q = 8 Q = 64MODE

LP BP HP/AP/N LP BP HP/AP/N LP BP HP/AP/N

1 -84 -90 -84 -80 -82 -85 -72 -73 -85

2 -88 -90 -88 -84 -82 -84 -77 -73 -76

3 -84 -90 -88 -80 -82 -82 -73 -73 -74

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262

4 -83 -89 -84 -79 -81 -85 -71 -73 -85

1 -87 -89 -86 -81 -81 -86 -73 -73 -86

2 -89 -88 -85 -83 -80 -82 -75 -72 -74

3 -87 -88 -85 -80 -82 -80 -71 -72 -72

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4 -87 -88 -86 -81 -81 -86 -71 -72 -86

MEASUREMENTBANDWIDTH Q = 1 Q = 8 Q = 64

Wideband -84 -80 -72

3kHz -87 -87 -86

C MessageWeighted

-93 -93 -93

Wideband RMS Noise (db ref. to 2.47VRMS, 7VP-P) ±5V Supplies

Note 1: fCLK = 1MHz for MAX261/MAX262, fCLK = 350kHz for MAX260Note 2: fCLK/f0 ratio programmed at N = 63 (see Table 2)Note 3: Clock feedthrough is removed with an RC lowpass ar 4f0, ie., R = 3.9kΩ,

C = 2000pF for MAX261.

Noise Spectral Distribution(MAX261, fCLK = 1MHz, dB ref. to 2.47VRMS,7VP-P)

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IntroductionEach MAX260/MAX261/MAX262 contains two second-order switched-capacitor active filters. Figure 1 showsthe filter's state variable topology, employed with twocascaded integrators and one summing amplifier. TheMAX261 and MAX262 also contain an uncommittedamplifier. On-chip switches and capacitors providefeedback to-control each filter section's f0 and Q.Internal capacitor ratios are primarily responsible forthe accuracy of these parameters. Although theseswitched-capacitor networks (SCN) are in fact sampledsystems, their behavior very closely matches that ofcontinuous filters, such as RC active filters. The ratio ofthe clock frequency to the filter center frequency(fCLK/f0) is kept large so that ideal second-order state-variable response is maintained.

The MAX262 uses a lower range of sampling (fCLK/f0)ratios than the MAX260 or MAX261 to allow higheroperating f0 frequencies and signal bandwidths. Thesereduced sample rates result in somewhat more devia-tion from ideal continuous filter parameters than withthe MAX260/MAX261. However, these differences canbe compensated using Figure 20 (see ApplicationHints) or Maxim's filter design software.

The MAX260 employs auto-zero circuitry not includedin the MAX261 or MAX262. This provides improved DCcharacteristics, and improved low-frequency perform-

ance at the expense of high-end f0 and signal band-width. The N/HP/AP outputs of the MAX260 are internal-ly sample-and-held as a result of i ts auto-zerooperation. Signal swing at this output is somewhatreduced as a result (MAX260 only). See Table 1 forbandwidth comparisons of the three filters.

Maxim also provides design programs that aid in con-verting filter response specifications into the f0 and Qprogram codes used by the MAX260 series devices.This software also precompensates f0 and Q when lowsample rates are used.

It is important to note that, in all MAX260 series filters,the filter's internal sample rate is one half the inputclock rate (CLKA or CLKB) due to an internal divisionby two. All clock-related data, tables, and other dis-cussions in this data sheet refer to the frequency at theCLKA or CLKB input, i.e., twice the internal sample rate,unless specifically stated otherwise.

Quick Look Design ProcedureThe MAX260, MAX261, and MAX262, with Maxim's filterdesign software, greatly simplify the design proceduresfor many active filters. Most designs can be realizedusing a three-step process described in this section. Ifthe design software is not used, or if the filter complexi-ty is beyond the scope of this section, refer to theremainder of this data sheet for more detailed applica-tions and design information.

M1M0

S2

SCNIN

S3S1

MODESELECT

SCN

Q0–Q6(TABLE 3)

F0–F5(TABLE 2)

S1

SAMPLE-HOLDMAX260 ONLY

N/HP/AP

BP

LP

S2

S3

+-

-

SCN = SWITCH-CAPACITOR NETWORK

+

-∫ ∫

SCN

SCN

Σ

S-H

Figure 1. Filter Block Diagram (One Second-Order Section)

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Step 1—Filter DesignStart with the program “PZ” to determine what type off i l ter is needed. This helps determine the type(Butterworth, Chebyshev, etc.) and the number of polesfor the optimum choice. The program also plots the fre-

quency response and calculates the pole/zero (f0) andQ values for each second-order section. EachMAX260/MAX261/MAX262 contains two second-ordersections, and devices can be cascaded for higherorder filters.

MAX260MAX261*MAX262*

INA

OUT

IN5

24

3

1

23

22

(20)14

21

LPA

HPA

BPA

LPB

HPB

BPB

INB

WR

D0

D1

A0

A2

A3

CLKA

CLKB

A1

16(15)

20(19)

6

1

2

345

67

11

2425

23

2221201918

DB-25 MALE PLUG(BACK VIEW)

12

15(14)

10

7

11

12

9 18(17) 17(16) CLK IN

TTL(SEE FIGURE 4)

0.1µF 0.1µF

-5V+5V

13

V+ V-GND

*PIN NUMBERS IN ( ) ARE FOR MAX261/MAX262

100 AB$ = "FILTER A" : GOSUB 150 : REM GET DATA FOR SECTION A110 ADD = 0 : GOSUB 220 : REM WRITE DATA TO THE PRINTER PORT120 AB$ = "FILTER B" : GOSUB 150 : REM GET DATA FOR B130 ADD = 32 : GOSUB 220 : REM WRITE DATA TO PRINTER PORT140 GOTO 100150 PRINT "MODE (1 to 4, see Table 5) "; AB$; : INPUT M160 IF M<1 OR M>4 THEN GOTO 150170 PRINT "CLOCK RATIO (0 to 63, N of Table 2) "; AB$; : INPUT F180 IF F<0 OR F>63 THEN GOTO 170190 PRINT "Q (0 to 127, N of Table 3) "; AB$; : INPUT Q200 IF Q<0 OR Q>127 THEN GOTO 190 ELSE : PRINT210 RETURN220 LPRINT CHR$(ADD+M-1); : ADD = ADD+4230 FOR I = 1 TO 3240 X = (ADD + (F - 4*INT(F/4))) : LPRINT CHR$(X);250 F=INT(F/4) : ADD = ADD + 4260 NEXT I270 FOR I = 1 TO 4280 X=(ADD + (Q - 4*INT(Q/4))) : LPRINT CHR$(X);290 Q=I (Q/4) :: ADD = ADD + 4300 NEXT I310 RETURN

Figure 2. Basic Program and Hardware Connections to Parallel Printer Port for “Quick Look” Using a PC

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Step 2—Generate ProgrammingCoefficients

Starting with the f0 and Q values obtained in Step 1, usethe program “MPP” to generate the digital coefficientsthat program each second-order section's f0 and Q. Theprogram displays values for “N” (“N = _ for f0” and “N =_ for Q”). N is the decimal equivalent of the binary codethat sets the filter section’s f0 or Q. These are the same“N”s that are listed in Tables 2 and 3.

An input clock frequency and filter mode must also beselected in this step; however, if a specific-clock rate isnot selected, “GEN” picks one. With regard to modeselection, mode 1 is the most convenient choice formost bandpass and lowpass filters. Exceptions areelliptic bandpass and lowpass filters, which requiremode 3. Highpass filters also use mode 3, while allpassfilters use mode 4. For further information regardingthese filter modes, see the Filter Operating Modes sec-tion.

Step 3—Loading the FilterWhen the N values for the f0 and Q of each second-order filter section are determined, the filter can then beprogrammed and operated. What follows is a con-venient method of programming the filter and evalu-ating a design if a PC is available.

A short BASIC program loads data into the MAX260/MAX261/MAX262 through the PC's parallel printer port.The program asks for the filter mode, as well as the Nvalues for the f0 and Q of each section. These coeffi-cients are then loaded into the filter in the form of ASCIIcharacters. This program can be used with or withoutMaxim's other filter design software. The program andthe appropriate hardware connections for a Centronics-type printer port are shown in Figure 2.

Filter Design SoftwareMaxim provides software programs to help speed thetransition from frequency response design require-ments to working hardware. A series of programs areavailable, including:

Program PZ. Given the requirements, such as centerfrequency, Q, passband ripple, and stopband attenua-tion, PZ calculates the pole frequencies, Q's, zeros,and the number of stages needed.

Program MPP. For programmed filters, MPP computesthe input codes to use and describes the expectedperformance of the design.

Program FR. When a design of one or more stages iscompleted, FR checks the final cascaded assembly.The output frequency response can be compared withthat expected from PZ.

Program PR.BAS Allows a MAX260/MAX261/MAX262to be programmed through a personal computer. Themode, f0, and Q of each section are typed in, and theproper codes are sent to the filter through the comput-er’s parallel printer port. This program is also providedin Figure 2.

Other design programs are also included for use withother Maxim filter products.

Other Filter ProductsMaxim has developed a number of other filter productsin addition to the MAX260, MAX261, and MAX262.

PIN-PROGRAMMABLE ACTIVE FILTERS—A dual sec-ond-order universal filter that needs no external compo-nents. A microprocessor interface is not required.

MAX263 0.4Hz to 30kHz f0 range

MAX264 1Hz to 75kHz f0 range

RESISTOR AND PIN-PROGRAMMABLE FILTERS—Adual second-order universal filter where f0 adjustmentbeyond pin-programmable resolution employs externalresistors.

MAX265 0.4Hz to 30kHz f0 range. Includes two uncommitted op amps.

MAX266 1Hz to 75kHz f0 range. Includes two un-committed op amps.

MF10 Industry Standard, Resistor Programmed Only

PIN-PROGRAMMABLE BANDPASS FILTERS—Adual second-order bandpass that needs no externalcomponents. A microprocessor interface is notrequired.

MAX267 0.4Hz to 30kHz f0 range

MAX268 1Hz to 75kHz f0 range

PROGRAMMABLE ANTI-ALIAS FILTER—A program-mable dual second-order continuous (not switched)lowpass filter. No clock noise is generated. Designedfor use as an anti-alias filter in front of, or as a smooth-ing filter following, any sampled filter or system.

MAX270 1kHz to 25kHz Cutoff Frequency Range

5th-ORDER LOW PASS FILTER—Features zero offsetand drift errors for designs requiring high DC accuracy.

MAX280, LT1062 0.1Hz to 20kHz Cutoff FrequencyRange

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PART Q MODE fCLK f0

1 1 1Hz–400kHz 0.01Hz–4.0kHz

1 2 1Hz–425kHz 0.01Hz–6.0kHz

1 3 1Hz–500kHz 0.01Hz–5.0kHz

1 4 1Hz–400kHz 0.01Hz–4.0kHz

8 1 1Hz–500kHz 0.01Hz–5.0kHz

8 2 1Hz–700kHz 0.01Hz–10.0kH

8 3 1Hz–700kHz 0.01Hz–5.0kHz

8 4 1Hz–600kHz 0.01Hz–4.0kHz

64 1 1Hz–750kHz 0.01Hz–7.5kHz

90 2 1Hz–500kHz 0.01Hz–7.0kHz

64 3 1Hz–400kHz 0.01Hz–4.0kHz

MAX260

64 4 1Hz–750kHz 0.01Hz–7.5kHz

1 1 40Hz–4.0MHz 0.4Hz–40kHz

1 2 40Hz–4.0MHz 0.5Hz–57kHz

1 3 40Hz–4.0MHz 0.4Hz–40kHz

1 4 40Hz–4.0MHz 0.4Hz–40kHz

8 1 40Hz–2.7MHz 0.4Hz–27kHz

8 2 40Hz–2.1MHz 0.5Hz–30kHz

MAX261

PART Q MODE fCLK f0

8 3 40Hz–1.7MHz 0.4Hz–17kHz

8 4 40Hz–2.7MHz 0.4Hz–27kHz

64 1 40Hz–2.0MHz 0.4Hz–20kHz

90 2 40Hz–1.2MHz 0.4Hz–18kHz

64 3 40Hz–1.2MHz 0.4Hz–12kHz

MAX261

64 4 40Hz–2.0MHz 0.4Hz–20kHz

1 1 40Hz–4.0MHz 1.0Hz–100kHz

1 2 40Hz–4.0MHz 1.4Hz–140kHz

1 3 40Hz–4.0MHz 1.0Hz–100kHz

1 4 40Hz–4.0MHz 1.0Hz–100kHz

8 1 40Hz–2.5MHz 1.0Hz–60kHz

6 2 40Hz–1.4MHz 1.4Hz–50kHz

8 3 40Hz–1.4MHz 1.0Hz–35kHz

8 4 40Hz–2.5MHz 1.0Hz–60kHz

64 1 40Hz–1.5MHz 1.0Hz–37kHz

90 2 40Hz–0.9MHz 1.4Hz–32kHz

64 3 40Hz–0.9MHz 1.0Hz–22kHz

MAX262

64 4 40Hz–1.5MHz 1.0Hz–37kHz

Table 1. Typical Clock and Center Frequency Limits

INA LPAN/HP/APA BPA

2 6 7

2 4

A0–A3 WR CLKA CLKBOSC OUT CLK OUT OP OUTOP IND0, D1

MODE

A PROGRAM MEMORYMODE, f0, Q

INTERFACE LOGIC

÷2

f0

15

Q CK

INB LPBN/HP/APB BPB

2 6 7

MODE

B PROGRAM MEMORYMODE, f0, Q

÷2

f0

V+

15

Q CK

V-

GND

+

-

MAX261/MAX262 ONLY

∫ ∫ ∫ ∫

Figure 3. MAX260/MAX261/MAX262 Block Diagram

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fCLK/f0 RATIOMAX260/MAX261 MAX262

PROGRAM CODE

MODES 1,3,4 MODE 2 MODES 1,3,4 MODE 2 N F5 F4 F3 F2 F1 F0100.53 71.09 40.84 28.88 0 0 0 0 0 0 0102.10 72.20 42.41 29.99 1 0 0 0 0 0 1103.67 73.31 43.98 31.10 2 0 0 0 0 1 0105.24 74.42 45.55 32.21 3 0 0 0 0 1 1106.81 75.53 47.12 33.32 4 0 0 0 1 0 0108.38 76.64 48.69 34.43 5 0 0 0 1 0 1109.96 77.75 50.27 35.54 6 0 0 0 1 1 0111.53 78.86 51.84 36.65 7 0 0 0 1 1 1113.10 79.97 53.41 37.76 8 0 0 1 0 0 0114.67 81.08 54.98 38.87 9 0 0 1 0 0 1116.24 82.19 56.55 39.99 10 0 0 1 0 1 0117.81 83.30 58.12 41.10 11 0 0 1 0 1 1119.38 84.42 59.69 42.21 12 0 0 1 1 0 0120.95 85.53 61.26 43.32 13 0 0 1 1 0 1122.52 86.64 62.83 44.43 14 0 0 1 1 1 0124.09 87.75 64.40 45.54 15 0 0 1 1 1 1125.66 88.86 65.97 46.65 16 0 1 0 0 0 0127.23 89.97 67.54 47.76 17 0 1 0 0 0 1128.81 91.80 69.12 48.87 18 0 1 0 0 1 0130.38 92.19 70.69 49.98 19 0 1 0 0 1 1131.95 93.30 72.26 51.10 20 0 1 0 1 0 0133.52 94.41 73.83 52.20 21 0 1 0 1 0 1135.08 95.52 75.40 53.31 22 0 1 0 1 1 0136.66 96.63 76.97 54.43 23 0 1 0 1 1 1138.23 97.74 78.53 55.54 24 0 1 1 0 0 0139.80 98.86 80.11 56.65 25 0 1 1 0 0 1141.37 99.97 81.68 57.76 26 0 1 1 0 1 0142.94 101.08 83.25 58.87 27 0 1 1 0 1 114.4.51 102.89 84.82 59.98 28 0 1 1 1 0 0146.08 103.30 86.39 61.09 29 0 1 1 1 0 1147.65 104.41 87.96 62.20 30 0 1 1 1 1 0149.23 105.52 89.54 63.31 31 0 1 1 1 1 1150.80 106.63 91.11 64.42 32 1 0 0 0 0 0152.37 107.74 92.68 65.53 33 1 0 0 0 0 1153.98 108.85 94.25 66.64 34 1 0 0 0 1 0155.51 109.96 95.82 67.75 35 1 0 0 0 1 1157.08 111.07 97.39 68.86 36 1 0 0 1 0 0158.65 112.18 98.96 69.98 37 1 0 0 1 0 1160.22 113.29 100.53 71.09 38 1 0 0 1 1 0161.79 114.41 102.10 72.20 39 1 0 0 1 1 1163.36 115.52 102.67 73.31 40 1 0 1 0 0 0164.93 116.63 105.24 74.42 41 1 0 1 0 0 1166.50 117.74 106.81 75.53 42 1 0 1 0 1 0168.08 118.85 108.38 76.64 43 1 0 1 0 1 1169.65 119.96 109.96 77.75 44 1 0 1 1 0 0171.22 121.07 111.53 78.86 45 1 0 1 1 0 1

Table 2. fCLK/f0 Program Selection Table

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Detailed Descriptionf0 and Q Programming

Figure 3 shows a block diagram of the MAX260. Eachsecond-order filter section has its own clock input andindependent f0 and Q control. The actual center fre-quency is a function of the filter's clock rate, 6-bit f0control word (see Table 2), and operating mode. The Qof each section is also set by a separate programmedinput (see Table 3). This way, each half of a MAX260/MAX261/MAX262 is tuned independently so that com-plex filter polynomials can be realized. Equations thatconvert program code numbers to fCLK/f0 and Q valuesare listed in the notes beneath Tables 2 and 3.

Oscillator and Clock InputsThe clock circuitry of the MAX260/MAX261/MAX262can operate with a crystal, resistor-capacitor (RC) net-work, or an external clock generator as shown in Figure4. If an RC oscillator is used, the clock rate, fCLK, nomi-nally equals 0.45/RC.

The duty cycle of the clock at CLKA and CLKB is unim-portant because the input is internally divided by 2 togenerate the sampling clock for each filter section. It isimportant to note that this internal division also halvesthe sample rate when considering aliasing and othersampled system phenomenon.

Microprocessor Interface f0, Q, and mode-selection data are stored in internalprogram memory. The memory contents are updatedby writing to addresses selected by A0–A3. D0, and D1are the data inputs. A map of the memory locations isshown in Table 4. Data is stored in the selectedaddress on the rising edge of WR. Address and datainputs are TTL and CMOS compatible when the filter ispowered from ±5V. With other power supply voltages,CMOS logic levels should be used. Interface timing isshown in Figure 5. Note: Clock inputs CLKA and CLKBhave no relation to the digital interface. They control theswitched-capacitor filter sample rate only.

Some noise may be generated on the filter outputs bytransitions at the logic inputs. If this is objectionable,

fCLK/f0 RATIOMAX260/MAX261 MAX262

PROGRAM CODE

MODES 1,3,4 MODE 2 MODES 1,3,4 MODE 2 N F5 F4 F3 F2 F1 F0172.79 122.18 113.10 79.97 46 1 0 1 1 1 0174.36 123.29 114.66 81.08 47 1 0 1 1 1 1175.93 124.40 11624 82.19 48 1 1 0 0 0 0177.50 125.51 117.81 83.30 49 1 1 0 0 0 1179.07 126.62 119.38 84.41 50 1 1 0 0 1 0180.64 127.73 120.95 85.53 51 1 1 0 0 1 1182.21 128.84 122.52 86.64 52 1 1 0 1 0 0183.78 129.96 124.09 87.75 53 1 1 0 1 0 1185.35 131.07 125.66 88.86 54 1 1 0 1 1 0186.92 132.18 127.23 89.97 55 1 1 0 1 1 1188.49 133.29 128.81 91.08 56 1 1 1 0 0 0190.07 134.40 130.38 92.19 57 1 1 1 0 0 1191.64 135.51 131.95 93.30 58 1 1 1 0 1 0193.21 136.62 133.52 94.41 59 1 1 1 0 1 1194.78 137.73 135.09 95.52 60 1 1 1 1 0 0196.35 138.84 136.66 96.63 61 1 1 1 1 0 1197.92 139.95 138.23 97.74 62 1 1 1 1 1 0199.49 141.06 139.80 98.85 63 1 1 1 1 1 1

Table 2. fCLK/f0 Program Selection Table (continued)

Note 1: For the MAX260/MAX261, fCLK/f0 = (64 + N)π / 2 in modes 1, 3, and 4, where N varies from 0 to 63.Note 2: For the MAX262, fCLK/f0 = (26 s N)π / 2 in modes 1, 3, and 4, where N varies 0 to 63.Note 3: In mode 2, all fCLK/f0 ratios are divided by √2. The functions are then:

MAX260/MAX261 fCLK/f0 = 1.11072 (64 + N), MAX262 fCLK/f0 = 1.11072 (26 + N)

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PROGRAMMED Q PROGRAM CODE

MODES1,3,4

MODE2 N Q6 Q5 Q4 Q3 Q2 Q1 Q0

0.500* 0.707* 0* 0 0 0 0 0 0 0

0.504 0.713 1 0 0 0 0 0 0 1

0.508 0.718 2 0 0 0 0 0 1 0

0.512 0.724 3 0 0 0 0 0 1 1

0.516 0.730 4 0 0 0 0 1 0 0

0.520 0.736 5 0 0 0 0 1 0 1

0.525 0.742 6 0 0 0 0 1 1 0

0.529 0.748 7 0 0 0 0 1 1 1

0.533 0.754 8 0 0 0 1 0 0 0

0.538 0.761 9 0 0 0 1 0 0 1

0.542 0.767 10 0 0 0 1 0 1 0

0.547 0.774 11 0 0 0 1 0 1 1

0.552 0.780 12 0 0 0 1 1 0 0

0.556 0.787 13 0 0 0 1 1 0 1

0.561 0.794 14 0 0 0 1 1 1 0

0.566 0.801 15 0 0 0 1 1 1 1

0.571 0.808 16 0 0 1 0 0 0 0

0.577 0.815 17 0 0 1 0 0 0 1

0.582 0.823 18 0 0 1 0 0 1 0

0.587 0.830 19 0 0 1 0 0 1 1

0.593 0.838 20 0 0 1 0 1 0 0

0.598 0.646 21 0 0 1 0 1 0 1

0.604 0.854 22 0 0 1 0 1 1 0

0.609 0.862 23 0 0 1 0 1 1 1

PROGRAMMED Q PROGRAM CODE

MODES1,3,4

MODE2 N Q6 Q5 Q4 Q3 Q2 Q1 Q0

0.615 0.870 24 0 0 1 1 0 0 0

0.621 0.879 25 0 0 1 1 0 0 1

0.627 0.887 26 0 0 1 1 0 1 0

0.634 0.896 27 0 0 1 1 0 1 1

0.640 0.905 28 0 0 1 1 1 0 0

0.646 0.914 29 0 0 1 1 1 0 1

0.653 0.924 30 0 0 1 1 1 1 0

0.660 0.933 31 0 0 1 1 1 1 1

0.667 0.943 32 0 1 0 0 0 0 0

0.674 0.953 33 0 1 0 0 0 0 1

0.681 0.963 34 0 1 0 0 0 1 0

0.688 0.973 35 0 1 0 0 0 1 1

0.696 0.984 36 0 1 0 0 1 0 0

0.703 0.995 37 0 1 0 0 1 0 1

0.711 1.01 38 0 1 0 0 1 1 0

0.719 1.02 39 0 1 0 0 1 1 1

0.727 1.03 40 0 1 0 1 0 0 0

0.736 1.04 41 0 1 0 1 0 0 1

0.744 1.05 42 0 1 0 1 0 1 0

0.753 1.06 43 0 1 0 1 0 1 1

0.762 1.08 44 0 1 0 1 1 0 0

0.771 1.09 45 0 1 0 1 1 0 1

0.780 1.10 46 0 1 0 1 1 1 0

0.790 1.12 47 0 1 0 1 1 1 1

Table 3. Q Program Selection Table

Note 4: * Writing all 0s into Q0A–Q6A on Filter A activates a low-power shutdown mode. BOTH filter sections are deactivated.Therefore, this Q value is only achievable in filter B.

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PROGRAMMED Q PROGRAM CODEMODES

1,3,4MODE

2N Q6 Q5 Q4 Q3 Q2 Q1 Q0

0.800 1.13 48 0 1 1 0 0 0 00.810 1.15 49 0 1 1 0 0 0 10.821 1.16 50 0 1 1 0 0 1 00.831 1.18 51 0 1 1 0 0 1 10.842 1.19 52 0 1 1 0 1 0 00.853 1.21 53 0 1 1 0 1 0 10.865 1.22 54 0 1 1 0 1 1 00.877 1.24 55 0 1 1 0 1 1 10.889 1.26 56 0 1 1 1 0 0 00.901 1.27 57 0 1 1 1 0 0 10.914 1.29 58 0 1 1 1 0 1 00.928 1.31 59 0 1 1 1 0 1 10.941 1.33 60 0 1 1 1 1 0 00.955 1.35 61 0 1 1 1 1 0 10.969 1.37 62 0 1 1 1 1 1 00.985 1.39 63 0 1 1 1 1 1 11.00 1.41 64 1 0 0 0 0 0 01.02 1.44 65 1 0 0 0 0 0 11.03 1.46 66 1 0 0 0 0 1 01.05 1.48 67 1 0 0 0 0 1 11.07 1.51 68 1 0 0 0 1 0 01.08 1.53 69 1 0 0 0 1 0 11.10 1.56 70 1 0 0 0 1 1 01.12 1.59 71 1 0 0 0 1 1 11.14 1.62 72 1 0 0 1 0 0 01.16 1.65 73 1 0 0 1 0 0 11.19 1.68 74 1 0 0 1 0 1 01.21 1.71 75 1 0 0 1 0 1 11.23 1.74 76 1 0 0 1 1 0 01.25 1.77 77 1 0 0 1 1 0 11.28 1.81 78 1 0 0 1 1 1 01.31 1.85 79 1 0 0 1 1 1 11.33 1.89 80 1 0 1 0 0 0 01.36 1.93 81 1 0 1 0 0 0 11.39 1.97 82 1 0 1 0 0 1 01.42 2.01 83 1 0 1 0 0 1 11.45 2.06 84 1 0 1 0 1 0 01.49 2.10 85 1 0 1 0 1 0 11.52 2.16 86 1 0 1 0 1 1 01.56 2.21 87 1 0 1 0 1 1 1

PROGRAMMED Q PROGRAM CODEMODES

1,3,4MODE

2N Q6 Q5 Q4 Q3 Q2 Q1 Q0

1.60 2.26 88 1 0 1 1 0 0 01.64 2.32 89 1 0 1 1 0 0 11.68 2.40 90 1 0 1 1 0 1 01.73 2.45 91 1 0 1 1 0 1 11.78 2.51 92 1 0 1 1 1 0 01.83 2.59 93 1 0 1 1 1 0 11.88 2.66 94 1 0 1 1 1 1 01.94 2.74 95 1 0 1 1 1 1 12.00 2.83 96 1 1 0 0 0 0 02.06 2.92 97 1 1 0 0 0 0 12.13 3.02 98 1 1 0 0 0 1 02.21 3.12 99 1 1 0 0 0 1 12.29 3.23 100 1 1 0 0 1 0 02.37 3.35 101 1 1 0 0 1 0 12.46 3.48 102 1 1 0 0 1 1 02.56 3.62 103 1 1 0 0 1 1 12.67 3.77 104 1 1 0 1 0 0 02.78 3.96 105 1 1 0 1 0 0 12.91 4.11 106 1 1 0 1 0 1 03.05 4.31 107 1 1 0 1 0 1 13.20 4.53 108 1 1 0 1 1 0 03.37 4.76 109 1 1 0 1 1 0 13.56 5.03 110 1 1 0 1 1 1 03.76 5.32 111 1 1 0 1 1 1 14.00 5.66 112 1 1 1 0 0 0 04.27 6.03 113 1 1 1 0 0 0 14.57 6.46 114 1 1 1 0 0 1 04.92 6.96 115 1 1 1 0 0 1 15.33 7.54 116 1 1 1 0 1 0 05.82 8.23 117 1 1 1 0 1 0 16.40 9.05 118 1 1 1 0 1 1 07.11 10.1 119 1 1 1 0 1 1 18.00 11.3 120 1 1 1 1 0 0 09.14 12.9 121 1 1 1 1 0 0 110.7 15.1 122 1 1 1 1 0 1 012.8 18.1 123 1 1 1 1 0 1 116.0 22.6 124 1 1 1 1 1 0 021.3 30.2 125 1 1 1 1 1 0 132.0 45.3 126 1 1 1 1 1 1 064.0 90.5 127 1 1 1 1 1 1 1

Table 3. Q Program Selection Table (continued)

Notes 5) In modes 1, 3, and 4: Q = 64 / (128 - N)6) In mode 2, the listed Q values are those of mode 1 multiplied by √2. Then Q = 90.51 / (128 - N)

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______________________________________________________________________________________ 15

the digital lines should be buffered from the device bylogic gates as shown in Figure 6.

Shutdown ModeThe MAX260/MAX261/MAX262 enters a shutdown/standby mode when all zeroes are written to the Qaddresses of filter A (Q0A–Q6A). When shut down,power consumption with ±5V supplies typically dropsto 10mW. When reactivating the filter after shutdown,allow 2ms to return to full operation.

Filter Operating ModesThere are several ways in which the summing amplifierand integrators in each MAX260/MAX261/MAX262 filtersection can be configured. The four most versatileinterconnections (modes) are selected by writing to

inputs M0 and M1 (see Tables 4 and 5). These modesuse no external components. A fifth mode, 3A, makesuse of an additional op amp (included in the MAX261and MAX262) and external resistors, but uses the sameinternal configuration and is selected with the sameprogramming code, as mode 3.

FILTER B

CLKOUT

12CLKB

fCLK = 0.45RC

8

OSCOUT

19(18)*CR

11

CLKA

FILTER A

FILTER B

CLKOUT CLKB

OSCOUT

CLKA

FILTER A

12819(18)*11

CRYSTAL

*OSC OUT IS PIN 18 ON MAX261/MAX262

FILTER B

CLKOUT

12CLKB

OSCOUT

N.C.11

CLKA

FILTER A

N.C.

EXTERNAL CLOCK IN(ANY DUTY CYCLE)

Figure 4. Clock Input Connections

DATA BIT ADDRESSD0 D1 A3 A2 A1 A0

LOCATION

FILTER AM0A M1A 0 0 0 0 0F0A F1A 0 0 0 1 1F2A F3A 0 0 1 0 2F4A F5A 0 0 1 1 3Q0A Q1A 0 1 0 0 4Q2A Q3A 0 1 0 1 5Q4A Q5A 0 1 1 0 6Q6A 0 1 1 1 7

FILTER BM0B M1B 1 0 0 0 8F0B F1B 1 0 0 1 9F2B F3B 1 0 1 0 10F4B F5B 1 0 1 1 11Q0B Q1B 1 1 0 0 12Q2B Q3B 1 1 0 1 13Q4B Q5B 1 1 1 0 14Q6B 1 1 1 1 15

Table 4. Program Address Locations

Note: Writing 0 into Q0A–Q6A (address locations 4–7) on filterA activates shutdown mode. BOTH filter sections deactivate.

D0, D1

WR

VALID DATA

tDS tDH

tWR

VALID ADDRESS

tAS

A0–A3

SEE INTERFACE SPECIFICATIONS FOR TIMING LIMITS

tAH

Figure 5. Interface Timing

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Figures 7 through 11 show symbolic representations ofthe MAX260 filter modes. Only one second-order sec-tion is shown in each case. The A and B sections ofone MAX260/MAX261/MAX262 can be programmed for

different modes if desired. The f0, fN (notch), Q, andvarious output gains in each case are shown in Table 5.

Filter Mode SelectionMODE 1 (Figure 7) is useful when implementing allpolelowpass and bandpass filters such as Butterworth,Chebyshev, Basset, etc. It can also be used for notchfilters, but only second-order notches because the rela-tive pole and zero locations are fixed. Higher ordernotch filters require more latitude in f0 and 1N, which iswhy they are more easily implemented with mode 3A.

1D3

4

7

8

13

14

2D

3D

4D

6D

WR

5D

1Q

2Q

3Q

20OCTAL D FLIP-FLOP

74HC374

VCC

5Q

6Q

4Q

A0

A1

A2

D1

D2

A3

2

5

6

12

15

1 10 11

-5V

9

OC CKGND

MAX260MAX261MAX262

A0

A1

A2

A3

D2

D1

+5V

V+

-5V

V-

GNDWR

Figure 6. Buffering/Latching Logic Inputs

SCNIN

SCN N BP

LP+-

-

MODE 1

+

-∫ ∫

SCN

Σ

SCN = SWITCHED-CAPACITOR NETWORK

Figure 7. Filter Mode 1: Second-Order Bandpass, Lowpass,and Notch

MODEM1,M0

FILTERFUNCTIONS

f0 Q fN HOLP HOBPHON1(f 0)

HON2(f fCLK/4)

OTHER

1 0, 0 LP, BP, N f0 -1 -Q -1 -12 0, 1 LP, BP, N f0√2 -0.5 -Q/√2 -0.5 -13 1, 0 LP, BP, HP -1 -Q HOHP = -1

-1 -Q HOHP = -1

4 1, 1 LP, BP, AP

SE

E T

AB

LE 2

SE

E T

AB

LE 3

-2 -2QHOAP = -1fZ = f0, QZ = Q

Table 5. Filter Modes for Second-Order Functions

Notes: f0 = Center Frequency

fN = Notch Frequency

HOLP = Lowpass Gain at DC

HOBP = Bandpass Gain at f0

HOHP = Highpass Gain as f approaches fCLK/4

HON1 = Notch Gain as f approaches DC

HON2 = Notch Gain as f approaches fCLK/4

HOAP = Allpass Gain

fz, Qz = f and Q of Complex Pole Pair

+ RR

G

H + R

RG

L f

RR

H

L0

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Mode 1, along with mode 4, supports the highest clockfrequencies (see Table 1) because the input summingamplifier is outside the filter’s resonant loop (Figure 7).The gain of the lowpass and notch outputs is 1, whilethe bandpass gain at the center frequency is Q. Forbandpass gains other than Q, the filter input or outputcan be scaled by a resistive divider or op amp.

MODE 2 (Figure 8) is used for all-pole lowpass andbandpass filters. Key advantages compared to mode 1are higher available Qs (see Table 3) and lower outputnoise. Mode 2’s available fCLK/f0 ratios are √2 less thanwith mode 1 (see Table 2), so a wider overall range off0s can be selected from a single clock when bothmodes are used together. This is demonstrated in theWide Passband Chebyshev Bandpass design example.

MODE 3 (Figure 9) is the only mode that produceshigh-pass filters. The maximum clock frequency issomewhat less than with mode 1 (see Table 1).

MODE 3A (Figure 10) uses a separate op amp to sumthe highpass and lowpass outputs of mode 3, creatinga separate notch output. This output allows the notch tobe set independently of f0 by adjusting the op amp’sfeedback resistor ratio (RH, RL). RH, RL, and RG areexternal resistors. Because the notch can be indepen-dently set, mode 3A is also useful when designingpole-zero filters such as elliptics.

MODE 4 (Figure 11) is the only mode that provides anallpass output. This is useful when implementing groupdelay equalization. In addition to this, mode 4 can alsobe used in all pole lowpass and bandpass filters. Alongwith mode 1, it is the fastest operating mode for the fil-ter, although the gains are different than in mode 1.When the allpass function is used, note that someamplitude peaking occurs (approximately 0.3dB whenQ = 8) at f0. Also note that f0 and Q sampling errors arehighest in mode 4 (see Figure 20).

SCNIN

SCN N BP

LP+-

-

MODE 2

+

-∫ ∫

SCN

SCN

Σ

Figure 8. Filter Mode 2: Second-Order Bandpass, Lowpass,and Notch

SCNIN

SCN HP BP

LP+-

-

MODE 3

+

-∫ ∫

SCN

SCN

Σ


Figure 9. Filter Mode 3: Second-Order Bandpass, Lowpass,and Highpass

SCNIN

SCN HP

RG

RH

RL

BP

LP+-

-

MODE 3A

N

+

-

+

-

∫ ∫

SCN

SCN

Σ


Figure 10. Filter Mode 3a: Second-Order Bandpass, Lowpass,Highpass, and Notch. For elliptic LP, BP, HP, and Notch, the Noutput is used.

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Description of Filter FunctionsBANDPASS (Figure 12)

For all pole bandpass and lowpass filters (Butterworth,Bessel, Chebyshev) use mode 1 if possible. If appropri-ate fCLK/f0 or Q values are not available in mode 1,mode 2 provides a selection that is closer to therequired values. Mode 1, however, has the highestbandwidth (see Table 1). For pole-zero filters, such aselliptics, see mode 3A.

HOBP = Bandpass output gain at ω = ωo

f0 = ω0 / 2π = The center frequency of the complexpole pair. Input-output phase shift is -180° at f0.

Q = The quality factor of the complex pole pair.Also the ratio of f0 to -3dB bandwidth of thesecond-order bandpass response.

LOWPASS See bandpass text. (Figure 13)

HOLP = Lowpass output gain at DC

f0 = ω0 / 2πHIGHPASS (Figure 14)

Mode 3 is the only mode with a highpass output. Itworks for all pole filter types such as Butterworth,Bessel and Chebyshev. Use mode 3A for fi ltersemploying both poles and zeros, such as elliptics.

HOHP = Highpass output gain as f approaches fCLK/4

f0 = ω0 / 2πNOTCH (Figure 15)

Mode 3A is recommended for multi-pole notch filters. Insecond-order filters, mode 1 can also be used. Theadvantages of mode 1 are higher bandwidth, com-pared to mode 3 (higher fN can be implemented), andno need for external components as required in mode3A.

HON2 = Notch output gain as f approaches fCLK/4

HON1 = Notch output gain as f approaches DC

fn = ωn / 2πALLPASS

Mode 4 is the only configuration in which an allpassfunction can be realized.

G s H s

s s QON

n

o o( )

( / ) = +

+ +2

2

2

2

2

ω

ω ω

G s H

s

s s QOHP

o o( )

( / ) =

+ +

2

2 2ω ω

G s H

s s QOLP

o

o o( )

( / ) =

+ +

ω

ω ω

2

22

G s Hs Q

s s QOBP

o

o o( )

( / )

( / ) =

+ +

ω

ω ω2 2

SCNIN

SCN AP

LP+-

-

MODE 4

BP

+

-∫ ∫

SCN

Σ


Figure 11. Filter Mode 4: Second-Order Bandpass, Lowpass,and Allpass

fL fO fH

HOBP

0.707 HOBP

BANDPASS OUTPUT

f(LOG SCALE)

GAIN

(V/V

)

Figure 12. Second-Order Bandpass Characteristics

Qf

f ff

f fQ Q

f fQ Q

O

H LO f f

L O

H O

L H

,

=−

= − +

+

= +

+

=

12

12

1

12

12

1

2

2

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HOAP = Allpass output gain for DC < f < fCLK / 4f0 = ω0 / 2π

Filter Design Procedure The procedure for most filter designs is to first convertthe required frequency response specifications to f0sand Qs for the appropriate number of second-ordersections that implement the filter. This can be done byusing design equations or tables in available liter-ature, or can be conveniently calculated using Maxim'sfilter design software. Once the f0s and Qs have beenfound, the next step is to turn them into the digital pro-gram coefficients required by the MAX260/MAX261/MAX262. An operating mode and clock frequency (orclock/center frequency ratio) must also be selected.

Next, if the sample rate (fCLK/2) is low enough to causesignificant errors, the selected f0s and Qs should becorrected to account for sampling effects by usingFigure 20 or Maxim's design software. In most cases,the sampling errors are small enough to require no cor-rection, i.e., less than 1%. In any case, with or withoutcorrection, the required f0s and Qs can then be select-ed from Tables 2 and 3. Maxim's filter design software

G s H s s Q

s s QOAP

o o

o o( )

( / )

( / ) = − +

+ +

2

2

2

2

ω ω

ω ω

fP fC

HOP

0.707 HOLP

HOLP

LOWPASS OUTPUT

f(LOG SCALE)

GAIN

(V/V

)

Figure 13. Second-Order Lowpass Characteristics

f f XQ Q

fp fQ

H H X

Q Q

C O

O

OP OLP

=

+

+

=

=

− −

−

−

11

21

1

21

11

21

11

1

4

2 2

2

2

2

fC fP

HOP

0.707 HOHP

HOHP

HIGHPASS OUTPUT

f(LOG SCALE)

GAIN

(V/V

)

Figure 14. Second-Order Highpass Characteristics

f f XQ Q

fp fQ

H H X

Q Q

C O

O

OP OHP

=

+

+

=

=

− −

−

−

11

21

1

21

11

21

11

1

4

2 2

2

2

2

f(LOG SCALE)

GAIN

(V/V

)

fN

HON1

HON

HON2

Figure 15. Second-Order Notch Characteristics

TOTAL SECTIONS TOTAL B.W. TOTAL Q

1 1.000 B 1.00 Q

2 0.644 B 1.55 Q

3 0.510 B 1.96 Q

4 0.435 B 2.30 Q

5 0.386 B 2.60 Q

Table 6. Cascading Identical BandpassFilter Sections

Note: B = individual stage bandwidth, Q = individualstage Q.

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20 ______________________________________________________________________________________

can also perform this last step. The desired f0s and Qsare stated, and the appropriate digital coefficients aresupplied.

Cascading FiltersIn some designs, such as very narrow band filters, sev-eral second-order sections with identical center fre-quency can be cascaded. The total Q of the resultantfilter is:

Q is the Q of each individual filter section, and N is thenumber of sections. In Table 6, the total Q and band-width are listed for up to five identical second-ordersections. B is the bandwidth of each section.

In high-order bandpass filters, stages with different f0sand Qs are also often cascaded. When this happens,the overall filter gain at the bandpass center frequencyis not simply the product of the individual gainsbecause f0, the frequency where each sections gain isspecified, is different for each second-order section.The gain of each section at the cascaded filter's centerfrequency must be determined to obtain the total gain.

For all-pole filters the gain, H(f0), as each second-ordersection's f0 is divided by an adjustment factor, G, toobtain that section's gain, H(f0BP), at the overall centerfrequency:

H1(f0BP) = H(f01) / G1 = Section 1’s Gain at f0BP

where F1 = f01 / fOBP

G1, Q1, and f01 are the gain adjustment factor, Q, andf0 for the first of the cascaded second-order sections.The gain of the other sections (2, 3, etc.) at f0BP isdetermined the same way. The overall gain is:

H(f0Bp) = H1(f0BP) x H2(f0BP) x etc.

For cascaded filters with zeros (fZ) such as elliptics, thegain adjustment factor for each stage is:

where F1Z = fz1 / f0BP, and F1 is the same as above.

Application HintsPower Supplies

The MAX260/MAX261/MAX262 can be operated with avariety of power supply configurations, including +5V to+12V single supply or ±2.5V to ±5V dual supplies.When a single supply is used, V- is connected to sys-tem ground and the filter's GND pin should be biasedat V+/2. The input signal is then either capacitively cou-pled to the filter input or biased to V+/2. Figure 16shows circuit connections for single-supply operation.

When power supplies other than ±5V are used, CMOSinput logic levels (HIGH = V+, LOW = GND or V-) arerequired for WR, D0, D1, A0–A3, OLKA, and CLKB.With ±5V supplies, either TTL or CMOS levels can beused. Note, however, that power consumption at ±5V isreduced if CLKA and CLKB are driven with ±5V, ratherthan TTL or 0 to 5V levels. Operation with +5V or ±2.5Vpower lowers power consumption, but also reducesbandwidth by approximately 25% compared to +12V or±5V supplies.

Best performance is achieved if V+ and V- are bypassedto ground with 4.7µF electrolytic (Tantalum is preferred.)and 0.1µF ceramic capacitors. These should be locatedas close to the supply pins as possible. The lead lengthof the bypass capacitors should be shortest at the V+

and V- pins. When using a single supply, V+ and GNDshould be bypassed to V- as shown in Figure 16.

Output Swing and ClippingMAX260/MAX261/MAX262 outputs are designed todrive 10kΩ loads. For the MAX261 and MAX262, all fil-ter outputs swing to within 0.15V of each supply railwith a 10kΩ load. In the MAX260 only, an internal sam-ple-hold circuit reduces voltage swing at the N/HP/APoutput compared to LP and BR. N/HP/AP, therefore,swings to within 1V (10kΩ load) of either rail on theMAX260.

To ensure that the outputs are not driven beyond theirmaximum range (output clipping), the peak amplituderesponse, individual section gains (HOBP, HOLP,HOHP), input signal level, and filter offset voltages mustbe carefully considered. It is especially important tocheck unused outputs for clipping (i.e., the lowpassoutput in a bandpass hookup), because overload atany filter stage severely distorts the overall response.The maximum signal swing with ±4.75V supplies and a1.0V filter offset is approximately ±3.5V.

For example, lets assume a fourth-order lowpass filter isbeing implemented with a Q of 2 using mode 1. With asingle 5V supply (i.e., ±2.5V with respect to chip GND)the maximum output signal is ±2V (w.r.t. GND). Since in

GQ F F F F Q

F F

Z

Z1

1 12

12

12 2

1 12 1 2

12

12

1

1

( ) ( / )

/

=−

− +

−

GQ F F Q

F11 1

2 21 1

2 1 2

1

1

( ) ( / )/

=− +

Total QQ

TN

/

=−( )2 11

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______________________________________________________________________________________ 21

mode 1 the maximum signal is 0 times the input signal,the input should not exceed ±(2/Q)V, or ±1V in this case.

Clock Feedthrough and NoiseTypical wideband noise for MAX260 series devices is0.5mVP-P from DC to 100kHz. The noise is virtuallyindependent of clock frequency. In multistage filters,the section with the highest Q should be placed first forlower output noise.

The output waveform of the MAX260 series and otherswitched capacitor filters appears as a sampled signalwith stepping or “staircasing” of the output waveformoccurring at the internal sample rate (fCLK/2). This step-ping, if objectionable, can be removed by adding a sin-gle-pole AC filter. With no input signal, clock-relatedfeedthrough is approximately 8mVP-P. This can also beattenuated with an RC-smoothing filter as shown withthe MAX261 in Figure 17.

Some noise also can be generated at the filter outputsby transitions at the logic inputs. If this is objectionable,the digital lines should be buffered from the device bylogic gates as shown in Figure 6.

Input ImpedanceThe input to each filter is the switched capacitor circuitshown in Figure 18. In the MAX260, the input capacitorcharges to the input voltage VIN during the first halfclock cycle. During the second half-cycle, its charge istransferred to the feedback capacitor. The resultantinput impedance can be approximated by:

RIN = 1 / (CINfCLK / 2) = 2 / (CINfCLK).

CIN is around 12pF, hence, for a clock frequency of500kHz, RIN = 333kΩ. The input also has about 5pF offixed capacitance to ground.

The MAX261/MAX262 input structure is shown in Figure19. Here CA = 12pF and CB = 0.016pF and only CB isswitched, so the input resistance is 750 times largercompared to the MAX260 (RIN = 250MΩ). TheMAX261/MAX262 have a fixed capacitance of approxi-mately 5pF to ground.

f0 and Q at Low Sample RatesWhen low fCLK/f0 ratios and low Q settings are select-ed, deviation from ideal continuous filter response canbe noticeable in some designs. This is due to interac-tion between Q and f0 at low fCLK/f0 ratios and Qs. Thedata in Figure 20 quantifies these differences. Since the

MAX260MAX261MAX262

WRA0–A3D0, D1

INAORINB

CMOSLOGIC

LEVELS

V+

V-

GND

0.1µF 0.1µF

+5V

4.7µF

4.7kΩ

4.7kΩ

NOTE: OP-AMP LEVEL SHIFT CIRCUIT HAS A GAIN OF 0.5 FROM V*.

VIN

VIN

TO V+

TO GND PIN

2.5kΩ7.5kΩ

10kΩ

10kΩ

+

-SEE NOTE

VIN

4.7µF

5V

0V

5V

0V

ANY DC

0V

Figure 16. Power Supply and Input Connections for Single Supply Operation

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22 ______________________________________________________________________________________

errors are predictable, the graphs can be used to cor-rect the selected f0 and Q so that the actual realizedparameters are on target. These predicted errors arenot unique to MAX260 series devices and, in fact,occur with all types of sampled filters. Consequently,these corrections can be applied to other switchedcapacitor filters. In the majority of cases, the errors arenot significant, i.e., less than 1%, and correction is notneeded. However, the MAX262 does employ a lowerrange of fCLK/f0 ratios than the MAX260 or MAX261 andis more prone to sampling errors, as the tables show.

Maxim's filter design software applies the previous cor-rections automatically as a function of desired fCLK/f0,and Q. Therefore, Figure 20 should not be used whenMaxim's software determines f0 and Q. This results inovercompensation of the sampling errors since the cor-rection factors are then counted twice.

The data plotted in Figure 20 applies for modes 1 and3. When using Figure 20 for mode 4, the f0 errorobtained from the graph should be multiplied by 1.5and the Q error should be multiplied by 3.0. In mode 2,the value of fCLK/f0 should be multiplied by √2 and theprogrammed Q should be divided by √2 before usingthe graphs.

As with all sampled systems, frequency components ofthe input signal above one half the sampling rate arealiased. In particular, input signal components near thesampling rate generate difference frequencies thatoften fall within the passband of the filter. Such aliasedsignals, when they appear at the output, are indistin-guishable from real input information. For example, thealiased output signal generated when a 99kHz wave-form is applied to a filter sampling at 100kHz (fCLK =200kHz) is 1kHz. This waveform is an attenuated ver-sion of the output that would result from a true 1kHzinput. Remember that, with the MAX260 series filters,the nyquist rate (one half the sample rate) is in factfCLK/4, because fCLK is internally divided by two.

A simple, passive RC lowpass input filter is usually suf-ficient to remove input frequencies that can causealiasing. In many cases, the input signal itself may beband limited and require no special anti-alias filtering.The wideband MAX262 uses lower fCLK/f0 ratios thanthe MAX260/MAX261 and, for this reason, is more likelyto require input filtering than the MAX260 or MAX281.

Trimming DC OffsetThe DC offset voltage at the LP or notch output can beadjusted with the circuit in Figure 21. This circuit alsouses the input op amp to implement a single-pole anti-alias filter. Note that the total offset is generally less inmultistage filters than when only one section is used,

MAX261

INA BPA

TRACE A500kHz TTL

TRACE B

OV

OV

OV

A 1V/DIV

B 5mV/DIV

C mV/DIV

1µs/div

TRACE C

C, 1000pF

R, 10kΩ

CLKA

Figure 17. MAX261 Bandpass Output Clock Noise

VINCFB

CIN

12pF

~5pF

+

-

fCLK2

2 CIN fCLK

RIN =

Figure 18. MAX260 Input Model

VIN

CFB

CA 12pF

CB

0.016pF

~5pF+

-

fCLK2

2 750 CA fCLK

RIN =

Figure 19. MAX261/MAX262 Input Model

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______________________________________________________________________________________ 23

since each offset is typical negative and each sectioninverts. When the HP or BP outputs are used, the offsetcan be removed with capacitor coupling.

Design ExamplesFourth-Order Chebyshev Bandpass Filter

Figure 22 shows both halves of a MAX260 cascaded toform a fourth-order Chebyshev bandpass filter. Thedesired parameters are:

Center frequency (f0) = 1kHz

Pass bandwidth = 200Hz

Stop bandwidth = 600Hz

Max passband ripple = 0.5dB

Min stopband attenuation = 15dB

From the previous parameters, the order (number ofpoles) and the f0 and Q of each section can be deter-mined. Such a derivation is beyond the scope of thisdata sheet; however, there are a number of sourcesthat provide design data for this procedure. Theseinclude look-up tables, design texts, and computer pro-grams. Design software is available from Maxim to pro-vide comprehensive solutions for most popular filterconfigurations. The A and B section parameters for theabove filter are:

f0A = 904Hz f0B = 1106Hz

QA = 7.05 QB = 7.05

To implement this filter, both halves operate in mode 1and use the same clock. See Tables 2 and 3. The pro-grammed parameters are:

CLKA = CLKB = 150kHz

fCLK/f0A = 166.50 (Mode 1, N = 42), actual f0A = 902.4Hz

fCLK/f0B = 136.66 (Mode 1, N = 23), actual f0B =1099.7Hz

QA = QB = 7.11 (Mode 1, N = 119)

Sampling errors are very small at this fCLK/f0 ratio, sothe actual realized Q is very close to 7.05 (see Figure20 or program MPP in the Filter Design Software sec-tion). Often the realized Q is not exactly the target valueat high Qs because programming resolution lowers asQ increases. This does not affect most filter designs,since three-digit Q accuracy is practically neverrequired, and a Q resolution of 1 is provided up to Qsof 10. The overall filter gain at f0 is 16.4V/V or 24.3dB(see the Cascading Filters section). If another gain isrequired, amplification or attenuation must be added atthe input, output, or between stages.

0

4

2

8

6

12

10

14

18

16

20

40 80 10060 120 140 160 180 200

fO ERROR vs. fCLK/fO RATIO (MODE 1, 3)

fCLK/fO RATIO

f O E

RROR

(%)

Q = 0.512

f0 ERROR IS PLOTTED FOR MODES 1 AND 3MODE 2: MULTIPLY ICLKIO BY √2 andDIVIDE Q BY √2 BEFORE USING GRAPHMODE 4: MUTIPLY fO ERROR BY 1.5

Q = 0.512

Q = 0.512

Q = 0.512

Q = 0.512

Q = 0.512

0

-2

-1

-4

-3

-5

-6

-7

40 80 10060 120 140 160 180 200

Q ERROR vs. fCLK/fO RATIO

fCLK/fO RATIO

Q ER

ROR

(%) Q = 0.5

Q ERROR IS PLOTTED FOR MODES 1 AND 3MODE 2: MULTIPLY fCLK/fO BY √2 andDIVIDE Q BY √2 BEFORE USING GRAPHMODE 4: MUTIPLY Q ERROR BY 1.5

Q = 0.83

Q = 7.11

Q = 3.05

Q = 0.6

Q = 1.21

Figure 20. Sampling Errors in fCLK/f0 and Q at Low fCLK/f0 andQ Settings

R2 100kΩ

R3 270kΩ

VIN

+5V

-5VOFFSETTRIM

TOFILTERINPUT

100kΩ+

-

R1 100kΩ

C1

NOTE: OP AMP INCLUDED WITH MAX261/MAX262

GAIN = -R1/R2

fLP =1

2πR1C2

Figure 21. Circuit for DC Offset Adjustment

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24 ______________________________________________________________________________________

In Figure 23, a series of response curves are shown forthe previous configuration using a MAX261 with clockfrequencies ranging from 750kHz to 4MHz (f0 from500Hz to 30kHz). Note that the rightmost curve showsabout 2dB of gain peaking compared to the lower fre-quency curves, indicating the upper limit of usable filteraccuracy at this Q (see Table 1).

Wide Passband Chebyshev BandpassIn this example (Figure 24), the desired parametersare:

Center frequency (f0) = 1kHz

Pass bandwidth = 1kHz

Stop bandwidth = 3kHz

Max passband ripple = 1dB

Min stopband attenuation = 20dB

From the previous parameters, we use either lookuptables, design texts, or Maxim's filter design programsto generate the order (number of poles), and the f0 andQ of each second-order section. The A and B parame-ters are:

f0A = 639Hz f0B = 1564Hz

QA = 2.01 QB = 2.01

To implement this filter, section A operates in mode 1and section B uses mode 2 to provide a wider overallrange of fCLK/f0 ratios. This way, one clock frequencycan drive both sections A and B. See Tables 2 and 3.


fCLK/f0A = 188.49 (Mode 1, N = 56), actual f0A = 636.6Hz

fCLK/f0B = 76.64 (Mode 2, N = 5), actual f0B = 156.5Hz

QA = 2.000 (Mode 1, N = 96), QB = 2.01 (Mode 2, N =83)

The overall passband gain at f0 is 0.64V/V or-3.9dB.

High-Frequency Chebyshev BandpassThe same Chebyshev response shape shown in Figure24 is implemented at higher frequencies with aMAX262 in Figure 25. The curves show plots for centerfrequencies of 15.6kHz, 31.3kHz, and 47kHz. Not onlyis this faster than the MAX260 implementation, butmode 1 can be used in both halves of the MAX262 forthis filter because the range of available fCLK/f0 ratios iswider with the MAX262 than the MAX260.

5 1

11 12

23 21

MAX260

VIN

INA BPA

CLKA

CLKPROGRAM

CLKB

INB BPB

WR, AX, DX

VOUT

40

-60200 2K1K500 20K10K5K

-35

FREQUENCY (Hz)

GAIN

(dB)

PHAS

E (D

EGRE

ES)

-10

15

-180

180

90

0

-90GAIN

PHASE

Figure 22. Fourth-Order Chebyshev Bandpass Filter

CLKA,B MODE fOA fOB QA QB

150kHz 1 N = 42 N = 23 N = 119 N = 119

30

-301K 10K5K2K 100K50K20K

-15

FREQUENCY (Hz)

GAIN

(dB)

0

15

Figure 23. MAX261 Fourth-Order Chebyshev Bandpass UsingCoefficients of Figure 22

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______________________________________________________________________________________ 25

Fourth-Order Butterworth LowpassFigure 26 shows a fourth-order Butterworth lowpasswith a cutoff frequency of 3kHz. Sections A and B of aMAX260 are cascaded. The f0 and Q parameters foreach section are:

f0A = 3kHz f0B = 3kHz

QA = 1.307 QB = 0.541

Mode 1 and a 400kHz clock are used. Because of lowQ values, the sampling errors of Figure 20 begin to looksignificant in this case. From the graphs, using fCLK/f0ratio near 133, f0A is about 4% high, f0B is 1.5% high,QA is -1.2% low, and QB is -0.5% low. If these errorsare not a problem, the corrections can be ignored.They are included here for best possible accuracy:


fCLK/f0A = 135.08 (N = 22), f0B = 2961Hz(-1.3% correction)

fCLK/f0B = 139.80 (N = 25), f0A = 2861Hz(-4.6% correction)

QA = 1.306 (N = 79, Q resolution prevents +0.5%correction)

QB = 0.547 (N = 11 +1.1% correction)

Measured wideband noise for this filter is 123µV RMS.If mode 2 were used, the noise would be 87µV RMS.For lower noise with either mode, the first sectionshould have the highest Q (section A in this example).

5 1

11 12

23 21

MAX260

VIN

INA BPA

CLKA

CLKPROGRAM

CLKB

INB BPB

WR, AX, DX

VOUT

10

-70100 1K500200 10K5K2K

-50

FREQUENCY (Hz)

GAIN

(dB)

-30

-10

-180

180

90

PHAS

E (D

EGRE

ES)

0

-90GAIN

PHASE

Figure 24. Wide Passband Chebyshev Bandpass Filter

CLKA,B MODEA MODEB fOA fOB QA QB

120kHz 1 2 N = 56 N = 5 N = 96 N = 83

5 1

11 12

23 21

MAX262

VIN

INA BPA

CLKA

CLKPROGRAM

CLKB

INB BPB

WR, AX, DX

VOUT

0

-501K 10K5K2K 100K50K20K

-40

-30

FREQUENCY (Hz)

GAIN

(dB) -20

-10

fO = 15.6kHzfCLK = 1MHz

fO = 31.3kHzfCLK = 2MHz

fO = 47kHzfCLK = 3MHz

Figure 25. High-Frequency Chebyshev Bandpass Filter

CLKA,B MODE fOA fOB QA QB

1 to 3MHz 1 N = 38 N = 0 N = 96 N = 96

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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Ordering Information (continued)PART TEMP RANGE PACKAGE A C C U R A C Y




MAX261BENG -40°C to +85°C Plastic DIP 2%








MAX2G2BENG -40°C to +85°C Plastic DIP 2%





*All devices—24-pin packages 0.3in-wide packages

V+

A1

0.199in(5.055mm)

A2CLKA CLKB

D0

CLK OUT

N.C.(OP IN)

V-A0 WR

HPB(N.C.)

N.C.(HPA)

HPA(OP OUT)N.C.(HPB)

BPA LPA INB LPB BPB

0.128in3.251mm

INAD1

OSC OUT

GND

A3

NOTE: LABELS IN PARENTHESES ( ) ARE FOR MAX261/MAX262 ONLY

Chip Topography

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Microprocessor Programmable Universal Active Filters · PDF fileorder universal switched-capacitor active filters allow microprocessor control of precise filter functions. No ... An