MEWS25-CNES -Development and Evaluation of Advanced … · ÆProducts listed in EPPL SEU saturated cross-section = 1.2x10-5cm²@ LET =110MeV.cm²/mg SET immune up to a LET of 110

25th Microelectronics Workshop – 2nd November 2012

2nd November 2012

[email protected]

Florence MALOUwith the participation of David DANGLA

CNES, France

Development and Evaluation of Advanced Electronic Components and Technologies

25th Microelectronics Workshop

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COMPONENTS DEVELOPMENT PROGRAM AT CNES

DEVELOPMENT AND SPACE EVALUATION FLOW

VLSI & ASIC TECHNOLOGIES DEVELOPMENT AND EVALUATION PROGRESS REPORT

DSM TECHNOLOGIES RELIABILITY AND RADIATION TESTS RESULTS

FUTURE CHALLENGES

CONCLUSION

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FUTURE CHALLENGES

CONCLUSION


OBJECTIVES OF THE COMPONENTS DEVELOPMENT PROGRAM

To contribute to the European non dependenceAvoid possible embargo (ITAR restriction, …),Contribute to the exploitation of the European capabilities in terms of space componentsPropose, in time, state of the art technologies and components with a good readiness level and at a reasonable cost

To Support the competitiveness of European Space industryEquipment manufacturers» Allow the space industry to have access to state of the arts components» Increase systems and equipment performances» Be able to propose new applications (New Generation telecom payloads, …)Component manufacturers» Develop a production capacity of HiRel and radiation hardened components to a reduced number of component

manufacturers» Develop as much as possible their products portfolio in order for them to be attractive and get back a significant

revenue

Program harmonized through the ESCC/CTB and coordinated with ESACollaboration with JAXABudgets : Approx. 2M€ per year - CNES funding participation target : 50 %

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FUTURE CHALLENGES

CONCLUSION


DEVELOPMENT PHASE

Define the target specification reflecting Space industry needs

Design the product on the selected process :Architecture studyMitigation techniquesModellingSimulationsDesign reviews to authorize or not to go-on manufacturing

Manufacture the prototypes

Perform electrical & radiation characterization :If the results are not in line with the target spec Design re-spin up to reach the performancesIf the design is OK Go to Evaluation stage


EVALUATION PHASE

What is the purpose of an Evaluation phase?

During this phase, components and technologies are extensively characterized and tested ( to destruction wherever possible)

Tests are designed to :Gauge reliability and lifetime

Provide stresses that» Simulate thermal, mechanical, electrical, vacuum

and radiation environments» Address intrinsic and extrinsic failure modes» Allow to determine the margins for these failure

mechanisms

The idea is to learn about the components, not just to verify that they can survive a pre-defined stress level or a suite of tests

Bathcurve


EVALUATION FLOW

Evaluation phase consists of :Preparation of an ETP (Evaluation Test Plan)Manufacturer Evaluation ( incl. subs if considered necessary)Component Evaluation Testing by the Manufacturer and monitoring by the Tech. Officer

Evaluation phase Outputs :Evaluation reportApplicable Detail Specification(s)Final PID(Process Identification Document)A Generic Specification if not existing

Introduction in EPPL (European Preferred Parts List)


EVALUATION FLOW

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FUTURE CHALLENGES

CONCLUSION


ASIC from ATMEL / STMicroelectonicsCMOS065 LP

Objectives :

DSM technology is required for next generation flexible Telecom payloads : Higher ASIC complexity : 20 to 30 Millions gates, Clock data path ~ 400 MHz , Power dissipation per ASIC ≤ 15 Watts, Multiple HSSL links at 6.25 Gbps

Process : ST 65nm LP CMOS (F) Agreement between ATMEL and ST: ST will be technology provider and ATMEL will be the ASIC vendor

65nm Space platform specification :

1st ASIC platform :Rad-Hard Dedicated Libraries for Space IO Libraries : I2C, CMOS IO and LVDS with cold spare feature 1.2GHz PLLNew Memories and associated BIST/ECC for SPACEExtension of library parameters to simulate 20ys aging≥100 kradsNo SEL at 70MeV/mg.cm², SEU hardened DFF’s

Status :

1st ASIC offer design completed with integrated ST Design in Reliability (DiR) methodologyESCC evaluation in progress by ST end Q2/13 (See preliminary results in next section )

ATMEL is initiating the 65nm ASIC deployment and design support to 1st Telecom ASICCAD Flow, HSSL IP hardening, Flip Chip package dvlpment, under ESA contracts, KO in Q4/12.

2nd ASIC platform :HSSL IP PLL for Delay compensationFlip-Chip package

+


ASIC from ATMEL0.15µm SOI

Objectives:Manage near obsolescence of digital .35µ and .18µ digital technologies for “small” (500Kg-1Mg) and “medium” (5Mg) ASIC’s needsProcess : LFoundry 0.15µm SOI (F)

0.15µm SOI offer specification :Digital radHard library 5V IO compatibility1.8V Low voltage - Processes with 3.3V I/Os logic devicesPLLEEPROM blocksAnalog devicesNo SEL at 80 MeV/mg/cm² at ambient & high temperatureSEU hardened DFF’sTested up to 300 krads. Radiation Level is 100 krads.

Status :Design completedDigital & Analog Test Vehicles availableElectrical characterization, Radiation and reliability tests in progressAlpha tests by TAS: circuit with analog blocks under design


FPGA from ATMEL

ATF280FMain features :

SRAM-based FPGA 280K equivalent ASIC gates14,400 cells ( two 3-input LUT or one 4-input LUT, one DFF)Unlimited reprogrammabilityNo SEL at a LET of 80 MeV/mg/cm2SEE-hardened (Configuration RAM, FreeRAM, DFF, JTAG, I/O buffers)RHBD no need for mitigation techniques during design300 kradsMQFP-256/352, MCGA-472, LGA-4720.18µm CMOS techno (F)

Status:Design completed IDS Tools Release 9.1.2a availableESCC evaluation tests completed under ESA contract. SMD number : 5962-12225

ATFS450EJoint ATMEL and HIREC development with CNES and JAXA respective supportBased on the ATMEL AT40K FPGA architecture and HIREC radiation hardening by design techniques

Target specification:SEU/SET hardened SRAM based reprogrammable FPGA 450K equivalent ASIC gates organized in an array of 152x152 core cells SEE-hardened (Configuration RAM, FreeRAM, DFF, JTAG, I/O buffers) RHBD no need for mitigation techniques during design100 kradsLapis 0.15μm SOI (J)

Status:Design completed3rd silicon prototypes availableElectrical characterization in progress : some bugs have been discovered on configuration memory read-back. Feasibility of a silicon fix on-goingReliability tests for Electro Migration and Stress Migration on going on Lapis 0.15µm SOI TC


VLSI from ATMEL

LEON2 AT697F µP

Dvlpt Supported by ESA and ESCC evalsupported by CNES

Main features :32-BIT SPARC PROCESSOR1 W at 100 MHzFault Tolerance by Design86 MIPS (Dhrystone 2.1)23 MFLOPS (Whetstone)300 kradsSEU error rate better than 1 E-5 error/device/daNo SEL below a LETth of 70 MeV.cm2/mgMQFP256 and LGA349 packages0.18µm CMOS techno (F)

Status :

ESCC evaluation completed in November 2011 : All results are satisfactoryESCC Detail Specification No. 9512/004 approved

Products listed in EPPL

40Mb Asynchronous SRAM

Target specification :2 config : 4Mbx10b or 1Mbx40b with no embedded EDAC2 options core: 1.2V std speed

and 1.4V high speed. 3.3V IOsPackages: x10bit in FP42 (tbc),

x40bit in CQFP132UMC 90nm Low Leakage CMOS technology (TW)

Status :1st silicon available (x40bit 1.2V version)Electrical characterization have shown some bugs at IOs levelDesign fix under investigation2nd Si expected in Q2/13


VLSI MODULES from ATMEL

Reprogrammable FPGA module

2 FPGA ATF280F + 2 EEPROM AT69170E in one package

Main features:2x ATF280F FPGA + 2x AT69170EMQFP352 package0.18µm CMOS techno (F)

Status:Design completed Electrical Characterization Completed targeted

spec reachedPrototypes, Starter Kit, User guide and Application

Note are available

Reprogrammable Computer :

1 FPGA ATF280F + 1 LEON2 AT697F in one package

Main features:32-bit SPARC V8 with Embedded FPGA90MIPS @SYSCLK=100MzMQFP352 package0.18µm CMOS techno (F)

Status:Design completedElectrical Characterization Completed targeted spec reachedPrototypes, Starter Kit, User guide and Application Note are availableESCC evaluation in progress end Q3/13

Atmel Reprogrammable FPGA module : open packageAtmel Reprogrammable computer : open package


HIGH SPEED CONVERTERS from E2V

EV10AS180 ADC

Dvlpt. in the frame of ESA program and ESCC eval in the frame of EuropeanCommunity's (CNES within FP7 consortium)

ADC Main Features :10-bit resolution1.5 Gsps Conversion Rate LBandSelectable 1:1/2/4 DEMUX1.7 W Power Dissipation100 kradsCI-CGA255 PackageB7HF200 SiGeC techno. from Infineon (G)

Status :Design Completed Reach target spec.ESCC evaluation in progressend Q4/12

EV12DS130 MUX-DACDvpt. and ESCC eval. in the frame of CNES

program

DAC Main Features :12-bit resolution3 Gsps Conversion rate6 GHz analog output bandwidth4:1 or 2:1 built in MUX (selectable) 1.3 W Power Dissipation NRZ, Narrow RTZ, 50% RTZ, RF modes100 kradsCi-CGA255 PackageB7HF200 SiGeC techno. from Infineon (G)

Status :Design completed Very good performancesESCC evaluation completed in Sept.12 : very good reliability and radiation results, see next slides

EPPL submission in Q4/12


STANDARD INTEGRATED CIRCUITS from STMicroelectronics / Completed activities

Immune up to 120MeV-cm2/mg at 2.7V and 125° C

SEL & SEFI

SET immune for a LET≤

116MeV.cm²/mg

SEU saturated cross-section =

4x10-4cm²@ LET =116MeV.cm²/mg

SET immune for a LET

≤20MeV.cm²/mg

SEU saturated cross-section =

3x10-4 cm²@ LET =60MeV.cm²/mg

SEU / SET

300 kradsTID

KSO48Package

2.5V2.5VVCC

85 mW at 20Msps100mW at 50Msps

Power

0.25µm CMOSTechno

30 Msps50 MspsFs

1412# bit

RHF1401RHF1201ADC


SEU saturated

cross-section = 1.2x10-5cm²@

LET =110MeV.cm²/mg

SET immune up to a LET of

110 MeV.cm²/

mg

SEU/SET

16-bit D-type Flip-

Flop

16-bit D-type Latch

16-bit bus transceiver

16-bit Bus

Buffer

fonction

0.35µm CMOSTechno

300 kradsTID

FP48Package

Immune up to 110 MeV-cm2/mg at 125° CSEL

162374162373162245162244VCHX


STANDARD INTEGRATED CIRCUITS from STMicroelectronics / Completed activities

17 mA maxICC

Immune up to 120 MeV-cm²/mg at 30V, at 125° CSEL

SET saturated cross-section = 9x10-3cm²,

LETth = 1.5 MeV/mg/cm²

SET saturated cross-section = 1x10-2cm²,

LETth = 1.5 MeV/mg/cm²

SET

FP8Package

15VVCC

100 krads50 kradsTID

BipolarTechno

50 %100 %Duty cycle

ST1845ST1843PWM

Low sensitivity in

the three config.

- Immune in Inverting config.

-Very low sensitivity in

Non-Inverting

config.(σsat~ 1E-6cm²).

-Low sensitivity in Subtracting config.(σsat~ 1E-5cm²).

SET saturated cross-section ~ 2,5x10-3cm², LETth < 3.3 MeV/mg/cm²

SET

4.5 to 5.5V4.5 to 5.5V4 to 14VVCC

16.6mA400µA2.3mAICC

1 GHz,

AV = +2

120MHz,

AV=+2

2MHz,

AV=+5 -3dB

Bandwidth

1800 V/μs115V/µs2.85V/µsSlew Rate

Immune at 125° C, LET up to 110MeV.cm2/mgSEL

0.25µm BiCMOSBipolarTechno

FP8Package

300 krads ELDRS freeTID

RHF330

High-Speed

RHF310

High-Speed

RHF43B

Precision

Op-amps


2.5 V, 3.3 V, 5.0 VOutput voltages

BipolarTechno

FP16, SMD.5, TO-257Package

SET sensitiveSET

Immune LET up to 110MeV.cm²/mg

SEL

300 krads ELDRS freeTID

2 and 3 AOutput currents

RHFL4913Voltage regulator


STANDARD INTEGRATED CIRCUITS from STMicroelectronics / Dvpt & ESCC Evaluation in progress

Fast ComparatorMain features :

Propagation time of 5 nsRise/fall time: 1.4 ns on 10 pFLow consumption: 1.4 mASingle supply: 3 V to 5.5 VFP8 packageST 0.25µm BiCMOS techno (F)

Status :Design completedElectrical Characterization Completed Very good Electrical ResultsRadiation Test in progressESCC evaluation in progress end Q2/13.

Voltage reference Main features :

Reference voltage = 1.2VHigh Precision: ± 0.1% @ 25°CLow Tempco:< 30ppm/°CFP10 packageST 0.25µm BiCMOS techno (F)

Status :Design completedElectrical Characterization Completed Very good Electrical ResultsRadiation Test in progressESCC evaluation in progress end Q2/13.

Differential amplifierTarget specification :

Slew rate: 780 V/μs min.Input voltage noise: 2.8 nV/√ HzHigh input impedance4.5V to 5.5V power supply rangeRad-hard

Status :Design in progress on 0.25µm BiCMOS techno (F)Si expected in Q2/13

16 bit DACTarget specification :

16-bit resolution at 5kHz bandwidth20-bit resolution at 250Hz bandwidth3.3 V analog supplyRad-hard

Status :Design in progress on 0.13µm CMOS techno (F)Si expected in Q1/13

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FUTURE CHALLENGES

CONCLUSION


65NM EVALUATION TEST PROGRAM

Evaluation Test Plan :Representative Test chips manufacturing of ST CMOS065LP Space platform

Test chips Electrical characterization in -55°C/+125°C temperature rangeConstruction analysis on TC1Reliability tests to confirm life time of 20 years @ Tj=110°C with temperature & voltage accelerations on TC1, TC2 & TC4Radiation tests : TID, SEE under heavy ions and protons on TC1 and TC2

TC1 (Rad hard digital libraries): TC2 (Rad-hard PLL + cold spare IOs) TC4 (commercial library subset):


65NM RELIABILITY TESTS RESULTS

First reliability results on TC4 test vehicleHTOL in progress on RH TC1 & TC2 test chipsSeveral tests were performed on TC4

65nm TC HTOL trials results :Acceleration factors were confirmedFor SRAM arrays, it is shown that all

compilers remain stable with margins withrespect to the specifications even after20yrs/110°C. EOL Vddmin values are showing 200mV margins with respect to compiler spec.

ST CMOS065LP CORE items are all passing SPACE mission profile

Standard Foundry qualification FIT calculations Vddnom, 125°C and 3x77 parts for criteria.

Experimental SRAM Vddmin drifts and absolute Vddmin value at End-Of-Life 20yrs.


65NM RADIATION TESTS RESULTS

Assessment phase : Heavy ions tests performed on a test vehicle with many mitigation schemes :

2 FFs architectures retainedECC confirmed robust and neededRAD tolerant Clock Trees SEU rate improvement factor with SKYROB ranging from 80 to 500

ST Clock Trees mitigation techniques in FF shifters

ESCC evaluation phase : Heavy ions and Protons tests on TC1 test chip with rad-hard library to confirm previous data

Test campaign in Q3/12

Test results under analysis


EV12DS130A DAC RELIABILITY TESTS RESULTS

HTOL 3000Hrs on 15 devices at Tj 156°C Test results :» No parametric drift at Ambient, Low and High

temperatures» EV12DS130AMGS9NB1 product has passed with

success 3000Hrs life test (Tj 156°C)

Infineon SiGeC B7HF200 technology cross-section

Package tests :Test conditions :

»500 x (-65° C / + 150°C) Temp. Cycling + 100 Thermal shock on 5 parts»50 Mechanical shock (1500g)+ 120 vibration (20g) on 5 parts

Test results :»No parametric drift. Seal test OK »No assembly degradation : Pull test and Ball shear test results were in spec. limits» Qualification of ball bonding process

Construction analysis :No defect after visual inspection and SEM

cross-section at package and die levels :» Pull test and Ball shear test results were in spec. limits» Good aspect of SiGeC process

E2V EV12DS130A : open package

Part_ID:21

IVCCA5_Mux4:1 Alim Max 85 ma ±5% -0,58%IVCCA3_Mux4:1 Alim Max 86 ma -5% -0,50%IVCCD_Mux4:1_Alim Max 87 ma -5% -0,78%FullScale_GA_Typ 112 v -1% -0,61%VOL_STVF 200 v -5% 0,19%VOH_STVF 202 v -5% -0,15%

Drift limitRelative deviation

Drift 0Hrs - 3000Hrs

Drift calculation after 3000hrs HTOL on 1 part


EV12DS130A DAC RADIATION TESTS RESULTS : TID

TID test results : No failure nor parameter drift up to 110 Krad (Si) at low dose rate of 36 rad/h

TID according to ESCC229005 parts dynamically biased + 5 parts unbiased

+ Reference part36 rad/h up to 110Krad 25°C anneal under bias during 24 hours after

completion of irradiationaccelerated ageing under bias (100°C for 168

hours)

Parameters monitored : Supply currents, leakage on static inputsLevel of harmonics H1, H2, H3, Fclk/4-Fout

and SFDR @3GS/s, Fout=2990MHz @-1dBFS in RF mode E2V EV12DS130A - Current consumption versus TID


EV12DS130A DAC RADIATION TESTS RESULTS : HEAVY IONS

SEE tests according to ESCC25100

No SEL observed up to a LET of 80MeV.cm²/mg at Tj=125°C

No SEFI detected

SET observed from LET 1.1 to 67.7 MeV.cm²/mgOnly short duration transient on DSPCLKDifferent behaviors can be observed on

DACOUT:Long duration transient for LET>31 MeV.cm²/mg» = successive erroneous conversion» Worst case transient duration is 100ns max» Periodicity not affected, but smooth variation of DACOUT

amplitude: Short duration transient. See Fig.1: Worst case duration of ~20ns max.

Same worst case Weibull curve can be applied on DSPCLK & DACOUT curves for all modes

Long SET DACOUT, NRTZ mode, 2760MS/s, LET=31MeV.cm²/mg

Rate/day

1.88E-02

Active

Quiet

GEO

1001.00E-0215 yearsCREME M3

0.333.00E+0016 daysCREME M8

MTBF (days)

53Complete mission

Heavy Ion – DSPCLK SET cross section for all configurations

Heavy Ion SEE Rate calculation with OMERE (DACOUT & DSPCLK)


EV12DS130A DAC RADIATION TESTS RESULTS : PROTONS

SEE tests according to ESCC25100

No SEL and no SEFI detected up to 200 MeV

Very few events detected even if the device appears to be sensitive down to 20 MeVWorst case Weibull parameter is consideredSame behavior on DSPCLK & DACOUTDSPCLK events:

only slight variation of 1 period or glitchesDACOUT events:

only very short transients of ~ 2 to 3 ns

11S

1

1

1.50E-10

DACOUT

1W (MeV)

1E th (MeV)

1.50E-10Saturation cross section (cm²)

DSPCLK

9.64E-04

Rate/day

Active

Quiet

GEO

0.00E+0015 yearsCREME M3

33.30E-0116 daysCREME M8

MTBF

(days)

1037Complete mission

Protons – SET DSPCLK cross section,all modesProtons – SET DACOUT cross section, all modes

Protons – Worst case Weibull parameters

Proton SEE Rate calculation with OMERE (DACOUT & DSPCLK)






FUTURE CHALLENGES

CONCLUSION


Atmel 2.5Mg RH SRAM based FPGA :To Develop an Mg SRAM based reprogrammable FPGAProcess : ST CMOS65LP (F)Architecture: NanoXplore

Target specification :

SRAM-based FPGA 2.5M equivalent ASIC gates324 clusters, 124’416 LUT5’832Kb RAMUnlimited reprogrammabilityRHBD no need for mitigation techniques during designRadiation performance:» SEL free for a LET of 100 MeV/mg/cm² @ 85°C junction,» No configuration memory upset up to 100 MeV/mg/cm²» SEU and SET susceptibility higher than a LET of 40 MeV/mg/cm².» 300KradsPackages: FlipChip and Highly Dissipative Hermetic Ceramic Package up to 2000

Status :CNES contract launched for the development of the first prototype. Project duration: 27 monthsComplementary ESA contracts for Hardware and Software will start in Q4/12

FUTURE CHALLENGES …

FRANCE GERMANY


FUTURE CHALLENGES …

Flip-Chip package for space :

To develop and evaluate Flip-Chip capability for 65nm digital components & ASIC

Investment by French government initiative : KO in Q3/12

After 65nm :

Process to be selectedRadiation and Reliability capabilities to be assessed versus space requirements






FUTURE CHALLENGES

CONCLUSION


CONCLUSION

CNES contribution to European Components Initiative for 7 years up to now

Many activities in different technological domains

Good collaboration/coordination :within the CTB and between CNES and ESAwith JAXA (FPGA 450Kgates on LAPIS 150nm SOI CMOS process)

A step forward to make available the future components necessary to improve the competitiveness of the European space industry in the

international market.


ACKNOWLEDGEMENTS

[email protected] & Business Development ManagerAtmel

[email protected] Data converters Project Manager E2V

Jean-Franç[email protected] BU ManagerSTMicroelectronics

[email protected] Space Program ManagerSTMicroelectronics

Documents

MEWS25-CNES -Development and Evaluation of Advanced … · ÆProducts listed in EPPL SEU saturated cross-section = 1.2x10-5cm²@ LET =110MeV.cm²/mg SET immune up to a LET of 110