ING. CARLOS OCHOAFPGA Product Assurance

INVAP S.E.

Simposio Argentino de Sistemas EmbebidosMETODOLOGIA DE DISEÑO CON

LOGICA PROGRAMABLE

3-5 Marzo de 2010

Agenda

Introduction

FPGA Product Assurance System

FPGA Design Methodology

Design Review Experiences

FPGA Design Examples

Conclusion

Introduction

Key Elements in FPGA Development Cycle

Structured Design Methodology

Experienced Design Team

Parts Supply Division

We Can get the end-to-end of the development cycle through…

Design Heritage in Flight Applications

Motivation

• Define and maintain the FPGA development methodology

• Check that the defined development methodology is applied

• Coordination of the design team

• Define tools management to be applied, and QA/QC system

• Start the Definition Phase of FPGA developments

• Plan and conduct design reviews (define criteria for successful review)

• Issue of MoM of all review meetings

• Experience summary report (“lesson learned”)

• Define Development Plan, and V&V Plan scopes

• Ensure the development of the product with the required quality levels

The responsible of the FPGA product assurance shall…

FPGA Product Assurance System

FPGA Development MethodologyDefinition Phase

Feasibility Study

Identification of FPGA Requirements

SRR

Architectural DesignVerification Plan

Requirements

Verification Definition

Development Plan

PDR

Detailed Design

RTL CodeTestbench

Functional Verification

Synthesis

Verification Report

Requiremets Spec

DUT Architectural Definition

Static Timing AnalysisArea and Timing Optimization

Netlist GenerationNetlist File

Synthesis Report

Timing Report

CDR

Device Programming

Design ValidationValidation Report

Design Release

MoM

MoM

MoM

MoM

Design and Verification

Acceptance Procedure

Flight Modules Production

Requiremets SpecDevelopment Plan

Functional Spec

Verification PlanFunctional Spec

(Area and Timing)

Design ImplementationPlace & Route

Verification post P&R

Programming File

Verification Report(Post P&R)

Design Document

Design DocumentVerification Plan and ReportRTL Code & Testbench

Prototype Implementation Validation Plan

(QA Protocol)QR/AR

QA Certification

Development Phases

Main Tasks

Potential Deliverables

Review Meetings

QA Role

Development Flow includes…

• ESA ECSS Space Product Assurance standardECSS-Q-60-02A

• INVAP Procedure: Design and Development ControlCDAD-2004-3PSGC-001-B

• Reuse Methodology Manual for SoC Designs

Based on…

FPGA Design Methodology

Identify FPGA requirements

DEFINITION PHASE

Assess feasibility of FPGA development

Evaluate costs, development time, responsibilities, development strategy

Deal with the client deliverables, including prototypes for validation

OUTPUTS

Requirements Specification

Development Plan

Definition Phase

Feasibility Study

Identification of FPGA Requirements

Architectural DesignVerification Plan

Requirements

Verification Definition

Development Plan

PDR

Detailed Design

RTL CodeTestbench

Functional Verification

Synthesis

Verification Report

Requiremets Spec

DUT Architectural Definition

Static Timing AnalysisArea and Timing Optimization

Netlist GenerationNetlist File

Synthesis Report

Timing Report

CDR

Device Programming

Design ValidationValidation Report

Design Release

MoM

MoM

MoM

MoM

Design and Verification

Acceptance Procedure

Flight Modules Production

Requiremets SpecDevelopment Plan

Functional Spec

Verification PlanFunctional Spec

(Area and Timing)

Design ImplementationPlace & Route

Verification post P&R

Programming File

Verification Report(Post P&R)

Design Document

Design DocumentVerification Plan and ReportRTL Code & Testbench

Prototype Implementation Validation Plan

(QA Protocol)QR/AR

QA Certification

SRR

FPGA Design MethodologyDEFINITION PHASERequirements Specification (“What”)

• HW/SW partitioning, configuration, operating modes

• FPGA interfaces, communication protocols• Operating frequency

• Electrical Constraints (Vcc, Iin/out, ZL)

• Applicable Algorithms

• Power up, and initialization state

• Reset configuration

• Error handling and test modes

• Physical constraints (pin-out, size, package)• Power and timing constraints• Reusability and portability considerations• Thermal and radiation environments constraints

Definition Phase

Feasibility Study

Identification of FPGA Requirements

Architectural DesignVerification Plan

Requirements

Verification Definition

Development Plan

PDR

Detailed Design

RTL CodeTestbench

Functional Verification

Synthesis

Verification Report

Requiremets Spec

DUT Architectural Definition

Static Timing AnalysisArea and Timing Optimization

Netlist GenerationNetlist File

Synthesis Report

Timing Report

CDR

Device Programming

Design ValidationValidation Report

Design Release

MoM

MoM

MoM

MoM

Design and Verification

Acceptance Procedure

Flight Modules Production

Requiremets SpecDevelopment Plan

Functional Spec

Verification PlanFunctional Spec

(Area and Timing)

Design ImplementationPlace & Route

Verification post P&R

Programming File

Verification Report(Post P&R)

Design Document

Design DocumentVerification Plan and ReportRTL Code & Testbench

Prototype Implementation Validation Plan

(QA Protocol)QR/AR

QA Certification

SRR

FPGA Design MethodologyDEFINITION PHASEDevelopment Plan (“How”)• FPGA name and basic functionality

• Reference documents (standards, coding guidelines)

• Design team and responsibilities

• Design tools, versions

• Design flow, HDL, control version (CVS)

• Schedule (WP duration, milestones, reviews)

• Deliverables (docs, design files, breadboards)

• Licensing and release plan

• Support plan (who, app notes)

• Computers, network resources

Project plan, including schedule and deliverables, is mandatory

Definition Phase

Feasibility Study

Identification of FPGA Requirements

Architectural DesignVerification Plan

Requirements

Verification Definition

Development Plan

PDR

Detailed Design

RTL CodeTestbench

Functional Verification

Synthesis

Verification Report

Requiremets Spec

DUT Architectural Definition

Static Timing AnalysisArea and Timing Optimization

Netlist GenerationNetlist File

Synthesis Report

Timing Report

CDR

Device Programming

Design ValidationValidation Report

Design Release

MoM

MoM

MoM

MoM

Design and Verification

Acceptance Procedure

Flight Modules Production

Requiremets SpecDevelopment Plan

Functional Spec

Verification PlanFunctional Spec

(Area and Timing)

Design ImplementationPlace & Route

Verification post P&R

Programming File

Verification Report(Post P&R)

Design Document

Design DocumentVerification Plan and ReportRTL Code & Testbench

Prototype Implementation Validation Plan

(QA Protocol)QR/AR

QA Certification

SRR

FPGA Design Methodology

DEFINITION PHASESystem Requirements Review (SRR)

• The Definition Phase concludes with the SRR, where the documentation generated within this phase shall be reviewed

• Approve consistency, quality, feasibility, and risk analysis, according to documentation generated during this phase

• This review results in the authorization to start the architectural design

• Output: Minute of Meeting (MoM)

In case the SRR is not carried out, the Functional Specification document shall be issued by the supplier, and approved by the client (see Architectural Design)

FPGA Design MethodologyARCHITECTURAL DESIGN

• Complete description of the design functionality

• After that the designer starts the RTL code

• High level models (algorithmic content)

Functional Specification includes…

• System overview

• Functional description (block diagram)

• Pin definitions• Register and parameter definitions

• Operational modes description

• CLK and RST configuration

• Additional information (waveforms, flow charts, text)

FPGA Design Methodology

ARCHITECTURAL DESIGN

Verification Plan

• Define the test environment used to verify the Core

• Includes TB architecture, test cases, verification metrics (code coverage), bus functional models

• Specification of verification tools

• In case WCA is required, it shall be defined in the Verification Plan

• Specify procedures to verify that the defined architecture meets the functional specification

FPGA Design Methodology

ARCHITECTURAL DESIGNPreliminary Design Review (PDR)

• The Architectural Design concludes with the PDR, where the documentation generated within this phase shall be reviewed

• Check that the architectural design documentation is complete and traceable with the previous phase one, in order to proceed with the detailed design

• Identify, justify and approve discrepancies between the Architectural Design and the Definition Phase documentation

• Check that the schedule is fulfilled

FPGA Design Methodology

DETAILED DESIGNDesign and Verification

• Design partitioning, according to the functional specification

Definition Phase

Feasibility Study

Identification of FPGA Requirements

Architectural DesignVerification Plan

Requirements

Verification Definition

Development Plan

Detailed Design

RTL CodeTestbench

Functional Verification

Synthesis

Verification Report

Requiremets Spec

DUT Architectural Definition

Static Timing AnalysisArea and Timing Optimization

Netlist GenerationNetlist File

Synthesis Report

Timing Report

CDR

Device Programming

Design ValidationValidation Report

Design Release

MoM

MoM

MoM

MoM

Design and Verification

Acceptance Procedure

Flight Modules Production

Requiremets SpecDevelopment Plan

Functional Spec

Verification PlanFunctional Spec

(Area and Timing)

Design ImplementationPlace & Route

Verification post P&R

Programming File

Verification Report(Post P&R)

Design Document

Design DocumentVerification Plan and ReportRTL Code & Testbench

Prototype Implementation Validation Plan

(QA Protocol)QR/AR

QA Certification

SRR

PDR

• RTL code description (VHDL) of the system

• Development of the test bench for the entire system

OUTPUTS

Design Document (upgrade of the spec functional or with implementation details, in case of reuse)

Verification report

• Functional verification of each sub-block

• Functional verification, according to Verification Plan

FPGA Design Methodology

DETAILED DESIGNSynthesis

• Netlist generation: It is the process in which the source description of the design is translated to a lower abstraction level description

• Static timing analysis (fmax, critical paths)

• Resource utilization (logic gates, flip-flops, global nets)

OUTPUTS

Netlist file

Synthesis report (area and timing)

• Run synthesis scripts (for area and timing optimization)

• Check that the code description is synthesizable

FPGA Design Methodology

DETAILED DESIGNDesign ImplementationThe P&R process is implemented taking as inputs the netlist file, technology libraries, and constraint files

OUTPUTS

Programming File

Post P&R Verification report

Placement: the process that assigns exact locations for various circuit components within the chip’s core area

Routing: the process of adding all wires needed to properly connect all of the placed components

Post P&R Verification (mandatory in OTP devices)Worst case simulation (as part of worst case analysis)

Timing report (gates and connection delays)

FPGA Design Methodology

DETAILED DESIGNCritical Design Review (CDR)

• The Detailed Design concludes with the CDR, where the documentation generated within this phase shall be reviewed

• Check consistency of the documentation generated in the previous phase

• VHDL, verification and implementation results review

• Check that the schedule is fulfilled

• Output: Minute of Meeting (MoM)

• CDR results in the approval of design and implementation, and the release for prototype (EM) implementation

FPGA Design Methodology

PROTOTYPE IMPLEMENTATION

Validation Plan / Acceptance Procedure

• Define requirements for test set up and breadboards

• Device programming procedure

• Specify measurements and test modes that are performed in order to verify that the devices contain the functionality they are designed for (*)• Validation is performed against requirements specification

• In case it is required, radiation verification test plan The acceptance procedure is a subset of the Verification Plan. It focuses the test to run, in order to get the QA design acceptance (*)

Device ProgrammingDesign ValidationValidation Report

FPGA Design Methodology

PROTOTYPE IMPLEMENTATIONQuality & Acceptance Review (QR/AR)

• The Prototype Implementation concludes with the QR/AR, where the documentation generated within this phase shall be reviewed

• Check the procedures, methods, tools, and the planned test were applied

• Check the device achieves functional and performance characteristics, satisfying requirements specification, according to the Acceptance Procedure

• Once concluded the execution of the Acceptance Procedure, it is transformed in a project protocol by a QA representative

FPGA Design Methodology

PROTOTYPE IMPLEMENTATIONQuality & Acceptance Review (QR/AR)

• The Prototype Implementation concludes with the QR/AR, where the documentation generated within this phase shall be reviewed

• Check the procedures, methods, tools, and the planned test were applied

• Check the device achieves functional and performance characteristics, satisfying requirements specification, according to the Acceptance Procedure

• Once concluded the execution of the Acceptance Procedure, it is transformed in a project protocol by a QA representative

FPGA Design Methodology

DESIGN RELEASE

• Finally, the release certification is issued by QA, approving the initialization of the Flight Modules production.

• Additional information, as reliability and radiation data shall be available

• The supplier shall maintain configuration control system to ensure the storage of the complete design data base during the entire lifetime of the device, including documentation, design, verification, and programming files

• Upon release of the FPGA, the design is put under configuration control

• DESIGN GUIDELINES FOR FPGA DEVELOPMENT

This documents resumes FPGA system design considerations, which shall be used as a reference for the FPGA designers through the design flow, and for the reviewers during the FPGA Design Reviews

FPGA Design Reviews Experiences

The scope of the design revision and the definition of requirements, in order to carry out the FPGA Design Review associated to the FPGA development

• FPGA DESIGN REVIEW REQUIREMENTS

FPGA Design Reviews Experiences

•A FPGA Critical Design Review was performed in the frame of SAC-D project

•Six FPGA designs were put under revision

•FPGA Review Team: Internal and external members. All design independent.

•Review results for each design were showed after revision

•Several RFAs were opened, and all of them were closed after revision

•Eighteen FPGA Chips are ready for flight in the SAC-D S/P

•At the moment FPGA Critical Design Reviews are starting for SAOCOM and SNCS projects

Space Area• Spacewire Driver

• DMA Controller with AMBA Bus

• Reed Solomon Encoder

• TRM Control for Active Antenna

• Interface MIL-STD-1553 Driver

• AOS CCSDS Data Formatter

• SSG Control Logic

• BAQ compression algorithm

• SDRAM Memory Controller

• VME Slave Interfase

High Speed Interface Memory Module

FPGA Design Examples

Memory Module - Eng Model

• SDRAM Controller

• Data Serializer to download data toFormatter

• Error correction circuit based onvoting logic.

• Logic to command scrubbing cyclesover entire memory space.

Space Area

FPGA Design Examples

Formatter Module - Eng Model

•Serial to Parallel SR

•Data formatting according AOS CCSDS Standard

•CRC Encoder

•Frame Synchronizer with TX Interface

Space Area

FPGA Design Examples

SMT Lead Forming Equipment

• Air Press

• Lead trim and form

Specific INVAP procedures, for flight FPGA programming, and assembly of CQFP packages, were issued.

Space Area

FPGA Design Examples

SAC-D / AQUARIUSFlight Model already integrated at INVAP facilities

We have…

• a demonstrated design experience, including flight systems

• a structured end-to-end design methodology

• an experienced design team

In such a way, we can afford the development of reliable, testable and reproducible, custom designed FPGA developments for space application.

Conclusion

Muchas Gracias!

Preguntas