Methods to Differentiate Mil/Aero Solutions Using FPGAs BOF session W – Focus on verification

Methods to Differentiate Mil/Aero Solutions Using FPGAsBOF session W – Focus on verification

Dan Gardner

Final MAPLD BOF Presentation

Gardner MAPLD 2005/P145_BOF-W

2

Requirements for FPGA Software in Mil/Aero

Cost effective delivery of mission performance— Initial Creation

Cost and speed of design— Predictable time to market at fixed cost— Fast iterations— Timing and system closure

— Complete Verification Commercial FPGA often skips many verification steps Some Mil/Aero applications have additional considerations

— Maintenance of Project Cost of life cycle maintainability of design Support of standard platforms Support Mil-preferred devices, documentation and flows


3

Technologies to Consider

All technologies listed below are required to build a complete methodology and will be covered

This presentation will essentially focus on the unique requirements of Mil/Aero FPGA applications:

— Rule checker with platform-independent coding styles— Design management— RTL + physical synthesis— I/O design with integration path to PCB— System-level design— Verification

Electronic System-Level (ESL) Overview Assertion based (CDC to validate SEU protection) Coverage driven Clock domain crossing (CDC)

— Embedded systems


4

Verification Technology

Rule checker with platform-independent coding styles

Design management Verification

— Electronic System-Level (ESL) Overview— Assertion based (CDC to validate SEU protection)— Coverage driven— Clock domain crossing (CDC)

Embedded systems


5

Rule Checkers

Encapsulate knowledge:– Expect built-in checks from standard sources

– Reuse Methodology Manual

– FPGA vendor recommendations

– Must allow quick customization for your own checks Use Early and Often:

— Perform checking interactively or in batch— Understand the causes of violations— Easily interact, organize, & track violations— Interactively trace & fix violations

Share knowledge:— Share checks with the team/company— Allow any designer to apply accumulated knowledge— Export results for reporting

Static Design Checking for VHDL/Verilog RTL


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HDL Designer: : Manage Text, Graphics, VHDL, Verilog, SystemC, SystemVerilog, PSL, C/C++, Scripts, Revision Control, Automated Design Documentation

Rule Checking & Project Management

Pro

cess Au

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ation

Pro

cess Au

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ation

Pro

cess Au

tom

ation

Pro

cess Au

tom

ation

Versio

n M

an

agem

en

tV

ersion

Ma

nag

eme

nt

Versio

n M

an

agem

en

tV

ersion

Ma

nag

eme

ntSynthesizeSynthesizeSynthesizeSynthesize

Design / DocumentDesign / DocumentDesign / DocumentDesign / Document PC

B – I/O

Desig

ner

PC

B – I/O

Desig

ner

PC

B – I/O

Desig

ner

PC

B – I/O

Desig

ner

VerificationVerificationVerificationVerification


7


Rule checker with platform-independent coding styles Design management Verification

— Electronic System-Level (ESL) Overview— Assertion based (CDC to validate SEU protection)— Coverage driven— Clock domain crossing (CDC)

Embedded systems


8

LanguageLanguageLanguageLanguage

Design Languages & Tasks

TaskTaskTaskTask

RequirementsRequirementsRequirementsRequirements

AlgorithmAlgorithmExplorationExplorationAlgorithmAlgorithm

ExplorationExploration

Architecture Architecture AnalysisAnalysis

Architecture Architecture AnalysisAnalysis

VerificationVerificationVerificationVerification

RTL DesignRTL DesignRTL DesignRTL Design

Text / UMLText / UMLText / UMLText / UML

TransactionTransactionLevelLevel

SystemCSystemC

TransactionTransactionLevelLevel

SystemCSystemC

VHDLVHDLVerilogVerilogVHDLVHDL

VerilogVerilog

HVLs extend & accelerate theRTL design process and enable RTL designers to cross

the chasm to system level design

AssertionsAssertionsPSL/SVAPSL/SVA

AssertionsAssertionsPSL/SVAPSL/SVA

SystemSystemVerilogVerilogSystemSystemVerilogVerilog

C/C++C/C++UntimedUntimedSystemCSystemC

C/C++C/C++UntimedUntimedSystemCSystemC


9

Abstraction Drives Design Productivity

RTLRTLRTLRTL

Algorithmic C++Algorithmic C++Algorithmic C++Algorithmic C++

Untimed TLM SystemCUntimed TLM SystemCUntimed TLM SystemCUntimed TLM SystemC

Timed TLM SystemCTimed TLM SystemCTimed TLM SystemCTimed TLM SystemC

Cycle Accurate SystemCCycle Accurate SystemCCycle Accurate SystemCCycle Accurate SystemC

SimulationSource Implementation

1x (7 days)

10,000x (1 min)

10x

100x

1,000x

1x (5 weeks)

20x (2 days!!)

2x (2 weeks)

Functional

Structural

Cycle

RTL

Transaction


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Automatic Generation of Verification Infrastructure

ComparatorComparatorComparatorComparator

Golden results DUT results

Original C++Original C++AlgorithmAlgorithm

Original C++Original C++AlgorithmAlgorithm RTLRTLRTLRTL

TransactorTransactorTransactorTransactor

TransactorTransactorTransactorTransactor

Facilitates the verification of the synthesized design

The original C++ testbench can be reused to verify the design

— RTL or cycle accurate— SystemC, VHDL or Verilog

Transactors convert function calls to pin-level signal activity

Pushbutton verification solution includes Makefiles and simulation scripts

Original C++Original C++TestbenchTestbench

Original C++Original C++TestbenchTestbench


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Exhaustive Algorithm VerificationWith Automated Real Time Prototypes

Quickly produce RTL code from algorithmic specifications

— Regardless of the quality of the architecture

Run RTL synthesis and P&R with integrated tool flows

Validate the functional correctness of the algorithm on FPGA prototyping boards

— Architecture optimization can be pursued in parallel

Algorithms

Precision RTL Synthesis

Catapult CSynthesis

FPGA VendorP&R

Prototyping

?

NetlistConstraints

C CodeConstraints

RTL CodeConstraints


12

HardwareASIC/FPGA

Place & Route

RTLSynthesis

Fixed PointC++ Model

Floating PointModel

Catapult CSynthesisConstraints +

Logic Analyzer

Algorithm Functional Description

Safer design flow Shorter time to RTL More efficient methodology Design optimized to system

requirements through incremental refinement

Catapult C Addresses the ESL Synthesis Challenge

Floating PointModel

Fixed PointModel

Micro-architectureDefinition

RTLDesign

RTL Area/TimingOptimization

RTLSynthesis

Place & Route

HardwareASIC/FPGA

ManualMethods

Logic Analyzer

+

MATLABSPW

C/C++

Precision RTLor DC

ASIC or FPGAVendor

Algorithm Functional Description

Sys

tem

Des

ign

erH

ard

war

e D

esig

ner

Ven

do

rTypical RTL Design Flow NEW Catapult C Design Flow


13

Methodology Explosion Targeting Verification

Assertion-based verification Functional coverage Constrained-random testing Coverage-driven verification Dynamic-formal verification Transaction-level verification Model checking And more . . .


14

Testbench Automation

(TBA)

IncludingCoverage-driven verification (CDV)Transaction-level modeling (TLM)

Assertion Based(ABV)

Formal(FV)

Clock-Domain Crossing (CDC)

Others (power, constraints, etc)

GeneralPurpose

ApplicationSpecific

Common Verification Methodologies


15

SystemVerilog for Verification

SystemVerilog is a complete Verification Language— Can be used with VHDL — Stimulus generation capabilities

Dynamically configurable constrained-random value generation Ability to generate constrained-random stimulus sequences Ability to randomly select control paths (test scenario selection, etc.)

— Functional coverage modeling Measure the verification quality and test effectiveness Dynamic reactivity with constrained-random stimulus generation

— Assertion-based verification Property specification Assertion & coverage monitoring

— High-level modeling (programming) capabilities Efficiently and effectively model the operational environment Develop reusable verification environments


16

Reference Model

AssertionCheckers

BusMonitor

AssertionCheckers

BusMonitor

Assertion-Based VerificationAssertions Enable Higher Quality Designs

Assertions provide observability for higher complexity designs

— ABV makes assertions a key element, ensuring that design properties are not violated

Assertions describe (un)desired behavior

Assertions dramatically shorten debug and repair time

Assertions stay on during block, chip and system-level tests

— Finds bugs you weren’t looking for


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Expect Widespread Use of Coverage-Driven Verification

PSL and SystemVerilog provide coverage constructs

Simulators integrating functional coverage to improve performance and debug

New test strategies require functional coverage— Random and constrained random tests need coverage to

determine what they tested


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Clock-Domain Crossings

Incorrect handling of Clock-Domain Crossing (CDC) signals is the 2nd major cause of re-spins

Traditional verification techniques do not work for CDC signals

CDC problems are subtle, will occur in hardware, and are complex to debug

Assertion Synthesis automates CDC verification, significantly reducing the risk of

CDC-related silicon re-spins

Assertion Synthesis automates CDC verification, significantly reducing the risk of

CDC-related silicon re-spins


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Complete Verification Flow

Questa-AFV

Questa-AFV

+0-In ABV

0-In FV

0-In CDCOthers T.B.D. (power, constraints, etc)

Assertion Based Verification

Language: SVA and/or PSL

Engine: Questa-AFV

IP: CheckWare

Automation: Assertion Synthesis


20


Rule checker with platform-independent coding styles Design management Verification

— Electronic System-Level (ESL) Overview— Assertion based (CDC to validate SEU protection)— Coverage Driven— Clock domain crossing (CDC)

Embedded systems


21

ASAPPlatform Exp

Platform FPGAs Need a Complete Flow

ISE ToolsChipscopeSW-HW OnChip DebugXRAYNucleus

InventraPrecision Synthesis

Modelsim

Platform Studio IDE

SeamlessISS

Microtec

BSP

Code|LabStacks

PPC405

PPC405

PLBArbiter

PLBArbiter

OPB<>

PLB

OPB<>

PLB

OPBArbiter

OPBArbiter

JTAGJTAGOPBGPIOOPBGPIO

16550UART16550UART

EMCCntrl

EMCCntrl

32KBBRAM

32KBBRAM

BRAMCntrl

BRAMCntrl

PPC405

PPC405

PLBArbiter

PLBArbiter

OPB<>

PLB

OPB<>

PLB

OPBArbiter

OPBArbiter

JTAGJTAGOPBGPIOOPBGPIO

16550UART16550UART

EMCCntrl

EMCCntrl

32KBBRAM

32KBBRAM

BRAMCntrl

BRAMCntrl

Software Hardware

PCB, Signal Integrity Tools


22

HW/SW Co-verification: Faster Iteration Loop

Supports: Edit/Compile/Verify

Eliminates: Edit/Synthesize/ Implement/Download/Verify

Promotes: Superior Visibility and Control

HDL Entry

Synthesis

Implementation

Download BitstreamInto FPGA

Evaluation Board

HDL Entry

HDL Compile

Seamless FPGACo-Verification

Without Co-verification With Co-verification


23

Summary

With engineers from software, hardware and system disciplines all converging on FPGAs, it is important to focus on the methods that can help differentiate your solution from others.

It is necessary to use all the basic verification and design tools, but there are new technologies emerging that can better address the unique requirements of Mil/Aero applications.

Documents

Methods to Differentiate Mil/Aero Solutions Using FPGAs BOF session W – Focus on verification