Memory system design with 8085.pdf

7/27/2019 Memory system design with 8085.pdf

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MEMORY SYSTEM DESIGN WITH 8085

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Demultiplexing of address and data bus

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Demultiplexing of address and data bus by ALE signal

{MSBTE – W2010 – 4M}

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Demultiplexing of address and data bus by ALE

signal

The address on the higher order bus remains on the bus for three clock periods.

However lower order address is lost after the first clock period.

This address needs to be latched and used for identifying the memory address

In the above figure a latch and an ALE signal is used to demultiplex the bus.

The bus AD7 - AD0 is connected as input to the latch 74LS373.

The ALE signal is connected to the enable(G) pin of the latch and the o/p control

(OC)signal of the latch is grounded.

ALE goes high during the T1 state

When ALE is high, the output of the latch changes according to input, hence the

o/p of the latch is the lower order address.

When ALE goes low the address is latched until the next ALE

Now the o/p of the latch represents the lower order address bus A7 – A0.

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Generation of control signals (MEMR, MEMW,

IOR, IOW signal)

MSBTE – S2011 – 4M

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Generation of control signals

RD is a control signal.

Since this signal is used for both reading memory and an input device, it is necessary for generating two different read signals: one for memory and other for input device

Similarly two different write signals are generated

The above figure shows 4 different control signals are generated by combining the signals RD, WRand IO/M

The signal IO/M goes low for the memory operation

This signal is ANDed with RD and WR signals by using 74LS32

When both the inputs are low the output of the gate is low and generate MEMR signal(memory read)

and MEMW signal (memory write)

When IO/M goes high, it indicates io operation

This signal is complemented using inverter IC 74LS04 and ANDed with RD and WR signals togenerate IOR(io read) and IOW (io write) control signals

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Address decoding techniques:

Address decoding is the process of generating chip select (CS*) signals from

the address bus for each device in the system

The address bus lines are split into two sections

1.The N most significant bits are used to generate the CS* signals for the different

devices.2. The M least significant signals are passed to the devices as addresses to the

different memory cells.

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Let’s assume a very simple microprocessor with 10 address lines (1K memory)

Let’s assume we wish to implement all its memory space and we use 128x8

memory chips SOLUTION

We will need 8 memory chips (8x128=1024)

We will need 3 address lines to select each one of the 8 chips

Each chip will need 7 address lines to address its internal memory cells

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The previous example specified that all addressable memory space was to

be implemented

If only a portion of the addressable space is going to be implemented there

are two basic address decoding strategies

1. Full address decoding

All the address lines are used to specify a memory location2. Partial address decoding

Since not all the address space is implemented, only a subset of the

address lines are needed to point to the physical memory locations

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Full address decoding

Let’ s assume a microprocessor with 10 address lines (1KB memory)

However, this time we wish to implement only 512 bytes of memory

We still must use 128-byte memory chips

Physical memory must be placed on the upper half of the memory map

SOLUTION

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Partial address decoding

Let’ s assume the same microprocessor with 10 address lines (1KB memory)

However, this time we wish to implement only 512 bytes of memory

We still must use 128-byte memory chips

Physical memory must be placed on the upper half of the memory map

SOLUTION

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Comparison of full and partial address decoding

FULL DECODING PARTIAL DECODING

All higher order address lines

are used to select memory or

i/o device

More hardware is required

System is complex and

expensive

Used for large systems

Few higher order address

lines are used to select

memory or i/o device

Less hardware is required

System is simple and

inexpensive

Used in small systems

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MEMORY INTERFACING

Eg: To interface 2k x 8 RAM to 8085 microprocessor

For 2k locations, no. of address lines required are 11 i.e. A0 – A10

The rest address lines are used for chip selection

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Memory system design with 8085.pdf