EMT 248: Memory Systems Semester II 2013/14School of Microelectronic Engineering Universiti Malaysia Perlis

Memory Classes

Memory ClassesPrime Memory (Main Memory)Invariably comprises solid state semiconductor devicesInterfaces directly with the three bus architecture of the computer system.Operates at speeds consistent with the speed of the processor.Characterized by relatively high cost per bit of storage.Many types of semiconductor memory loses stored data when the power is removed from the device. (volatile)Storage Memory (Secondary Memory)Invariably electromechanical devices - CDs, discs, tapes etcInterfaces to the system busses via I/O devices such as disc controllers.For the processor to use data stored in secondary memory it must first be transferred to main memory.Characterised by very low cost per bit of storage and is non-volatile.

Types of Main MemoryRandom Access Memory (RAM)The processor can save data in RAM - memory write operationThe processor can retrieve data from RAM - memory read operationIn most cases RAM is volatile - i.e. stored data lost when power removed.There are two types of RAM :Static RAM - Provided electrical power is maintained the data, once stored, remains stored indefinitely unless overwritten.Dynamic RAM - Data stored in dynamic RAM is lost unless it is read on a regular basis ( typically once per ms )Read Only Memory (ROM)Non-volatile memory which can only be read by the processor.Special programming facilities are required to store data in ROM.ROM is often used for program storage in systems without secondary memory.

RAM Architecture8k x 8 RAM Chip

Memory ArchitectureTotal number of memory cells per chipnumber of locations x number of bits per location(8192 x 8 = 65536 in the example)Memory cells are organised as a square matrix( 256 rows x 256 columns in the example )A row of the matrix is selected by one output of the row decoder. The row decoder accepts n address bits and decodes them into 2n outputs.( n = 8 selects 1 of 256 rows in the example )A row of the matrix can be considered to comprise a number of locations( a row comprises 32 locations in the example )

Memory ArchitectureThe column decoder selects a location in a row of the matrix.A column of the matrix is selected by one output of the column decoder. The column decoder accepts m address bits and decodes them into 2m outputs.( m = 5 selects 1 of 32 columns in the example )The total number of address bits required to specify a location within the memory device is m + n( m + n = 13 in the exampleNote: 213 = 8192 )

Memory OperationOnce the memory device receives address information ( 13 binary digits on inputs A0 - A13 in the example ) the decoding logic selects the addressed location.The addressed location is interfaced to the external data bus via back-to-back tri-state buffers.The memory devices data bus input buffers are enabled when the device receives an asserted WR/ signal and data on the external bus gets written to the addressed memory location.The memory devices data bus output buffers are enabled when the device receives an asserted RD/ signal and data at the addressed memory location is placed on the external bus for an external device to read.

Truth Table for Memory Device Control LogicThe chip enable inputs, CE1* and CE2 permit memory systems to comprise more than a single memory device.To provide the required memory system for a computer application may require tens or even hundreds of memory devices.

Memory System DesignWhen the processor wishes to read or write to memory, it specifies the memory location to be involved in the data transfer by its address.The addressed memory location and only the addressed memory location, should respond if the computer is to perform correctly.It is incumbent on the memory devices themselves and memory decoding logic external to the processor, to ensure this happens.

Example of Memory System DesignA certain 8085A based microcomputer system has the following memory specifications :2K ROM starting at address 0000 H to be implemented with a 1 off 2716 ROM ( the 2716 is organised 2K x 8 ) 4K ROM starting at address F000 H to be implemented with a 1 off 2732 ROM ( the 2732 is organised 4K x 8 )16K RAM starting at address 0800 H to be implemented with 8 off HM6116 RAM ( the 6116 is organised 2K x 8 )Draw the memory mapDevelop the decoding logicDraw a schematic diagram of the complete system

Example of Memory System DesignThe memory devices

Example of Memory System DesignThe memory map is a pictorial representation of where the memory blocks are located in the total address space of the processor

Example of Memory System Design

Example of Memory System DesignThe coloured addresses in the diagram are decoded internally by the devices.The addresses not coloured have to be externally decoded and used to drive the chip selects of the respective devices. Decoding Logic

Example of Memory System Design

Memory Decoding SystemsExhaustive DecodingWhen all the address lines of the processor (either by the internal device decoders or external memory decoders) are used to specify the address of a memory location, exhaustive decoding is said to be used.The preceding example uses exhaustive decoding for all memory devices.Partial DecodingIf one or more of the processors address lines are not used by either the external memory decoders or internal device decoders to specify an address then partial decoding is said to be used.

Memory Decoding SystemsIt is only possible to interface the full compliment of memory to a microprocessor if exhaustive decoding is used for all the memory devices.If one address line is not used to specify a memory location then the location will respond to 2 different processor addresses.If two address line are not used to specify a memory location then the location will respond to 4 different processor addresses.If three address line are not used to specify a memory location then the location will respond to 8 different processor addresses. Etc, etc

Opcode fetch machine cycle of 8085

Each instruction of the processor has one byte opcode.

The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to fetch the opcode from memory.

Hence, every instruction starts with opcode fetch machine cycle.

The time taken by the processor to execute the opcode fetch cycle is 4T.

In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.Opcode fetch machine cycle of 8085

Memory Read Cycles

The memory read machine cycle is executed by the processor to read a data byte from memory.The processor takes 3T states to execute this cycle.The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle.The following are the sequence of actions performed by microprocessor during this machine cycle:In the first T-state (T1) 8085 places address on address bus and issues ALE signal. At the same time, IO/M signal is made low, since it is memory related operation. In the second T-state (T2), processor issues RD/ control signal to memory. In response to this, memory places data on data bus.In the third T-state (T3), processor reads data from data bus, and de-asserts RD/ signal.Memory Read Cycles

Memory Write Cycles

Memory Write CyclesThe memory write machine cycle is executed by the processor to write a data byte in a memory location. The processor takes, 3T states to execute this machine cycle. The following are sequence of actions performed by processor in this machine cycle:In first T-state (T1), 8085 processor places 16- bit address on address bus and issues ALE signal.At the same time, it makes IO/M signal to low, indicating it is memory related operation.In second T-state (T2), processor places data to be written on data bus and asserts WR/ signal to the memory.In the third T-state (T3), memory stores the data and processor de-asserts WR/ signal.

Timing diagram for MVI A,32HQuestion:

Two machine codes, 3EH and 32H are store in the memory location 2000H and 2001H, respectively. The first machine code (32E) represents the opcode to load a data byte in the accumulator, and the second code (32H) represent the data byte to be loaded in the accumulator. Illustrate the timing diagram for these machine codes to be executed.

Timing diagram for MVI A,32H

Timing diagram for MVI A,32HAt T1, the microprocessor identifies that it is an Opcode Fetch cycle by placing 011 on the status signal (IO/M = 0, S1 = 1 and S2 = 1). It place the memory address (2000H) from the program counter on the address bus, 20H on A15-A8, and 00H on AD7 AD0 and increment the program counter to 2001H to point the next machine code.The ALE signal goes high during T1, which used to latch the low-order address 00H from the bus AD7 AD0.At T2, the 8085 assert the RD/ control signal, which enables the memory, and the memory places the bytes 3EH from the location 2000H on the data bus.Then the 8085 places the opcode in the instruction register and disable the RD/ signal. The fetch cycle is completed in state T3.

During T4, the 8085 decodes the opcode and finds out that a second bytes needs to be read. After the T3 state, the contents of the bus A15-A8 are unknown, and the data bus AD7-AD0 goes into high impedance.After completion of the Opcode Fetch cycle, the 8085 place the address 2001H on the address bus and increments the program counter to the next address 2002H. The second machine cycle M2 is identified as Memory Read cycle (IO/M = 0, S1 = 1 and S2 = 0) and the ALE is asseted.At T2, the RD/ signal becomes active and enables the memory chipAt the rising edge of T2, the 8085 actives the data bus as an input bus, memory places the data byte 32H on the data bus, and the 8085 reads and stores the bytes in the accumulator during T3.Timing diagram for MVI A,32H

Timing diagram for STA 526AH

STA means Store Accumulator -The contents of the accumulator is stored in the specified address(526A).The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH(see fig). - OF machine cycleThen the lower order memory address is read(6A). - Memory Read Machine CycleRead the higher order memory address (52).- Memory Read Machine CycleThe combination of both the addresses are considered and the content from accumulator is written in 526A. - Memory Write Machine CycleAssume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A.Timing diagram for STA 526AH