Memory System Unit-IV 10/23/20151Unit-4 : Memory System

Memory System

Unit-IV

04/20/23 1Unit-4 : Memory System

Basic concepts (contd..)

Up to 2k addressableMDR

MAR

k-bitaddress bus

n-bitdata bus

Control lines

( , MFC, etc.)

Processor Memory

locations

Word length = n bits

WR /

Recall that the data transfers between a processor and memory involves two registers MAR and MDR. If the address bus is k-bits, then the length of MAR is k bits.If the word length is n-bits, then the length of MDR is n bits. Control lines include R/W and MFC. For Read operation R/W = 1 and for Write operation R/W = 0.



• Measures for the speed of a memory:– Elapsed time between the initiation of an operation

and the completion of an operation is the memory access time.

– Minimum time between the initiation of two successive memory operations is memory cycle time.

• In general, the faster a memory system, the costlier it is and the smaller it is.



• An important design issue is to provide a computer system with as large and fast a memory as possible, within a given cost target.

• Several techniques to increase the effective size and speed of the memory:– Cache memory (to increase the effective speed).– Virtual memory (to increase the effective size).


Semiconductor RAM memories

• Random Access Memory (RAM) memory unit is a unit where any location can be addressed in a fixed amount of time, independent of the location’s address.


Semiconductor RAM memories

• Internal organization of memory chips:– Each memory cell can hold one bit of information.– Memory cells are organized in the form of an array. – One row is one memory word. – All cells of a row are connected to a common line,

known as the “word line”. – Word line is connected to the address decoder.– Sense/write circuits are connected to the data

input/output lines of the memory chip.


Semiconductor RAM memories Internal organization of memory chips

FF

circuitSense / Write

Addressdecoder

FF

CS

cellsMemory

circuitSense / Write Sense / Write

circuit

Data input/output lines:

A0

A1

A2

A3

W0

W1

W15

7 1 0

WR /

7 1 0

b7 b1 b0

•••

•••

•••

•••

•••

•••

•••

•••

•••


Semiconductor RAM memories Internal organization of memory chips

CS

Sense/ Writecircuitry

arraymemory cell

address5-bit row

input/outputData

5-bitdecoder

address5-bit column

address10-bit

output multiplexer 32-to-1

input demultiplexer

32 32

WR/

W0

W1

W31

and


Semiconductor RAM memories• Static RAMs (SRAMs):

– Consist of circuits that are capable of retaining their state as long as the power is applied.

– Volatile memories, because their contents are lost when power is interrupted.

– Access times of static RAMs are in the range of few nanoseconds.

– However, the cost is usually high.

• Dynamic RAMs (DRAMs):– Do not retain their state indefinitely.– Contents must be periodically refreshed. – Contents may be refreshed while accessing them for

reading. 04/20/23 9Unit-4 : Memory System

Static Memories - SRAM

• Contain circuits that retains their state as long as power is applied

• Implementation– cross connect two inverters to form a latch– transistors act as switches that open or close

under the control of the Word Line


Static Memories - SRAM

• Operation– Write: Sense/ write circuit places value on line

b and compliment on b’; forces cell into correct state

– Read: Activate Word Line to close switches T1 and T2 ; b carries the value of the circuit; Sense/ write circuit monitors b and b’ and set out accordingly


A Static RAM Cell


CMOS Memory Cell

• Major advantage of very low power consumption– current flows only when the cell is being

accessed – 5 volt and 3.3 volt versions

• Implementation– transistor pairs forms the inverters– in state 1, point X is high

• transistors T3 and T6 are on while T4 and T5 are off04/20/23 13Unit-4 : Memory System

A CMOS Memory Cell


SRAM Operation• Transistor arrangement

gives stable logic state• State 1

– C1 high, C2 low

– T1 T4 off, T2 T3 on

• State 0

– C2 high, C1 low

– T2 T3 off, T1 T4 on

• Address line transistors T5 T6 form switches

• Write – apply value to B and complement to B

• Read – value is on line B, no rewrite required

feedback


SRAM - Static RAM

• Bits stored in flip-flop• No charges to leak• No refreshing needed when powered - does not

need refresh circuits, does not waste time refreshing• More complex cell– more transistors per cell• Larger per bit• More expensive• Faster• Used for cache memory


DRAM - Dynamic RAM• Bits stored as charge in capacitors• Charges leak in milliseconds• Need periodic refreshing even when powered –

read, rewrite by CPU• Need to refresh → ‘dynamic’ RAM• Simpler construction but need refresh circuits• Smaller per bit• Less expensive• Slower• Used for main memory04/20/23 17Unit-4 : Memory System

• Address line active when bit read or written– Transistor switch high – line closed

(current flows)• Write

– Voltage to bit line• High for 1, low for 0

– Signal (activate) address line• Transfers charge to capacitor

• Read– Address line selected

• transistor turns on– Charge from capacitor fed via bit line

to sense amplifier• Compares with reference value to

determine 0 or 1– Capacitor charge must now be

restored - rewrite – cycle time!

DRAM Operation

WRITE

READ


Asynchronous DRAMInternal organization of a Dynamic RAM memory chip

Column

CSSense / Write

circuits

cell arraylatchaddress

Row

Column

latch

decoderRow

decoderaddress

4096 512 8

R/ WA20 9- A8 0-

RAS

CAS

•Organized as 4kx4k array.4096 cells in each row are divided into 512 groups of 8.•Each row can store 512 bytes.12 bits to select a row, and 9 bits to select a group in a row. •Total of 21 bits. •Reduce the number of bits by multiplexing row and columnaddresses. •First apply the row address, RASsignal latches the row address.•Then apply the column address,CAS signal latches the address.•Timing of the memory unit is controlled by a specialized unitwhich generates RAS and CAS.•This is asynchronous DRAM.


Semiconductor RAM memories(contd..)

• Recall the operation of the memory:– First all the contents of a row are selected based on a row

address.– Particular byte is selected based on the column address.

• Suppose if we want to access the consecutive bytes in the selected row.

• This can be done without having to reselect the row. – Add a latch at the output of the sense circuits in each row. – All the latches are loaded when the row is selected. – Different column addresses can be applied to select and

place different bytes on the data lines.


Semiconductor RAM memories(contd..)

• Consecutive sequence of column addresses can be applied under the control signal CAS, without reselecting the row.– Allows a block of data to be transferred at a much

faster rate than random accesses.– A small collection/group of bytes is usually referred to

as a block.

• This transfer capability is referred to as the fast page mode feature.


Conventional DRAM Organization

• d x w DRAM:– dw total bits organized as d supercells of size

w bits cols

rows

0 1 2 3

0

1

2

3

internal row buffer

16 x 8 DRAM chip

addr

data

supercell(2,1)

2 bits/

8 bits/

memorycontroller

(to CPU)


Reading DRAM Supercell (2,1)• Step 1(a): Row access strobe (RAS) selects row 2.

cols

rows

RAS = 20 1 2 3

0

1

2

internal row buffer

16 x 8 DRAM chip

3

addr

data

2/

8/

memorycontroller

• Step 1(b): Row 2 copied from DRAM array to row buffer.


Reading DRAM Supercell (2,1)• Step 2(a): Column access strobe (CAS) selects column 1.

cols

rows

0 1 2 3

0

1

2

3

internal row buffer

16 x 8 DRAM chip

CAS = 1

addr

data

2/

8/

memorycontroller

• Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU.

supercell (2,1)

supercell (2,1)

To CPU


Basic DRAM read & write

• Strobe address in two steps


A D

OE_L

256K x 8DRAM9 8

WE_LCAS_LRAS_L

OE_L

A Row Address

WE_L

Junk

Read AccessTime

Output EnableDelay

CAS_L

RAS_L

Col Address Row Address JunkCol Address

D High Z Data Out

DRAM Read Cycle Time

Early Read Cycle: OE_L asserted before CAS_L Late Read Cycle: OE_L asserted after CAS_L

• Every DRAM access begins at:– Assertion of the RAS_L– 2 ways to read: early or late v.

CAS

Junk Data Out High Z

DRAM READ Timing


Early Read Sequencing

• Assert Row Address• Assert RAS_L

– Commence read cycle– Meet Row Addr setup time before RAS/hold time after RAS

• Assert OE_L• Assert Col Address• Assert CAS_L

– Meet Col Addr setup time before CAS/hold time after CAS

• Valid Data Out after access time• Disassert OE_L, CAS_L, RAS_L to end cycle04/20/23 27Unit-4 : Memory System

Late Read Sequencing

• Assert Row Address• Assert RAS_L

– Commence read cycle– Meet Row Addr setup time before RAS/hold time after RAS

• Assert Col Address• Assert CAS_L

– Meet Col Addr setup time before CAS/hold time after CAS

• Assert OE_L• Valid Data Out after access time• Disassert OE_L, CAS_L, RAS_L to end cycle04/20/23 28Unit-4 : Memory System

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Memory System Unit-IV 10/23/20151Unit-4 : Memory System