Memory

• Read only memory (ROM) – nonvolatile • Data remains when power is turned off, data are

written into the ROM during its fabrication at the factory

• PROM- Programmable ROM. Can be programmed by user but this can only be done once

• EPROM – erasable programmable ROM• Contents of EPROM can be erased by exposing it to

ultraviolet light• EEPROM – Electrical Erasable PROM (your USB

memory stick)

Exercise

• There is a BIOS in your computer, what kind of memory is it?

Block diagram of a ROM

ROM interface – address input, data output, /CE – chip enable, /OE – output enable (for READ operation)

Memory Read Operation• To read a ROM, we need to issue the proper

address• There is a delay between address inputs and data

outputs• The access time (tACC), chip enable time (tCE), and

chip deselect time (tDF) are important timing properties

• You need these information for developing a real computer system

Timing parameters

• The access time – delay occurs before data stored at the addressed location are stable at the outputs (ie how long it takes to access data). The microprocessor must wait for tACC before reading the data

ROM read operation

• Access time is regarded as address to output delay. Typical value is 250ns

• tCE – represents the Chip Enable to output delay, usually this is equal to access time

• Deselect time – amount of time the device takes for data outputs to return to high-Z state after /OE becomes inactive

Read operation tAA=access time tCO= chip select to output delaytHZ = deselect to output float

Question• A normal 8086 read cycle takes 4 clocks• For a system with a 8MHz clock• Now you are required to develop the

memory system for the computer which of the following devices will you use?

1. Tacc = 0.125us $100

2. Tacc = 0.2us $50

3. Tacc = 0.4us $20

Choosing the proper memory

Configuration of ROM for 8-bit bus

How the circuitoperates?

EEPROM – electrical Erasable ROM

• Data stored in an EEPROM can be erased electrically

• Example inside the AduC832 (or 8051) microcontroller, there are 64KBytes of EEPROM

Programming the EPROM

• In an erased EPROM, all cells hold logic 1• Vpp is in logic 1 for data to be read from EPROM• Vpp is ON (eg Vpp = 25V for 2716 EPROM) for

programming mode (writing)• 2716 is a 2Kx8 EPROM• To write data to the EPROM a 25V signal is

needed so an external device is necessary

Modern EEPROM

http://www.siliconfareast.com/flash-memory.htm

Charges in thefloating gate represent the dataControl gate blocked out data = 0

FLASH EEPROM

• http://electronics.howstuffworks.com/flash-memory.htm

Random access memory (RAM)• Data can be read as well as written into the

memory chip • Static ram (SRAM) – data remains valid as

long as the power is ON• Dynamic RAM (DRAM) – needs to

periodically restore (recharge) the data in each storage location by addressing them

• If storage nodes are not recharged at regular intervals of time, data would be lost. This process is called refreshing

A static RAMThe two inverters are cross-connected to form a latch. The latch is connected to two bit lines by transistors T1 and T2. These transistors act as switches that can be opened or closed under control of the word line. When the word line is at ground level, the transistors are turned off and the latch retains its state. Example, if the logic value at point X is 1 and at point Y is 0, this state is maintained as long as the signal on the word line is at ground level.

SRAM circuit

From decodinglogic

To controlRAM:CE – chip enableOE – output enable(for read operation)WE – write enable (for write operation)

Write-cycle for SRAM• To write, we must produce the signal in proper

order• Minimum duration of a write cycle is tWC (write

cycle time )• Address must remain stable during the whole

cycle• Chip enable (CE) signal becomes active• The Write Enable (WE) will be active after the

address setup time tAS elapses

RAM write operation• Data should now ready and must be valid

for tDW (data valid to end of write)

• Data should remain valid (tDH) after the write

• A short recovery period (tWR) takes place after /WE returns to 1 before the write cycle is complete (address is removed)

Write cycle

Timing parameters for a write cycle

Parameter Time (ns)

Tc (rd) read cycle time 120

TWC (wr) write cycle time 120

TWP write pulse width 60

Tsu (A) address set up time 20

Tsu (S) chip select setup time 60

Tsu (D) data setup time 50

Th address hold time 0

Th (D) data hold time 5

Read Cycle• Read cycle for RAM is similar to the ROM• Minimum duration of a read cycle is tRC (read

cycle time)• Address must remain stable during the whole

cycle• Chip enable becomes active• The Enable(s) (CE) will be active after the address

is stable• Data should now ready • Data should remain valid after the OE and CE

have been removed

Read CycleCO – time betweenValid data and chip enable

OE – time betweenValid data and output enable

DRAM

• DRAM has a higher density

• Cost less

• Consume less power

• Take up less space

• We can get 64Mx1, 128Mx1 modules

DRAM structure

Needs to periodically restore (recharge) the data in each storage location by addressing them because the data is stored in the form of a charge on a capacitor as shown in the circuit. To store information in this cell, transistor T is turned on and an appropriate voltage is applied to the bit line. This causes a known amount of charge to be stored in the capacitor.

DRAM

DRAM

DRAM

• An example of a DRAM – 2164B

• It is a 64K-bit (64Kx1) device with only 16 pins

• To address 64K address, requires 16-bit address line

• 16-bit address is divided into two separate parts: 8-bit row address, and 8-bit column address. And these are time-multiplexed

DRAM-2164B

Address bus is time multiplexedRAS – row address strobeCAS – column address strobe

Addressing the DRAM• The row address is first applied • /RAS is pulsed to ‘0’ to latch the address into the

device• The column address is applied and /CAS strobed

to ‘0’• If RAS is left at ‘0’ after the row address is

latched inside the device, the address is maintained within the device

DRAM organization

ROW

Column

DRAM• Data cells along the selected row can be

accessed by simply supplying successive column addresses

• This is called page mode accesses

• (How many bits are there in a row?)

• Advantage - faster access of memory is achieved

Addressing the DRAM-64Kx16 setup

Refreshing the DRAM

• The DRAM must be refreshed every 2ms

• Refreshing is achieved by cycling through the row addresses (i.e. generating all the row address)

• During refreshing, /CAS is at logic ‘1’ and no data are output

Example 416800 DRAM • The 416800 DRAM is 2Mx8 device and the data

is parallel (8-bit) but address is multiplexed divided into ROW and Column.

• In order to access 2M memory locations, it takes 21 address bits. In the device, the address lines are multiplexed into: 12 address lines for row address and column address is only 9-bit.

• The refresh must be done in every 64ms.

416800 DRAM

32Mx8 DRAM

16Kx16K arrayEach row has 2K bytes data

To select a rowneeds 14 bits

To select a column 11 bits

System memory configuration

Memory configuration for ADuC832

ADuC832 memory architecture

Address Decoding• Address decoding is required because many memory chips

are used by a computer system• At each memory read/write only a number of chips is used • Decoding mechanism is used to guarantee that the proper

chips are selected• Certainly, capacity of modern memory device is large

(GB!!) so decoding may not be necessary but if you consider the development of SSD then decoding will become necessary if a SSD is 250G then you still need to use more than 1 memory device

• Decoding is necessary inside the memory chip

Address decoding

• To design, first determine the number of chips required

• Then determine how many address lines are needed for the decoding purpose

• Example if 4 chips are used then you need 2 address lines for decoding

Example

For 8086 system, max. 1M bytes of memory Now we use 4 256Kx8 memory chip.Note:Even addresses memory locations should be in the same chipOdd addresses memory locations should be in the same chip

So the 4 memory chips will be divided into Even and Odd group (two chips per group)Only consider the even group, since the chip is only 256K so the Memory locations stored by one chip is from 00000 to 7FFFF (with only the even locations)The other chip holds 80000 to FFFFF (only the even locations)

Example

Address80000 to FFFFF

Address00000 to 7FFFF

Odd Even

Now if the address issued is 12345H which memory chip shouldbe selected?What address line(s) can be used for the decoding ?

Decoding system

Decoder

Memories

Memories

Address lines used for driving the memories

AddressUsed for Selecting The memoryblock

Outputs from decoderusually used as /CE for the memories

Decoder

Inputs Outputs

Any device that can relateits output to its inputs can beused as a decoderOutput = f(inputs)

Address Chip enable (/CE)

Decoding• Based on the previous example

– The decoding address line is A19

– A19 = 0 then select addresses from 00000H – 7FFFFH

– A19=1 then select addresses from 80000H – FFFFFH

– A0 and BHE are used to select the even and odd

• Can you identify a device that can be used for decoding?

Decoding

A19

/CE of 00000H – 7FFFFH

/CE of 80000H – FFFFFH

What is this?

Decoder

Address Decoding Techniques

• An address decoder is a circuit that examines the address lines and enables the memory (producing the /CE signals) for a specified range of addresses. This is vital in any memory design because one block of memory must not be allowed to overlap another.

• Logic Gate Decoders (ANDS, ORS, NANDS, AND NORS).

Address Decoder circuits

• A digital decoder is a circuit that recognizes a particular binary pattern on its input lines and produces an active output indication.

When will you get an active memory select?Ans. When all inputs are 0s then the output is 0

NAND Gate Decoder Circuit

Output of the NAND gate is active when all inputs are 1s so The address from A19 to A11 is 111111111 (FF8)From A0 to A10 is used to address the memory chip

Logic gates as decoder

• A logic gate only comes with one output so if your system has many memory chips then you need one gate per memory chip!!!!!!

The 3-to-8 Line Decoder (74LS138)• The truth table shows that only one of the

eight outputs ever goes low at any time. Three enable inputs /G2A,/G2B, and G1 must all be active.

• Once the 74LS138 is enabled, the address inputs A,B, and C select which output pin goes low.– Remarks: / means logic low (0) signal level.

Truth Table for 74LS138 Decoder

AddressLines willConnect To A, B and C

64KByte Memory Bank Circuit

To enable the decoder, the NAND output (connected to G2B) must be 0 therefore A19 to A17 must be 111. The G1 input must be 1 so A16 is 1 so address lines A19 to A16 must be 1111 (F)

Example-128 MB Memory Circuit

Example-128 MB Memory Circuit (Cont’d)

BE – Bank Enable There are 4 banks to support data in byte, word and double word

How to design a decoding systemDesign a memory system for a 8086 based computerUsing 64K byte memory chips.

To design the memory system, we must first identify the followings:

How many address lines for the 64Kbyte chip?How many chips are needed for the 8086 system?Determine the address ranges for each memory blockDetermine the number of address lines can be used for decodingIdentify a suitable decoderDraw the block diagram

Example

How many address lines for the 64Kbyte chip?16-bitHow many chips are needed for the 8086 system?8086 system can address 1M so 16 chips are neededThe system should be divided into Even address and Odd addressEven address enabled by A0, Odd address enabled by BHE8 chips will be used for the even address and a decoder can be used

Decoding• 16 memory chips become 8

groups • Each group includes 2 devices

(even + odd)• Each group includes 128K

memory locations• Assign addresses represented

by each group • Look for common bit pattern

within addresses of the same group

• The common bits will be used for decoding

Common bits group Address range

A19A18A17

111

7 E0000H-

FFFFFH

A19A18A17

110

6 C0000H-

DFFFFH

A19A18A17

1 0 1

5 A0000H-

BFFFFH

A19A18A17

100

4 80000H-

9FFFFH

A19A18A17

0 11

3 60000H-

7FFFFH

A19A18A17

0 10

2 40000H-

5FFFFH

A19A18A17

0 0 1

1 20000H-

3FFFFH

A19A18A17

0 0 0

0 00000H-

1FFFFH

Self test• How many bytes can be stored by a 32Kx4 memory chip? (Ans. 16K bytes)• How many 16K bytes memory chips are required to form a 1M system? (Ans.

1M/16K = 64)• How many address lines are required to address a 16K bytes memory ? (Ans.

14) • Why the signal ALE is necessary for a 8086 microprocessor? (Ans. Because

the address bus is multiplexed)• Why memory decoding is necessary for a computer system? (Ans. To select

the proper memory chips when an address is issued)• What is High-block, Low-block? (High-block represents the odd memory

address, low-block is the even addresses )• The two address range F8000-F8FFF and FA000-FAFFF can be decoded by

what address bit(s)? (Ans. Must first examine the binary pattern of the addresses. F8000-F8FFF = 11111000 (for the first two digits) FA000 – FAFFF is 11111010 (for the first two digits) so the difference between the two ranges is bit A14. Therefore, A14 can be used to decode the two ranges. )

Exercise• Develop a 16-bit wide memory interface that

contains ROM memory at locations 000000H – 01FFFFH for the 80386SX microprocessor.

• A 386SX microprocessor has 24-bit address• The ROM used is 32Kx8 • The decoding logic should output signal to select

the chip (/CS) • Select a proper decoding device (eg multiplexer,

PAL, simple logic gates )

Exercise A memory decoding system for an 8086 computer system is shown in figure. Determine the capacity of the memory device included in the figure.

•128Kbytes•32Kbytes•64Kbytes•96Kbytes None of the above

Exercise• Develop a 16-bit wide memory interface that contains

SRAM memory at locations 200000H – 21FFFFH for the 80386SX microprocessor. (total of 128K bytes)

• A 386SX microprocessor has 24-bit address• The SRAM used is 32Kx8 (so you need 4 memory chips)• The decoding logic should output signal to select the

chip (CS) , as well as enable the write operation (WE)• Select a proper decoding device (eg multiplexer, PAL,

simple logic gates )• You can refer to Figure 10-32

Question from 2011 Exam• Design a memory system for a 16-bit

microprocessor using 1Mx8 memory devices and the processor has 26 address lines. The memory system only covers the memory range from 200000H to 9FFFFFH. If 3x8 multiplexers are used for decoding, identify the address lines connected to the selection inputs as well as the enable inputs of one of the multiplexer. Which outputs of the multiplexer are connected to the chip selects (CS) of the memory devices?

Serial EEPROM

• If building a simple device and memory is needed to store data nowadays, most commonly used memory device is serial EEPROM

• As the number of pins to connect to the device is small

Serial EEPROM• Clock and data transitions:• Data on the SDA pin may change only during SCL low time periods.

Data changes during SCL high periods will indicate a start or stop condition.

• Start condition: • A high-to-low transition of SDA with SCL high is a start condition

which must precede any other command• Stop condition:• A low-to-high transition of SDA with SCL high is a stop condition.

After a read sequence, the stop command will place the EEPROM in a standby power mode.

• Acknowledge:• The EEPROM sends a zero during the ninth clock cycle to

acknowledge that it has received each word.

Timing

Timing for data

Device addressing