A Nonvolatile 2-Mbit CBRAM Memory Core

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007 839

A Nonvolatile 2-Mbit CBRAM Memory CoreFeaturing Advanced Read and Program Control

Stefan Dietrich, Michael Angerbauer, Milena Ivanov, Dietmar Gogl, Heinz Hoenigschmid, Michael Kund,Corvin Liaw, Michael Markert, Ralf Symanczyk, Laith Altimime, Serge Bournat, and Gerhard Mueller

Abstract—A 2-Mbit CBRAM (Conductive Bridging RandomAccess Memory) core has been developed utilizing a 90 nm,VDD = 1 5 V process technology. The presented design uses an8F2 (0.0648 m2) 1T1CBJ (1-Transistor/1-Conductive BridgingJunction) cell and introduces a fast feedback regulated CBJread voltage and a novel program charge control using dummycell bleeder devices. Random read/write cycle times 50 ns aredemonstrated.

Index Terms—1T1CBJ, CBRAM, program, universal memory.

I. INTRODUCTION

I N THE CONTINUING development of a universal memory[1], the emerging CBRAM technology combines key

features of established Flash, SRAM, and DRAM memoryplatforms such as small cell size, nonvolatility, high write en-durance, and fast random access speed. Therefore, the CBRAMtechnology offers the potential to become such a new prevalentfuture memory technology [2]–[4].

For the first time, a 2-Mbit CBRAM chip architecture andrespective core circuits are described, establishing the mainbuilding blocks for a future CBRAM product. Since the readand write operation of this emerging memory technology isfairly new compared to existing memories, some novel circuittechniques are required. In this paper, it is shown that regulatingthe read voltage across the memory cell becomes es-sential for all resistive memory technologies exhibiting a largeoff/on resistance ratio. Additionally, by using a novel program-ming scheme unintended programming charge is significantlyreduced. Applying the proposed concepts random read/writecycle times 50 ns are shown.

II. CBRAM CELL AND OPERATION

Fig. 1 illustrates the cross section and cell schematic of theimplemented 1T1CBJ cell. In this chart, two CB junction cellsare displayed, each connected to a common bit line (BL) by anarray device. The connection of the CB cells to the bit line is ac-complished by activation of either word line WL or WL ,respectively. The word line system is realized in a segmentedmultilevel metallization scheme with a global master word lineand local word line drivers. The local word line driver con-necting the segmented word line implemented in metallization

Manuscript received August 25, 2006; revised December 19, 2006.M. Angerbauer, M. Ivanov, D. Gogl, H. Hoenigschmid, M. Kund, C. Liaw,

M. Markert, R. Symanczyk, L. Altimime, and G. Mueller are with QimondaAG, 85579 Neubiberg, Germany (e-mail: [email protected]).

S. Bournat is with Altis Semiconductor, 91105 Corbeil Essonnes, France.Digital Object Identifier 10.1109/JSSC.2007.892207

Fig. 1. (a) Cross section and (b) cell schematic of the 1T1CBJ cell. WL pitch=BL pitch= 2F = 180 nm. CSL: Column Select Line; M2, M1, M0: hierarchicalmetallization levels; VC: Via Contact; SC: Storage Contact; CC: Cell Contact;CB: Contact Bitline; CA: Contact Array device; CN: Contact Node.

layer M1 and the poly gate word line is not shown in the crosssection view of Fig. 1(a).

The CBRAM switching mechanism is based on the polaritydependent electrochemical deposition and removal of metal ina thin solid state electrolyte film. In this concept, a fast programoperation is achieved by applying a positive bias ( 600 mV,

A) at the oxidizable common anode plate [PL inFig. 1(a)] which is kept at VDD voltage level and the storagecontact (SC) resulting in a redox reaction driving Ag ions intothe chalcogenide glass (for example, germanium selenide). Thisleads to the formation of metal-rich clusters, which form a stableconductive bridge between both electrodes .

The device can be switched back to the erased state by ap-plying a reverse bias ( 200 mV, 20 A). In thiscase, the concentration of the metal ions is reduced and the con-ductive bridge is erased . In order to read theCB junction element a positive read bias 150 mV is appliedbetween plate anode and storage contact and the current flowingthrough the bit line is detected by a current sense amplifier (SA).

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840 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007

Fig. 2. CBRAM read/program/erase characteristics.

Fig. 3. CBRAM R =R resistance measurement, programmed at a cur-rent compliance I = 10 �A.

In Fig. 2, measurements of CBRAM read/write characteristicsare shown. The axis of the chart shows the voltage in voltsapplied between the anode plate and the storage contact of theCBRAM cell whereas on the axis the cell current is displayedin A. As can be seen from the upper current limitation, the cur-rent compliance for the program operation was set to 10 A bythe tester.

Measurements of the respective resistancecharacteristics are shown in Fig. 3. On the axis the voltageduring a read operation is shown in volts whereas on theaxis the resistance of the memory cell is illustrated in ohms.When the conductive bridge is established in the germaniumselenide chalcogenide material, an on-resistance of wasachieved whereas the off resistance measures . Thislarge difference of seven orders of magnitude generates a largeread signal margin and enables multilevel capability for futurechip designs.

The results of endurance measurements performed at roomtemperature are presented in Fig. 4. On the axis the numberof write operations is shown. Furthermore, the CB junction cellresistances and in ohms and the threshold voltagesof the switching processes (program and erase) in millivolts areillustrated on the axis. The and resistance valuesremain within a window of one order of magnitude each, evenafter more than 1 million cycles. The threshold voltages forswitching the cell from program state to erase state and viceversa are observed to be constant within the measured range.

Fig. 5 shows the results of data retention measurements at ele-vated temperatures of 50 C and 70 C, respectively. The

Fig. 4. CBRAM switching parameters after endurance tests at room tempera-ture (from [2]).

Fig. 5. CBRAM data retention measured at elevated temperatures (from [2]).

Fig. 6. CBRAM switching parameters at different operating temperatures(from [2]).

values remain at a constant value of , whereas thevalues slightly increase in time. This results in an extrapolatedresistance ratio of more than after ten years.

Measurements of the operating temperature in the range from40 C to 110 C are shown in Fig. 6. The resistance

values decrease by one order of magnitude for elevated temper-atures, whereas the and the threshold voltage values re-main constant within the measured range.

The CBRAM cell array was implemented using a 90-nmDRAM process with a three-level BEOL add-on module anduses a shared bit line contact. An F cell size measuring0.0648 m was achieved using a folded bit line architecturewhich is commonly known from DRAM designs.


DIETRICH et al.: A NONVOLATILE 2-Mbit CBRAM MEMORY CORE FEATURING ADVANCED READ AND PROGRAM CONTROL 841

Fig. 7. The 128-Kbit segment layout including local WL driver, CSL, and read/write circuitry.

Fig. 8. Segment architecture (folded BL concept).

III. CHIP ARCHITECTURE

The 2-Mbit chip consists of sixteen 128-Kbit segments(512WL 256BL pairs) connected by local word line drivers.Fig. 7 illustrates the layout of a 128-Kbit segment includingcorresponding core circuits like local word line driver, columnselect line (CSL) decoder, and CSL switch, as well as read/writecircuits. These are laid out on pitch and provide respective con-trol signals. Since it is a test chip design, all signal timingsand voltages are externally supplied by the tester (no on chipvoltage pumps) and no cell redundancy was implemented. Theshown 128-Kb segment measures about 90 m by 90 m, theword line direction is vertical, the bit lines run in horizontaldirection. The internal supply voltage for all circuits is 1.5 V;the word line is boosted to 3 V. Two 64-Kb slices are containedwithin a 128-Kb segment where CSL switches together witha multiplexer connect 128 bit line pairs and two reference bitline pairs of the memory slice within a segment to the sharedmaster bit line (called MBL in Fig. 8) which finally providesthe connection to read and write circuitry. Two current senseamplifiers are connected to a 64-Kb slice.

Fig. 9. Sensing system.

The CBRAM cells connected to the reference bit lines arepre-programmed to opposite states ( and , respec-tively) and are shorted together during the read operation. Thiscomplementary reference cell concept ensures that the resultingreference current is at an ideal midpoint reference.

A segmented word line architecture with power decoded localword line drivers was designed to enable a relaxed pitch of about6F for the master word line, which is layed out in a metal layerabove the bit line and driven over the entire length of 1.7 mm ofthe sixteen 128-Kb arrays.

IV. READ CONTROL

In Fig. 9, a cross section of the sensing system is illustrated.At the bottom, the 1T1CB junction array is shown, representedby one CB junction and two reference cells out of 128 bit linepairs and 2 reference bit line pairs in total. If the word line (WL)is activated, the CB junction and reference cells are connectedto the bit line (BL) and reference bit lines (RefBL0/RefBL1),respectively. Subject to the chosen column address, column se-lect switches (CSL) connect the bit line to the true master bit line(MBLt) and the reference bit lines to the complement master bitline (MBLc). The shorting of the reference cells via MBLc ishereby obtained with the help of the appropriate column selectand multiplexer logic and ensures an ideal mid point referencefor the sensing operation as described in the chip architectureoverview.

In a current sensing concept, the voltage across the memorycell should be kept constant and the resulting cell current canthen be detected by a current sense amplifier. As previously dis-cussed, the resistance of the CBRAM cell varies over severalorders of magnitude and therefore a conventional static pFET



Fig. 10. V comparison: Feedback regulated versus conventional source-follower type approach.

source-follower approach would not be able to keep the bit linepotential at a constant level over the whole CBRAM cell resis-tance range. Therefore, in this design, the bit lines are clampedto the optimum read voltage by feedback regulated pFETs P1/P2where is applied to the regulator input. The read voltage

at the CB junction can then be calculated as the platevoltage minus the regulated master bit line voltage .The resulting cell currents through the CB junctions correspondto the states of the data and reference cells within the memoryarray and are translated into a differential voltage at the loaddevices N1 and N2 which are n-channel devices configured asdiodes. Therefore, signals SAN and SAP are the inputs for thefollowing comparator stage COMP which transforms the readsignal into a digital output DO. The sense amplifier reference isobtained by averaging the currents of two reference cells writtento the opposite and states.

Fig. 10 displays the CB junction resistance in ohms on theaxis versus the obtained read voltage in volts on theaxis. Using the feedback regulated pFET approach discussed

above an accuracy of 4 mV over a wide CB junction resistancerange (from to ) was obtained. The second graphin Fig. 10 represents the conventional source follower type ap-proach which degrades significantly for lower resistance values.This means that a regulated read voltage is required for memo-ries which exhibit a large resistance spread between off and onstates in order to guarantee a reliable read signal.

In Fig. 11, the settling time of the feedback regulation circuitis displayed on the axis in nanoseconds and on the axis theobtained read voltage is plotted in volts. The simulationwas performed for the worst case situation of a low ohmic CBjunction cell in the state of 10 k . As can be seen, the tar-geted 150 mV read voltage was achieved after a 9 ns settlingtime which is key requisite for fast access and cycle times.

V. PROGRAM CONTROL

The write circuitry for erase and programming control isshown in Fig. 12. At the lower half of the figure, a cross sectionof the CB junction array is displayed, represented by a CBjunction cell and a dummy bleeder cell. The reference cells arenot shown in this illustration, the functionality of the bleedercell will be explained later. By activating the word line (WL),the CB junction is connected to the bit line (BL) via the array

Fig. 11. V settling time (simulated for worst case condition of low resis-tive R = R ).

Fig. 12. Writing (program/erase) system.

device. Activation of the respective column select switch con-nects the bit line to the corresponding master bit line (MBLt).During an erase operation, the signal Erase is at 0 V enablinga current flow from the voltage called through themaster bit line (MBL) and bit line (BL) network to . Duringa program operation, the signal Prog is at VDD V andthe current, which is called , flows from through themaster bit line and bit line network to ground. In this case, themirror devices N3 and N4 provide a current complianceto avoid destruction and over-programming of the CB junction.Ideally, is equal to . The write multiplexer (WRITEMUX) ensures that only one program and erase logic is neededfor writing to true master bit line (MBLt) or complementmaster bit line (MBLc). During reference cell write operation,the column select switch and multiplexing circuitry (CSL) iscapable of separating the two reference bit lines (RefBL) whichare normally shorted by the master bit line. This guarantees



Fig. 13. I comparison: Dummy bleeder device versus conventional ap-proach without bleeder device.

Fig. 14. Charge comparison: Dummy bleeder device versus conventional ap-proach without bleeder device.

the correct setting of the reference cells duringpre-programming.

However, due to initial charge balancing of the plate capaci-tance and the capacitances of the bit line and master bit line( , ), a critical current peak for occurs during pro-gramming before N3/N4 become effective.

In order to reduce this current peak, a dummy word line(DWL, located at array edge) is activated concurrently withthe regular word line which then creates a parallel current paththrough a CBJ dummy bleeder device. Therefore, this devicesuccessfully reduces the unintended charge by more than 50%and reaches current compliance at 25 ns. Without the bleederdevice the current compliance is reached after 60 ns. Figs. 13and 14 show the respective simulations.

VI. FULL CHIP SIMULATION

Full chip circuit simulations for an erase-read-program-readsequence are shown in Fig. 15.

On the axis of this figure the time is displayed in nanosec-onds whereas on the axis the voltage is illustrated in volts forvarious control signals. During the erase and program opera-tion the master bit line (MBL) is connected to voltage levelsabove and below the common plate voltage of 1.5 V to enable

Fig. 15. Full chip simulation: Erase-Read-Program-Read sequence, V =

3 V (boosted WL scheme), reference BLs connected to SAP, V = VDD =

1:5 V.

the bidirectional write scheme. During an erase operation themaster bit line is tight to a voltage of 2.3 V generating a re-verse bias of 2.3 V 800 mV whichguarantees enough margin compared to the necessary bias of

200 mV described in the cell operation overview. During pro-gram operation the master bit line is discharged to ground, gen-erating a positive bias of 1.5 V. During read, the master bitline is tight to 1.35 V through the feedback regulatedcircuit explained in the read control section to supply the tar-geted 150 mV read voltage to theCBRAM cell. Random read/write cycle times less than 50 ns aredemonstrated while obtaining a sufficient read signal larger than80 mV. The read signal values are measured between the com-parator input nodes SAN/SAP which are illustrated in Fig. 9. Aread access time of 35 ns measured from addresses valid to dataout was achieved.

VII. CONCLUSION

For the first time, an F 1T1CBJ based 2-Mbit CBRAMcore design using a 90 nm, VDD 1.5 V process technologyhas been presented. The introduced read voltage regulationachieves 4 mV accuracy over a wide CBJ resistance range from

to while obtaining a settling time less than 9 ns.The novel program charge control using dummy cell bleederdevices was designed to reduce unintended programmingcharge by more than 50%. Full chip simulations demonstrate arandom read/write cycle time less than 50 ns. Together with theshown endurance ( cycles) and nonvolatility (10 yearsat 70 C) measurement data the CBRAM potential as futureuniversal memory technology was illustrated.

REFERENCES

[1] G. Müller et al., “Status and outlook of emerging non volatile memorytechnologies,” in IEDM Tech. Dig., 2004, pp. 567–570.

[2] M. Kund et al., “Conductive bridging RAM (CBRAM): An emergingnon-volatile memory technology scalable to sub 20 nm,” in IEDM Tech.Dig., 2005, pp. 773–776.

[3] R. Symanczyk et al., “Electrical characterization of solid state ionicmemory elements,” in NVMTS Tech. Dig., 2003, pp. 17–1.

[4] M. Kund et al., “Non-volatile memory based on solid electrolytes,” inNVMTS Tech. Dig., 2004, pp. 10–17.



Stefan Dietrich was born in Munich, Germany, onMay 12, 1965. He received the Diploma in physicsfrom the Technical University of Munich and thePh.D. degree from the University of Augsburg,Germany, in 1993 and 1996, respectively.

In 1996, he joined the Memory Products divisionof Infineon Technologies (formerly Siemens Semi-conductors) in Munich, Germany, which became Qi-monda AG. Since then, he has been engaged in de-velopment of high-speed graphics dynamic memo-ries and emerging memory platforms.

Dr. Dietrich is a member of the German Physical Society.

Michael Angerbauer was born in Trostberg, Ger-many, on January 13, 1981. He received the Diplomain electrical engineering from the University of Ap-plied Science in Rosenheim in 2005.

In July 2005, he joined Infineon Technologies,Munich, Germany, which became Qimonda AG.Since then, he has worked for the design depart-ment of developing new circuit solutions for newnonvolatile memories.

Milena Ivanov was born in Vratsa, Bulgaria, onJanuary 12, 1978. She received the Master degree intelecommunications from the Technical Universityof Sofia, Bulgaria, in 1996, and the Diploma inelectrical engineering from the Technical Universityof Munich, Germany, in 2005.

She joined the Memory Products Division of Infi-neon Technologies in 2005 (now Qimonda AG) andis active in development of emerging memories, inparticular, conductive bridging RAM.

Dietmar Gogl received the Dipl.-Ing. degree inelectrical engineering from the Technical Universityof Munich, Germany, in 1993 and the Dr.-Ing. degreefrom the Gerhard-Mercator-University, Duisburg,Germany, in 1997.

From 1994 to 1998, he was with the FraunhoferInstitute of Microelectronic Circuits and Sys-tems, Duisburg, Germany, working on embeddedEEPROM memories for ASIC applications in bulkCMOS and high-temperature SIMOX CMOS tech-nology. From 1999 to 2000, he was with Infineon

Technologies in Duisburg and Munich, Germany, working on the developmentof nonvolatile memory solutions for microcontroller systems and MRAMsensing techniques. In 2000, he joined the MRAM Development Allianceof IBM and Infineon Technologies in East Fishkill, NY, and Burlington,VT, where he was engaged in the development of MRAM test chips andMRAM sensing techniques. Since July 2004, he has been with the InfineonTechnologies/Qimonda development center in Burlington, VT, where he hasbeen working on nonvolatile memory and DRAM circuit design.

Heinz Hoenigschmid received the Master degree inelectrical engineering from the Technical Universityof Munich, Germany.

During his 16 years with Qimonda (formerlyInfineon) he was engaged in memory chip designsand project management of advanced DRAM gener-ations and contributed to circuit, testsite and productdemonstrator developments for emerging memories.He is currently a Senior Manager responsible for thedesign of emerging memories. He holds more than60 U.S. patents.

Michael Kund was born in Cologne in 1965. He re-ceived the Dipl.-Phys. degree in 1992 and the Dr. rer.nat. degree in 1995, both from the Technical Univer-sity of Munich, Germany.

In 1996, he joined Siemens Semiconductors andin 2001 Infineon Technologies (now Qimonda)working on production engineering, design analysisand design for testability for high-performanceDRAMs. Since 2002, he has been working onemerging memory technologies. His main researchinterests are memory devices, design and characteri-

zation. He holds eight registered patents and has 25 patents pending.Dr. Kund is a member of the German Physical Society.

Corvin Liaw was born in Ostfildern-Ruit, Germany.He received the Dipl.-Ing. degree from the Universityof Stuttgart, Germany, in 2003, and a degree as Inge-nieur from ENST Paris, France, in 2003. He is cur-rently working toward the Ph.D. degree at the Tech-nical University of Munich, Germany.

His current research interests include the electricalcharacterization and the core circuit design of theConductive Bridging Random Access Memorytechnology.

Michael Markert was born in Spittal a. d. Drau,Austria, on December 21, 1968.

He joined the hardware development group for per-sonal computers at Siemens, later Siemens Nixdorf,in 1989. Since 1996 he is working for Qimonda (for-merly Infineon, formerly Siemens Semiconductor).He was engaged for about 10 years in developmentof high-end graphic memories. In 2005, he changedto the development group for new memory platforms.

Ralf Symanczyk was born in Bad Bentheim, Ger-many. He received the Masters degree in physicsfrom the University of Muenster in 1986, and thePh.D. degree from the University of Duisburg in1993.

From 1995 to 2002, he worked at DaimlerChryslerAerospace/Temic (Telefunken microelectronic) onelectrical characterization and physical failureanalysis of electronic systems and components forautomotive and military applications. In 2002, hejoined the Memory Products Division of Infineon

Technologies, which became Qimonda AG in 2006. His main research interestsare electrical and physical device characterization and new semiconductormemories.

Laith Altimime was born in 1962. After receivingthe Honours degree in 1989 in applied physicsand semiconductors electronics from Heriot WattUniversity in Edinburgh (Scotland), he joined NECSemiconductors—UK as a device yield and integra-tion engineer. He also worked in NEC-Japan andNEC-China.

In 2002, he moved to Germany as head of fabengineering in a new foundry startup, Communicant.He then joined Infineon in 2004 as Project Managerfor nonvolatile memory technologies development

(CBRAM and MRAM) at Altis Semiconductors (France).



Serge Bournat was born in Thiers, France, in 1961.He received the Engineering School diploma in 1984and the ABD in 1985, both from Ecole Supérieure dePhysique et Chimie de Paris.

In 1986, he joined IBM Microelectronics workingin semiconductor production engineering. In 2000,he joined Altis Semiconductor, an IBM/Infineon jointventure. Since 2003, he has been in charge of the de-velopment program of future memory technologies.

Gerhard Mueller received the Diploma in physicsand the Ph.D. degree from the Technical Universityof Munich, Germany, in 1989 and 1992, respectively.

After working for AT&T Bell Laboratories,Murray Hill, NJ, and Philips Research, Eindhoven,The Netherlands, in 1996 he joined the MemoryProducts division of Infineon Technologies (for-merly Siemens Semiconductors, now Qimonda)in Munich, Germany. He is currently a Senior Di-rector responsible for the development of emergingmemory technologies. His past roles included being

the team leader of a product design department. Within this role in the DRAMDevelopment Alliance (Hopewell Junction, NY) he was working on 512 Mband 1 Gb DRAM product demonstrators. After that, he was a Project Managerresponsible for Infineon’s MRAM activities in Germany and then within theMRAM Development Alliance.


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A Nonvolatile 2-Mbit CBRAM Memory Core