Mechanical drawing for front end chip output pads arrangement

Front end chip outline, simulation input pads and output pad arrangement

Inp

ut p

adOu

tpu

t p

ads

Front end chip

Part of AD620 amplifier for front end chip Vth and Vref

Part of ADG436 switch for front end chip calibration signals

Part of FPGA pins which will be tested In Xilinx board

Part of SMB connector for Front end chip calibration signals

Part of jumper for front end chipVs

Part for SSD detector outline with two pad for bias