PSoC Programmable System-0n-Chip™ · Low Power CapSense™ Block Configurable Capacitive Sensing Elements Supports Combination of CapSense Buttons, Sliders, Touch - pads, and Proximity

CY8C20234, CY8C20334CY8C20434, CY8C20534

PSoC® Programmable System-0n-Chip™

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document Number: 001-05356 Rev. *H Revised April 16, 2009

Features■ Low Power CapSense™ Block

❐ Configurable Capacitive Sensing Elements❐ Supports Combination of CapSense Buttons, Sliders, Touch-

pads, and Proximity Sensors

■ Powerful Harvard Architecture Processor❐ M8C Processor Speeds Running up to 12 MHz❐ Low Power at High Speed❐ 2.4V to 5.25V Operating Voltage❐ Industrial Temperature Range: -40°C to +85°C

■ Flexible On-Chip Memory❐ 8K Flash Program Storage

50,000 Erase/Write Cycles ❐ 512 Bytes SRAM Data Storage❐ Partial Flash Updates❐ Flexible Protection Modes❐ Interrupt Controller❐ In-System Serial Programming (ISSP)

■ Complete Development Tools❐ Free Development Tool (PSoC Designer™)❐ Full Featured, In-Circuit Emulator, and

Programmer❐ Full Speed Emulation❐ Complex Breakpoint Structure❐ 128K Trace Memory

■ Precision, Programmable Clocking❐ Internal ±5.0% 6/12 MHz Main Oscillator❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and

Sleep

■ Programmable Pin Configurations❐ Pull Up, High Z, Open Drain, and CMOS Drive Modes on All

GPIO❐ Up to 28 Analog Inputs on GPIO❐ Configurable Inputs on All GPIO❐ Selectable, Regulated Digital I/O on Port 1

• 3.0V, 20 mA Total Port 1 Source Current• 5 mA Strong Drive Mode on Port 1 Versatile Analog Mux

❐ Common Internal Analog Bus❐ Simultaneous Connection of I/O Combinations ❐ Comparator Noise Immunity❐ Low Dropout Voltage Regulator for the Analog Array

■ Additional System Resources❐ Configurable Communication Speeds

• I2C: Selectable to 50 kHz, 100 kHz, or 400 kHz• SPI: Configurable between 46.9 kHz and 3 MHz

❐ I2C Slave ❐ SPI Master and SPI Slave❐ Watchdog and Sleep Timers❐ Internal Voltage Reference❐ Integrated Supervisory Circuit

SRAM512 Bytes

System Bus

InterruptController

6/12 MHz Internal Main Oscillator

Global Analog Interconnect

PSoCCORE

CPU Core(M8C)

SROM Flash 8K

SYSTEM RESOURCES

ANALOGSYSTEM

AnalogRef.

I2C Slave/SPIMaster-Slave

POR and LVD

System Resets

Port 1 Port 0

Sleep andWatchdog

AnalogMux

Port 3 Port 2

CapSenseBlock

Config LDO

Logic Block Diagram

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Document Number: 001-05356 Rev. *H Page 2 of 34

PSoC® Functional OverviewThe PSoCfamily consists of many Programmable System-on-Chips with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog and digital blocks and programmable interconnect. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.The PSoC architecture for this device family, as shown in Figure 1, consists of three main areas: the Core, the System Resources, and the CapSense Analog System. A common versatile bus enables connection between I/O and the analog system. Each CY8C20x34 PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 28 general purpose IO (GPIO) are also included. The GPIO provide access to the MCU and analog mux.

PSoC CoreThe PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, IMO (Internal Main Oscillator), and ILO (Internal Low speed Oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard architecture microprocessor.System Resources provide additional capability such as a configurable I2C slave or SPI master-slave communication interface and various system resets supported by the M8C.The Analog System consists of the CapSense PSoC block and an internal 1.8V analog reference. Together they support capac-itive sensing of up to 28 inputs.

CapSense Analog SystemThe Analog System contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins is completed quickly and easily across multiple ports.

Figure 1. Analog System Block Diagram

Analog Multiplexer SystemThe Analog Mux Bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator.Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

■ Complex capacitive sensing interfaces such as sliders and touch pads

■ Chip-wide mux that enables analog input from any I/O pin

■ Crosspoint connection between any I/O pin combinationsWhen designing capacitive sensing applications, refer to the latest signal-to-noise signal level requirements Application Notes, found under http://www.cypress.com >> DESIGN RESOURCES >> Application Notes. In general, unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) requirement for CapSense applications is 5:1.

IDAC

ReferenceBuffer

Vr

Cinternal

Ana

log

Glo

bal B

us

Cap Sense Counters

Com paratorMux

Mux Refs

CapSenseClock Select

RelaxationOscillator

(RO)

CSCLK

IMO

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Additional System ResourcesSystem Resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits of each system resource are presented below.

■ The I2C slave or SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires run at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock).

■ Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.8V reference provides an absolute reference for capacitive sensing.

■ The 5V maximum input, 3V fixed output, low dropout regulator (LDO) provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO.

Getting StartedThe quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming infor-mation, see the PSoC® Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices.For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc.

Application NotesApplication notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab.

Development KitsPSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark.

TrainingFree PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs.

Cypros ConsultantsCertified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros.

Solutions LibraryVisit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various appli-cation designs that include firmware and hardware design files that enable you to complete your designs quickly.

Technical Support

For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736.

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Development ToolsPSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family.

PSoC Designer Software Subsystems

System-Level ViewA drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication inter-faces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements.PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device.

Chip-Level ViewThe chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application.The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.

Hybrid DesignsYou can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools.

Code Generation ToolsPSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours.

Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices.The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

DebuggerThe PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help SystemThe online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

In-Circuit EmulatorA low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices.The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

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Designing with PSoC DesignerThe development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components2. Configure components3. Organize and Connect4. Generate, Verify, and Debug

Select ComponentsBoth the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called “user modules”. User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties.

Configure ComponentsEach of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus.Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design.

Organize and ConnectYou can build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions.In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer’s output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources.

Generate, Verify, and DebugWhen you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system.Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code.A complete code development environment allows you to develop and customize your applications in C, assembly language, or both.The last step in the development process takes place inside PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.

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Document ConventionsTable 1 lists the acronyms that are used in this document.

Units of MeasureA units of measure table is located in the Electrical Specifications section. Table 7 on page 14 lists all the abbreviations used to measure the PSoC devices.

Numeric NamingHexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers are also represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b or 01000011b). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimals.

Table 1. Acronyms Used

Acronym DescriptionAC Alternating CurrentAPI Application Programming InterfaceCPU Central Processing UnitDC Direct CurrentGPIO General Purpose IOGUI Graphical User InterfaceICE In-Circuit EmulatorILO Internal Low Speed OscillatorIMO Internal Main OscillatorI/O Input Or OutputLSb Least Significant BitLVD Low Voltage DetectMSb Most Significant BitPOR Power On ResetPPOR Precision Power On ResetPSoC® Programmable System-on-Chip™SLIMO Slow IMOSRAM Static Random Access Memory

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Pin Information This section describes, lists, and illustrates the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC device pins and pinout configurations.The CY8C20x34 PSoC device is available in a variety of packages that are listed and shown in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital I/O.

16-Pin Part Pinout Figure 2. CY8C20234 16-Pin PSoC Device

Table 2. Pin Definitions - CY8C20234 16-Pin (QFN)

Pin No.Type

Name DescriptionDigital Analog

1 I/O I P2[5]2 I/O I P2[1]3 IOH I P1[7] I2C SCL, SPI SS4 IOH I P1[5] I2C SDA, SPI MISO5 IOH I P1[3] SPI CLK6 IOH I P1[1] CLK[1], I2C SCL, SPI MOSI7 Power Vss Ground Connection8 IOH I P1[0] DATA[1], I2C SDA9 IOH I P1[2]10 IOH I P1[4] Optional External Clock Input (EXTCLK)11 Input XRES Active High External Reset with Internal Pull Down12 I/O I P0[4]13 Power Vdd Supply Voltage14 I/O I P0[7]15 I/O I P0[3] Integrating Input16 I/O I P0[1]A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive

QFN(Top View)

AI, P2[5]

AI, I2C SCL, SPI SS, P1[7]AI, I2C SDA, SPI MISO, P1[5]

AI,

SP

I CLK

, P1[

3]

1234

1110

9

16 15 14 13

P0[3

], AI

P0[7

], AI

Vdd

P0[4], AI

CLK

, I2C

SC

L, S

PI M

OSI

P1[

1]

AI, D

ATA

, I2C

SD

A, P

1[0]

P1[2], AI

AI, P2[1]P1[4], AI, EXTCLKXRES

P0[1

], AI

Vss

12

5 6 7 8

Note1. These are the ISSP pins, that are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

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24-Pin Part PinoutFigure 3. CY8C20334 24-Pin PSoC Device

QFN(Top View)

AI, P2[5]


AI, SPI CLK, P1[3]

123456

181716151413

P0[2], AIP0[0], AI

24 23 22 21 20 19

P0[

3], A

IP

0[5]

, AI

P0[

7], A

IV

dd

P0[4], AI

7 8 9 10 11 12

SP

I MO

SI,

P1[

1]

AI,

DA

TA*,

I2C

SD

A, P

1[0]

AI,

P1[

2]

AI, P2[3]AI, P2[1]

NC

P1[6], AI

AI,

EX

TCLK

, P1[

4]

XRESP2[0], AI

P0[

6], A

I

AI, C

LK*,

I2C

SC

LP

0[1]

, AI

Vss

Table 3. Pin Definitions - CY8C20334 24-Pin (QFN) [2]

Pin No.Type


1 I/O I P2[5]2 I/O I P2[3]3 I/O I P2[1]4 IOH I P1[7] I2C SCL, SPI SS5 IOH I P1[5] I2C SDA, SPI MISO6 IOH I P1[3] SPI CLK7 IOH I P1[1] CLK[1], I2C SCL, SPI MOSI8 NC No Connection9 Power Vss Ground Connection10 IOH I P1[0] DATA[1], I2C SDA11 IOH I P1[2]12 IOH I P1[4] Optional External Clock Input (EXTCLK)13 IOH I P1[6]14 Input XRES Active High External Reset with Internal Pull Down15 I/O I P2[0]16 I/O I P0[0]17 I/O I P0[2]18 I/O I P0[4]19 I/O I P0[6] Analog Bypass20 Power Vdd Supply Voltage21 I/O I P0[7]22 I/O I P0[5]23 I/O I P0[3] Integrating Input24 I/O I P0[1]CP Power Vss Center Pad is connected to GroundA = Analog, I = Input, O = Output, OH = 5 mA High Output Drive

Note2. The center pad on the QFN package is connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically

floated and not connected to any other signal.

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AI P0[7]AI P0[5]AI P0[3]AI P0[1]AI P2[7]AI P2[5]AI P2[3] SSOP

123456789

1011121314

2827262524232221201918171615

AI P2[1]Vss

Vss

AI P1[3]

AI, I2C SCL P1[7]AI, I2C SDA P1[5]

SCL P1[1]AI, I2C

VddP0[6] AIP0[4] AIP0[2] AIP0[0] AIP2[6] AIP2[4] AIP2[2] AIP2[0] AIXRESP1[6] AIP1[4] EXTCLK, AI P1[2] AIP1[0] I2C SDA, AI

Table 4. Pin Definitions - CY8C20534 28-Pin (SSOP)

Pin No.Type


1 I/O I P0[7] Analog Column Mux Input2 I/O I P0[5] Analog Column Mux Input and Column Output3 I/O I P0[3] Analog Column Mux Input and Column Output, Integrating Input4 I/O I P0[1] Analog Column Mux Input, Integrating Input5 I/O I P2[7]6 I/O I P2[5]7 I/O I P2[3] Direct Switched Capacitor Block Input8 I/O I P2[1] Direct Switched Capacitor Block Input9 Power Vss Ground Connection10 I/O I P1[7] I2C Serial Clock (SCL)11 I/O I P1[5] I2C Serial Data (SDA)12 I/O I P1[3]13 I/O I P1[1] I2C Serial Clock (SCL), ISSP-SCLK[1]

14 Power Vss Ground Connection15 I/O I P1[0] I2C Serial Data (SDA), ISSP-SDATA[1]

16 I/O I P1[2]17 I/O I P1[4] Optional External Clock Input (EXTCLK)18 I/O I P1[6] 19 Input XRES Active High External Reset with Internal Pull Down20 I/O I P2[0] Direct Switched Capacitor Block Input21 I/O I P2[2] Direct Switched Capacitor Block Input22 I/O I P2[4]23 I/O I P2[6]24 I/O I P0[0] Analog Column Mux Input25 I/O I P0[2] Analog Column Mux Input26 I/O I P0[4] Analog Column Mux Input27 I/O I P0[6] Analog Column Mux Input28 Power Vdd Supply Voltage A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.

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AI, P0[1]AI, P2[7]AI, P2[5]AI, P2[3]AI, P2[1]AI, P3[3]

QFN(Top View)

9 10 11 12 13 14 15 16

12345678

2423222120191817

32 31 30 29 28 27 26 25

Vss

P0[

3], A

I

P0[

7], A

IVd

dP

0[6]

, AI

P0[

4], A

IP

0[2]

, AI

AI, P3[1]SPI SS, P1[7]

P0[0], AIP2[6], AI

P3[0], AIXRES

AI,

I2C

SD

A, S

PI M

ISO

, P1[

5]A

I, S

PI C

LK, P

1[3]

AI,

CLK

*, I2

C S

CL,

SP

I MO

SI,

P1[

1]V

ssAI

, DA

TA*,

I2C

SD

A, P

1[0]

AI, P

1[2]

AI,

EX

TCLK

, P1[

4]AI

, P1[

6]

P2[4], AIP2[2], AIP2[0], AIP3[2], AI

P0[

5], A

I

AI, I2C SCL

Table 5. Pin Definitions - CY8C20434 32-Pin (QFN) [2]

Pin No.Type


1 I/O I P0[1]2 I/O I P2[7]3 I/O I P2[5]4 I/O I P2[3]5 I/O I P2[1]6 I/O I P3[3]7 I/O I P3[1]8 IOH I P1[7] I2C SCL, SPI SS9 IOH I P1[5] I2C SDA, SPI MISO10 IOH I P1[3] SPI CLK11 IOH I P1[1] CLK[1], I2C SCL, SPI MOSI12 Power Vss Ground Connection13 IOH I P1[0] DATA[1], I2C SDA14 IOH I P1[2]15 IOH I P1[4] Optional External Clock Input (EXTCLK)16 IOH I P1[6]17 Input XRES Active High External Reset With Internal Pull Down18 I/O I P3[0]19 I/O I P3[2]20 I/O I P2[0]21 I/O I P2[2]22 I/O I P2[4]

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23 I/O I P2[6]24 I/O I P0[0]25 I/O I P0[2]26 I/O I P0[4]27 I/O I P0[6] Analog Bypass28 Power Vdd Supply Voltage29 I/O I P0[7]30 I/O I P0[5]31 I/O I P0[3] Integrating Input32 Power Vss Ground ConnectionCP Power Vss Center Pad Is Connected to Ground A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.

Table 5. Pin Definitions - CY8C20434 32-Pin (QFN) [2] (continued)

Pin No.Type


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48-Pin OCD Part PinoutThe 48-Pin QFN part table and pin diagram is for the CY8C20000 On-Chip Debug (OCD) PSoC device. This part is only used for in-circuit debugging. It is NOT available for production.

Figure 6. CY8C20000 48-Pin OCD PSoC Device

OCD QFNN

CVs

sP0

[3],

AIP0

[5],

AIP0

[7],

AIO

CD

EO

CD

OVd

dP0

[6],

AIN

CN

CN

C

101112

NCAI, P0[1]AI, P2[7]AI, P2[5]AI, P2[3]AI, P2[1]AI, P3[3]AI, P3[1]


NCNC

3534333231302928272625

3648 47 46 45 44 43 42 41 40 39 38 37

P0[2], AIP0[0], AIP2[6], AIP2[4], AIP2[2], AIP2[0], AIP3[2], AIP3[0], AIXRESP1[6], AIP1[4], EXTCLK, AI

P0[4], AI123456789

13 14 15 16 17 18 19 20 21 22 23 24

NC

NC

AI, S

PI C

LK, P

1[3]

AI, C

LK*,

I2C

SC

L, S

PI M

OS

I, P1

[1]

Vss

CC

LKH

CLK

AI,

DAT

A*, I

2C S

DA,

P1[

0]A

I, P1

[2]

NC

NC

NC

Table 6. Pin Definitions - CY8C20000 48-Pin OCD (QFN) [2]

Pin No. Digital Analog Name Description1 NC No Connection2 I/O I P0[1]3 I/O I P2[7]4 I/O I P2[5]5 I/O I P2[3]6 I/O I P2[1]7 I/O I P3[3]8 I/O I P3[1]9 IOH I P1[7] I2C SCL, SPI SS10 IOH I P1[5] I2C SDA, SPI MISO11 I/O I P0[1]12 NC No Connection13 NC No Connection14 NC No Connection15 NC No Connection16 IOH I P1[3] SPI CLK17 IOH I P1[1] CLK[1], I2C SCL, SPI MOSI18 Power Vss Ground Connection

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19 CCLK OCD CPU Clock Output20 HCLK OCD High Speed Clock Output21 IOH I P1[0] DATA[1], I2C SDA22 IOH I P1[2]23 NC No Connection24 NC No Connection25 NC No Connection26 IOH I P1[4] Optional External Clock Input (EXTCLK)27 IOH I P1[6]28 Input XRES Active High External Reset with Internal Pull Down29 I/O I P3[0]30 I/O I P3[2]31 I/O I P2[0]32 I/O I P2[2]33 I/O I P2[4]34 I/O I P2[6]35 I/O I P0[0]36 I/O I P0[2]37 NC No Connection38 NC No Connection39 NC No Connection40 I/O I P0[6] Analog Bypass41 Power Vdd Supply Voltage42 OCDO OCD Odd Data Output43 OCDE OCD Even Data I/O44 I/O I P0[7]45 I/O I P0[5]46 I/O I P0[3] Integrating Input47 Power Vss Ground Connection48 NC No ConnectionCP Power Vss Center Pad is connected to GroundA = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive.

Table 6. Pin Definitions - CY8C20000 48-Pin OCD (QFN) [2] (continued)

Pin No. Digital Analog Name Description

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Electrical SpecificationsThis section presents the DC and AC electrical specifications of the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC devices. For the latest electrical specifications, check the most recent data sheet by visiting the web at http://www.cypress.com/psoc.Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC as specified, except where mentioned.Refer to Table 17 on page 20 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.

Figure 7. Voltage versus CPU Frequency and IMO Frequency Trim Options

Table 7 lists the units of measure that are used in this section.

Table 7. Units of Measure

Symbol Unit of Measure Symbol Unit of MeasureoC degree Celsius μW microwattsdB decibels mA milliamperefF femto farad ms millisecondHz hertz mV millivoltsKB 1024 bytes nA nanoampereKbit 1024 bits ns nanosecondkHz kilohertz nV nanovoltskΩ kilohm W ohm

MHz megahertz pA picoampereMΩ megaohm pF picofaradμA microampere pp peak-to-peakμF microfarad ppm parts per millionμH microhenry ps picosecondμs microsecond sps samples per secondμV microvolts s sigma: one standard deviation

μVrms microvolts root-mean-square V volts

5.25

4.75

3.00

750 kHz 12 MHzCPU Frequency

Vdd

Volta

ge

5.25

4.75

3.00

750 kHz 6 MHz 12 MHzIMO Frequency

Vdd

Volta

ge

3.60

3 MHz

2.40

SLIMOMode=1

2.40

3 MHz

Valid

Operating

Region

SLIMOMode=1

SLIMOMode=0

SLIMOMode=1

SLIMOMode=0

2.70

SLIMOMode=1

SLIMOMode=0

2.70

6 MHz

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Absolute Maximum Ratings

Operating Temperature

Table 8. Absolute Maximum Ratings

Symbol Description Min Typ Max Units NotesTSTG Storage Temperature -55 25 +100 oC Higher storage temperatures

reduces data retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC degrades reliability.

TA Ambient Temperature with Power Applied -40 – +85 oCVdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 VVIO DC Input Voltage Vss - 0.5 – Vdd + 0.5 VVIOZ DC Voltage Applied to Tri-state Vss - 0.5 – Vdd + 0.5 VIMIO Maximum Current into any Port Pin -25 – +50 mAESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.LU Latch-up Current – – 200 mA

Table 9. Operating Temperature

Symbol Description Min Typ Max Units NotesTA Ambient Temperature -40 – +85 oCTJ Junction Temperature -40 – +100 oC The temperature rise from ambient

to junction is package specific. See Table 15 on page 18. The user must limit the power consumption to comply with this requirement.

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DC Electrical CharacteristicsDC Chip Level SpecificationsTable 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

DC General Purpose IO SpecificationsUnless otherwise noted, Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C. These are for design guidance only.

Table 10. DC Chip Level Specifications

Symbol Description Min Typ Max Units NotesVdd Supply Voltage 2.40 – 5.25 V See Table 15 on page 18.IDD12 Supply Current, IMO = 12 MHz – 1.5 2.5 mA Conditions are Vdd = 3.0V,

TA = 25oC, CPU = 12 MHz.IDD6 Supply Current, IMO = 6 MHz – 1 1.5 mA Conditions are Vdd = 3.0V,

TA = 25oC, CPU = 6 MHzISB27 Sleep (Mode) Current with POR, LVD, Sleep

Timer, WDT, and Internal Slow Oscillator Active. Mid Temperature Range.

– 2.6 4. μA Vdd = 2.55V, 0oC ≤ TA ≤ 40oC

ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and Internal Slow Oscillator Active.

– 2.8 5 μA Vdd = 3.3V, -40oC ≤ TA ≤ 85oC

Table 11. 5V and 3.3V DC GPIO Specifications Symbol Description Min Typ Max Units Notes

RPU Pull Up Resistor 4 5.6 8 kΩVOH1 High Output Voltage

Port 0, 2, or 3 PinsVdd - 0.2 – – V IOH < 10 μA, Vdd > 3.0V, maximum

of 20 mA source current in all IOs.VOH2 High Output Voltage

Port 0, 2, or 3 PinsVdd - 0.9 – – V IOH = 1 mA, Vdd > 3.0V, maximum


Port 1 Pins with LDO Regulator DisabledVdd - 0.2 – – V IOH < 10 μA, Vdd > 3.0V, maximum


Port 1 Pins with LDO Regulator DisabledVdd - 0.9 – – V IOH = 5 mA, Vdd > 3.0V, maximum


Port 1 Pins with 3.0V LDO Regulator Enabled

2.7 3.0 3.3 V IOH < 10 μA, Vdd > 3.1V, maximum of 4 IOs all sourcing 5 mA.

VOH6 High Output Voltage Port 1 Pins with 3.0V LDO Regulator Enabled

2.2 – – V IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA source current in all IOs.


2.1 2.4 2.7 V IOH < 10 μA, Vdd > 3.0V, maximum of 20 mA source current in all IOs.


2.0 – – V IOH < 200 μA, Vdd > 3.0V, maximum of 20 mA source current in all IOs.


1.6 1.8 2.0 V IOH < 10 μA 3.0V ≤ Vdd ≤ 3.6V 0oC ≤ TA ≤ 85oC Maximum of 20 mA source current in all IOs.

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1.5 – – V IOH < 100 μA. 3.0V ≤ Vdd ≤ 3.6V. 0oC ≤ TA ≤ 85oC. Maximum of 20 mA source current in all IOs.

VOL Low Output Voltage – – 0.75 V IOL = 20 mA, Vdd > 3.0V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]).

VIL Input Low Voltage – – 0.8 V 3.6V ≤ Vdd ≤ 5.25VVIH Input High Voltage 2.0 – V 3.6V ≤ Vdd ≤ 5.25VVH Input Hysteresis Voltage – 140 – mVIIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μACIN Capacitive Load on Pins as Input 0.5 1.7 5 pF Package and pin dependent

Temperature = 25oCCOUT Capacitive Load on Pins as Output 0.5 1.7 5 pF Package and pin dependent

Temperature = 25oC

Table 11. 5V and 3.3V DC GPIO Specifications (continued)

Symbol Description Min Typ Max Units Notes

Table 12. 2.7V DC GPIO Specifications Symbol Description Min Typ Max Units Notes

RPU Pull Up Resistor 4 5.6 8 kΩVOH1 High Output Voltage

Port 1 Pins with LDO Regulator DisabledVdd - 0.2 – – V IOH < 10 μA, maximum of 10 mA

source current in all IOs.VOH2 High Output Voltage

Port 1 Pins with LDO Regulator DisabledVdd - 0.5 – – V IOH = 2 mA, maximum of 10 mA

source current in all IOs.VOL Low Output Voltage – – 0.75 V IOL = 10 mA, maximum of 30 mA

sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]).

VOLP1 Low Output Voltage Port 1 Pins – – 0.4 V IOL=5 mAMaximum of 50 mA sink current on even port pins (for example, P0[2] and P3[4]) and 50 mA sink current on odd port pins (for example, P0[3] and P2[5]).2.4V ≤ Vdd < 3.6V

VIL Input Low Voltage – – 0.75 V 2.4V ≤ Vdd < 3.6VVIH1 Input High Voltage 1.4 – – V 2.4V ≤ Vdd < 2.7VVIH2 Input High Voltage 1.6 – – V 2.7V ≤ Vdd < 3.6VVH Input Hysteresis Voltage – 60 – mVIIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μACIN Capacitive Load on Pins as Input 0.5 1.7 5 pF Package and pin dependent

Temperature = 25oCCOUT Capacitive Load on Pins as Output 0.5 1.7 5 pF Package and pin dependent

Temperature = 25oC

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DC Analog Mux Bus Specifications

Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

DC Low Power Comparator Specifications

Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C. These are for design guidance only.

DC POR and LVD Specifications

Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

Table 13. DC Analog Mux Bus Specifications

Symbol Description Min Typ Max Units NotesRSW Switch Resistance to Common Analog Bus – – 400

800W W

Vdd ≥ 2.7V 2.4V ≤ Vdd ≤ 2.7V

Table 14. DC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes

VREFLPC Low power comparator (LPC) reference voltage range

0.2 – Vdd – 1 V

ISLPC LPC supply current – 10 40 μAVOSLPC LPC voltage offset – 2.5 30 mV

Table 15. DC POR and LVD Specifications Symbol Description Min Typ Max Units Notes

VPPOR0VPPOR1VPPOR2

Vdd Value for PPOR TripPORLEV[1:0] = 00bPORLEV[1:0] = 01bPORLEV[1:0] = 10b

–––

2.362.602.82

2.402.652.95

VVV

Vdd is greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog.

VLVD0VLVD1VLVD2VLVD3VLVD4VLVD5VLVD6VLVD7

Vdd Value for LVD TripVM[2:0] = 000bVM[2:0] = 001bVM[2:0] = 010bVM[2:0] = 011bVM[2:0] = 100bVM[2:0] = 101bVM[2:0] = 110bVM[2:0] = 111b

2.392.542.752.852.96

––

4.52

2.452.712.923.023.13

––

4.73

2.51[3]

2.78[4]

2.99[5]

3.093.20

––

4.83

V

VVVVVVV

Notes3. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply.4. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply.5. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply.

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DC Programming Specifications

Table 16 lists the guaranteed minimum and maximum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Flash Endurance and Retention specifications with the use of the EEPROM User Module are valid only within the range: 25°C +/-20C during the Flash Write operation. Reference the EEPROM User Module data sheet instructions for EEPROM Flash Write requirements outside of the 25°C +/-20°C temperature window.

Table 16. DC Programming Specifications

Symbol Description Min Typ Max Units NotesVddIWRITE Supply Voltage for Flash Write Operations 2.70 – – VIDDP Supply Current During Programming or

Verify– 5 25 mA

VILP Input Low Voltage During Programming or Verify

– – 0.8 V

VIHP Input High Voltage During Programming or Verify

2.2 – – V

IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify

– – 0.2 mA Driving internal pull down resistor.

IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify

– – 1.5 mA Driving internal pull down resistor.

VOLV Output Low Voltage During Programming or Verify

– – Vss + 0.75 V

VOHV Output High Voltage During Programming or Verify

Vdd –1.0 – Vdd V

FlashENPB Flash Endurance (per block) 50,000 – – – Erase/write cycles per block.FlashENT Flash Endurance (total)[6] 1,800,000 – – – Erase/write cycles.FlashDR Flash Data Retention 10 – – Years

Note6. A maximum of 36 x 50,000 block endurance cycles is allowed. This is balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of

25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles).

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AC Electrical CharacteristicsAC Chip Level SpecificationsTable 17, Table 18, and Table 19 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

Table 17. 5V and 3.3V AC Chip-Level Specifications

Symbol Description Min Typ Max Units NotesFCPU1 CPU Frequency (3.3V Nominal) 0.75 – 12.6 MHz 12 MHz only for SLIMO Mode = 0F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHzFIMO12 Internal Main Oscillator Stability for 12 MHz

(Commercial Temperature)[7]11.4 12 12.6 MHz Trimmed for 3.3V operation using

factory trim values. See Figure 7 on page 14, SLIMO Mode = 0.

FIMO6 Internal Main Oscillator Stability for 6 MHz (Commercial Temperature)

5.70 6.0 6.30 MHz Trimmed for 3.3V operation using factory trim values. See Figure 7 on page 14, SLIMO Mode = 1.

DCIMO Duty Cycle of IMO 40 50 60 %TRAMP Supply Ramp Time 0 – – μsTXRST External Reset Pulse Width 10 – – μs

Table 18. 2.7V AC Chip Level Specifications

Symbol Description Min Typ Max Units NotesFCPU1 CPU Frequency (2.7V Nominal) 0.75 – 3.25 MHzF32K1 Internal Low Speed Oscillator Frequency 8 32 96 kHzFIMO12 Internal Main Oscillator Stability for 12 MHz






Note7. 0 to 70 °C ambient, Vdd = 3.3 V.

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AC General Purpose IO SpecificationsTable 20 and Table 21 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

Figure 8. GPIO Timing Diagram

Table 19. 2.7V AC Chip Level Specifications

Symbol Description Min Typ Max Units NotesFCPU1 CPU Frequency (2.7V Minimum) 0.75 – 6.3 MHzF32K1 Internal Low Speed Oscillator Frequency 8 32 96 kHzFIMO12 Internal Main Oscillator Stability for 12 MHz






Table 20. 5V and 3.3V AC GPIO Specifications

Symbol Description Min Typ Max Units NotesFGPIO GPIO Operating Frequency 0 – 6 MHz Normal Strong Mode, Port 1.TRise023 Rise Time, Strong Mode, Cload = 50 pF

Ports 0, 2, 315 – 80 ns Vdd = 3.0 to 3.6V and 4.75V to 5.25V,

10% - 90%TRise1 Rise Time, Strong Mode, Cload = 50 pF

Port 110 – 50 ns Vdd = 3.0 to 3.6V, 10% - 90%

TFall Fall Time, Strong Mode, Cload = 50 pF All Ports

10 – 50 ns Vdd = 3.0 to 3.6V and 4.75V to 5.25V, 10% - 90%

Table 21. 2.7V AC GPIO Specifications

Symbol Description Min Typ Max Units NotesFGPIO GPIO Operating Frequency 0 – 1.5 MHz Normal Strong Mode, Port 1.TRise023 Rise Time, Strong Mode, Cload = 50 pF

Ports 0, 2, 315 – 100 ns Vdd = 2.4 to 3.0V, 10% - 90%

TRise1 Rise Time, Strong Mode, Cload = 50 pF Port 1

10 – 70 ns Vdd = 2.4 to 3.0V, 10% - 90%

TFall Fall Time, Strong Mode, Cload = 50 pF All Ports

10 – 70 ns Vdd = 2.4 to 3.0V, 10% - 90%

TFallTRise023TRise1

90%

10%

GPIOPin

OutputVoltage

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AC Comparator Amplifier SpecificationsTable 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

AC Analog Mux Bus SpecificationsTable 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

AC Low Power Comparator SpecificationsTable 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C. These are for design guidance only.

AC External Clock Specifications

Table 25, Table 26, Table 27, and Table 28 list the guaranteed maximum and minimum specifications for the voltage and tempera-ture ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

Table 22. AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units NotesTCOMP Comparator Response Time, 50 mV

Overdrive100200

ns ns

Vdd ≥ 3.0V. 2.4V < Vcc < 3.0V.

Table 23. AC Analog Mux Bus Specifications

Symbol Description Min Typ Max Units NotesFSW Switch Rate – – 3.17 MHz

Table 24. AC Low Power Comparator Specifications

Symbol Description Min Typ Max Units NotesTRLPC LPC response time – – 50 μs ≥ 50 mV overdrive comparator

reference set within VREFLPC.

Table 25. 5V AC External Clock Specifications

Symbol Description Min Typ Max Units NotesFOSCEXT Frequency 0.750 – 12.6 MHz– High Period 38 – 5300 ns– Low Period 38 – – ns– Power Up IMO to Switch 150 – – μs

Table 26. 3.3V AC External Clock Specifications

Symbol Description Min Typ Max Units NotesFOSCEXT Frequency with CPU Clock divide by 1 0.750 – 12.6 MHz Maximum CPU frequency is 12 MHz

at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

– High Period with CPU Clock divide by 1 41.7 – 5300 ns– Low Period with CPU Clock divide by 1 41.7 – – ns– Power Up IMO to Switch 150 – – μs

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AC Programming SpecificationsTable 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

Table 27. 2.7V (Nominal) AC External Clock Specifications

Symbol Description Min Typ Max Units NotesFOSCEXT Frequency with CPU Clock divide by 1 0.750 – 3.080 MHz Maximum CPU frequency is 3 MHz at

2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

FOSCEXT Frequency with CPU Clock divide by 2 or greater

0.15 – 6.35 MHz If the frequency of the external clock is greater than 3 MHz, the CPU clock divider is set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met.

– High Period with CPU Clock divide by 1 160 – 5300 ns– Low Period with CPU Clock divide by 1 160 – – ns– Power Up IMO to Switch 150 – – μs

Table 28. 2.7V (Minimum) AC External Clock Specifications

Symbol Description Min Typ Max Units NotesFOSCEXT Frequency with CPU Clock divide by 1 0.750 – 6.30 MHz Maximum CPU frequency is 6 MHz at

2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.

FOSCEXT Frequency with CPU Clock divide by 2 or greater

0.15 – 12.6 MHz If the frequency of the external clock is greater than 6 MHz, the CPU clock divider is set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met.

– High Period with CPU Clock divide by 1 160 – 5300 ns– Low Period with CPU Clock divide by 1 160 – – ns– Power Up IMO to Switch 150 – – μs

Table 29. AC Programming Specifications

Symbol Description Min Typ Max Units NotesTRSCLK Rise Time of SCLK 1 – 20 nsTFSCLK Fall Time of SCLK 1 – 20 nsTSSCLK Data Set up Time to Falling Edge of SCLK 40 – – nsTHSCLK Data Hold Time from Falling Edge of SCLK 40 – – nsFSCLK Frequency of SCLK 0 – 8 MHzTERASEB Flash Erase Time (Block) – 15 – msTWRITE Flash Block Write Time – 30 – msTDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns 3.6 < VddTDSCLK3 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6TDSCLK2 Data Out Delay from Falling Edge of SCLK – – 70 ns 2.4 ≤ Vdd ≤ 3.0

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AC SPI SpecificationsTable 30 and Table 31 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

AC I2C SpecificationsTable 32 and Table 33 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only.

Table 30. 5V and 3.3V AC SPI Specifications

Symbol Description Min Typ Max Units NotesFSPIM Maximum Input Clock Frequency Selection,

Master– – 6.3 MHz Output clock frequency is half of input

clock rate.FSPIS Maximum Input Clock Frequency Selection,

Slave– – 2.05 MHz

TSS Width of SS_ Negated Between Transmis-sions

50 – – ns

Table 31. 2.7V AC SPI Specifications

Symbol Description Min Typ Max Units NotesFSPIM Maximum Input Clock Frequency Selection,

Master– – 3.15 MHz Output clock frequency is half of input

clock rate.FSPIS Maximum Input Clock Frequency Selection,

Slave– – 1.025 MHz

TSS Width of SS_ Negated Between Transmis-sions

50 – – ns

Table 32. AC Characteristics of the I2C SDA and SCL Pins for Vdd ≥ 3.0V

Symbol DescriptionStandard Mode Fast Mode

UnitsMin Max Min Max

FSCLI2C SCL Clock Frequency 0 100 0 400 kHz

THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated

4.0 – 0.6 – μs

TLOWI2C LOW Period of the SCL Clock 4.7 – 1.3 – μs

THIGHI2C HIGH Period of the SCL Clock 4.0 – 0.6 – μs

TSUSTAI2C Setup Time for a Repeated START Condition

4.7 – 0.6 – μs

THDDATI2C Data Hold Time 0 – 0 – μs

TSUDATI2C Data Setup Time 250 – 100[8] – ns

TSUSTOI2C Setup Time for STOP Condition 4.0 – 0.6 – μs

TBUFI2C Bus Free Time Between a STOP and START Condition

4.7 – 1.3 – μs

TSPI2C Pulse Width of spikes are suppressed by the input filter

– – 0 50 ns

Note8. A Fast Mode I2C bus device is used in a Standard Mode I2C bus system but the requirement tSU; DAT Š 250 ns is met. This automatically is the case if the device

does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released.

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Figure 9. Definition for Timing for Fast/Standard Mode on the I2C Bus

Table 33. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)

Symbol DescriptionStandard Mode Fast Mode

UnitsMin Max Min Max

FSCLI2C SCL Clock Frequency. 0 100 – – kHz

THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated.

4.0 – – – μs

TLOWI2C LOW Period of the SCL Clock. 4.7 – – – μs

THIGHI2C HIGH Period of the SCL Clock 4.0 – – – μs

TSUSTAI2C Setup Time for a Repeated START Condition.

4.7 – – – μs

THDDATI2C Data Hold Time. 0 – – – μs

TSUDATI2C Data Setup Time. 250 – – – ns

TSUSTOI2C Setup Time for STOP Condition. 4.0 – – – μs

TBUFI2C Bus Free Time Between a STOP and START Condition.

4.7 – – – μs

TSPI2C Pulse Width of spikes are suppressed by the input filter.

– – – – ns

SDA

SCL

S Sr SP

TBUFI2C

TSPI2CTHDSTAI2C

TSUSTOI2CTSUSTAI2C

TLOWI2C

THIGHI2CTHDDATI2CTHDSTAI2C

TSUDATI2C

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Packaging DimensionsThis section illustrates the packaging specifications for the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC devices along with the thermal impedances for each package.It is important to note that emulation tools require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161.

Figure 10. 16-Pin Chip On Lead 3 X 3 mm Package Outline (Sawn)

001-09116 *D

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Figure 11. 24-Pin (4 x 4 x 0.6 mm) Sawn QFN

Figure 12. 28-Pin (210-Mil) SSOP

1

2. REFER ENC E JEDEC # M O -248

NO TES :

3. UN IT PACKAGE W EIG HT : 0.024 gram s

1. HA TCH IS SO LD ER AB LE EXPO SED M ETAL.

4. ALL D IM ENSIO NS A RE IN M ILLIM ETERS

19

18

13

24

12 7

6

001-13937 *B

51-85079 *C

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Figure 13. 32-Pin QFN 5 x 5 mmX 0.60 Max (Sawn)

Figure 14. 32-Pin (5 x 5 mm 0.60 MAX) QFN

001-48913 *A

001-06392 *A

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Figure 15. 48-Pin (7 x 7 mm) QFN

For information on the preferred dimensions for mounting the QFN packages, see the application note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.It is important to note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices.

Thermal Impedances Table 34 illustrates the minimum solder reflow peak temperature to achieve good solderability.

Solder Reflow Peak TemperatureTable 35 illustrates the minimum solder reflow peak temperature to achieve good solderability.

1. HATCH AREA IS SOLDERABLE EXPOSED METAL.

2. REFERENCE JEDEC#: MO-220

4. ALL DIMENSIONS ARE IN MM [MIN/MAX]

NOTES:

48LD QFN 7 X 7mm PACKAGE OUTLINE

PART #

LEAD FREESTANDARD

LY48A

5. PACKAGE CODE

001-12919SEE NOTES *A

JSO

UNLESS OTHERWISE SPECIFIEDALL DIMENSIONS ARE IN INCHES [MILLIMETERS]

MATERIAL

STANDARD TOLERANCES ON:DECIMALS

.XXX

.XXXX

.XX

-+

-++- COMPANY CONFIDENTIAL

DESIGNED BY

APPROVED BY

APPROVED BY

DRAWNANGLES-+ CHK BY

DATE

DATE

DATE

DATE

DATE

CYPRESSTITLE

SIZE PART NO. DWG NO REV

02/02/07DESCRIPTION

3. PACKAGE WEIGHT: 0.13g

LF48A

PAD EXPOSED

SOLDERABLE

(SUBCON PUNCH TYPE PKG with 5.1 X 5.1 EPAD)001-12919 *A

Table 34. Thermal Impedances Per Package

Package Typical θJA [9]

16 QFN 46 oC/W24 QFN[10] 25 oC/W28 SSOP 96 oC/W32 QFN[10] 27 oC/W48 QFN[10] 28 oC/W

Table 35. Solder Reflow Peak TemperaturePackage Min Peak Temperature [11] Max Peak Temperature

16 QFN 240oC 260oC24 QFN 240oC 260oC28 SSOP 240oC 260oC32 QFN 240oC 260oC48 QFN 240oC 260oC

Notes9. TJ = TA + Power x θJA.10. To achieve the thermal impedance specified for the QFN package, the center thermal pad is soldered to the PCB ground plane.11. Higher temperatures is required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.

Refer to the solder manufacturer specifications.

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Development Tool SelectionSoftwarePSoC Designer™At the core of the PSoC development software suite is PSoC Designer. This is used by thousands of PSoC developers. This robust software is facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com under DESIGN RESOURCES >> Software and Drivers.

PSoC ProgrammerPSoC Programmer is flexible enough and is used on the bench in development and also suitable for factory programming. PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com/psocprogrammer.C CompilersPSoC Designer comes with a free HI-TECH C Lite C compiler. The HI-TECH C Lite compiler is free, supports all PSoC devices, integrates fully with PSoC Designer and PSoC Express, and runs on Windows versions up to 32-bit Vista. Compilers with additional features are available at additional cost from their manufactures. ■ HI-TECH C PRO for the PSoC is available from

http://www.htsoft.com.■ ImageCraft Cypress Edition Compiler is available from

http://www.imagecraft.com.Development KitsAll development kits are sold at the Cypress Online Store.

CY3215-DK Basic Development KitThe CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer supports the advance emulation features also. The kit includes:

■ PSoC Designer Software CD■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter■ Mini-Eval Programming Board

■ 110 ~ 240V Power Supply, Euro-Plug Adapter■ iMAGEcraft C Compiler (Registration Required)■ ISSP Cable

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

CY3210-ExpressDK PSoC Express Development KitThe CY3210-ExpressDK is for advanced prototyping and devel-opment with PSoC Express (used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules, and more. The kit includes:

■ PSoC Express Software CD

■ Express Development Board

■ Four Fan Modules

■ Two Proto Modules

■ MiniProg In-System Serial Programmer

■ MiniEval PCB Evaluation Board

■ Jumper Wire Kit

■ USB 2.0 Cable

■ Serial Cable (DB9)

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples



Evaluation ToolsAll evaluation tools are sold at the Cypress Online Store.

CY3210-MiniProg1The CY3210-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

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CY3210-PSoCEval1The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of bread-boarding space to meet all of your evaluation needs. The kit includes:

■ Evaluation Board with LCD Module


■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)



■ USB 2.0 Cable

CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a devel-opment board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

■ PSoCEvalUSB Board

■ LCD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ PSoC Designer and Example Projects CD


■ Wire Pack

Device ProgrammersAll device programmers are purchased from the Cypress Online Store.

CY3216 Modular ProgrammerThe CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

■ Modular Programmer Base

■ 3 Programming Module Cards




■ USB 2.0 Cable

CY3207ISSP In-System Serial Programmer (ISSP)The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment. Note that CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

Accessories (Emulation and Programming)

Third Party ToolsSeveral tools are specially designed by the following third party vendors to accompany PSoC devices during development and production. Specific details of each of these tools are found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards.

Build a PSoC Emulator into Your Board

For details on emulating the circuit before going to volume pro-duction using an on-chip debug (OCD) non-production PSoC device, see Application Note AN2323 “Debugging - Build a PSoC Emulator into Your Board” at http://www.cypress.com.

Table 36. Emulation and Programming Accessories

Part Number Pin Package Flex-Pod Kit [12] Foot Kit [13] Prototyping

Module Adapter [14]

CY8C20234-12LKXI 16 SOIC - CY3250-16QFN-FK CY3210-0X34 -CY8C20334-12LQXI 24 QFN CY3250-20334QFN CY3250-24QFN-FK CY3210-0X34 AS-24-28-01ML-6CY8C20534-12PVXI 28 SSOP - CY3250-28SSOP-FK CY3210-0X34 -CY8C20434-12LKXI 32 QFN CY3250-20434QFN CY3250-32QFN-FK CY3210-0X34 AS-32-28-03ML-6

Notes12. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.13. Foot kit includes surface mount feet that is soldered to the target PCB.14. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters is found at

http://www.emulation.com.

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Ordering InformationTable 37 lists the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC device’s key package features and ordering codes.

Figure 16. Ordering Code Definitions

Table 37. PSoC Device Key Features and Ordering Information

Ordering Code Package Flash (Bytes)

SRAM (Bytes)

Digital Blocks

CapSenseBlocks

Digital I/O Pins

Analog Inputs

AnalogOutputs

XRES Pin

CY8C20234-12LKXI 16-Pin (3x3 mm 0.60 MAX) Sawn QFN

8K 512 0 1 13 13[15] 0 Yes

CY8C20234-12LKXIT 16-Pin (3x3 mm 0.60 MAX) Sawn QFN (Tape and Reel)

8K 512 0 1 13 13[15] 0 Yes

CY8C20334-12LQXI 24-Pin (4x4 mm 0.60 MAX) SAWN QFN

8K 512 0 1 20 20[15] 0 Yes

CY8C20334-12LQXIT 24-Pin (4x4 mm 0.60 MAX) Sawn QFN (Tape and Reel)

8K 512 0 1 20 20[15] 0 Yes

CY8C20434-12LKXI 32-Pin (5x5 mm 0.60 MAX) QFN

8K 512 0 1 28 28[15] 0 Yes

CY8C20434-12LKXIT 32-Pin (5x5 mm 0.60 MAX) QFN (Tape and Reel)

8K 512 0 1 28 28[15] 0 Yes

CY8C20434-12LQXI 32-Pin (5x5 mm 0.60 MAX) Thin Sawn QFN

8K 512 0 1 28 28 0 Yes

CY8C20434-12LQXIT 32-Pin (5x5 mm 0.60 MAX) Thin Sawn QFN (Tape and Reel)

8K 512 0 1 28 28 0 Yes

CY8C20534-PVXI 28-Pin (210-Mil) SSOP 8K 512 0 1 24 24 0 YesCY8C20534-PVXIT 28-Pin (210-Mil) SSOP

(Tape and Reel)8K 512 0 1 24 24 0 Yes

CY8C20000-12LFXI 48-Pin OCD QFN[16] 8K 512 0 1 28 28[15] 0 YesNote For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

CY 8 C 20 xxx- 12 xx

Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX/LQX = QFN Pb-Free AX = TQFP Pb-Free

Speed: 12 MHzPart NumberFamily CodeTechnology Code: C = CMOSMarketing Code: 8 = Cypress PSoCCompany ID: CY = Cypress

Notes15. Dual function Digital I/O Pins also connect to the common analog mux.16. This part may be used for in-circuit debugging. It is NOT available for production.

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Document History Page Document Title: CY8C20234/CY8C20334/CY8C20434/CY8C20534 PSoC® Programmable System-on-Chip™Document Number: 001-05356

Revision ECN Orig. of Change

Submission Date Description of Change

** 404571 HMT See ECN New silicon and document (Revision **).*A 418513 HMT See ECN Updated Electrical Specifications, including Storage Temperature and

Maximum Input Clock Frequency. Updated Features and Analog System Overview. Modified 32-pin QFN E-PAD dimensions. Added new 32-pin QFN. Add High Output Drive indicator to all P1[x] pinouts. Updated trademarks.

*B 490071 HMT See ECN Made data sheet “Final”. Added new Development Tool section. Added OCD pinout and package diagram. Added 16-pin QFN. Updated 24-pin and 32-pin QFN package diagrams to 0.60 MAX thickness. Changed from commercial to industrial temperature range. Updated Storage Temperature specification and notes. Updated thermal resistance data. Added development tool kit part numbers. Finetuned features and electrical specifications.

*C 788177 HMT See ECN Added CapSense SNR requirement reference. Added Low Power Comparator (LPC) AC/DC electrical specifications tables. Added 2.7V minimum specifications. Updated figure standards. Updated Technical Training paragraph. Added QFN package clarifications and dimensions. Updated ECN-ed Amkor dimensioned QFN package diagram revisions.

*D 1356805 HMT/SFVTMP3/HCL/SFV

See ECN Updated 24-pin QFN Theta JA. Added External Reset Pulse Width, TXRST, specification. Fixed 48-pin QFN.vsd. Updated the table introduction and high output voltage description in section two. The sentence: "Exceeding maximum ratings may shorten the battery life of the device.” does not apply to all data sheets. Therefore, the word "battery" is changed to "useful.” Took out tabs after table and figure numbers in titles and added two hard spaces. Updated the section, DC General Purpose IO Specifications on page 16 with new text. Updated VOH5 and VOH6 to say, ”High Output Voltage, Port 1 Pins with 3.0V LDO Regulator Enabled.” Updated VOH7 and VOH8 with the text, “maximum of 20 mA source current in all IOs.”Added 28-pin SSOP part, pinout, package. Updated specs. Modified dev. tool part numbers.

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Document Number: 001-05356 Rev. *H Revised April 16, 2009 Page 34 of 34PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.All products and company names mentioned in this document may be the trademarks of their respective holders.

CY8C20234, CY8C20334CY8C20434, CY8C20534

Sales, Solutions, and Legal Information Worldwide Sales and Design SupportCypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

ProductsPSoC psoc.cypress.comClocks & Buffers clocks.cypress.comWireless wireless.cypress.comMemories memory.cypress.comImage Sensors image.cypress.com

PSoC SolutionsGeneral psoc.cypress.com/solutionsLow Power/Low Voltage psoc.cypress.com/low-powerPrecision Analog psoc.cypress.com/precision-analogLCD Drive psoc.cypress.com/lcd-driveCAN 2.0b psoc.cypress.com/canUSB psoc.cypress.com/usb

*E 2197347 UVS/AESA See ECN Added 32-pin Sawn QFN Pin diagramRemoved package diagram: 32-Pin (5 X 5 mm) SAWN QFN(001-42168 *A)Updated Ordering Information table with CY8C20434-12LQXI and CY8C20434-12LQXIT ordering details.Corrected Table 16. DC Programming Specifications - Included above the table "Flash Endurance and Retention specifications with the use of the EEPROM User Module are valid only within the range: 25°C +/-20C during the Flash Write operation. Refer the EEPROM User Module data sheet instructions for EEPROM Flash Write requirements outside of the 25°C +/-20°C temperature window."

*F 2542938 RLRM/AESA 07/30/2008 Corrected Ordering Information format. Updated package diagrams 001-13937 and 001-30999. Updated data sheet template. Corrected Figure 6 (28-pin diagram).

*G 2610469 SNV/PYRS 11/20/08 Updated VOH5, VOH7, and VOH9 specifications*H 2693024 DPT/PYRS 04/16/2009 Changed title from PSoC® Mixed Signal Array to PSoC® Programmable

System-on-Chip™Replaced package outline drawing for 32-Pin Sawn QFNUpdated “Development Tool Selection” on page 30 Updated “Development Tools” on page 4 and “Designing with PSoC Designer” on page 5Updated “Getting Started” on page 3

Document History Page (continued)

Document Title: CY8C20234/CY8C20334/CY8C20434/CY8C20534 PSoC® Programmable System-on-Chip™Document Number: 001-05356

Revision ECN Orig. of Change

Submission Date Description of Change

© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use ofany circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used formedical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use ascritical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systemsapplication implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypressintegrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited withoutthe express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIESOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does notassume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems wherea malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturerassumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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Documents

PSoC Programmable System-0n-Chip™ · Low Power CapSense™ Block Configurable Capacitive Sensing Elements Supports Combination of CapSense Buttons, Sliders, Touch - pads, and Proximity