Materials Conference

Enabling an End-to-End Ecosystem for 22FDX - Materials, Design, Manufacturing

J. CordovezRegion Head, EMEAGLOBALFOUNDRIES, München, Germany

AbstractFDSOI technology has benefited from appreciable market traction by delivering low-power and cost-effective-performance to wireless and battery-powered applications. In order for such an advanced technology to efficiently serve its target markets, it requires a robust end-to-end ecosystem that enables prompt and high-quality delivery of differentiated solutions. Specifically, the complexity and compressed schedules of organic product development have reached inaccessible levels, therefore platform ecosystems must be crafted to create an open market place for tailored solutions and services that lower the barrier of entry into next generation silicon. To this end, the GLOBALFOUNDRIES 22nm FDSOI “22FDX®”technology, has been deployed accompanied by a complete ecosystem – from substrate to packaging - that offers open access to enablers that accelerate the development of wireless, IoT, automotive, and mobility segment solutions. This work will present the 22FDX design ecosystem features and focus on FDSOI materials, semiconductor and system design methodology, fabrication, andvalue-add service offerings. Examples of these ecosystem value adders will be presented including FDSOI-specific use-cases related to materials, design, and manufacturing.

BiografieJuan Cordovez joined GLOBALFOUNDRIES in November 2012 and brings almost 20 years of semiconductor customer engagement, field technical sales, and design innovation experience. He leads the GLOBALFOUNDRIES EMEA Region and is responsible for end-to-end customer engagement from lead through revenue. Prior to this Sales and Business Development role, Juan led the GLOBALFOUNDRIES Customer Design Enablement team including including ownership of Field Applications Engineering, PDK, Device Modeling, and Design Methodology. Prior to GLOBALFOUNDRIES, Juan served as Vice President of Sentinel IC Technologies. In this role he conceived business model and founded independent design enablement startup focusing on RF/analog/power design productivity. Juan was architect and principal programmer of several patented RF CMOS SoC and BCD IC design productivity tools as well as lead for customer engagement and software support. Prior to founding Sentinel, he was the manager of Design Enablement and Design Support at

Jazz Semiconductor. Prior to Jazz Semiconductor, he was with Conexant Systems in the Advanced Process Technology group. Juan received BS and MS degrees in Electrical Engineering from the University of California, Irvine. He has authored over 12 technical publications and educational seminars, holds several patents in the area of IC Design Enablement, and is a Senior Member of the IEEE.

J. BarthaProfessorTU Dresden, Dresden, Germany

BiographyProf. Dr. Johann W. Bartha received a Diploma and PhD. degree in solid state physics at the University of Hannover, Germany. He was two years Post Doc at the IBM T. J. Watson Research Center Yorktown Heights, N. Y. were he investigated Metal Polyimide interfaces for applications in multi layer ceramic packaging. 1985 he joined the IBM German Manufacturing Technology Center (GMTC) at Sindelfingen Germany as staff member and became responsible for plasma based technologies in semiconductor processing as a senior staff member. 1994 he accepted a C3 professorship at the University of Applied Sciences at Münster, Germany where he established a laboratory for micro manufacturing. 1999 he accepted a C4 professorship as head of the chair for Semiconductor Technology at the Technische Universität Dresden (TUD). Since March 2003 he is director of the Institute of Semiconductor- and Microsystems Technologies at TUD and established a strong collaboration between the Dresden University and the local semiconductor Industry. The research focus at his chair is BEOL processing, 3D integration including electrical and optical TSVs as well as Silicon thin film PV. The search for ultrathin conformal Cu barriers as required in damascene technology initiated the interest in ALD. In the meantime, the materials studied include high-k dielectrics, moisture barriers, metals, nitrides and graphene. Specific focus is on in-situ and in-vacuo analysis of the nucleation and growth within the ALD processes.

Engineered Substrates : enabling performance, power and cost to meet applications requirements

C. MalevilleEVP, Digital Electronics Business Unit General ManagerSOITEC, Crolles, France

AbstractMoore’s law, More than Moore, more Moore..; industry is showing great imagination in describing trends in semiconductors. Overall, it appears that applications requirements such asmobility and connectivity, Automotive, image sensors, … are all converging towards more analog blocks and functions, complemented by digital on demand. Power budget, driven by battery time or thermal constraints, is becoming major requirement as long, of course, as cost remains compatible with market segment. FDSOI adoption is a good example of how this combination of good analog behavior and premium performance is able to fit with major markets roadmaps. In this talk, engineered substrate properties and design will be discussed as a strong basement for device enablement,variability and overall positioning to meet end user requirements. Such advanced substrates are also becoming integration platforms to combine more functions covering digital, communication, Photonics, imager domains, in order to provide broader applications within same handset.

BiografieChristophe Maleville has been appointed senior vice president of Soitec’s Digital Electronics BU in 2010. He joined Soitec in 1993 and was a driving force behind the company’s joint research activities with CEA-Leti. For several years, he led new SOI process development, oversaw SOI technology transfer from R&D to production, and managed customer certifications. He also served as vice president, SOI Products Platform at Soitec, working closely with key customers worldwide. Maleville has authored or co-authored more than 30 papers and also holds some 30 patents. Hehas a PhD in microelectronics from Grenoble Institute of Technology and obtained an executive MBA from INSEAD.

Physics of Advanced Devices for IoT Applications

T. SkotnickiFellow and Technical Vice PresidentSTMicroelectronics, Crolles, France

AbstractElectronics is more and more pervasive in everyday life: smartphones, smart cars, smart cities, smart health, smart agriculture, etc. that all rely on Internet of Things (IoT) technologies. A key requirements these applications imply at the device level are: low power, low voltage and low leak. UTBB (ultra-thin body and BOX) FDSOI (Fully Depleted Silicon On Insulator) is a planar semiconductor technology that is particularly well suited for IoT applications. We will show its advantages with respect to low power, low leak and low voltage operation. We will demonstratethis on the example of the 28nm UTBB SOI technology that STMicroelectronics is offering for LP mobile applications and in particular for IoT systems.

BiografieThomas SKOTNICKI is the STMicroelectronics Company Fellow and Technical Vice-President in charge of Disruptive Technologies. In 2007, he received the title of Professor from the President of Poland, and recently has been appointed the Director of CEZAMAT (Research Consortium) in Warsaw, Poland. The focus of his program at STMicroelectronics is on Low Power / Low Variability for 28nm and beyond CMOS, on innovative device structures, new memory concepts and cells, and on integration of new materials for CMOS. He has inferred the advantages of Ultra-Thin Body and BOX FDSOI from his Voltage Doping Transformation in 1988, and has consequently driven this concept towards successful industrialization that was decided at STMicroelectronics in 2011. From 2010 he has extended the scope of his program to include Energy Harvesting for autonomous Low Power systems and devices. He holds more than 80 patents on new devices, circuits and technologies. He has presented over 50 Invited Papers and Short Course Lectures, (co-) authored about 350 scientific papers (review based), and several book chapters in the field of CMOS and Energy Harvesting. From 2001 to 2007, he served as Editor for IEEE Transactions On Electron Devices. He has been teaching at EPFL (Lausanne, Switzerland) and SUPELEC (Rennes, France), and has supervised and led to successful defence 26 PhD theses. He has been serving in numerous Conference Program and Executive Committees (IEDM, VLSI, ESSDERC, ECS, SNW, IWJT), Academia Advisory Boards, Governmental Expert Commissions, R&D Program Steering Committees, IEEE Award Committees (JJ Ebers and Frederik Philips), and ITRS (who had been using his/his team softwareMASTAR for 12 consecutive editions). He is an IEEE Fellow and SEE Senior Member.

Current status and trends in RF SOI material and device

J.-P. RaskinProfessorUniversité catholique de Louvain, Louvain-la-Neuve, Belgium

AbstractPerformance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency commercial applications pushing the limits of CMOS technology. Thanks to the introduction of the trap-rich high-resistivity SOI substrate on the market, the ICs requirements in term of linearity for RF switches, for instance, are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this lecture, their analog/RF behavior is described and compared. Both show pretty similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances. The use of specific RF test structures at the early stage of a technological node development is of first importance to analyze the transistor parasitic resistances and capacitances, the transistor cutoff frequencies, the self-heating, and the substrate coupling and non-linear behavior. The relative impact of the transistor and the passive elements and interconnections on the small- and large-signal RF performance of SOI RF switches and power amplifier will be presented.

BiografieJean-Pierre RASKIN (IEEE M'97, IEEE SM’06, IEEE F’14) was born in Aye, Belgium, in 1971. He received the Industrial Engineer degree from the Institut Supérieur Industriel d'Arlon, Belgium, in 1993, and the M.S. and Ph.D. degrees in Applied Sciences from the Université catholique de Louvain (UCL), Louvain-la-Neuve, Belgium, in 1994 and 1997, respectively. From 1994 to 1997, he was a Research Engineer at the Microwave Laboratory, UCL, Belgium. He worked on the modeling, characterization and fabrication of MMIC's in Silicon-on-Insulator (SOI) technology forlow-power, low-voltage applications. In 1998, he joined the EECS Department of The University of Michigan, Ann Arbor, USA. He has been involved in the development and characterization of micromachining fabrication techniques for microwave and millimeter-wave circuits and microelectromechanical transducers/amplifiers working in harsh environments. In 2000, he joined the Microwave Laboratory of UCL, Louvain-la-Neuve, Belgium, as Associate Professor, and he has been a Full Professor since 2007. From September 2009 to September 2010, he wasvisiting professor at Newcastle University, Newcastle Upon Tyne, UK. Since 2014 he has been the head of the Electrical Engineering Department of UCL. His research interests are the modeling, wideband characterization and fabrication of advancedSOI MOSFETs as well as micro and nanofabrication of MEMS / NEMS sensors and actuators, including the extraction of intrinsic material properties at nanometer scale. He is IEEE Fellow, EuMA Associate Member, Société de l'électricité, de l'électronique et des

technologies de l'information et de la communication (SEE) Member, and Material Research Society (MRS) Member. He was the recipient of the Médaille BLONDEL 2015, famous French reward that honors each year a researcher for outstanding advances in science which have demonstrated a major impact in the electrical and electronics industry. He received the SOI Consortium Award in 2016 in recognition in his vision and pioneering work for RF SOI. He is author or co-author of more than 700 scientific articles.

Enhanced SOI manufacturing process for new generation MEMS devices

V.-P. LempinenSenior Manager, Customer SupportOkmetic Oy, Vantaa, Finland

AbstractThe rapidly growing IoT industry sets new demands for microelectromechanical system (MEMS)devices, the central building blocks of smart systems. Advanced MEMS devices are commonly built on thick-film bonded Silicon-On-Insulator wafers (BSOI), to gain benefits in precision and control of MEMS structures, device miniaturization and packaging. BSOI substrates offer advantages also in high voltage semiconductor device applications, where electrical isolation ofdevices is improved and allowing smaller device footprint. The tightening requirements on SOI wafer specification and device layer thickness uniformity in particular are driving traditional planarization technologies like CMP to their limits. Okmetic’s new process with superior thickness variation control fully independent of SOI film thickness and suitable for high volume production complements today’s manufacturing technologies perfectly. This new trimming technique for thick-film SOI processes reduces film thickness variation by a factor of five achieving a typical thickness variation of 20-30 nm (1σ) across a 200 mm SOI wafer. This is clearly beyond those achievable through traditional BSOI volume production. The process performance has no equal for film thicknesses above 5 µm but it can also be used in applications previously dominated by alternative SOI technologies in the range < 2 µm such as specific high-performance MEMS sensors, SOI-based smart power devices and silicon photonic devices. The process also brings significant advantages for MEMS applications in which SOI film thickness variation is critical, such as silicon oscillators and pressure sensors.

BiografieMr. Lempinen received his M.Sc. in Materials Physics in 1999. Mr. Lempinen has over 15 years of experience in Silicon based material engineering. He has worked for Okmetic since 2000 andheld various positions related to R&D, process engineering and applications support. Currently he is working as Senior Manager, Customer Support being responsible for the company’s globaltechnical customer support organization. Prior to his time at Okmetic, Lempinen was involved in photovoltaic research in Electron Physics laboratory of Helsinki University of Technology, Finland and Microelectronics Research Center of Iowa state University, U.S.A.

T. MikolajickChair of Nanoelectronic Materials TU Dresden andScientific Director of NaMlab gGmbHNamlab and TU Dresden, Dresden, Germany

BiographyThomas Mikolajick received the Diploma (Dipl.-Ing.) in electrical engineering in 1990 and his phD in electrical engineering in 1996 both from the University Erlangen-Nuremberg. From 1996 till 2006 he was in the semiconductor industry developing CMOS processes, Ferroelectric Memories, emerging Non-volatile Memories and Flash Memories first at Siemens Semiconductorand later at Infineon. In late 2006 he moved back to academia taking over a professorship for material science of electron devices and sensors at the University of Technology Freiberg, and in October 2009 he started at Technische Universität Dresden were he now holds a professorship for Nanoelectronic Materials in combination with the position of scientific director

at NaMLab GmbH. Since April 2010 he is the coordinator of the “Cool Silicon” Cluster in Dresden. Prof. Mikolajick is author or co-author of more than 300 publications in scientific journals or at scientific conferences and inventor or co-inventor of about 50 patents.

Ferroelectric hafnia - Enabling next generation semiconductor memories

M. MennengaBusiness DevelopmentFerroelectric Memory GmbH, Dresden, Germany

Abstract10 years ago, ferroelectricity has been discovered in hafnium oxide (HfO2). Since then, intense academic and industry R&D have proven the ideal suitability of ferroelectric HfO2 for memory applications ranging from standalone NVM or DRAM replacement to a fundamental change in the embedded memory space. This talk explains the fundamental memory characteristics of ferroelectric HfO2 highlighting the ideal suitability of the material for requirements that are set by today’s semiconductor products. Ultra-low power consumption and compatibility to advanced manufacturing environments are only a few of these requirements besides scalability, high write speeds and robust reliability. Within the last 10 years of R&D it could be verified that the ferroelectric properties in hafnia indeed meet these criteria and therefore promise to enable next generation memory products at the latest technology nodes. Besides the intrinsic memory properties, the talk will also cover the implementation of the memory material in FeFET memory cells. This memory cell, which is based on replacing the gate insulator of a standard logic transistor by a ferroelectric material, is sometimes consideredthe “holy grail” in semiconductor device engineering. The discovery of ferroelectricity in HfO2 has revived this almost forgotten memory concept once again. In 2016, the Ferroelectric Memory Company has been formed in order bring the FeFET memory concept finally into mass markets. We will present the latest status in FeFET development and give an outlook on our memory roadmap.

BiografieMenno Mennenga is a co-founder of FMC where he is responsible for business development. He worked for Advanced Micro Devices (AMD), Atmel, and, as a Freelance Consultant, for several other first tier semiconductor companies. His professional experience includes system architecture, engineering management, marketing, and sales. He holds electrical engineering degrees from Texas A&M University and Dresden University of Technology.

FeFET: A promising embedded Non-Volatile Memory solution for leading edgeHKMG CMOS technologies

S. DünkelIntegration Engineer NVMGLOBALFOUNDRIES Fab1, Dresden, Germany

AbstractFerroelectric HfO2 enables a scalable and CMOS compatible embedded non-volatile memory (eNVM), keeping pace with the scaling demands of leading-edge logic technologies. We have developed an innovative and non-invasive eNVM process applicable for HKMG technologies. The hafnium-based FeFET was embedded into GLOBALFOUNDRIES high-volume gate-first 28nmHKMG super low power platform (28SLP). The simultaneous integration of CMOS devices together with the FeFET on the same chip is demonstrated in this talk. The FeFET gate stack (material, thickness, etc.) can be optimized independently from the baseline 28nm device integration. An arbitrarily mixed placement of CMOS and FeFET devices in the same circuit is possible. We will show test results of an embedded 32 MBit memory array and discuss pattern write and read capability. High temperature data retention, program/erase endurance and benchmarking against other memory concepts will be presented.

BiografieDr. Stefan Dünkel received the Diploma (Dipl.-Ing.(FH)) in electrical engineering in 2005 from the University of Applied Sciences Dresden, Germany, and his PhD in microelectronics from Dresden University of Technology in 2010. In the same year, he joined GLOBALFOUNDRIES, working as a device engineer on the development of 45nm, 32nm and 28nm SOI and bulk CMOS technologies. Since 2015 he is working as an integration engineer in the embedded-NVMgroup focusing on the development and prototyping of different memory concepts. Dr. Dünkel is author or co-author of more than 40 publications in scientific journals or at scientific conferences and inventor or co-inventor of about 75 patents.

Orthorhombic phase formation in doped HfO2 for ferroelectrics

M. PopoviciSenior ResearcherImec, Leuven, Belgium

AbstractFerroelectric (FE) materials are potential candidates for emerging memory applications due to their spontaneous polarization, which can be reversed by the application of an electric field. A ferroelectric gate stack for non-volatile random-access memory (RAM) applications utilizes the polarization of the ferroelectric material within the gate stack. Atomic layer deposition of thin films in 3D structures is the most envisaged method to achieve 3D Ferroelectric Field-Effect Transistors (FEFET). The observation of ferroelectricity in HfO2, currently mainstream as gate dielectric in semiconductor logic technology, has redirected focus to this material as ferroelectric. HfO2 is a polymorphic material. The monoclinic phase is the most common crystalstructure obtained through thermal treatment at temperatures below 900oC when thin films are deposited as a pure HfO2. However, the cubic HfO2, which is known as a very high temperature phase, can appear at lower temperatures when doped by a metal during deposition. Larger radius dopants (e.g. Gd3+) in comparison to Hf4+ favor the formation of thecubic phase, whereas smaller radius dopants (e.g. Al3+) can induce the appearance of the tetragonal phase. However, the appearance of the less-known non-centrosymmetric orthorhombic phase (o-HfO2) can be triggered below a certain doping level and layer thickness and when the cystallization of the doped HfO2 films take place under the stress induced by a cap layer. At imec, we investigate the fabrication of a 3D vertical FEFET with silicon-insulator-silicon (SIS) structure. A 3D ferroelectric Al doped HfO2 device for NAND applications was fabricated. Electrical results confirmed the presence of the ferroelectric phase with a coercive voltage (2Vc) of 6V extracted from the hysteresis loop. Reliability studies showed the potential of this device for nonvolatile memory applications.

BiografieMihaela Popovici is senior researcher within the Semiconductor Technology and Systems unit atimec, Belgium. She has a BSc and MSc in Chemical Engineering and received her PhD in Materials Science and Engineering in 2004 at the “Politehnica” University of Timisoara, Romania. After a two years post-doc at Philips Research Netherlands (Photonic Materials and Devices department) she joined imec in 2007. Her main expertise resides in dielectric oxides and metal thin films development (ALD, CVD and PVD), physical and electrical characterization and design of complex materials stacks with applications in microelectronic electronic devices, such as metal-insulator-metal (MIM) capacitors for DRAM, Ferroelectrics and active layers mainly for RRAM, STT-MRAM and Interconnect applications. Currently she is the technical lead of the DRAM MIMCAP project and involved as material expertin the Ferroelectrics project at imec. During her career, together with the technical teams, she has demonstrated the ability to bring innovation, reflected by her patent and publication track record. Today she has an h-index of 15.

The automotive transformation – new technology drivers, the role of the semiconductor industry and the need for new industry alliances

A. AalSemiconductor StrategyVolkswagen AG, Electronic Analysis / Robustness, Wolfsburg, Germany

AbstractA strongly growing fraction of required semiconductor functions in upcoming vehicle architectures, as of today, is based on semiconductor technologies and IP sets that have not been designed and qualified for automotive use. The corresponding gaps between automotive application requirements and semiconductor product capabilities w.r.t. automotive sub-functionalities, reliability, safety and security have to be analyzed and closed within the framework of a systematic, technical and economic risk management process. This process itself needs to be aligned, agreed and standardized along the supply chain. New and intense communication and work structures between car OEMs and semiconductor vendors (IDMs, Fabless & Foundries) as well as tier one’s are needed as the dependability on semiconductor market dynamics (availability, different targeted markets, etc.) and time-to-market innovations forces increase more than ever. It is an evolutional and logical step within the automotive transformation to partially act as an electronic vendor since 65% of major costs will be electronics and SW by 2025. The mentioned process (“capability enhancement process”) covers the automotive application (i.e. ECU), the underlying hardware system (PCBA) and corresponding active and passive components from a technical as well as an economic and architecture perspective. This includes system design for change management (updateability and upgradeability) - a hot topic that is strongly market driven as innovation cycles continue to shrink (ADAS/AI, CCAR, Infotainment). Considering the whole vehicle live cycle cost structure, itis obvious that the technology cycle time has immense influence on change management cost efforts and re-qualification processes. A technology that is very promising from a reliability, cost and market durability standpoint is FDSOI. So, comments on the opportunities of FDSOI forautomotive as well as the need for potentially new package technologies will also be given.

BiografieAndreas Aal drives the semiconductor strategy and reliability assurance activities within the electric-/electronic development department at Volkswagen, Germany, which he joint 2011. Hisactivities concentrate on technology capability enhancement of nodes down to 12 nm as well as optimization of power electronics for automotive applications. He leads two semiconductor related European projects and is a strong representative of the through-the-supply-chain-joint-development approach. Mr. Aal has been working within the semiconductor industry since 1998 holding different positions from engineering to management working on production monitoring, process and technology development, qualification and failure analysis. Andreas (certified reliability professional) published and co-authored various papers, has given invited talks and tutorials, served as reviewer for different Journals and has served in the

technical and management committee for IEEE IIRW. He is a member of the IEEE Electron Devices, CPMT, Nuclear and Plasma Sciences, Reliability and Solid-State Circuits Societies and also a frequent participant / contributor of the JEDEC subcommittee 14.2. Since 2007 he is chairof the German ITG group 8.5.6 (VDE) on (f) WLR, reliability simulations and qualification.

C. AdelmannPrincipal Member of Technical StaffImec, Leuven, Belgium

BiographyChristoph Adelmann obtained a PhD degree in condensed matter physics in 2002 from Université Joseph Fourier Grenoble for work at the CEA Grenoble. Until 2006, he was a postdoctoral research associate at the Department of Chemical Engineering and Materials Science at the University of Minnesota working on spintronic materials and devices. He subsequently joined imec where he is working as a Principal Member of Technical Staff in the Thin Films Group on metallic and dielectric materials for logic, interconnects, and memory as well as on novel devices for nanoelectronic applications. He is currently the technical lead of projects on advanced alternative metallization for BEOL as well as magnetoelectric and spintronic devices for beyond-CMOS logic applications.

Maximum Utilization of Chemically Amplified Resist

M. MomotaResearch ManagerFUJIFILM Corporation, Electronic Materials Research Laboratories, Shizuoka, Japan

AbstractVariety of technologies have been developed to overcome resolution limit on photolithography because of the smaller design rules to realize low voltage, high integration, cost down, etc. For the purpose, photo resist plays the one of the important roles to drive pattern shrinkage, whereFUJIFILM proposed Negative Tone Development (NTD) in order to fully utilize ArF Chemically Amplified Resist (CAR) capability since 2005. Organic solvent dissolves unexposed resist to form negative tone image, which process can print highly fine dark pattern by the high contrastof the bright mask. (e.g. hole or dark trench patterns formed by dot or bright line masks) In this presentation, chemistry and features of NTD will be described, besides, NTD can be diverted to KrF or EUV lithography, of which expected advantages will be introduced, respectively.

BiografieMakoto Momota joined Fujifilm Research & Development Centre in 1990, then to move Fujifilm Electronic Materials Japan in 2003. In 2005, he was relocated to Fujifilm Electronic Materials U.S.A. as a Product Development Manager for advanced 193 nm resist. He had developed variety of photo resists from i-line, 248nm, up to 193nm, who is currently involved in Electronic Material Research Laboratory in Fujifilm since 2007 as a Research Manager, for advanced resistmaterials development.

Batch ALD and CVD Nanolayers for More than Moore Devices

P.M. ZagwijnSenior Technical Product ManagerASM International N.V., Almere, Netherlands

AbstractThe emerging era marked as the Internet of Things shows increasing demand of so-called More than Moore (MtM) devices. They find numerous applications, including sensing and detecting in the consumer, health, lifestyle, and automotive markets. In this paper we report on Atomic Layer Deposition (ALD) Technology and Chemical Vapor Deposition (CVD) Applications that enable development of novel MtM devices. ALD Metal Oxide films with high performance parameters such as excellent barrier properties are reviewed. ALD Metal Nitride films form the basis for electrodes that need to be deposited in high aspect ratio structures. We have characterized the capability of selected ALD processes to deposit highly conformal films on 3D structures at low temperatures. Other ALD and CVD dielectrics that modify strain in resonators and MEMS devices are also discussed. All ALD and CVD nanolayers are developed on high productivity platforms for both large and small wafer sizes, to match the low cost manufacturing environment required for the MtM device markets. Examples of device applications discussed include light output enhancement layers for LED components, high sensitivity Gate stacks in Bio-MEMS detectors, improved adhesion layers for TSV metals in MEMS, and High Voltage Gate Dielectrics for III-Nitride Power Devices. Keywords—ALD; CVD; MEMS; Internet of Things; More than Moore; GaN Power; LED

BiografieAfter receiving his PhD degree in Physics and Mathematics from the University of Amsterdam in1993 on Ga Delta-Doping Layers in Silicon, Peter Marc ZAGWIJN did Post-Doctoral research at the FOM-Institute of Atomic and Molecular Physics in Amsterdam in cooperation with Philips Research Laboratories on Model Systems for Scandate Cathodes. He joined ASM in 1996 in Research and Development and as a Principal Process Engineer worked on a suite of Nanolayer Applications on 150mm, 200mm and 300mm wafer sizes. After 8 years in R&D he specialized in the Technical Marketing of Advanced Applications for ASM’s Thermal Products Platforms, currently as a Senior Technical Product Manager. He holds 4 US patents and has (co-)authored more than 30 scientific papers all on the structureand growth of Nanolayers.

FEOL Patterning Challenges for Sub 14nm FDSOI Technology

N. PossemeSenior ScientistCEA-LETI, Grenoble, France

AbstractFully-depleted SOI devices (FDSOI) are proven to provide excellent control of gate electrostatics. This makes them a real solution to meet performance requirements down to 10nm technology node. However new architectures such as stacked silicon nanowires will be required to maintain low leakage current when further downscaling gate length. Additionally new materials are required to build transistor channel complying with ON-state current expectations, such as new channel materials such as germanium or compound semiconductorsor low k materials at the spacer level. These changes in transistor integration raise quite a number of new challenges for etching and stripping in that they introduce new materials with uncommon properties compared to usual silicon-based devices. Another challenging aspect of device downscaling is the enhanced demand for high-selectivity etch. In spacer definition for instance, maximum allowable silicon recess in source / drain regions is less than 0.5nm for the 14nm node. New techniques are being developed that involve a prior modification of the etched layer down to a controlled depth, followed by the removal of the modified layer selectively to the non-modified material. On the technology side, immersion 193nm lithography has reached its limits in resolution and the most critical levels require costly dual or quad-patterning technique to achieve stringent CDspecifications in current 14nm and beyond. Solutions to further expand 193nm lithography capabilities at lower costs are showing promising results, such as sidewall image transfer (SIT) or directed self-assembly (DSA). Nevertheless these newly developed techniques involve process adaptations on the plasma etching side since they induce changes in the masking materials.

BiografieDr. Nicolas Posseme is senior scientist at CEA-LETI. He received his Ph.D. degree in microelectronics from the University Joseph Fourier of Grenoble,France (2005). He has worked for LETI in different institutions such as ST Microelectronics, IBM and Applied Materials where he lead several research work in the field of plasma etching for nanoelectronics. He has published over 70 scientific papers and two books on the field of plasma etching, and is holding over 20 patents.

Interconnect Technology Trends for Single Digit Nodes

M. NaikPrincipal Member of Technical StaffApplied Materials Inc, Sunnyvale, United States

AbstractInterconnect resistance is the one of the most critical high value problem for CMOS scaling. There is nice little trade-off between resistance scaling, good metal fill and reliability. We will explore the challenges and options for extending Copper metallization from the perspective of these trade-offs. Beyond Cu, resistance scaling will be driven by conductors that have mean free path lower than that of Cu; which promise larger conductor volume and better reliability. We will take a close look at the leading candidates and summarize the state of the art.

BiografieMehul Naik is a Principal Member of Technical staff with the Advanced Product Technology Development team in the Transistor and Interconnect Group at Applied Materials Inc. He is responsible for the Interconnect Program and serves as a cross-functional owner of Applied’s interconnect roadmap. Mehul has over 20 years of experience in the Interconnect space where he has authored over 45 publications and holds 50 U.S patents on various topics including Cu and alternate metallization, CMP, selective deposition, process flows, low k integration, and double patterning. He currently serves as program committee member on the International Interconnect Technology Conference(IITC) and Advanced Metallization Conference(AMC). Previously, he has served as the Chair for the Back-End Processes Technical Advisory Board, and was a member of the Interconnect and Packaging Sciences Science Area Coordinating Committee in Semiconductor Research Corporation. Mehul holds a Ph.D. in Chemical Engineering from Rensselaer Polytechnic Institute.

FD-SOI multi-film thickness metrology tool

S. Braunproject/product leaderHSEB Dresden, Dresden, Germany

AbstractFully depleted silicon on insulator wafers (FD-SOI) are increasingly conquering today’s technologies and customer products. Though technology benefits like high switching speed andlow power consumption are strongly dependent from wafer’s film thicknesses and homogeneityfor what reason a tight control of these features during wafer and chip manufacturing are indispensable. Thus, the FD-SOI industry needs new solutions to measure ultra-thin multi-layer systems with sub-angstrom reproducibility, high spatial resolution, and production worthy throughput. In order to offer our customers an extensive and reliable solution to their needs, HSEB presentsthe second evolution of the fully automated ultra-thin film inspection tool BALDUR 303 FD-SOI. Phase I of BALDUR FD-SOI already offered a comprehensive list of features like thickness measurement and reproducibility in sub-angstrom range, adjustable spatial resolution from full wafer overview to submicron inspection, report of tool performance indices like reproducibility and accuracy on wafer and lot basis and a production worthy wafer throughput. BALDUR Phase II makes a step ahead to measuring multi-film systems by offering simultaneous measurement of two film thicknesses with a selectable combination of light frequencies (patent pending). A product-dependent selection of light frequencies enhances the range of applications to even thinner layers and new materials. It additionally raises the reproducibility and overcomes systematic limitations of the first phase. The throughput has been further enhanced and the selectable high spatial resolution allows to control overall wafer uniformity as well as sub-µm film thickness homogeneity down to single-µm areas. The BALDUR system complements HSEB's field proven modular tool platforms for fully automated inspection and metrology applications. Thus, it can run fully automatic as well as in a manual mode and incorporates all automation requirements in a SEMI conform manner.

BiografieSebastian Braun did his master degree in Mechatronic (deepening: Simulation and Control) at the Technical University Darmstadt in 2013. After participating as product developer in differentminor medical and automation projects, in 2014 he was promoted to leadership of a comprehensive redevelopment project of a cable manufacturing machine. After completion of alpha and beta phase, he changed to HSEB and assumed the product management of BALDUR platform in 2016.

Additive impact on Cu microstructure for sub 10µm L/S

T. BeckGlobal Business Manager, Semiconductor Advanced PackagingAtotech Deutschland GmbH, Berlin, Germany

AbstractNext generation devices require decreasing the RDL pitch down to 2x2µm. Redistribution layersare essential to a variety of packaging technologies, as it is with more RDLs that I/O density is increased. A higher I/O density 1) provides more physical connections to the PCB, enabling better heat flow, which is critical to thermal performance; 2) enables improved electrical performance, as more outputs results in faster electrical signals between die; 3) allows the package to perform more operations in parallel due to the presence of more electrical pathways. In sum increasing the I/O count allows for more complex, high speed die to be packaged and facilitates improved reliability performance. Successful formation and plating of such fine features, however, pose a challenge for both suppliers and manufacturers, with the primary plating challenge being the simultaneous platingof ultra fine L/S, large Cu pads, and filling of microvias with a deposition rate that optimizes throughput. Additionally, the mechanical properties and impurity requirements for the Cu deposition become more difficult to control and optimize with sub 10µm L/S: 1) large grain, polygonal Cu crystal structure for high ductility – which may influence the prevalence of cracks in the metal lines – and low resistivity which impacts electrical performance; 2) low internal stress for minimized wafer warpage and good adhesion – both of which impact yield; and 3) loworganic co-deposition for minimized microvoiding. Electroplating with standard Cu electrolytes results in microvoiding that amass after thermal cycle testing and may lead to failures or breakages in the Cu metal lines. To overcome this, the bath conditions, additives, and current density should be adjusted to optimize their influence on the deposit properties in terms of impurities and grain size. This paper will discuss how additives on the molecular scale impact Cu microstructure and will present plating results achieved with a new electrolyte.

BiografieFor the past seven years, Thomas Beck has managed and grown Atotech’s Semiconductor Advanced Packaging division. His primary responsibilities include the management and execution of all activities and objectives related to R&D, process development, integration and introduction of new technologies, global marketing and sales strategies, among others, for bothECD and electroless processes. Previously he held the same position for a different technology division within Atotech, called Surface Finishes. As Business Manager for Surface Finishes, he led many projects to market success.

Quantum Mechanical Simulation for the Analysis, Optimization and Accelerated Development of Precursors and Processes for Atomic Layer Deposition (ALD)

C. KrauterSenior Applications ScientistSchrödinger GmbH, Materials Science, Mannheim,Germany

AbstractContinued miniaturization and increasingly exact requirements for thin film deposition in the semiconductor industry is driving the search for new effective, efficient, selective precursors and processes. The requirements of defect-free, conformal films, and precise thickness control have focused attention on atomic layer deposition (ALD). ALD precursors so far have been developed through a trial-and-error experimental approach, leveraging the expertise and tribal knowledge of individual research groups. Precursors can show significant variation in performance, depending on specific choice of co-reactant, deposition stage, and processing conditions. The chemical design space for reactive thin film precursors is enormous and there isurgent need for the development of computational approaches to help identify new ligand-metal architectures and functional co-reactants that deliver the required surface activity for next-generation thin-film deposition processes. In this presentation we discuss quantum mechanical simulation (e.g. density functional theory, DFT) applied to ALD precursor reactivity and state-of-the-art automated screening approaches to assist experimental efforts leading toward optimized precursors for next-generation ALD processes.

BiografieDr. Caroline M. Krauter has a strong background in computational chemistry. She obtained her PhD in 2014 from Heidelberg University in the field of theoretical chemistry under the supervision of PD Dr. Markus Pernpointner and Prof. Dr. Andreas Dreuw. Her thesis focused on the theoretical description of photochemical processes in organic materials. From 2014 to 2016she was a postdoctoral fellow in the group of Prof. Emily A. Carter at Princeton University whereshe was working on plasmon-induced heterogeneous catalysis on the surface of metal nanoparticles. In 2016 she joined Schrödinger as a senior applications scientist where she is working on applying atomic-scale chemical simulation techniques in the field of materials science.

Information Age and Connectivity Enabled by Advanced Electronic Materials

R. BeicaGlobal Director New Business DevelopmentThe Dow Chemical Company, Strategy Planning, Marketing and New Business Development, Dow Electronic Materials, Marlborough MA, United States

AbstractThe development of electronics and computing technologies have significantly evolved over the years; it has also driven the semiconductor industry to develop new technologies that can address a wide range of market needs and applications. If major technology advancements were driven by Moore’s Law and scaling the technology node, going forward, to address the market requirements for connectivity, cloud and ubiquitous computing, the focus of the industry will be shifting more towards heterogeneous and system integration. Electronic Materials plays a critical role across the entire process flow of electronics manufacturing from front-end to back-end: making the device, building the interconnects and substrates, packaging and assembling multiple components. Information Age products will further drive the need for more functionalities, higher performance while continuing to reduce cost and form factor. The world is becoming more and more dependent on data which will require the necessary hardware, increased speed and bandwidth technologies to support it. To address future smart device requirements, further innovation in materials, processes and integration technologies will be needed. The presentation will provide an overview and evolution of the advanced packaging market, highlighting the importance of heterogeneous integration and electronic materials to address the needs of future Information Age applications.

BiografieRozalia Beica, Global Director New Business Development, Dow Electronic Materials Rozalia focuses on strategic activities, identifying new technologies and markets for advanced packaging and interconnects. She has 25 years of international working experience across various industries, including industrial, electronics and semiconductors. For 18 years she was involved in the research, applications and strategic marketing of Advanced Packaging and 3D interconnect technologies, with global leading responsibilities at specialty chemicals (Rohm andHaas), equipment (Semitool, Applied Materials and Lam Research) and device manufacturing (Maxim IC). Prior to joining Dow, Rozalia was the CTO of Yole Développement where she led the market research, technology and strategy consulting activities for Advanced Packaging and Semiconductor Manufacturing. Throughout her career, Rozalia has been actively supporting industry activities worldwide: Program Director of EMC3D Consortia, General Chair of IMAPS Device Packaging and Global Semiconductor and Electronics Forums, Technical Advisory Board Member at SRC, chairing and participating in several committees (ITRS, ECTC, IMAPS, IWLPC, 3DIC, EPTC, ESTC, CPMT) and recently started chairing the WLP efforts within Heterogeneous Integration Roadmap activities. She has over 100 presentations and publications (including 3 book chapters on 3D IC technologies), several keynotes, invited presentations and panel participations. Rozalia earned a M.Sc in Chemical Engineering from Polytechnic University "Traian Vuia" (Romania), a M.Sc. In Management of Technology from KW University (US), and a Global Executive MBA from Instituto de Empresa Business School (Spain).