Emerging Materials for Front End IC Process Thirsk FEOL Opportunitie… · · 2010-12-18Emerging Materials for Front End IC Process Mark ... alternative to LOCOS / PECVD and is

Emerging Materials for Front End IC Process

Mark ThirskLinx Consulting

+1 617 273 [email protected]

Device Making Unit Operations - 2007

0

20

40

60

80

100%

Cleans

0.065

0.09

0.13

0.18

0.25

0.35

0.5

0.8

1>1

CMP i-line resist Implant

Total = 12,229,682

248nm resist193nm resist193i

ARCs SiCOHSTIECD CuALD

AluminumSeed

Barrier

Source: Linx ConsultingLINX CONSULTING

2SEE BEYOND THE HORIZON

Select Device Making Unit Operations - 2011

0

20

40

60

80

100%

Cleans

0.032

0.045

0.065

0.09

0.13

0.18

0.25

0.35

0.5

0.81

>1CMP i-line resist Implant

Total = 18,923,301

248nm resist193nm resist193i

ARCs

SiCOHSTIStrainECD CuALD

AluminumSeed

Barrier

Source: Linx Consulting

LINX CONSULTING3

SEE BEYOND THE HORIZON

Relative Unit Operations And Growth

Source: Linx Consulting

1

2

5

10

20

50

100

200

500

0.0001 0.0002 0.0005 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1

Unit OperationsCAGR 2006 to 2011

Aluminum

Implant

ALD

ECD Cu

Strain

STI

SiCOH

ARCs

193i

193nm resist

248nm resisti-line resist

CMPCleans

Proportion of Unit Operations

Average

LINX CONSULTING4


FEOL Processes Covered

STI and CMP

Gate Stack Engineering

Strain Engineering

Pre-Metal Dielectric

High k Capacitor Dielectrics

Patterning Technologies

Contacts/Plugs

Cleans

LINX CONSULTING5


Shallow Trench Isolation

• Shallow Trench isolation is an isolation technique implemented on sub-0.18-micron technologies as an alternative to LOCOS / PECVD and is carried out one time per device at sub-180 nm to isolate transistors

• The flatness of the resulting wafer enables more precise pattern definition for subsequent layers• With the use of SACVD for gap filling in STI, this can be extended to 32 nm and beyond• Higher aspect ratios are required for memory devices

LINX CONSULTING6


STI - Processes

PARAMETERS HDP CVD HARP SPIN ON

TOOL HDP CVD SA CVD (low temperature)

TRACK for SOG deposition; HDP CVD on top of SOG

FILM THICKNESS 3000 angstroms 3000 angstroms 3000 angstroms

PRECURSORS TEOS O3 AND TEOS POLYSILOZANE, cured in NH3

MATERIAL COST PER DEPOSITION

$0.06 $0.10 $1.5

LINX CONSULTING7


Direct STI CMP

0%

10%

20%

30%

40%

50%

60%

70%

80%

-

10,000

20,000

30,000

40,000

50,000

60,000

70,000

2002

2003

2004

2005

2006

2007

2008

2009

2010

2011

0.032

0.045

0.065

0.09

0.13

%≤65 nm

1000’s of operations

LINX CONSULTING8


Ceria based HSS Slurry is the primary option for STI down to 45nm

Below 65 nm Fixed Abrasive approaches with embedded Ceria are being adopted• Processes often use HSS and FA• Fixed Abrasive has very low

sensitivity to topography and excellent selectivity for 32nm

Ceria - One Slurry Fits All?

USE DILUTION PROCESS BENEFITS

STI 1:2:7 - Abrasive:Additives:DIW Dilute compared to colloidal/fumed silica slurry with stable removal rate and easy cleanability

PMD 1:2 - STI Slurry:DIW Higher rate in comparison to colloidal/fumed silica slurry. Stability of removal rate and easy cleanability

OXIDE 1:3 - STI Slurry:DIW Cost, high rate and easy cleanability

The concept of one slurry that can be tailored for several applications is being pursued

LINX CONSULTING9


High-κ Gate Integration

Conventional silicon dioxide gate dielectric structure compared to a proposed high-κ dielectric structures

Poly Gate

1.2 nm SiONStrained Si Substrate

Metal Gate

High k Dielectric

Strained Si Substrate

Metal Gate

High k DielectricStrained Si Substrate

Poly Gate

Cap Layer

Gate Last Approach

1 Critical Litho level1 Litho Level2 CMP steps

Gate First Approach

1 Critical Litho level1 Litho Level0 CMP steps

~1.6x Capacitance~0.01x Leakage

LINX CONSULTING10


Gate Integration Alternatives

High k Deposition

Poly Deposition

Gate Litho & Etch

Strain and PMD PMD CMP Poly Etch

High k Deposition

Cap Deposition Cap Litho

Metal Gate

Deposition

Poly Deposition Gate Litho

Gate First Process

Gate Last Process

P Metal Deposition

P Metal Litho & Etch

N Metal Deposition Metal Fill Metal CMP

Spacer, Strain

Deposition

PMD Deposition PMD CMP

Dielectric Cap Layer - Lanthanum, Dysprosium for NMOS, Aluminum for PMOS

LINX CONSULTING11


High-κ Gate Dielectric

PARAMETERS 45 nm 32 nm perspectives

FILM THICKNESS 25-30 A 15-20 A

DEPOSITION TIME 8-10 sec 7-8 sec

PRECURSORS TDMA Hf and TDEA Hf and HfCl4 are the main precursors used in ALD of HfO2

TEMA Hf and Hf TDMAT -Hafnium dimethylamide Hf(N(CH3)2)4 and Hafnium alkoxides are also used


$11.25 to $30

POST DEPOSITION TREATMENTS Thermal Thermal

LINX CONSULTING12


Metal Gate

• Intel announced that they have achieved 1-nm electrically-thick high-k dielectrics, dual-band-edge work function metal gates, third-generation strained silicon, using low-cost 193-nm dry patterning for critical layers

• FUSi approaches with Ni and Ytterbium implants is not broadly used

• Linx patent review on metal gates show likely materials needs are:– High-κ dielectric - HfO2, HfSiO, HfSiON– NMOS - Zr, W, Ta, Hf, Ti, Al, Metal carbide, transition metal aluminides (e.g. Ti3Al, ZrAl) – PMOS - Ru, Pa , Pt, Co, Ni, TiAlN, WCN, Metal oxide – Low resistance layers - TiN, W, Ti, Al, Ta, TaN, Co, polysilicon

• Judging by the literature, HfSiON seems to be the consensus dielectric material, with a nominal κ of ~12, which can be also tuned by ozonization or nitridation. This is likely a single node solution.

• Possible low-resistance filler metals, W, Ta, TiN and TaN, and polysilicon because the CMP is already well established in HVM

LINX CONSULTING13


Metal Gate Deposition

PARAMETERS 45 nm 32 nm perspectives

TOOL Process will be a hybrid PVD and ALD. PVD will be Ni-Si (FUSI) and a HfSiO. There is also a spike anneal treatment and possibly UV cure as well.

FILM THICKNESS 40-50A 35-40A

DEPOSITION TIME 50 sec 40 sec

PRECURSORS TaN films were deposited by ALD from commercial Tert-Butylimido-Tris(Diethylamido)Tantalum (TBTDET) and two novel mixed amido/imido/guanidinato and mixed amido/imido/hydrazidoprecursors

TaN films were deposited by ALD from commercial (Tert-Butylimido-Tris(Diethylamido)Tantalum) TBTDET and two novel mixed amido/imido/guanidinato and mixed amido/imido/hydrazidoprecursors


$10 $8-10

POST DEPOSITION TREATMENTS Cooling Cooling

LINX CONSULTING14


Strain Engineering

PMD dielectric layers, shallow trench isolation, and SiGesource/drain replacement can all induce useful strain on the channels of MOSFETs . these techniques can give a better trade-off of ION for IOFF in planar designs

Tensile SiNCompressive SiN

Tensile PMD

Tensile STISelective Epi SiGe

Strained Si / SiGe

LINX CONSULTING15


Strain Engineering

• Approximately 1% induced strain results in a 10 to 20% improvement in Ion

Epi SiGe at S/D

Strained Layers

Global BiAxialStrain

Buried SiGeInducing UniaxialStrain

LINX CONSULTING16


Strain Engineering - Processing

COMPRESSIVE TENSILE

FILMS Si3N4 SiGe

PRECUROSRS First generation reportedly use silaneand ammonia. Common precursors also include dichlorosilane and ammonia, processed at about 700° to 800°C. The first generation of low temperature nitrides include BTBAS and HCDS, which are processed at 600° to 700°C

GeH4 and silane are mostly used. SiGe needs to be deposited in pads. This means that there is an oxide or nitride mask step. HCl is used as an etchant.

NEXT GENERATION

Future products may include TSA and SAM 24 from Air Liquide and TBOS, both for ALD and CVD processes

Precursors with Ge and Cl are being investigated

LINX CONSULTING17


PMD Films – Processes

PARAMETERS HDP CVD SA CVD and PE CVD SPIN ON

FILM THICKNESS – 65 nm

4000-4500A 4000-4500A ~4000-4500A

PRECURSORS TEOS OMCATS3MS

HSQ


$0.1 $0.5 to $1.0 $0.8 to $1.5

45 nm NODE – FILM & PRECURSORS

Continuation of same films materials and processes

32 nm NODE – FILM & PRECURSORS

Continuation of same films materials and processes

LINX CONSULTING18


• SACVD BPSG systems can extend CVD technology with a new ozonated BPSG process offering technical and operating benefits over existing systems in the pre-metal dielectric

• Spin-on PMDs are used to meet the requirements as current PMD technologies of HDP CVD and BPSG reflow are constrained by void formation or high thermal budget requirement

DRAM Capacitor Dielectrics

Stacked capacitor-over-bit line (COB) architecture for the memory arrays

Cross section taken in the plane of the bit line showing recessed channel array transistors (RCATs) used for the word-line transistors

LINX CONSULTING19



1. For ALD of hafnium oxide and hafnium oxynitride, hafnium ethylmethylamide (TEMA Hf) Hf(N(CH3)(C2H5))4, is a good liquid precursor

2. M(OR)y in which M is a metal such as hafnium, lanthanum, zirconium, titanium, tantalum, yttrium oraluminum, R is an alkyl group (e.g., an ethyl, propyl, isopropyl, t-butyl, or neopentyl group), and y isbetween 3 and 5

3. Metal - cyclopentadienyls (M(C5H5)n or M(Cp)n) are being explored for metal ALD, but not extensivelyfor high-k ALD

MATERIALS PRICE ($/g) GENERATION

TMA & HFSiON/TMA 6 to 8 90

TEMAHf, TEMAZrHF/TMA & ZrSiO

12 to 16 65

TEMAHf, TEMAZr, BST, GST, Ta-based 12 to 18 45

Zr/RARE EARTHSRu/TaTaSiNHfSixOy

12+ 32323232

LINX CONSULTING20



PARAMETERS TMA HF & laminates ZrSiO/rare earths

TOOLS Jusung, Kokusai, TEL, Aixtron, Aviza, AMAT, IPS

FILM THICKNESS 300-500A 200-300A 200-300AAnneal required

PRECURSORS TMA - Trimethyl aluminumAl (CH3)3 for Al2O3

TDMAHF; Dicyclopentadienyldimethyl hafnium, Hf(C5H5)2(CH3)2; Because of its low residual carbon content and high deposition rate, TEMA Hf is currently the preferred hafnium precursor for ALD hafnium silicate films

TEMA Zr tetrakis(dimethylamido)zirconium (Zr(NMe2)4)


$6 to $8 $15 to $30 $18 to $32

POST DEPOSITION TREATMENTS

Slow cooling Slow cooling Slow cooling

LINX CONSULTING21


Novel Precursor Markets

$0

$50

$100

$150

$200

$250

2007 2008 2009 2010 2011

mil

lio

ns

HK Capacitor Dielectric Strain HKGD Metal Gate

LINX CONSULTING22


Patterning Trends

• Lithography alone may not be enough to meet the need for shrinking device features– Patterning processes will become significantly more complex

• We have not yet met the requirement to change λ again– EUV showing good progress, but some way to go yet

• No show-stoppers in sight, but the road is not as smooth as it has been– Implementation of Double Patterning– Implementation of Ultra High NA Immersion

LINX CONSULTING23


IC Lithography Roadmap

ITRS 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014

ITRS 2005 / 6Half Pitch / nm

90 80 70 65 57 50 45 40 35 32 28

2 year cycle 90 65 45 32 22

Dry Optical Lithography

Immersion Lithography

EUV

Imprint

Direct Write E-beam *** *** *** *** *** *** *** ***

*** for development and prototyping applications only

Expected Solution Potential Solution Unlikely Solution

Double PatterningDouble Exposure

LINX CONSULTING 5-24SEE BEYOND THE HORIZON

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80

90

100

0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65 1.75 1.85 1.95

1/2

Pitc

h

NA

k1 = 0.35k1 = 0.30k1 = 0.25k1 = 0.20k1 = 0.175k1 = 0.15

Double Patterning Benefits

193nm

H20 immersion solution

Gen2 Fluid solution

Gen3 Fluid & Material solution

Best Case Resolution Benefits for Double Patterning Immersion solutions

LINX CONSULTING25


Complexity of the Layer Stack

• Increasing number of layers required for Patterning Functionality

Reflection control

Image Capture

Pattern Transfer

BARC

Hardmask

TARC

Silicon cont. BARC

Spin on Hardmask

Under Layer

Amorphous Carbon

Top Coat

Photoresist

DE Materials

Immersion Fluid

Conditioning Filter

Multiple use for Double Patterning

Photoresist

Ca. 1990

LINX CONSULTING26


Total Patterning Market Growth

$0

$500

$1,000

$1,500

$2,000

$2,500

2006 2007 2008 2009 2010 2011

$ 00

0s

SiBARCSOHMUL193 TARC284 TARCi-line TARC193 BARC248 BARCi-line BARC193i Resist193 Resist248 Resisti-line Resist

LINX CONSULTING27


Relative Patterning Cost

CVD PrecursorSpin On MaterialEtchant

LINX CONSULTING28


$0

$10

$20

$30

$40

$50

$60

$70

$80

$90

2006 2007 2008 2009 2010 2011

$ 0

00

s

SiBARCSOHMUL

Multilayer Material Market Size Multilayer Patterning CoO

DeviceLogicMemory

Node90 65 45 32

70 50 40

DRAM Contacts

NAND

Contacts

Gate

Logic

FEOLGate

Contacts

Via 1

Pattern ModificationDouble Patterning

CH Shrink

CD Modification Roadmap

Flow

Chemical

Chemical

CVD / Plasma Spacer

Etch Trim

Plasma

Plasma

Chemical

Chemical Freezing

Plasma

Plasma

Plasma

Chemical

LINX CONSULTING29


Tungsten CMP Operations

0%

20%

40%

60%

80%

100%

120%

-

50,000

100,000

150,000

200,000

250,000

2002 2003 2004 2005 2006 2007 2008 2009 2010 2011

0.032

0.045

0.065

0.09

0.13

0.18

0.25

% ≥ 65 nm

1000’s of operations

LINX CONSULTING30


W ALD nucleation ensures contact reliability for high AR with highly controllable and uniformly deposits. ALD nucleation ensures a wide process window for the subsequent via fill of the tungsten plug using conventional CVD

Cleaning Technology Opportunities

FEOL

Critical Cleans

Acid Mixtures

Post Implant Strip

Plasma Wet

BEOL

Post Etch Residue

Formulated Cleans Dilute HF

Pre-Deposition

Formulated Cleans

Improved BEOL Cleans compatible

with advanced layer stacks

Formulated Cleans with high selectivity of

metal oxides

Advanced cleans to minimize etch and physical damage

Formulated Cleans or Additives to replace

SPM and SC1

LINX CONSULTING31


Improved FEOL Cleans

• Currently the overwhelming number of FEOL cleaning operations are inorganic based aqueous cleans in batch immersion systems. Although single wafer processes are emerging, and dilute chemistries are being employed to reduce waste, cost and improve safety, the possibility of simplified, effective processes that solve the trade-offs of aggressive chemistry and megasonic damage can succeed

• Damage-free cleaning that avoids Silicon loss, while minimizing the requirement for high physical energy such as megasonics

• Ability to measure smaller particles. Control improvements are impossible contamination cannot be measured

- Smaller particles on surfaces - especially in trench structures- Smaller particles in chemicals

• Applied Materials AM1, distributed by Mitsubishi, combines a chelating agent in a SPM formulation reducing the requirement for an SC2 step

LINX CONSULTING32


Relative Markets Opportunities

1

2

5

10

20

50

100

200

500%

0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100.00%

$500 Mio.Market

Size 2011

CMP

Cleans

193nmresist

ARCs

i-lineresist

248nm resist

Implant

Aluminum

ALD

Seed

193i

SiCOHMultiLayer Mats

ECD Cu

STI

Strain

$500 Mio.Market

Size 2011

Proportion of Unit Operations

CAGR Unit Operations - 07 to 11

Front End processes generally growing more rapidly than other segments, although current market sizes are smaller

LINX CONSULTING33


BEOLFEOL & BEOL

FEOL

Conclusions

• Memory device volume and architecture will be a key factor in the future materials demand landscape

• A multitude of new materials and performance requirements will emerge in the next 5 years– New materials, ancillaries and processes will proliferate– FEOL process will grow faster and while being concentrated in advanced

manufacturers

• The competitive landscape throughout the value chain is changing, and may struggle to support new requirements

LINX CONSULTING SEE BEYOND THE HORIZON34

Supplemental Slides

Double Patterning Examples

LINX CONSULTING35


Spacer Double Patterning

Sacrificial planarizing material (i.e. PETEOS)

CVD Spacer (i.e. Nitride, SiON etc.)

2nd Sacrificial material

High resolution, low OLE pattern achieved with last generation lithography

LINX CONSULTING36


Resist Freeze Double Patterning - Lines

High resolutionPotential poor OLE Need to bias first resist patternPotential line width differences

Pattern Resist Structures

Coat with Freeze material

Repeat resist pattern

Etch Transfer

LINX CONSULTING37


Resist Freeze Double Patterning - Trenches

High resolutionPotential poor OLE Trench patterns intrinsically more difficultSingle hard mask requirement

Pattern Resist Structures

Coat with Shrink material and etch

Repeat resist & shrink

Etch transfer to hardmaskStripEtch with hard mask

LINX CONSULTING38


Competition Status - AMAT

• AMAT press release on Improved APF film:• APF-e film is also highly selective to polysilicon (6:1) and oxide etching (15:1) and aims to eliminate

the line edge roughness associated with photoresist-only schemes to allow tighter critical dimensional control for improved device performance and yield. APF-e technology also eliminates the expensive wet cleaning steps needed by multi-layer resist processes, the company said

• The APF optically engineered patterning film stack combines the CVD-based amorphous carbon APF or APF-e hardmask films with Applied’s dielectric anti-reflective coating (DARC) films to enable advanced lithography and etching using standard lithography tools. Applied’s APF films are already being used in up to seven layers in 70nm flash memory chips, including shallow trench isolation and sub-40nm gate definition, plus other key applications. Even more layers are expected to be implemented in next-generation devices

LINX CONSULTING39


Documents

Emerging Materials for Front End IC Process Thirsk FEOL Opportunitie… · · 2010-12-18Emerging Materials for Front End IC Process Mark ... alternative to LOCOS / PECVD and is