Mat Lab and VLSI

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MAT LAB & VLSI Project List

SIMULATION PROJECTS

DIGITAL SIGNAL PROCESSING (ADSP & TEXAS)

IMAGE PROCESSING

SBIMP04 Phase adaptive super resolution of mamographic images using complex waveletsSBIMP07 Image quality assessment based on multi scale geometric analysisSBIMP10 Image segmentation via spline regressionSBIMP17 Low bit rate image compressionSBIMP18 Morphological Background detectionSBIMP23 Digital image steganographySCIMP01 An Affine Symmetric Image Model and Its ApplicationsSCIMP02 Constrained and Dimensionality-Independent Path OpeningsSCIMP03 High Resolution Cerebral Blood Flow Imaging by Registered Laser Speckle Contrast AnalysisSCIMP04 Multivariate Image Segmentation Using Semantic Region Growing with Adaptive Edge PenaltySCIMP05 Scanned Compound Document Encoding Using Multiscale Recurrent PatternsSCIMP06 Green Noise Digital Halftoning With Multiscale Error DiffusionSCIMP07 Tracking and Activity Recognition Through Consensus in Distributed Camera NetworksSCIMP08 TurboPixel Segmentation Using Eigen-ImageSCIMP09 Fast cartoon + texture image filtersSCIMP10 Automatic Parameter Selection for Denoising Algorithms Using a No-Reference Measure of

Image ContentSCIMP11 Generalized Probabilistic Scale Space for Image RestorationSCIMP12 Image Segmentation by MAP-ML EstimationsSCIMP13 A Statistical Pixel Intensity Model for Segmentation of Confocal Laser Scanning Microscopy

ImagesSCIMP14 Fast Query for Exemplar-Based Image CompletionSCIMP15 Multiscale AM-FM Demodulation and Image Reconstruction Methods With Improved AccuracySCIMP16 Sparse Image Reconstruction For Molecular ImagingSCIMP17 Phase Adaptive Super Resolution Of Mammography Images Using Complex WaveletsSCIMP18 A hybrid geometric–statistical deformable model for automated 3-d segmentation in brain MRISCIMP19 Cost-Effective Hidden Markov Model-Based Image SegmentationSCIMP20 A Fast Multilevel Algorithm For Wavelet-Regularized Image RestorationSCIMP21 Morphological Background Detection And Enhancement Of Images With Poor LightingSCIMP22 High-Fidelity Data Embedding For Image AnnotationSCIMP23 Fingerprint enhancement and recognition using Back Propagation AlgorithmSCIMP24 Digital Image Steganography in Spatial & Frequency DomainSCIMP25 Upper surface of the diaphragm estimate using 3D CT ImagesSCIMP26 Digital Image Watermarking and recovery of the secret imageSCIMP27 Automatic Exudates Detection from the eyes of Diabetic Patients



SIMULATION PROJECTS


IMAGE PROCESSING






SIMULATION PROJECTS


IMAGE PROCESSING





SCIMP28 Image retrieval using Color, Texture and ShapeSCIMP29 Face Detection Using Adaboost algorithmSCIMP30 Color Image SegmentationSDIMP01 On the Selection of Optimal Feature Region Set for Robust Digital Image WatermarkingSDIMP02 Blind Deconvolution Using Generalized Cross-Validation Approach to Regularization

Parameter EstimationSDIMP03 An Optimal Data Hiding Scheme With Tree-Based Parity CheckSDIMP04 IMAGE Resolution Enhancement by Using Discrete and Stationary Wavelet DecompositionSDIMP05 HAIRIS: A Method for Automatic Image Registration Through Histogram-Based Image

SegmentationSDIMP06 Fine-Granularity and Spatially-Adaptive Regularization for Projection-Based Image DeblurringSDIMP07 A Generalized Unsharp Masking AlgorithmSDIMP08 Real time artifact-free image up scalingSDIMP09 Boundary Detection in Medical Images Using Edge Following Algorithm Based on Intensity

Gradient and Texture Gradient FeaturesSDIMP10 MRF-Based Intensity Invariant Elastic Registration of Cardiac Perfusion Images Using

Saliency InformationSDIMP11 Multichannel Image Registration by Feature-Based Information FusionSDIMP12 Optimal Threshold Selection for Segmentation of Dense Homogeneous Objects in

Tomographic Reconstructions

DIGITAL SIGNAL PROCESSING

SCDSP01 Energy Efficient Multi-Object Tracking in Sensor NetworksSCDSP02 Cooperative Diversity of Spectrum Sensing for Cognitive Radio SystemsSCDSP03 Differential Modulation for Bidirectional Relaying With Analog Network CodingSCDSP04 Greedy Gossip with EavesdroppingSCDSP05 Two-channel Linear Phase FIR QMF Bank Minimax Design via Global Nonconvex Optimization

ProgrammingSCDSP06 Bounds on the Number of Identifiable Outliers in Source Localization by Linear ProgrammingSCDSP07 Phased-MIMO Radar: A Tradeoff Between Phased-Array and MIMO RadarsSCDSP08 Localization in underwater dispersive channels using the time-frequency-phase continuity of

signalsSCDSP10 Allpass VFD Filter DesignSCDSP11 Beam forming With a Maximum Negentropy CriterionSCDSP12 An ensemble speaker and speaking environment modeling approach to robust speech

recognitionSCDSP13 Observer-controller based digital PLLSCDSP14 Illumination sensing in led lighting systems based on frequency division multiplexingSCDSP15 Reversible Re-sampling of integer signalsSDDSP01 QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO ReceiversSDDSP02 Subspace SNR Maximization: The Constrained Stochastic Matched FilterSDDSP03 Optimal Wideband Spectrum Sensing Framework for Cognitive Radio SystemsSDDSP04 Algorithms and Bounds for Distributed TDOA-Based Positioning Using OFDM SignalsSDDSP05 Diversity Gain for MIMO Neyman–Pearson Signal Detection


COMMUNICATION

SBCM01 Communication coverage for wireless passive networksSBCM03 Channel coding for high speed linksSBCM06 Training design for repititve slot based cfo estimation in ofdmSCCM01 Novel Overlay/Underlay Cognitive Radio Waveforms Using SD-SMSE Framework to Enhance

Spectrum Efficiency–Part II: Analysis in Fading ChannelsSCCM02 On the Relationship Between the Multi-Antenna Secrecy Communications and Cognitive Radio

CommunicationsSCCM03 Analysis and Compensation for Nonlinear Interference of Two High-Order Modulation Carriers

over Satellite LinkSCCM04 Variable-Rate M-PSK Communications without Channel Amplitude EstimationSCCM05 Information Theoretic Capacity of Cellular Multiple Access Channel with Shadow FadingSCCM06 Joint Estimation of I/Q Imbalance, CFO and Channel Response for MIMO OFDM SystemsSCCM07 Asymptotic Error Analysis of Diversity Schemes on Arbitrarily Correlated Rayleigh ChannelsSCCM08 Bandwidth Allocation for Fluid Input Generalized Processor Sharing ServersSCCM09 Noncoherent Frame SynchronizationSCCM10 A Dynamic System Approach for Radio Location Fingerprinting in Wireless Local Area

NetworksSCCM11 Communication Coverage In Wireless Passive Sensor NetworksSCCM12 Rayleigh Fading Networks: A Cross-Layer WaySCCM13 Channel coding for high-speed links: a systematic Look at code performance and system

simulationSCCM14 Training design for repetitive-slot-based CFO estimation in OFDMSCCM15 Efficient detection ordering scheme for MIMO Transmission using power controlSDCM01 On Adaptive Lattice Reduction over Correlated Fading ChannelsSDCM02 Relay Selection from a Battery Energy Efficiency PerspectiveSDCM03 Symbol-Level Synchronization and LDPC Code Design for Insertion/Deletion ChannelsSDCM04 Optimized Differential GFSK DemodulatorSDCM05 Interference Cancellation and Detection for More than Two UsersSDCM06 Coded Free-Space Optical Links over Strong Turbulence and Misalignment Fading ChannelsSDCM07 Maximum-Likelihood FFH/MFSK Receiver over Rayleigh-Fading Channels with Composite

Effects of MTJ and PBNJSDCM08 Space-Time Block Coded Spatial ModulationSDCM09 Cooperative Diversity for Free-Space Optical Communications: Transceiver Design and

Performance AnalysisSDCM10 Single-Relay Cooperative Diversity with Scaled Selection Combining

POWER ELECTRONICS

SCPW01 Linear Stabilization of a DC Bus Supplying a Constant Power Load: A General DesignApproach

SCPW02 Efficiency Oriented Design of ZVS Half Bridge Series Resonant Inverter With VariableFrequency Duty Cycle Control

SCPW03 Space Vector Modulation for Two-Level Unidirectional PWM RectifiersSCPW04 An Efficient AC-DC Step-up Converter for Low Voltage Energy HarvestingSCPW05 A Bridgeless PFC Boost Rectifier With Optimized Magnetic UtilizationSCPW06 Analysis and Implementation of a Hybrid High Power Factor Three-Phase Unidirectional


RectifierSCPW07 Generalized Topologies of Multiple Single-Phase Motor DrivesSCPW08 Design and Analysis of a Grid-Connected Photovoltaic Power SystemSCPW09 A Modified SEPIC Converter for High Power Factor Rectifier and Universal Input Voltage

ApplicationsSCPW10 Soft Switched CCM Boost Converters With High Voltage Gain for High Power ApplicationsSCPW11 Design Oriented Analysis and Performance Evaluation of Buck PFC Front EndSCPW12 Digital Combination of Buck and Boost Converters to Control a Positive Buck–Boost Converter

and Improve the Output TransientsSCPW13 EMI Noise Prediction for Electronic BallastsSCPW14 High-Density EMI Filter Design for DC-Fed motor drivesSDPW01 Modelling and Control of a Three-Phase Four-Switch PWM Voltage-Source Rectifier in d-q

Synchronous FrameSDPW02 Improved Asymmetric Space Vector Modulation for Voltage Source Converters with Low Carrier

RatioSDPW03 A Single-Phase High Power Factor Rectifier, Based on a Two-Quadrant Shunt Active FilterSDPW05 Single-Phase Z-Source InverterSDPW08 Diode-Clamped Three Level Inverter Based Battery/ Super capacitor Direct Integration Scheme

for Renewable Energy SystemsSDPW09 Efficient Sequential Switching Hybrid Modulation Techniques for Cascaded Multilevel InvertersSDPW10 High-Efficiency Regulation Method for a Zero-Current and Zero-Voltage Current-Fed Push–Pull

ConverterSDPW11 Performance of a High-Efficiency Switched- Capacitor-Based Resonant Converter With Phase-

Shift ControlSDPW14 A Modified Single-Phase Quasi-Z-Source AC-AC ConverterSDPW15 UPQC-S: A Novel Concept of Simultaneous Voltage Sag/Swell and Load Reactive Power

Compensations Utilizing Series Inverter of UPQC

. VLSICORE VLSI

SBVL01 A Fast Hardware Approach for Approximate,Efficient Logarithm and AntilogarithmComputations

SBVL04 A Low-Power Low-Area Multiplier Based on Shift-and-Add ArchitectureSCVL01 On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan CircuitsSCVL02 Asynchronous Data-Driven Circuit SynthesisSCVL03 A Multibank Memory-Based VLSI Architecture of DVB Symbol DeinterleaverSCVL05 A Galois field-based logic synthesis with testabilitySCVL07 BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add ArchitectureSCVL08 A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S-Box ArchitectureSCVL10 A Low-Power Delay Buffer Using Gated Driver TreeSCVL11 A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number

SystemSDVL01 Accumulator Based 3-Weight Pattern Generation(Testing)SDVL02 A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT ApplicationsSDVL03 High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications


SDVL04 High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder TreeSDVL08 Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip

CommunicationsSDVL09 Low-Power and Area-Efficient Carry Select AdderSDVL10 A Low-Power Single-Phase Clock Multiband Flexible DividerSDVL11 Fixed-State Tests for Delay Faults in Scan DesignsSDVL13 Mapping Multi-Domain Applications onto Coarse-Grained Reconfigurable Architectures.SDVL14 An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect

Detection.SDVL15 Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing

PRNG.SDVL16 Single Cycle Access Structure for Logic Test \

IMAGE PROCESSING

SBVL09 Spread Spectrum Image Watermarking with Digital DesigneSBVL13 A Compact AES Encryption Core on Xilinx FPGASCVL22 On Reducing Scan Shift Activity at RTLSCVL23 Spread Spectrum Image Watermarking With Digital DesignSCVL24 An improved RC6 algorithm with the same structure of encryption and decryption

COMMUNICATION

SBVL17 A New Low Power Test Pattern Generator Using a Variable-Length Ring CounterSBVL20 Fault Secure Encoder and Decoder for Nano Memory ApplicationsSCVL26 New Architectural Design of CA-Based CodecSCVL27 An Efficient 4-D 8PSK TCM Decoder ArchitectureSCVL28 Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI

ImplementationSDVL20 Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing

ApplicationsSDVL21 A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit DesignSDVL22 High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS CodesSDVL23 A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption

Standard Using Composite FieldsSDVL29 An Efficient Architecture Design for VGA Monitor ControllerSDVL30 The Communication Interface Design of AT89C51 Preparation Robot Based on Serial

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Mat Lab and VLSI