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Technical Report TR-157 June 1971 NGL-21-002-008

An Overview of Associative or Content-Addressable Memory Systems

and a KWIC Index to the Literature

by

Jack Minker

An Overview of Associative or Content-Addressable

Memory Systems and a KWIC Index to the Literature

1956-1970

by

Jack Minker*

University of Maryland

Keywords: Content-addressable, associative, parallel-processors, supercon

ductive, cryogenics, multi-aperture.

CR Categories: 6.2, 4.1, 3.9.

Abstract

This bibliography of associative or content-addressable memory systems

covers the literature from approximately 1956 through 1970. A brief overview

of the literature referencing pertinent articles is provided. The overview

is current to approximately 1969 when itwas written. In addition, the biblio

graphy is presented as a Key Word In Context Index (KWIC).** Areas discussed

in the overview are applications, hardware implementation, computer organiza

tions with associative memories, and software aspects.

*The author would like to express his appreciation to Miss Hiroko Kobayaski, 'Mrs. Barbara H. Zimmerman and Mrs. Shelly Heller of the University of Maryland for their assistance in obtaining some of the bibliographic material, for standardizing citations, and for developing the KWIC index: He would also like to express his appreciation to Mrs. June Stagg of AUERBACH Corporation

who, over several years, helped to compile the bibliography. Finally, he would like to express appreciation to his colleague Mr. Warren E.Shindle at the AUERBACH Corporation for his assistance with the bibliography and for numerous discussions and joint work in associative memory technology.

**The computer time used to develop the KWIC index was supported by the National Aeronautics and Space Administration under Grant NGL-21-002-008 to the Computer Science Center of the University of Maryland.

1. Introduction

Content-addressable-and associative memory systems have been-under active

investigation since 1956. Work in'this field received its impetus from.the

efforts of Slade and McMahon [SMTC57] who described cryogenic catalog memory

cell designs. Such memories have been referred to variously as catalog

memories [SMTC57],,associative memories [KPAM61], parallel-search memories

[FAAF62], content-addressable memories EFRCA63], and-data-addressed memories

[NFAC62].

The International Federation of Information Processing Society Glossary

defines an associative store as, "astore whose registers are not identified

by their name or position but-by their content."* Inexplaining the defini

tion by an example, the glossary further notes that the retrieval of any one,

item in such a store would be accomplished by searching all registers in paral

lel to retrieve the relevant data by a-content search with but a single opera

tion. An excellent survey of associative memory technology has been provided

by Hanlon,[HACA66]. This overview emphasizes work accomplished subsequent to

Hanlon's article.

An associative processor consists of an associative memory and additional

hardware to permit manipulation of the data in the memory store.

Typical elements of an associative processor are:

1. The memory array which provides the data storage itself.

2' The comparand register which contains the data to be compared against

the contents of the memory array for searches; may provide a shifting

register for some input/output operations; and can play an intermediate

role in the transfer of data between the memory array and a general

*Joint Technical Committee on Terminology. IFIP-ICC Vocabulary of Information

Processing. Amsterdam: North Holland Publishing Company, 1966.

purpose computer depending upon the configuration inwhich the

processor is employed.

3. The mask register which is used tocontain data specifying portions

of words for operations involving only word portions.

4. The resolver which is used to determine the'location of response bits

in the response store.

-5. The search logic which causes the search commands received by the

memory to be executed properly. Search operations are generally

accomplished in a bit serial, word parallel fashion starting at the

most significant bit'

6. The response store which receives vectors indicating which data,satisfy

a given search criterion and which can execute logical operations,

such as shifting and Boolean operations on these vectors. -

For example, an associative processor, developed by the Goodyear Aerospace

Corporation, The Goodyear Associative Processor [BDPP66], has the elements

described above. Fuller and his associates [BCS066] propose that in addition

to a parallel read operation, associative memories have a multi-write capability

to enter words inparallel into the associative processor's memory array.

2. Applications of Associative Memoties

The importance of a content-addressable memory lies not only in the ability

to search the memory by content, but to do so in parallel within approximately

the same amount of time that would be required to access a single memory ele

ment in today's .digital computers. Because of this capability, numerous

speculative articles have been written specifying the various fields of appli

cation inwhich such memories could be applied. Some of the application

areas proposed have been for sorting [SLAM62]; pattern recognition [USPD59,

MDTL61, YYPR66]; solution of partial differential equations EBBP062J; radar

track correlation [JKTT62, KAA068]; path finding in graphs [CBPF68]; document

retrieval' [CBDA62, YYAC66]; machine translation [BTAC66, HJAC67]; relational

data searches [SLAS66, SLAS67, LSAP65]; question-answering systems [ASTA67];

data storage and retrieval systems [GMA066, FBS065, DGAS66]; chemical sub

structure searching [ACAM68] and numerous other applications (see [EFSA63]

and [GJTF62] for several applications of:associative processings).

With the exception of a very limited number of areas, as noted by Hanlon

[HACA66], "...the superiority of the content-addressable memory or associative

processor is only implied, not proved." For a number of applications de

veloped since Hanlon completed his survey, small associative memories do not

appear particularly advantageous. Applications of this type include: (1)

formatted file problems [GMA066, FBS065]; (2) dictionar look-up for trans

lation efforts [BTAC66]; (3) automatic abstracting problems [GRHA66]; and

(4) for use with compilers [PCAM67]. In both [DGAS66] and EFBS065J, a

specific associative processor integrated with a second generation computer

environment was postulated. Machine coding was generated in each instance.

Although some advantage could be shown for an associative memory configuration,

the cost differential and actual time saved would not make the approach worth

the effort. The compiler study [PCAM67], concluded that the input/output for

memory loads was excessive in the use of a small' associative memory for com,

pilation.

Whenoriginally conceived, associative-memories were thought of as devices

to permit the easy manipulation of large masses of data. More recently they

have been thought of as-devices to aid in the~control functions associated

with a data processor. Chu [CYA065] proposed an associative memory to assist

in dynamic storage allocation problems.. A small associative-memory can be

used to keep a map of memory and of program locations to assist in dynamic~q'

storage allocation. The IBM 360 series [BGM064] contains a small associative

memory used in this way. Green et al. [GMA066] note that a small associative

memory might be used'to store queued requests for input/output devices such

as discs and drums so that the requests could be retrieved in a'sequence that

would minimize access time or latency time. Prywess has made a similar

observation. Gundersbn et al. [GFAT66] have been studying the"useof

associative memories for other control functions within a multi-processor

computer organization. Bird, et al. FBCS066] have used an associative memory

to scan the output of drum tracks in parallel for a fixed-field formatted file

application. That is,the associative memory was used as a filter between

the drum and the central processor.

3. Associative Memory Implementations and ComputerOrganizations

Although several individuals speculated as early as 1961 that large

associative memories would be available [MTSC61, RJCM61], no such memories

appear to be imminent. To implement an associative or content-addressable

memory, a considerable amount of logic at each cell is required. To achieve

complicated cell circuit designs at a reasonable cost, researchers believed

that cryogenic or superconductive technology developments were required.

There have been several different approaches towards hardware elements

for associative memories. These fall in the areas of cryoelectrics, magnetics,

and tunnel diodes.

3.1 Cryoelectrics

Work in cryoelectrics was perhaps the first area investigated. Such in

vestigators as Slade [SATW59, SMTC57]; Seeber [SLAM62, SLAL63, SRAS60, SRCA60,

SRSM61]; Newhouse and Fruin [NFAC62]; Davies [DPAP64, DPDF63]; Mann and Rogers

[MRAC62], discuss various implementations of cryoelectric memories. The

latter report upon experimental work in which small arrays of cells were

utilized, and have also described a bit logic for "between limits" retrieval.

As more complicated operations are specified, the number of cryotrons per cell

becomes large. Newhouse and Fruin [NFAC62] claimed the feasibility of a

300,000 bit (approximately 8,000 word) memory in 162 although their experiment

was conducted on a three-word module consisting of 81 crossed-fil croyotons.

Although technological developments in evaporation and insulation of films

promised the realization of larger arrays than those envisioned by Newhouse

and Fruin, no such developments have taken place. Indeed, interest in cryo

genic devices for associative memories appears to be waning, while interest in

other areas appears to be developing. Abrons and Burns [ABSM64] consider the

development stages in applying superconductive devices and review superconductive

memories. Burns [BLCR65] is developing a large superconductive random access

memory using batch fabrication techniques based on the RCA superconductive

continuous sheet memory. The approach shows promise for random-access mem

ories in the range of lO7 bits and potentially for a.1O9 bit size.

3.2 Magnetics

Because magnetic devices appeared to promise earlier realization of an

associative memory than did a cryoelectric memory, many such devices have been

developed. Consideration has been given to magnetic cores [HSS064, KPAM61

MPAM61]; transfluxors [LSAM63]; biax cores ECMAM64]}; and Multi-aperture logic

elements [RCAP64J among several magnetic techniques. Due to the high power

dissipation and high cost associated with the magnetic approach, the memories

are necessarily small and have limited extendability in that they.cannot store

large data files. A magnetic film approach, which permits an associative

memory using non-destructive readout, has been reported by Joseph and Kaplan

[JKTT62]. Kaplan has estimated [KAAS63, JKTT62] that with bi-core thin-film

elements, a 10,000 word associative memory is feasible. The Goodyear Aero

space Corporation [GRAH64, BDPP66] was funded by Rome Air Development Center

[AF 30 [602-3549] to construct a 2048 word associative processor, The Goodyear

Association Processor (GAP). GAP is constructed using the BILOC elements to

hold each bit. The memory consists of two 1024 word memories of 48 bits per

word that share common logic. Green, et al [GMA066] analyze the cost of

magnetic memory elements and alternative logic for associative processors such

as GAP. These estimates include the relative costs for the basic associative

memory array, the logic required to drive the memory, and the response stores

required to manipulate the output of a series of search requests submitted to

the processor.

Other devices have been used for associative memories. A memory organization

using tunnel diodes is described by Fuller [FRCA63]. These memories seem to

hold some promise. Some other devices used for memory arrays are laminated

ferrites [WMWN63], magnetic films [RCAP64], and solenoid arrays [PGAS64].

3.3 Associative Memory Organizations in computer Systems

In considering associative memories, it is important to view them in the

context in which they are to be employed, rather than as abstract entities.

Thus, one must investigate such memories within the context of a general pur

pose computing system. Fuller [FRCA63] performed one such investigation in

which the content-addressable memory was used as a special purpose device with

little logic. Dugan, et al [DGAS66] consider several possible ways inwhich

an associative memory may be connected and configured with a general purpose

computer. These are:

(1) Peripheral Device - connected on a.normal transfer channel in the

same manner as a disc or drum.

(2) Multiprocessor - a device that has its own instruction repertoire

and can operate simultaneously with a central processor.

(3) Integrated - the associative memory is embedded as a part of core

memory and can operate upon data both in an associative manner and

in a conventional manner.

(4) Special I/O Search Controller - the associative memory is used to

coordinate, control, and optimize search operations employing peri

pheral devices and thereby to assist the overall computation process

by decreasing the imbalance between memory speeds.

With each of the above configurations, variants are possible with alter

native logic mechanizations of the associative memory. The alternatives range

from devices capable of elementary searches on equality, less than or equal,

greater than or equal, maximum, minimum, etc., to devices that contain full

parallel hardware, thereby permitting complex.operations and extending the

memor& to have the capabilities of a processor.

In addition .to the above interfaces,' a number of designers have consider

ed associative processors. One development in this regard is the Associative

Store Processor (ASP) [LSAP65, SLAS66, SLAS67], described by Love, Savitt and

Troop. The ASP machine organization provides the parallel search facilities

of an assoctative memory plus inter-cell communication. The dominant element

in the ASP machine organization is the context-addressed memory. This memory

.stores both data and programs and is intended to provide the ability to

identify, in parallel, unknown items by specifying the context of relations

in which the unknowns appear. A relatively small read-only memory isemployed

to store a micro-program for executing ASP instructions. However, the ASP

machine organization has not reached a hardware implementation stage. An

interpreter [SLAS68] has been implemented for the IBM 360 family of computers

to simulate a portion of the ASP system.

The ILLIAC IV [BCIL68, KAA068, IUIL67], which is an outgrowth of the

Solomon Computer [SBTS63, SBTS62, CGTS65], should provide extensive parallel

processing capability. The ILLIAC IV is currently being implemented for the

University of Illinois by the Burroughs Corporation. As noted in [BCIL68]

"The nucleus of the system is the ILLIAC IV array, a matrix of 256 identical

processing units, configured into four identical quadrants, each having 64

processing units under the direction of a comion control unit. These array

elements perform the computational tasks for the system." Each of the 256

processing elements has 2048 words of 64 bit memory. Associative processing

is accomplished 'by performing search operationswhen the elements of the

search field are in.the same relative position. in.each processor. The cycle

time is 240 nanoseconds. The processing elements have a 32 bit mode where

each quadrant could be considered as 128 parallel operating units. The pro

cessing elements can ccmmunicate data to form neighboring processing elements

by means of routing instructions.

The complete ILLIAC IV system for the University of Illinois includes a

B6500 computer to perform input/output operations and compilation, and con

tains an operating system. A l09 bit, head-per-track disk file with a 40

millisecond rotation speed provides an effective transfer rate of l09 bits/

second. Westlund [WGAT68] has developed a timing simulator for the ILLIAC IV.

The simulator, written in ALGOL, is implemented on the Burroughs B5500.

Kisylia [KAAA68] proposes an associative memory processor with distribu

ted logic. His work is based upon the organization proposed by Lee and

Paull [LPAC63]. The modification made by Kisylia lies in the construction of

the memory cell and in the various modes of local communication each cell-en

joys with its neighbors. Processing may take place simultaneously on three

distinct levels in the machine. The hardware organization has not been im

plemented.

Murtha [MJHP66] has written a comprehensive and thorough article on

highly parallel processing systems in which he describes associative memories

and associative processors. Both hardware and software technical details of

a large number of parallel-processors are covered, In addition, he explains

how an associative memory cell operates and describes the inter-communicating

cell developed by Lee [LCIC62]. Murtha notes that, "...Probably the most

ambitious hardware development is a cryogenic processor being built by Texas

Instruments. It will have 5000 words of 65 bits each with a parallel read

cycle time of about 10 psec. It is expected to be operating in the fall of

1966." As of the time period covered by this article, this author is not aware

that the memory has been delivered to the sponsors, Rome Air Development

Center (RADC).

Knapp [KMRP67] describes work sponsored by the Rome Air Development

Center (RADC) in associative memory technology. -In1967 RADC was sponsoring

the following hardware assotiative memory developments: an Associative List Selector (ALS) that implements a fast hash addressing scheme, is under development by Goodyear Aerospace Corporation [GBAL66]; a 120-bit 2350 cryotion

associative processor plane is being fabricated by Texas Instruments, Incorporated [PJFA65, RGCA64J; a breadboard model of an associative memory that

uses ferroelectric and photoconductor elements has been developed by the

Marquardt Corporation [HBED66, HBAT65J; techniques for fabricating distribu

tive logic and memory networks using monolithic chips, wafers and individual

minature component elements are under development by the Westinghouse Aerospace Division [TRFT66]; and an, associative memory array using enhancement

insulated-gate complementary, thin-film field-effect transistor has been de

veloped and partially tested by RCA under Contract AF30(602)-2718.

All of the above hardware organizations have permitted both the reading

and the wri.ting of data from and to an associative memory. Fixed or semi

permanent stores have been used as content-addressable memories. Goldberg and Green [GGLF61J have reported upon a fixed content-addressable memory that involves the use of permanent wiring of information in an array of linear

cores. Lewin,, et al [LBFR65] have developed a fixed content-addressable memory where electronic punched cards are used as the storage medium. Lewis

[LMAS65] has written a thorough survey of fixed memories for both content and conventional memories. Read-only memories are useful when one has ehcyclopedic

information not subject to change, but they are :not useful-when the data base

issubject to change.

3.4 Software Simulation of Associative Memories

In addition to the simulation of an associative processor, ASP [SLAS68],

attempts have been made to simulate associative memory properties via soft

ware techniques. Feldman [FJA065], using a hash code to access entries in a

table, basically simulates the,exact match capabilities of an associative

memory. The data accessed is organized in a ring data structure. His approach

is very useful for systems that do not require the full capabilities of an

associative memory (i.e.,, the ability to interrogate the entire memory on any

combination of bits within a word, rather than on only an exact match).

Rovner [RPAI66] has modified the hash code concept to organize the data where

it exceeds the capacity of core. In this modification a two-level data store

consisting of core and drum is required. Rovner develops a scheme

for a paged software-simulated associative memory. Again, only the exact

match is considered. Hilbing [HFTA68] also considers paged associative

memory systems. Ash, et al [ASTA67] have used Feldman's approach to organize

data for a question-answering system under development. The system is called

TRAMPS. Rovner and Feldman [RFTL68, FRAA68] .have developed an associative

language called LEAP to facilitate programming their simulated associative

processor. LEAP is an extension of ALGOL to include associations, sets and a

number of auxiliary constructs. LEAP is a family of languages; each language

adds a different set of features, to the ALGOL base. Forms of LEAP contain

matrix operations, property sets, and on-line graphics [FRAA68, RPAA68]. Gall

and Brotherton [BGAL66], describe an Associative List Selector (ALS) hardware

device with capabilities similar to those of the associative memory that

Rovner and Feldman are working out through a software simulation. The ALS is

a hardware implementation of hash addressing to give a fast search capability

on equality.

4. Software Studies

The area of software for associative memories has by and large been

neglected. Falkoff [FAAF62], using Iversoa's notation, has developed numerous

algorithms for associative memories. Estrin and'Fuller [EFAF63] have also

described algorithms for associative memories. They further note that

content-addressable memories are more flexible than list structures since,

within a list structure, data is ordered with respect to predecessors and

successors of elements on a list. However, in a content-addressable memory,

data sets are unordered. Lewin [LMRO62] has developed an elegant technique

requiring two sense outputs for each digit of the word and requiring 2m-l

cycles for the complete readout of m words that match the interrogation bit

configuration. The time is a function of the number of multipi6 matches and

is not a function of the size of the associative store. A new proof of

Lewin's result has been developed by Wolinsky [WAAS68].

Dugan, et al [DGAS66] note that several macro type instructions are re

quired for dealing with several classes of data in an associative memory.

They describe a routine called SPO that saves all response stores andstatus

(busy) bits and "deactivates" that AM segment not defined by SPO. Other macros

noted were NGT (to find the,value of a data word from a list which is next

greater than the comparand), AND (to find the conjunction of two lists of data

words), and an executive type routine, DISPATCHER, that handles the problem of

data loads to the associative memory. They note that programming for

associative memories is "difficult to learn because associative configurations

are conceptually different from other configurations". Green, et al [GMA066]

expand upon the implications of associative processing for programmers reported

by Dugan.

There are severalI i-&i ti features that couldkiiitp the software manipulative

problem. Bird, et al [BCS066] note that a multi-write capability that permits

one to write simultaneously into memory registers is important for associative,

manipulation. Dugan, et al [DGAS66] note that the abili.ty to retai.n and to

manipulate tag bits ina word and to perform indirect addressing or index

modifications of associative instructions for associative memory locations

are important hardware features required by software personnel.

http:abili.ty

5. summary

Associative memory hardware technology has not yet 'come of age. After

more than twelve years of effort in the field, only experimental hardware or

small memories exist. Simulation-solutions have yet to 'nclude the full

.capability of associative memories. Sbftware studies indicate that programm

ing associative memories is complex and that much more work is required in

this area. Although the associative-property is useful, manipulating

associatively stored data may be complex.

Two application areas that look promising for associative memories are

those of control operations and question-answering systems. A survey of

question-answering systems is provided by Simmons [SRAE65]. More recent work

is provided in [KCNL68, WWPS68, SBAC68, GRTU68].

No one has yet completed a study that conclusively shows that associati-ve

memories or processors in a computer environment are clearly better than a

conventional memory. For the types of problems he considers, Feldman [FJAO65]

notes that a simulation of an associative memory on conventional hardware is

competitive with the hardware approach.

It is clear that the promise of associative or content-addressable memories

has not materialized. Much work remains to be done to achieve large data

stores of associative memories. The software approaches to achieve associative

capabilities will become increasingly important as associative hardware con

tinues to remain limited. More quantitative studies, rather than speculative

studies, are required to determine the precise advantages or disadvantages of

associative memory technology.

As may be seen from the size of this bibliography, the literature in

associative memory technology continues to grow rapidly. It is hoped that

future studies will provide further insight into the prospects for this technology.

Preface to KWIC* Index

The bibliography consists of two parts. The first part is the Key Word In Context (KWIC) Index which lists the titles sorted according to index

words selected from the title. Preceding each title is a six-character code. The coding scheme (devised by the late H. P. Luhn who developed one of the first KWIC indexes) is composed by taking the first character of the author's last name, the first character of his first name, the first character of the

first and second words of the title, and the date of the article. A slight modification of the code applies for multiple authors, corporate authors and other non-standard situations. The second part of the bibliography consists

of the citations themselves sorted according to the coding scheme. In addition to the citation, the computer review number is'provided whenever the

article has been reviewed in Computing Reviews. The citation appears only once in the second part of the bibliography even though there may be multiple

authors. References in the text are specified in terms of the code.

The bibliography has been accumulated over several years starting in 1963. Among the journals covered in the bibliography are the Joint Computer Con

ferences, Association for Computing Machinery publications and Defense Docu

mentation Center publications. Other journals have also been searched in

accumulating the bibliography. Two searches of the Defense Documentation Center holdings were requested: search control No. 001550 and 101547 October

7, 1968. Wherever possible, patents concerning associative memory developments

have been included.

*The Key Word In Context Index (KWIC) program used was developed by Mr. J. Gary

Augustson and Mr. Arnold Miller of the University of Maryland Computer ScienceCenter for the UNIVAC 1108 computer.

PAAT65 REASONANT ABSORPTION NON-DESTRUCTIVE READ-OUT TFCHNIQUE.=A THIN MAGNETIC FILM CdMPITE IEMORY USING PSAA67 AN ABSTRACT PARALLEL PROCESSING SYSTEM.= CAM69 CIATIVF MEMORY ACCEPTORS ZASSo FRVTA9 OPOLOGY RANDOM ACCESS MEMORY ORGANI?ATIONS=VART!ALF T WRAT MULTIPLE-WORD ACCESS PEMOPTFS,=A TRANSISTOPTUNNEL DIODE CELL FOR ASSOCIATIVE MEMORIES AND NECS67 LL9 FOR RANDOM ACCESS MEMOPIES.=CRYOTRON STORAGE Cr FHVTa9 OPOLOGY RANDOM ACCESS MEMORY ORGANIATONS.=VARAR.E T lvkIO(2 OF STORAGE AND ACCESS TPCHNICUPS SUITAStE FOR USE IN LARORP CAPACITY DIGITAL. MFMORIES. =INVETIGATON PNFIal STOPACE AND ACCESS TFCHNTnlSS.=FUNDAMFNTAL INVEqTIGATION OF DIGITAL COMPUTER LAAA61I REDUCE THE ACCESS TIME FOR TNSTRUCTTONS IN LOOPS.=AN APPLICATION FOR A SMALL, FAST ASSOCIATIVE M HGOR97 QUASI-RANDOM ACCESS MEMORY SYSTEM.: BLCR65 LECTRIC RANDOM ACCESS MEMORY, PHASF 3.=CRYOE BACR6,6 LECTRIC RANDOM ACCESS MEMOPY - PHASE 3.=CRYOE NOCS65 ING FOR RANDOM ACCESS MFMORTES.=CONTINUOUS SHEFT SFNS BDCR64 LECTRIC RANDOM ACCESS MEMORY, PHASE P 1n ( 9 ) BIT MEMORY.=CRYOE NvCA65 CRYOGENICS - ACHIEVFMENT AND POTENTIAL.: FRAL6 7 ACHIEVING LARGF SCALE COMPUTING CAPAPI.ITIFS THROUGH ASSoCIATIVE PARALLEL kROCESSING: FHAL ACHIEVING LARGE COMPUTING CAPABILITIES THROUGH ASSOCIATIVE PARALLEL PROCESSING.= SDAL GJBT6O , SIMULTANEOUS

ACHIEVING ACTION

LARGE COqPUI1NG CAPARILITIES THROUGH AN ARRAY COMPUTER.= =RINARY TESTS FOR TWO TERMINAL

BkAAe,9 EALIZATION FOR ACTIVE SONAR S1ONAL PROCFSSTNG.=AN ASSOCIATTVF MEMORY PARALLFL nFLTIC R WEVO7 MS - CYCLIC TO ACYCLIC GRAPH TRANSFORMATTONq.=MODFLC OF COMPUTATIONAL SYSTF KMSP64 HASIS ON ADAPTATION TO 11SF THROUGH MAN-MACHINE TNTERACTION.=SOME PROBLEMS IN INFORMATION SCIENCE W YcAT63 ADAPTIVE THRFqHOLn LOGIC.: ACTC65 CTION OF AN' ADAPTIVE MAN-MACHINE ASSOCTATIVE MEMnRY FOR INFORMATION RETRIFVAL.TOWARDS CONTROLLED t KMAM62 ADAPTIVE MFCHANTSPS IN DIGITAL. I CONCFPT I PROCESSING. = YoDCA68 Y DESIGN USING ADAPTIVE AND ASSOCIATIVE TFCHNIOIES.=COMPUTER-AIDED STRATEG EvCA62 CORRECTION AND ADnFNDUM =CORPEC YYAN66 A NONBuLK ADDITION TECHN'IOIE FOR ASSOCIATIVE PRnCESSORS.= ISSB6 SORTING BY ADtRESS CALCIILAYION.= SGA064 ASSOCIATIVELY AUFRESS DISTRIBUTED MEMORY.=APPLTCATTON OF AN FESA63 NS FOR CONTENT ADPRESSABLE MEMORTES=SOME.APPLICATIO. P:EAIA9 RATORY CONTENT ADDRESSABLE MEMO Y SYSTFM.=AN IMPROVED FTELD-CONTROLLED POLARIZATION-TRANSFEO DEVICE AND T FRCA63 CONTENT ADDRESSARLE MEMORY SYSTEMS.= LCCA6B CONTENT ADORESSABLE AND DISTRIEUTED LOGIC MEMORIFS. z H:jACf7 A CONTENT ADDRESSABLE MEMO'Y WITH APPLICATIONS TO MACHINE TRANSLATION.= LpAC64 A CONTENT ADrRESSARLE DISTPIPJTED LOGIC MEMORY WITH APPLICATIONS TO INFORMATION RETRIEVAL.= BRCAr,6' CONTENT ADDRESSARLE MEMORY.= Bk

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CONSIDERATIONS

CONSIDERATIONS

RASEP' ON R!NG9S-CYI.!NrFlg-A IN LANGUAGE AND MACHINE ORGANIZATION.= f PROCFSSING. =ADAPTIVE MECHANISM

=A MACk-INE FOR PERFORMING VIqtAL ,RECOGNITION Hy =CONTENT ADDRESSARLE

PARALLEL PROCESSING AND PARALLEL PROCESSORS.=A COMP[ITFR SYSTEMS=CPFCIAL SFqION 0 RANDOM WALKS ON HIGHLY PARALLEL MACHINES.=A PATH PER FILE ITEM.=MAGNETIC REALIZATION FOR MIRF IETECTION.=THE ASSOCIATIVE PROCESS ALGOPITHM.=A MODIFICATION AND TTF APPLICATTONS.=AN ALGO =MEMORY HIERARCHY - C IN UTILIZATION OF A NETWORK OF COMPUTERS.=

USE OF ANTENNA

SURVEY OF PROBLEMS AND PRFLI

SPPAe3 ING AND DESIGN

BCC162

HJOIAO RCUIT COMPUTER

SGANAO NCIPLE FOR-THE

ACTCA5 RIMENTS IN THE

FESA63 PLICATIONS FOR

PFAIA9 HE EXPLORATORY

FRCA63

LcCAAB

LsAMe3 ALL MAGNETIC

LPAC64 A

HjAC67 A

BRCA67

BRCAeG

GECAA7

BRCA66

SLPC65 PANEL ?

SRCAA7

hDHS64 HIGH-SPEED,

PHCA62

LpAC63 A

CDCAA5

LMRO62" D kISTS FROM A

EJIP70 ING WITH QUEUED

NJAO69 ATIVE MEMORY OR

SHCA66

CwPW67 PLATED WIRE

EFAFA3 ALGORITHMS FOR

FRCA63

BHCA67

RPOA68

RPEO67 UATION OF THREE

RRTC6,& TRANSFLUXOR

SFAC64 A

CwCA65

CWCA66

CiCA65

TRTC62 TRUE

CRCA67

EFSA63 PPLICATIONS FOR

ERCA64

HACA66 RPAG69 ASS DELAY LINE SwAS68 NTIALLY HOMING RPAGe9 ASS DELAY LINE BHAO66 ASSOCIATIVE OR Nf.CA6E CYA065 APPLICATION OF

RCCA66

SHCAA6

.SHC067 COMMENT ON ' CSDT66 F A DELAY-LINE GKAC A GKAw UPERCONDUCTING KHSAA" UPERCONDUCTIVE GKAC67 A .BH064 THE CRYOGENIC

CONSIDERATIONS

CONSIDERATIONS

CONSTRUCTED

CONSTRUCTION

CONSTRUCTION

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

CONTENT

OF A HIGHLY PARALIEL COMPUTEP.=PROGRAMM IN THE DESIGN OF A COMPUTER WITH HIGH LOGIC-TO-MFMORY SPEED RATIb.= OF MICPOELECTRONTC COMPONENTS AND SYSTEM.=ON ITERATIVE CT OF A MEMORY DEVICF.=A NEW PRY OF AN ADAPTIVE MAN-MACHINE ASSOCIATIVE MEMORY FOR INFORMATION RETRIEVAL.=TOWAR ADDRFSSABLE MEMORTES=SOME AP APOPFSSALE MEMORY SYSTEM.=AN IMPROVED FIELD-CONTROLLED POLARZATION-TRANSFER ADODRSSAFLE MEMORY SYSTEMS.= AODR SSABLE AND DISTRIBUTED LOGIC MEMORIES. ADDRFSSED MEMORY.= ADDRFSSARLE DISTRTRUTEO LOGIC MEMORY WITH APPLICATIONS TO INFORMATION RETRIEVA AnDRFSSAPLE MEMORY WITH APPLICATIONS TO MACHINE TRANSLATION.= AnDRFSSARLE MEMORIES.= ADDRFSSAPLE MEMORY.= ADDRFSSED MEMORY.= AODRFSSARLE MEMORY.= ADDRFSABLE MEMORIES,= ADDRFSSED MEMORY.= SEARCH IN A LARGE, ROTATING, MASS MEMORY.= ADDRFSSING AND INFORMATION RFTRIEVAL.= ADDRFSSABLE DISTRIBUTED LOGIC MEMORY WITH APPLICATION TO TNFORMAYITN RtTRIEVAL ADDRESSABLE MEMORY SYSTEMS CONCEPTS.= ADDRFSqED MEYORy.=RETRIFVAL oF ORDERE

CoNTENT-ADDRFSSABLE MEMORIES=INTERRIPT PROCESS CONTENT-ADDRESSABLE MEMORY SYSTEMS AND A KWIC INDEX TO THE LITERATURE 1q5-I970=AN OVERVIEW OF A CONTENT-ADDRESSAPLE PROGRAMMING TECHNIQUES.= CONTENT-ADDRESSAPLE MEMORIES WITH BIT-STEERING TECHNIQUE.= CoNTENT-ADDRESSABLE MEMORY ORGANIZATION.= CONTENT-ADDRESSABLE MEMORY SYSTEMS.= CONTENT-ADDRESSABLE MEMORY.= CoNTENT-ADDRESSARLE MEMORY SYSTEM.=DESTGN AND RVALUATION OF A GLASS DELAY 'LINE CONTENT-ADDRESSABLE MEMORY SYSTEMS uSING GLASS DELAY LINES.=EVAL CONTENT-ADDRESSApLE MEMORY.= CONTENT-ADDRESSABLF DI'TRIBUTFD LOGIC MEMORY WITH 'APPLICATIONSTO INFORMATION RFTRIEVALi CONTENT-ADDRESSA8LE MEMORY TECHNIQUFS.= CONTENT-ADDRESSABLE MEMORY TECHNIUFS.= CONTENT-hDDRESSABLE MEMORY TECHNIQUFS,= CoNTENT-ADDRESSADLF MEMORY.= CONTENT-ADDRESSABLE MEMORY TECHNIQUFS.= CONTENT-ADDRESSABLE MEMORIES.=SOME A CONTENT-ADDRESSABLE DISTRIRUTED-LOGTC MEMORIES,= CONTENT-ADDRESSABLE ANn ASSOCIATIVE MEMORY SYSTEMS - A SURVEY.= CONTENT-ADDRESSED MEMORY SYSTEM=A GL CONTENT-ADDRESSED MEMORY MODEL.=A SFQUE CONTENT-ADDRESSED MEMORY SYSTEM.=A oL CoNTENT-ADDRESSE STORFS.=ASSOCI CoNTENT-ADDRESSED MEMORY USING MAGNETORESISTIVF READOUT OF MAGNETIC THIN FTEMS.: CONTENT-ADDRESSE" MEMORY FOR DYNAMIC STORAGE ALLOCATION.=APPLIC CONTENT-ADDRESSED MEMORY.= CONTENT-ADDRESSED MEMORY USING MAGNFTO- OR ELECTRO-OPTTCAL INTFPROGATION.= CONTENT-ADDRESSED MEMORY USING MAGNFTO- OR FLFCTRO-OPTICAL INTERROGATION.#= CONTENT-ADDRESSED MEMOPY.=DESIGN TECHNIQUES 0 CONTINOUS FILM MEMORY CELL FOR SUPERCONDUCTIVE ASSOCIATIVE MEvORIESi CONTINUOUS FILM WEMORy=A WORf-ORGANIZED S CONTINUOUS FILM MEMORY CELLS=S CONTINUOUS FILM MEMORY PRIVEN BY MULTIPLE COINCIDENT PULSES-CONTINUOUS FILM MEM ORY CELL.=OPERATION OF

BLCS60

NOCS65

ENA06S THE CRYOGENIC

GMEA65 UPERCONDUCTING

SjDLA9 ER FOR PROCESS

GHAM68 TH ASSOCIATIVE'

BMAAF,9 D SYNTHESIS OF

HHCS68

HTPC68 ASSOCIATIVE

HBSU64 AS A REAL-TIME

GFAT66 TECHNIQUES FOR

FAPS60 OGRAM SEQUENCE

HHADb3 A DIRECTORY

SHTC62 THE CENTRAL

RFST64 TO COMMAND AND

RFST64 TO COMMAND AND

GGAT67 TECHNIQUES FOR

RLGC64 MUNICATION AND

RFST64 ICATION SYSTEM

AETF61 FORMULATION OF

vITA69 EMENT

ACTC65 TOWARDS

RPAA67 ING SYSTEM FOR

RFAA67 ING SYSTEM FOR

CAOT68 ON THE

BJAS61 AND CODE

NRC63 ATORS AND CODE

AFBI65 SPEED NORO ONE

RHTW68 2-1/20

EvCA62

EETU67 ACKING AND

.JKTT62 TARGET TRACK

PGAS64 MORY UTILIZING

wcACe8 A

NYSP61 BY CAPACITIVE

HpEC EVALUATION

NBTC60 THE

HiSC65 ACTERISTICS OF

SNTW66 THREE-wIRE

BSCS65 ITY SENSING OF

CGMM66 NG METHODS FOR

BSCR64 t BACM63

BACR64

BACR66 * C(,VM67 NG METHODS FOR BLCR65 ARCMA3

BcAL63 LARGE CAPACITY

BLCM64

CLAC67 A

PJPD6B PROCESSING VIA

WNAN6B A NEW

BBBC66 BASING

RJR063 RESEARCH ON

YYAC66 A

PwUOA5 LY ASSOCIATIVE

CONTINUOUS

CONTINUOUS

CONTINUOUS-

CONTINUOUS

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

CONTROLLED

CONTROLLED

CONVENTIONAL

CONVENTIONAL

CONVERGENCE

CONVERTER

CONVERTERS

CORE

CORE

CORRECTION

CORRELATION

CORRELATION

CORRELATION

COUPLE

COUPLING

CRITERIA

CROSSED-FILM

CROSSED-FILM

CRYOELECTRIC

CRYOELECTRIC

CRYOELECTRIC

CRYOELECTRIC

CRYOELECTRIC

CRYOELECTRIC

CRYOELECTRIC

CRYOELECTRIC

CRYOELECTRIC,

CRYOELECTRIC

CRYOELECTRIC

CRYOELECTRIC

CRYOELECTRIC

CRYOELFCTRICS

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

SHEET SUPERCONDUCTING MEMORY.= SHEET SENSING FOR RANDOM ACCFSS MEMORIES.= FILM MEMORY.=ANACYSIS OF FILM STORE.=EXPERIMENTAL AND THEORETICAL ASPECTS OF THE S =DISTRIBUTED LOGIC MEMORY COMPUT =A MULTIPROCESSOR WI

'MECHANISMS FOR PARALLEL PROCFSSES.=ANALYSIS AN STORAGE USE IN IMPLEMENTING AN ASSOCIATIVE MEMORY FOR A TIME-SHARED PROCESSOR0 =PAGE-CONTROL SCHEMES IN A MUiLTIPROCESSOR WITH =SOMF USES OF AN ASSOCIATIVE MEMORY FUNCTIONS IN A MUI TIPROCESSOP.=ASSOCIATIVE ,IN A MuLTIPROCESSING SYSTEM uSING ASSOCIATIVE STORAGE.=PR SYSTFM FOR MULTIPROGRAMMING.= UNIT OF THE ATLAS COMPUTER.= =STUnY TO DETERMINE THE APPLICABILITY OF THE SOLOMON COMPUTER VOLuME I. INFORMATION STORAGE, RETRIEVAL ANn COMMUNICATION SYSTFM CONTROL,=ST

FUNCTIONS IN A MULTI-PROCESSOR SIMULATION INVESTTGATTON.=ASSOCIATIOE LANGIIAGES.=GRAPHICAL COM =STUDY TO DETERMINE THE APPLICABILITY OF THE SOLOMON COMPUTER TO COMMAND AND C SYSTEM OPTIMIZATION PRORLEMS.=THE FIXED-PLUS-VARIABLE COMPUTER SYSTEM TN rYNAM BY MONAPOLAR CURRPNTS.=THE ANALYSIS OF THE CRYOTRONIC ASSOCIATIVE EL EXPERIMENTS IN THE CONSTRUCTION OF AN ADAPTIVE MAN, MACHINE ASSOCIAYIvE MEMORY DIGITAL COMPUTERS=AN ASSOCIATIVE PROCESS -DIGITAL COMPUTERS.=AN ASSOCIATIVE PROCESS OF OTSCRETE APPROYIMATIONS TO THE NAVIER STOKES EQUATIONS;= =A SFMI-PERMANENT MAGNETIC ASSOCIATIVE MEMORY =MAGNFTIC COMPAR PER PIT ASSOCTATTiE ELEMENT.=RILOC - A HIGH SEARCH MEMORY.= AND ADCENDUM.= =THE USE OF ASSOCIATIVE PROCFSSORS IN RADAR TR WITH A SEARCH MEMORY.= ADDRFSSING.=A SEMIPEPMANENT ME MAGNFTIC FILM DEVICE FOR ASSOCIATIVE MEMORIES.= =SEMT-PERMANENT STORAGE FOR ASSOCIATIVE MEMORIES.= CRYOTRON AND ITS APPLICATION TO DIGITAL COMPUTERS.= CRYOTRON CIRCUITS.=SwITCHING CHAR MEMORY SYSTEMS.= MEMORY PLANES.=CAV MEMOPIFS.=MANUFACTURI RANDOM ACCESS MEMORYP PHASE v In C 9 ) BIT MEMORy.= MEMOPIES.= RECEIVER TECHNIQUFS.= RANDOM ACCESS MEMORY - PHASE 3.= MEMORIFS.=MANUFACTURI RANnOM ACCESS MEMORYP PHASE 3.= MEMORIES.= MEMORY WITH CAVITY SENSING.:A MEMORTFS.= DISTRIBUTED LOGIC MEMORY,= =PARALLEL DATA MEMORY SYSTEM= COMPIITFRS IN SPACE= ASSOCIATIVE MEMORIES.= ASsOCTATIVg MEMORY FOR INFORmATTON RgTRJRVAv; DATA PfOCCfOP.=OvSAN OP A PUL.

TRFSe1 TY STUDY FOR A

GMACAO A P.IFAe6 G OF 5000 WORD ISCA

RJRO63 RESEARCH ON

RR064 RESEARCH ON

RjRO,3 RESEARCH ON

BR0064 ERATION OF THE

WRAC62 A

yOD061 A LARGE SCALE

AMGE62 G. E.

GECM65

GECA67

GECM65

IBCM5

HHCMA4

VRPF67 FOR FUTURE OF

RJCA64

BLD062 A LARGE-SCALE

yTAC67 A

YTSD64 ATIC DESIGN OF

RwAM63 THMS AND THEIR

SRCA6O"

STFSe TY STUDY FOR A

PwDOA4 LY ASSOCIATIVE

yyAC66 A

RJCA64

VHCR66

RGCA64

PFCT63

PjFA65 AND TESTING OF

BRCA63

PuND66 EVELOPMENTS IN

ABCA64

BPOe6 A SPACE-BASED

PJFA67 G OF 5000 WORD

NFACr,2 A

RRAO2 AN ASSOCIATIVE

HwAO APPLICATION OF

ENAO5 NALYSIS OF THE

8S064 STRUCTURE OF A

RICM65

NVCA65,.

ssyTpo THIN FILM

NFCS67 LACA65

RDTD66 ESIGN OF LARGE

SATW59 THE WOVEN

YCASA4 A STUDY OF

RJCRe4 SAAC62 A SmTCS7 THE SSTFhO THIN-FILM wSCAA3 CRYOTRONS AND PECMS7 LICL66 HMCS6O

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENIC

CRYOGENICS

CRYOGENICS

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

CRYOTRON

ASSOCIATIVE MEVORY.:FEASIRILT MIILT'IPLE INSTANTANEOUS RESPONSE FILE.'= ASSOCIATIVE PROCFSSOR.=FARRICATION AND TESTIN ASSOCIATIVE MEMORY TFCHNIQUES.= ASSOCIATIVE MEMORIES.= ASSOCIATIVE MEMORIES.= ASSOCTAT.IVE MEMORIES.= CONTINUOUS FILM MFMORYCELL.=OP I BETWEEN LIMITS I ASSOCIATIVE MEMORY.= MEMOPY.=fESIGN OF ASSOCIATIVE MEMORY CIRCUIT DEVELOPED;= MEMORY.= ASSOCIATIVE MEMORY.= MEMORY.= MEMOpY SYSTEM.= MEMORY SYSTEMS.= APPLICATTONS.=PRFPICTIONS ASSOCIATIVE MEMORY RFSEARCH.= MEMORY SYSTEY.=DEqIGN OF ASSOCIATIVE MEMORY.= LOGIC CIRCUITS.=SYSTEM IMPLEMENTATION.=ASSOCIATIVE MEMORY ALGORI ASSOCIATIVE MEMORY.= ASSOCIATIVE MEMORY.=FEASIBILT DATA PROCESSOR.=DFSIGN OF A FUL ASSOCIATIVE MEMORY SYSTEM FOR INFORMATION RETRIEVAL.= ASSOCIATIVE MEMORY TECHNIQUEq.= RESEARCH.= ASSOCIATIVE PROCESSOR PLANE TEST AND EVALUATION.=-