CUSTOM ASIC FOR ELECTRONEUROGRAPHIC

RECORDING USING NERVE CUFF ELECTRODES

Marcelo Bar6

Electrical Engineer, Universidad de la Republica, Uruguay 1997

THESIS SUBMITTED IN PARTIAL FULFILLMENT OF

THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF APPLIED SCIENCE

in the School

of

Engineering Science

O Marcelo Baru 2003

SIMON FRASER UNIVERSITY

February 2003

All rights reserved. This work may not be reproduced in whole or in part, by photocopy

or other means, without permission of the author.

Approval

Name: Marcelo Bani

Degree: Master of Applied Science

Title of thesis: Custom ASIC for Electroneurographic Recording

Using Nerve Cuff Electrodes

Examining Commit tee:

Chairman:

Date approved:

Dr. Andrew Rawicz, Professor School of Engineering Science

Dr. Ash Parameswaran, Professor School of Engineering Science Senior Supervisor

' ~ r . A&Iy off&, Professor School of Kinesiology Supervisor

W G i & EAP School of Engineeri Examiner

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extended essay (the title of which is shown below) to users of the Simon Fraser

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response to a request from the library of any other university, or other educational

institution, on its own behalf or for one of its users. I further agree that permission for

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Dean of Graduate Studies. It is understood that copying or publication of this work

for financial gain shall not be allowed without my written permission.

Author: (signature)

(name)

Abstract

This document reports the design, fabrication and testing of two

generations of custom ASICs designed for the recording of

electroneurographic (ENG) activity using nerve cuff electrodes. The

circuit consists of a fully-integrated, ultra low-noise, high CMRRIPSRR

preamplifier circuit, followed by a cascade of four stages that provide

filtering and further amplification of the neural signal. A precision full-

wave rectifier (PFWR) that utilizes neither diodes nor resistors, follows

the band-pass amplifying circuit. The circuit was implemented using a

1.6 pm commercial Bipolar-CMOS process. The complete circuit is

intended for a multi-channel implantable functional electrical

stimulation (FES) device based on closed-loop feedback control. The

characteristics of the signal to be amplified as well as the requirements

for the circuit are reviewed. The design is detailed to the transistor level,

emphasizing the careful sizing by using the (%/I,) method. Bench test

and in vivo results are presented.

Dedication

To the patience, love and support from my wife.

To my family and friends, for supporting me in this journey of

studying and living overseas.

To the memory of Hugo Valdenegro, for teaching me electronics and

for having given me the opportunity to work with him.

To my grandfather, for showing me how to overcome adversity.

Acknowledgments

First of all, I would like to thank all the members of the examining

committee for their interest in this project.

I am extremely thankful to Dr. Andy Hoffer for giving me the

opportunity of working in such interesting and challenging project, and

for offering me a position with Neurostream Technologies Inc.

I would also like to thank Dr. Ash Parameswaran for being my

academic supervisor and for teaching me micromachining, and Allan

Dyck for his help troubleshooting cadence" during the pilot stages of

this research.

Finally, I would like to thank the Grupo de Microelectronica at the

Universidad de la Republica, Uruguay, and in particular Dr. Fernando

Silveira, for fruitful discussions throughout the years and for their

support.

Table of Contents

. . ................................................................................... Approval ii

... .................................................................................... Abstract 111

................................................................................ Dedication iv

..................................................................... Acknowledgments v

............................................................................ List of Tables x

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi

1 . Introduction .......................................................................... 1

1.1 Characteristics of the nerve cuff electrodes .................. 2

1.2 Initial requirements for the band-pass amplifying

................................................................................... circuit - 4

1.3 Prior art .......................................................................... 5

1.4 Building blocks of the developed ASIC ......................... 7

1.5 Transconductance-over-drain current (%/ID) method

....................................................... and technology selected 10

2 . DC Protection Circuit and Preamplifier ................................. 14

2.1 Selection of the DC protection circuit and input stage

................................................................ of the preamplifier 14

2.2 Selection of the preamplifier configuration ................... 17

......................................................... 2.3 Preamplifier design 22

..................................... 2.3.1 Input transistors M 1 - M2 26

................... 2.3.2 Current source transistors M 3 a - M3f 26

2.3.3 Transistors M4 of the active load ........................... 28

......................................................... 2.3.4 Output stage 28

........................................................ 2.3.5 Second stage 3 0

............................................... 2.3.6 PSRR improvement 31

2.3.7 Determination of the voltage reference VBIAs and . . ................................................................. minimum VDD 32

.............................. 2.3.8 Generation of the current IBIAs -32

................................................................... 3 . High-Pass Filter -35

3.1 Selection of the high-pass filter configuration .............. 35

................................................... 3.2 High-pass filter design 36

........................................ 4 . Non-inverting, Low-pass Amplifier 39

4.1 Selection of the non-inverting, low-pass amplifier

......................................................................... configuration 39

..................... 4.2 Non-inverting, low-pass amplifier design 41

... 4.2.1 Input transistors M 1 and biasing transistors M 3 4 1

........................... 4.2.2 Transistors M2 of the active load 41

......................................................... 4.2.3 Second stage 42

......................................................... 4.2.4 Output stage 43

5 . ~ s ~ i c e " Simulations and Layout of the Band-Pass

........................................ Amplifying Circuit - First Generation 45

.................................................................... 5.1 Simulations 45

............................................................................. 5.2 Layout 48

.......................................................... 5.2.1 Preamplifier 48

.......................................... 5.2.2 High current reference 49

..................................................... 5.2.3 High-pass filter 50

........................................... 5.2.4 Low current reference 50

.......................... 5.2.5 Non.inverting. low-pass amplifier 51

................................................ 5.2.6 Layout photograph 51

6 . Precision Full-Wave Rectifier ................................................. 53

6.1 Selection of the configuration ........................................ 53

6.2 Design of the voltage inverter DDA ............................... 58

vii

6.2.1 Input transistors M 1 and current source

............................................................... transistors M 3 60

........................... 6.2.2 Transistors M2 of the active load 60

......................................................... 6.2.3 Second stage 61

.................. 6.2.4 Tweaking of the DDA systematic offset 61

.............................................. 6.3 Design of the comparator 62

6.3.1 Input transistors M1 and current source

............................................................... transistors M 3 63

6.3.2 Transistors M2 of the active load ........................... 63

......................................................... 6.3.3 Second stage 63

........................................... 6.4 Input switches and inverter 64

7 . ~ s ~ i c e @ Simulations and Layout of the Precision Full-Wave

Rectifier Circuit ......................................................................... 65

7.1 Simulations .................................................................... 65

7.2 Layout ............................................................................. 67

........................................... 8 . First Generation Testing Results 69

8.1 Band-pass amplifying circuit ........................................ 69

............................................ 8.2 Precision full-wave rectifier 72

..................................................... 8.3 In vivo testing results 75

8.4 Requirements for the second generation of the

band-pass amplifying circuit ............................................... 79

.......................................................... 9 . Preamplifier Re-design 81

................................................... 9.1 Configuration selected 81

........................................ 9.2 Dimensioning of components 83

............................................. 9.2.1 Input transistors M 1 83

........ 9.2.2 Transistors M2 of the cascode current mirror 83

9.2.3 Biasing resistors RA and transistors Q3 ................. 84

... V l l l

................. 9.2.4 Current source transistors M4 and M5 85

....................... 9.2.5 Biasing branch given by resistor RR 85

............................. 9.2.6 Biasing transistors M6 and M7 86

..................................................... 9.2.7 Output stage 8 7

......................................................... 9.2.8 Second stage 88

9.2.9 Determination of the new voltage reference VBrAs .... 89

10 . ~ s ~ i c e " Simulations, Layout and Testing Results of the

................................................................... Second Generation -90

................................................................. 10.1 Simulations -90

........................................................................... 10.2 Layout 91

..................................... 10.2.1 Re-designed preamplifier 91

.............................................. 10.2.2 Layout photograph 92

.............................................................. 10.3 Testing results 93

........................................... 1 1 . Conclusions and Future Work -97

1 1.1 Conclusions .................................................................. 97

................................................................. 1 1.2 Future work -98

............................................................................ Abbreviations 10 1

.................................................................................. Appendix 102

................................................................................ References 105

List of Tables

............ Table 2.1. Transistor sizes of the high current reference 34

Table 3.1. Transistor sizes of the low current reference ............. 37

Table 5.1: HspiceB typical simulation results of the band-pass

amplifying extracted circuit (first generation) ............................ 46

Table 5.2. Final sizes drawn for the preamplifier transistors ..... 49

Table 5.3: Final sizes drawn for the high current reference

................................................................................ transistors 50

Table 5.4: Final sizes drawn for the high-pass filter transistors . 50

Table 5.5: Final sizes drawn for the transistors of the

non-inverting, low-pass amplifier .............................................. 51

Table 7.1 : Final sizes drawn for the comparator transistors ...... 68

Table 8.1: Measured characteristics of the first generation

..................................................................... circuits # 1 and #2 71

Table 10.1: HspiceB typical simulation results of the band-pass

amplifying extracted circuit (second generation) ........................ 90

Table 10.2: Final sizes drawn for the re-designed preamplifier

................................................................................ transistors 91

Table 10.3: Second generation final specifications once

embedded in Neurostream's first prototype ............................... 94

List of Figures

Figure 1.1 : Impedance model of a tripolar nerve cuff recording

................................................................................... electrode 2

Figure 1.2: Arrangement of a single-channel, balanced-tripolar

nerve cuff recording electrode around a nerve ........................... 3

Figure 1.3: Constitutive building blocks of the ASIC developed . 8

Figure 1.4: Calculated (solid line) and measured data plots of

(&/ID) vs . ID/(W/L) ................................................................... 11

Figure 2.1 : Classical DC protection circuit ................................ 15

Figure 2.2. Proposed DC protection circuit ................................ 16

Figure 2.3: Classical 'resistor' feedback instrumentation

amplifier based on three operational amplifiers ......................... 18

Figure 2.4: 'Direct current' feedback instrumentation amplifier

(adapted from [Arnaud et a1 . 19981) .......................................... -19

Figure 2.5: Block diagram of an 'indirect current' feedback

instrumentation amplifier ........................................................ -20

Figure 2.6: Preamplifier configuration based on a differential

................................................................... difference amplifier 21

Figure 2.7: Individual building blocks of the band-pass

amplifying circuit considered in the noise evaluation ................ 23

Figure 2.8. Generation of the current IBIAS ................................. 33

Figure 3.1 : High-pass filter implemented .................................. -35

Figure 3.2. Generation of the current IBIAS~ ................................ 37

Figure 4.1 : Non-inverting, low-pass amplifier implemented ....... 40

Figure 5.1: Simulated frequency response of the first

generation of the band-pass amplifying circuit (typical model) ... 46

Figure 5.2.a: Layout of the first generation

............................................................ (die area 2.2 x 2.2 mm) -52

Figure 5.2.b: Photograph of the first generation ....................... .52

Figure 6.1 : Classical precision full-wave rectifier based on

.............................................................. operational amplifiers .54

Figure 6.2: Second embodiment disclosed by Kimura in

U.S. patent no. 5,306,968 ......................................................... 55

Figure 6.3: Precision full-wave rectifier disclosed by

Arnaud et al. [Arnaud et al. 19981 ............................................. 56

Figure 6.4: Precision full-wave rectifier implemented in this

project ...................................................................................... 57

Figure 6.5: Differential difference amplifier of the precision

full-wave rectifier implemented ................................................ .59

Figure 6.6: Comparator of the precision full-wave rectifier

implemented ............................................................................. 62

Figure 7.1: Simulated DC transfer characteristic of the

negative precision full-wave rectifier implemented.. ................... 66

Figure 7.2: Simulated dynamic response of the negative

precision full-wave rectifier implemented to a 3 kHz sinusoidal

.......................................................... input signal of 0.4 V,,&.. -67

Figure 8.1: Layout of the feedback resistors R1 and R2 .............. 70

Figure 8.2: Measured frequency responses of the two

band-pass amplifying circuits # 1 and #2 tested ........................ 71

Figure 8.3: Measured DC transfer characteristic of the negative

................................. precision full-wave rectifier implemented .73

Figure 8.4: Measured dynamic response of the negative

xii

precision full-wave rectifier implemented to a 3 kHz sinusoidal

input signal of 0.4 V p e ~ ............................................................. 74

Figure 8.5. Zoom in of the switching region of Figure 8.4 .......... 75

Figure 8.6: In vivo ENG signals recorded from the animal

research subject under anesthesia ............................................ 76

Figure 8.7. Recorded stimulus artifact on sciatic nerve ............. 77

Figure 8.8: Proposed solution for the recording band reduction 78

Figure 9.1. Preamplifier second generation ................................ 82

Figure 10.1 .a. Layout of the second generation

(die area 2.2 x 2.2 mm) ............................................................ -92

Figure 10.1 . b. Photograph of the second generation .................. 93

Figure 10.2: 6 ms-bin-integrated ENG signal processed on-line

from the animal research subject walking on a treadmill,

recorded using the second generation ....................................... 95

Figure 1 1.1 : Proposed integrated solution for the recording

band reduction ........................................................................ -99

xiii

Chapter 1

Introduction

For the past thirty years, nerve cuff electrodes have been used as an

implantable electrical interface for chronic recording of electrical activity

in peripheral nerves [Hoffer and Loeb 19801. These have been primarily

tested in animal research and in a small number of human subjects. In

pilot experiments [Haugland and Hoffer 1994, Haugland and Sinkjzr

1995, and Strange and Hoffer 19991, natural sensory signals recorded by

nerve cuff electrodes provided a reliable source of feedback for closed-

loop control of prototype FES devices.

Several different nerve signals will be needed for control of complex

FES systems. So far, nerve signals have been mainly recorded using

commercially available amplifiers located externally to the body, without

concerns about power requirements or equipment size. Such recording

setups also require long leads that course transcutaneously. This

configuration increases the risk of wire breakage, reduces portability,

contributes to signal shunting and greater pick-up of unwanted signals,

and, most importantly, increases the risk of infection for the patient.

Consequently, for clinical acceptability, "wireless cuffs" will be essential.

In order to achieve this, a full-custom, ultra low-noise, high CMRRIPSRR

band-pass amplifying circuit and a diode/resistorless PFWR have been

designed for the front-end of an intended closed-loop FES implantable

device.

In the next two sections, the characteristics of the electrodes and

signals to be amplified, and the constraints and initial requirements

imposed by the field of application, are presented.

1.1 Characteristics of the nerve cuff electrodes

The most important difficulty in recording from peripheral nerves

comes from the fact that nerves in the body are not isolated. Nerve cuff

electrodes were designed to solve this problem. Basically they serve two

purposes: first, they resolve potentials generated by nerve fibers by

constraining the flow of action currents (currents associated with action

potentials) within a narrow resistive path, and second, they record the

neural activity with least contamination from the much higher

electromyographic (EMG) signals generated by adjacent muscles [Hoffer

19751.

For example, a single-channel cuff electrode consists of an insulating

wall (usually made of silicone rubber). Within it, three or more

circumferential electrodes (usually made of stainless steel) are arranged

in a balanced tripolar configuration to maximize noise rejection.

Insulating the nerves causes action currents, generated by axons inside

the cuff, to flow along a resistive pathway provided by the enclosed tissue

and fluid. Two parameters, cuff inside diameter and inter-electrode

separation, determine the resulting neural potential shape and

amplitude. Figure 1.1 shows the impedance model of a nerve cuff

electrode.

Figure 1.1: Impedance model of a tripolar nerve cuff recording electrode

The impedances Z, and 2, model the resistance of the tissue and fluid

filling the cuff. They are in the order of a few kS2 to some tens of kR. The

impedances Z,, 2, and Z, model the electrode-tissue interface

capacitance. They are in the order of some tens of nF to a few pF. Finally,

Z, models the impedance of the tissue surrounding the cuff. It is in the

order of a few hundred S2.

Figure 1.2 shows the arrangement of a single-channel, balanced-

tripolar nerve cuff recording electrode.

Nerve

Figure 1.2: Arrangement of a single-channel, balanced-tripolar nerve cuff recording electrode around a nerve

As it can be observed in Figure 1.2, this is a "center vs. tied ends"

recording geometry (electrodes at the end of the cuff are shortened

together), which is the optimal way to reduce pickup of EMG and other

noise generated by current sources external to the nerve cuff (for a

demonstration using equivalent impedances see [Thomsen 19981).

Natural neural recordings in peripheral nerves using cuff electrodes

are typically in the range of a few pV [Hoffer and Loeb 19801. The

frequency range of recordings goes from 1 kHz to 10 kHz, with maximal

power below 3 kHz [Nikolid et al. 19941. The EMG activity surrounding

the cuff, with a peak around 250 Hz, is in the order of mV, which can

easily contaminate the neural activity. A s mentioned above, the "center

vs. tied ends" geometry reduces the pickup of EMG activity since the

nerve cuff electrode sees it as a "common mode" signal. Hence, the band-

pass amplifying circuit (see Figure 1.2) must provide a good rejection to

common mode signals (good CMRR).

1.2 Initial requirements for the band-pass amplifying circuit

The initial1 electrical requirements (at ambient temperature) chosen

for the band-pass amplifying circuit were the following:

Second order or higher band-pass amplifier. The low frequency pole

shall be 850 Hz + 15% and the high frequency pole shall be 9 kHz + 15%;

Rationale: This general recording band was selected based on "in vivo"

experiments performed at the NeuroKinesiology Lab at S.F.U. However, in

order to obtain the best signal-to-noise ratio (S/N), the band shall be

adjusted for each particular application.

Band-pass gain @ 3 kHz shall be higher than 87 dB;

Rationale: This allows enough amplification for further processing of the

neural signal (the maximum expected input signal is 15 pVpeak).

Equivalent input noise level @ 3 kHz shall be lower than 1.50 pV,,;

The second generation developed has tighter requirements, in particular with respect to the equivalent input noise level. These requirements will be detailed later on, before the second generation is described.

Rationale: This provides sufficient S / N for the processing of the neural

signal.

CMRR @ 250 Hz shall be higher than 90 dB.

Rationale: This provides sufficient rejection to EMG signals. In this way, the

CMRR of the system "nerve cuff electrode plus recording circuitry" will be

dictated by misbalances in the electrode.

The information contained in the band-passed, amplified nerve signal

appears to be stored in the amplitude rather than in the frequency. A

simple way of measuring amplitude is to rectify and integrate such

signal. In a multi-channel FES device, it is preferable to do both post-

processing operations in an analog fashion, since this will ease the

sampling requirements of the digital processing circuitry reducing power

consumption. The rectifier, as well as the band-pass amplifying circuit

specified above, must be low power and fully integrated since they are

intended to be used in a practical multi-channel FES implantable device.

In this project, two generations of a custom ASIC containing a fully-

integrated, ultra low-noise, high CMRR/PSRR band-pass amplifying

circuit and a fully-integrated, low-power PFWR that utilizes no diodes or

resistors, were designed, fabricated and tested.

The next section presents the prior art in the field of nerve cuff signal

amplifier design.

1.3 Prior art

The biggest problem in recording neural signals using nerve cuff

electrodes is the very low signal amplitude and low S/N that are

characteristic of these signal sources. When dealing with signals in the

pV range, minimization of the noise of the first stage of the amplifying

circuit is of extreme importance. Under such conditions, it is useful to

passively boost the signal amplitude with an audio transformer before it

encounters the first active amplification stage (usually a preamplifier).

This has been a common practice in recordings using external circuitry

[Nikolik et al. 19941. For implantable devices, the main disadvantage of

this proposition is the size of the transformers commercially available.

Even the smallest miniaturized audio transformers today in the market

have an area of around 1 cm2. Since several of these will be needed in a

multi-channel FES device, this solution is impractical. Hence, the noise

will be dictated by the input stage that is selected for the preamplifier.

Recently, an implantable, single-channel cuff-recording system,

fabricated using discrete components, which uses no input transformer

was disclosed [Donaldson et al. 20001. This design, although useful for

research purposes, has limitations in its clinical applicability due to its

size and power requirements, and is not suitable for clinical applications

where several recording channels are needed.

Various designs of custom-integrated amplifiers for neural activity

recording have been presented throughout the years. However, these

designs have generally dealt with neural source amplitudes at least two

orders of magnitude higher than the signals that are recorded using

nerve cuff electrodes. To my knowledge, the only relevant prior art in the

field of integrated circuits for the present application was a design

validated through SPICE simulations, where there is no mention to the

noise level achieved [Papathanasiou and Lehmann 20001. A major

disadvantage of this proposition is the fact that the amplifier gain is of

the open-loop type and the protection against a single semiconductor

failure2 is implemented using external components. In a commercial FES

system based on closed-loop feedback control, it will be imperative to be

able to change the gain of the amplifier in order to accommodate different

ENG recording ranges (for examples natural sensory information and

compound-action-potentials elicited by electrical stimulation) into the

same output voltage range. In particular, it is a must to have variable

gain if the recorded signal is going to be digitized using implanted

circuitry.

Open-loop amplifiers also present several problems associated with

their high gains. Two of the main problems are potential saturation due

to intrinsic amplifier offset and muscular activity (EMG) of much higher

amplitude than the nerve signals of interest, requiring the amplifier

special circuit techniques to compensate for these effects. The present

design avoids such problems and can provide several externally-

controlled gain levels with a minor modification, as required for the

development of FES systems based on closed-loop feedback control.

The next section presents the building blocks that constitute the

custom ASIC developed.

1.4 Building blocks of the developed ASIC

Based on the requirements detailed in section 1.1, the circuit built

was originally divided into the constitutive building blocks shown in

Figure 1.3.

The need to have protection against a single semiconductor failure will be explained in section 1.3.

\ Multi-channel, Nerve Peripheral Cuff Recording

Nerve Electrode

Figure 1.3: Constitutive building blocks of the ASIC developed

In this particular medical application, it is imperative to minimize the DC

current flow through the electrodes to avoid electrolysis, or in the case of

a semiconductor failure, to protect the nerves from irreversible damage.

Therefore, the signal picked up by the nerve cuff electrode is first passed

through a DC protection circuit that either blocks or minimizes any DC

current flow through the electrodes. Indeed, it is a regulatory

requirement to provide dual DC protection, so two simultaneous

semiconductor failures would be needed for any DC to flow through the

body. Due to the time constants involved, this protection is commonly

implemented using discrete components. Consequently, minimization of

this stage area is crucial for the integration of several recording

channels. In this project, I implemented an alternative way to solve the

protection circuit, which minimizes the number of external components.

Furthermore, the protection circuit developed is common to all channels,

avoiding the need of separate stages for each one, and does not degrade

the CMRR of the recording channel.

If well designed, the preamplifier dictates the noise and CMRR of the

recording channel. A s shown in Figure 1.3, in this case the preamplifier

was designed as a single-ended output circuit. Obviously, a differential

output would be the best solution in terms of preamplifier performance,

but area and power penalties must be paid. These penalties can be

avoided if the desired performance can also be achieved with a single-

ended output configuration. As it will be explained later, in this

particular design, the input stage of such preamplifier also implements

part of the DC protection circuit, therefore minimizing the size of each

recording channel.

The band-pass amplifier in Figure 1.3 provides band-pass filtering

and further amplification of the neural signal. This was achieved by

cascading two identical first-order band-pass filters, each one composed

of a high-pass filter and a non-inverting amplifier. In this way, offset is

compensated throughout the circuit except for the last stage. The low-

pass filtering behavior of the band-pass amplifier circuit is embedded in

the non-inverting amplifier, as it will be shown later.

Finally, the offset of the amplified and filtered signal is removed before

being inputted to the PFWR. The final output of the ASIC developed in

this project is the output of such rectifier.

The next section presents the (&/I,) method used to carefully size

each transistor in the developed ASIC, as well as presenting the

integrated circuit technology that was selected for the circuit fabrication.

1.5 Transconductance-over-drain current ( g d ~ ) method and

techno logy se lected

In CMOS analog circuits, different characteristics can be achieved by

biasing the transistors in different regions of operation. For example, the

transistors of a differential input pair in an operational amplifier need to

be biased near the weak inversion region (also known as sub-threshold

region) in order to have the largest possible transconductance for a given

biasing current and the lowest gate-source, saturation, and offset

voltages. In contrast, the transistors in a current mirror need to be

biased near the strong inversion region, to have good matching between

them. The equations governing these two regions of operation are well

known, which simplifies the task of finding the appropriate sizes of the

transistors. However, in many cases, the best compromise between

different characteristics is obtained by biasing the transistors in the

moderate inversion region. The (%/ID) method introduced by Silveira et

al. in 1996 [Silveira et al. 19961, based on the relation between the

transconductance-over-drain current ratio (&/ID) and the normalized

current ID/(W/L), allows a unified treatment of all regions of operation of

the MOS transistors. The application of this method, coupled with the

EKV model [Enz et al. 19951 with a set of parameters extracted from

measurements for the target process, allowed an accurate sizing of the

transistors. Figure 1.4 shows the calculated and measured plots of

(&,/ID) vs. ID/(W/L)3 in a 2.4 pm CMOS technology previously used

[Arnaud et al. 19981.

The curve depends on the transistor type. The one shown is for an NMOS one.

25

20

2- 7 - 15 n - \

E a 10

Strong

l Tn Figure 1.4: Calculated (solid line) and measured data plots of (&/ID) vs. ID/(W/L)

One procedure used to find the appropriate size of each transistor was

the following: a (&/I,) value was chosen, based on different trade-offs as

explained before. From this value, an I,/(W/L) value was obtained using

a similar plot as the one in Figure 1.4 (the function was implemented in

MATLAB@ for the final technology used). Then, using the current I,

needed through such transistor, the W/L ratio was obtained. Finally, L

values were chosen for each transistor based on particular

characteristics needed (gain, noise, etc.). In many cases, however, the

design started by selecting an ID/[2 n PC,, (U,)2 (W/L)I4 value, also known

as the "inversion coefficient" (from now on referred as IC), to obtain a

The "nn represents the subthreshold slope factor, "pCoxn the gain factor, and "UT" the thermal voltage.

- 11 -

(%/ID) value. This was particularly useful near the weak or strong

inversion regions, where large variations of the IC produce small

variations in the (%/I,) values. The implementation of the function in

MATLAB@ also provided gate-source voltages, as well as drain-source

saturation ones, for the particular transistor dimensioned. This allowed

evaluating minimum and maximum common mode voltages, minimum

power supplies needed, etc.

Many factors were considered in the selection of the integrated circuit

technology finally used. The most important factor was the need of a

high-voltage technology that will allow to develop a monolithic integrated

circuit for closed-loop FES control. This fact precluded the utilization of a

standard CMOS technology, since this technology withstands voltages

only up to 5 V. This important factor made me search for a high-voltage

technology that could withstand breakdown voltages of up to 20 V. The

ABN process from American Microsystems Inc. (AMI) in Idaho, U.S.A.

was selected. It is a high-voltage, low-noise 1.6 pm5 Bipolar-CMOS

technology (not a BiCMOS since it does not possess a buried n+ layer to

reduce collector resistance). I fabricated prototypes using a reasonably

priced multi-project prototyping service provided by MOSIS.

In addition to standard CMOS transistors, which are useful for low-

power design, the mentioned technology provides high performance,

junction-isolated vertical Bipolar transistors (NPN) that are especially

needed for full integration. Special layout techniques were used to

guarantee that the high collector resistance did not degrade the

A minimum length of 2 pm was selected as a reliability criteria for layout.

- 12 -

performance of such NPN transistors. Also, floating junction diodes are

preferable for the generation of the implanted chip voltage supply and are

available using this selected technology.

In order to complete the documentation provided by AM1

characterizing the technology, measurements of Early Voltages were

performed (on a wafer provided by the foundry) for quick hand

calculations. These measurements were performed using the

manipulator and the HP4 155 Semiconductor Parameter Analyzer from

the ENSC Clean Room. The results extrapolated were 3 V/pm for NMOS

transistors and 2 V/pm for PMOS ones.

The next chapter presents the design of the DC protection circuit and

preamplifier of Figure 1.3.

Chapter 2

DC Protection Circuit and Preamplifier

This chapter presents the design of the DC protection circuit and the

preamplifier. Different configurations were studied and are presented,

before selecting the most appropriate to meet all the initial pertinent

requirements detailed in section 1.1. Careful attention is paid to the

contribution of different components to the noise figure.

2.1 Selection of the DC protection circuit and input stage of

the preamplifier

A s mentioned in section 1.2, the circuit noise will be dominated by the

input stage of the preamplifier. Knowing this, I could have started the

design by using Bipolar transistors in such input stage, since these

transistors present less noise than CMOS ones for a given biasing

current. However, as mentioned in section 1.3, in this application is

imperative to minimize the DC current flow through the electrodes, to

avoid electrolysis and irreversible nerve damage. Consequently, using

~ ipo la r transistors in the input stage would have required placing two

protection stages before it for safety reasons, since Bipolar transistors

require large input bias current for their operation that can be hundreds

of nA (if special compensation techniques are not used to reduce such

bias currents). In a multi-channel FES application, these protection

stages would occupy a large area since they would have to be

implemented using discrete components due to the time constants

involved, and the circuits placed to reduce the biasing currents would

also add unnecessary extra noise.

Instead of Bipolar transistors, in this design I used a CMOS-based

input stage to achieve low noise. Since the input bias current of a MOS

transistor is in the order of fA, only one protection stage is needed, since

the second one is the input stage of the preamplifier itself.

A classical DC protection circuit is shown in Figure 2.1.

Cuff Electrode

\ with CMOS

\ b Input Stage

\ &, 4- voltage Reference

Figure 2.1 : Classical DC protection circuit

The two capacitors CB and the two resistors RB form two high-pass filters.

These filters have to be matched in order not to degrade the good CMRR

of the preamplifier. Selecting resistor R, much higher than resistors RB

increases the resistive pathway to "ground" for common mode signals,

reducing the mismatches between the two resistors RB of the high-pass

filters (the CMRR is still degraded by mismatches in the capacitors C,).

The voltage reference (also commonly represented as V,,,,), which needs

to be generated in the implant and has a value somewhere between the

power supplies, is usually connected to the "ground" wire of the cuff

electrode, which provides shielding for recording purposes. Typical

values for the components in Figure 2.1 are: CB = 33 nF, RB = 22 kR, and

Rs = 10 MR. The 22 kR resistor and 33 nF capacitor allow rapid recovery

after a blanking period following a stimulation pulse. In the frequency

domain this corresponds to a roll-off frequency of the high-pass filter at

around 220 Hz, which is out of the recording band of interest. Capacitor

C, is traditionally placed to reduce RF noise pickup by shunting the

inputs. A typical value for this capacitor is 1 nF. The main disadvantage

of this DC protection stage for a multi-channel FES application is the

fact that most of the components that form it have to be external,

therefore occupying a large area.

In this project instead, I solved the DC protection circuit by providing

the voltage reference through a high value resistor in parallel with a

capacitor. Figure 2.2 shows the configuration.

RP Reference

Figure 2.2: Proposed DC protection circuit

In case of a semiconductor failure in the CMOS input stage of the

preamplifier, the DC current will flow through the high value resistor Rp,

which is dimensioned according to safety standards (maximum DC

current allowed through the electrodes). Capacitor Cp shunts the high

value resistor in the recording band of interest, which minimizes noise

pickup. The beauty of this DC protection circuit is that it is common to

all recording channels in a multi-channel FES device, and does not

degrade the CMRR per se, since it uses the voltage reference which is a

common mode signal for the circuit. The values of Rp and Cp vary

depending on the voltage reference and the acceptable maximum DC

current, but they are usually in the range of a few MR and nF

respectively.

It is worth pointing out that this DC protection circuit proposed could

have not be implemented with a Bipolar-based input stage since, even

with biasing reducing schemes, there would always be a residual DC

current that would have to flow somewhere, in this case through the

electrode. This residual current can still be up to a few tens of nA, which

would polarize the tissue-electrode interface. This certainly would be a

problem in a closed-loop FES device where sensing has to happen

between stimuli, because such residual current would cause a transitory

in the recording that changes with time while the tissue-electrode

capacitance discharges.

Now that the DC protection circuit and the input stage of the

preamplifier have been selected, the next section discusses different

configurations analyzed for the preamplifier before selecting the most

appropriate for the particular application.

2.2 Selection of the preamplifier configuration

There are two different approaches for the design of an

instrumentation amplifier: resistive and current feedback. Among the

resistive feedback instrumentation amplifiers, the most commonly used

is the "classical" instrumentation amplifier based on three operational

amplifiers. Figure 2.3 shows such configuration.

1 Reference

Figure 2.3: Classical 'resistor' feedback instrumentation amplifier based on three operational amplifiers

If well designed, this instrumentation amplifier can reach a CMRR

higher than 90 dB, which is acceptable for this application. Also, low-

noise can be achieved if the two input operational amplifiers are designed

so. However, the major drawback of this choice is the fact that it utilizes

three operational amplifiers driving several small-value resistors if full

integration is required. Each operational amplifier has to be

compensated individually, adding unnecessary power consumption to

the circuit, hence being not suitable for the present application.

Now, in the case of current feedback instrumentation amplifiers, there

is a subdivision in two categories: direct and indirect current feedback.

An example of the first type is shown in Figure 2.4, which was

implemented as part of a rate-adaptive pacemaker [Arnaud et al. 19981.

Figure 2.4: 'Direct current' feedback instrumentation amplifier (adapted from [Arnaud et al. 19981)

In this configuration, the output voltage Vom is fed back to the

sources of the input transistors M1 through transistors M2 (integrator R,-

C, is used to compensate offset). It can be seen that if n g,,-,, Rs << 2 and n

g,,-,, R G >> 2, the instrumentation amplifier has a band-pass characteristic

with a gain equal to RG/Rs. Although this configuration is suitable for

low-power and low-noise applications if some external components are

used, it presents a major drawback: the gain from the feedback pair M2 to

the output V,,, is equal to Rs/RG, which is the inverse of the gain from

the input transistors M,. This means that if, for example, the total offset

plus signal at the input of the instrumentation amplifier is 10 mV and

the gain is set to be 20, the misbalance needed between transistors M2 to

compensate the offset is 200 mV. These large misbalances will reduce the

CMRR of the instrumentation amplifier if the input transistors get out of

their biasing region, since V,, must be always V,,,, greater than VF for

the circuit to behave correctly (near weak inversion VDSSAT2 is actually

around 200 mV). Consequently, the direct current feedback approach is

not suitable for the present application.

Finally, in the indirect current feedback approach (also known as the

differential difference amplifier "DDA" approach) [Huijsing 19761-

[Sackinger and Guggenbuhl 19871, the output voltage is not fed back

directly to the input of the amplifier but to the input of a second input

stage. The output currents of these two input stages are compared and

fed back to a loop amplifier. Figure 2.5 shows a block diagram of this

configuration.

voltage + +, Reference

Figure 2.5: Block diagram of an 'indirect current' feedback instrumentation amplifier

In such figure, transconductance stage T1 converts the input voltage

into a current il = V,, and the second transconductance stage T2 does

the same with the attenuated output voltage. Loop amplifier A with high

gain will force i, - i2 = 0, and therefore the overall transfer function

becomes

Generally, the ratio of the two transconductances is chosen equal to 1

and the gain is set by the ratio of the resistors. The advantage of this is

that the absolute errors in the transconductances are not important, as

long as they are well matched and their ratio remains constant. Finally,

it is worth pointing out that in this approach the CMRR only depends on

the input stage TI.

Figure 2.6 shows the actual preamplifier configuration implemented

based on the indirect current feedback approach (transistors M1 and M2

were chosen equal for the reason mentioned in the last paragraph).

Vnn +

Figure 2.6: Preamplifier configuration based on a differential difference amplifier

In this case, the MI and M2 differential pairs implement the two

transcoductance elements. The current sources M 3 of these differential

pairs are implemented using the cascode technique [Gregorian and

Temes 19861. This provides good matching of the two input stages, a

crucial factor in the performance of a DDA. On the other hand, the use of

cascode current sources added a PMOS threshold voltage VT to the

minimum supply voltage VDD needed for operation. In this case, however,

the supply voltage VDD was not a limiting factor.

The differential current generated by transistors M1 - M2 is converted

into a single-ended current by the current mirror M4. Transistor M5 is

part of a second stage that provides further gain to the loop amplifier (in

this case the loop amplifier is actually the first and the second amplifying

stages themselves). The second stage could have been transistors M5 and

M3g done, but this proved not to be sufficient and CM1 and RMl were

therefore introduced for frequency compensation [Gray and Meyer 19821.

Finally, the equivalent Darlington PNP transistor M6-Q 1 provides very

low output impedance while drawing no current from the second stage

[Alvarez 19931. In this way, the preamplifier was designed to have

negligible systematic offset independently of variations in the electrical

characteristics of the fabrication process. This factor is also crucial for

the successful performance of a DDA.

The remaining components of the preamplifier will be described in the

next section, where the actual design is disclosed.

2.3 Preamplifier design

I started the design by analyzing the noise figure of the complete

circuit. Before presenting such expression, it is useful to remember that

a preamplifier, followed by a cascade of two band-pass amplifiers,

compose the band-pass amplifying circuit. Each of the band-pass

amplifiers is further composed of a high-pass filter and a non-inverting,

low-pass amplifier. Figure 2.7 presents the individual building blocks

considered in the noise evaluation.

Figure 2.7: Individual building blocks of the band-pass amplifying circuit considered in the noise evaluation

The equivalent input noise Si has the expression shown in equation

2.2.

The factors involved in such expression are the following:

S , represents the noise contribution of an MI (equal to M2) input

transistor (refer to Figure 2.6). These four transistors M1 - M2

contribute to the input noise directly. The preamplifier noise is

dominated by this factor.

SR2 represents the noise contribution of resistance R2 that also

passes directly to the input.

SM, represents the noise contribution of an M4 current mirror

transistor. The contribution of this load is reduced by the square of

the ratio of their transconductance to that of the input transistors

MI.

The noise of the equivalent resistor RHPF of the high-pass filter is

also reduced by two factors. First of all is reduced by the closed-

loop gain of the preamplifier (AcDDA), since this stage is previous to

the filter one, and secondly it decreases with frequency as stated in

equation 2.2. This decrease is logical since, beyond the high-pass

filter pole (fHpF), capacitor CHPF becomes a "short-circuit",

consequently placing the equivalent resistor RHpF in parallel with

resistor R1 + R2, being R, + R2 << RHPF.

The last factor is the noise added by the first of the non-inverting,

low-pass amplifiers (AMP). This noise is also reduced by the closed-

loop gain AcDDA and should be designed to be negligible.

After identifying the noise factors, I started the design by considering

only thermal noise components due to the range of frequencies involved.

A quick hand calculation gives that in order to achieve a noise level of

approximately 1 pV,, in a 10 kHz bandwidth, the equivalent input noise

level should be a = 10 nv/&. Since the input transistors of the

preamplifier dominate the noise, the required level of MOSFET

transconductance could only be achieved near the weak inversion region.

The selection of the MOSFET type for the input transistors was

studied in detail. It is well known that in strong inversion the flicker

noise of a PMOS transistor is lower than that of an NMOS one. Though,

recent studies showed that flicker noise in PMOS transistors significantly

increase when the device moves from strong inversion toward weak

inversion [Binkley et al. 19981. Still others have reported the flicker noise

going down [Binkley 19991, indicating that it arises from a mechanism

that is strongly affected by details of device fabrication. The very severe

increase in flicker noise was not observed in the technology used in this

project. Therefore, PMOS transistors were selected for the input stage.

By implementing in MATLAB@ the transfer function of the band-pass

amplifying circuit and the noise equation giving by 2.2, thermal noise

levels for each factor were assigned. Here, the best compromise between

total equivalent input noise, power consumption, full integration and

area of the input transistors was chosen. This led to the following typical

values:

& = 5.5 nv/& (chosen according to a reasonable

transconductance value).

& = 5.0 nv/& (chosen according to a reasonable integrated

resistor and power consumption).

& = 11.0 nv/& (chosen based on a ratio equal to 3 in order

to minimize the effect of the load M4 in the noise figure while

obtaining a reasonable size for this transistor).

,/c = 325.6 nv/& (chosen based on a maximum integrated

capacitor CHPF of 30 pF and an arbitrarily preamplifier gain AcDDA equal

These selections of thermal noise levels, plus the contribution of the

lower flicker noise6, gave a simulated total typical equivalent input noise

of 0.96 pV,, @ 37 "C for the worst-case recording band (the noise is

almost the same @ ambient temperature). This first approximation to the

equivalent input noise value expected allowed me to size the components

Flicker noise models were provided by the foundry.

present in Figure 2.6. The noise worst-case was later simulated by

~ s ~ i c e @ to confirm it met the requirement of 1.50 pV,, maximum.

The next sections detail the preamplifier design to the transistor level.

2.3.1 Input transistors MI - M2

The noise level dS, = 5.5 n v/& assigned to transistors M 1, together

with the thermal noise equation near the weak inversion

region dS, = ,/Zn , determined a minimum transconductance G,

equal to 393 pa-'. An IC (refer to the definition in section 1.4) equal to

0.64 was selected based on a reasonable input transistor size. This value

of IC resulted in a transistor biased in between the moderate and weak

inversion regions. From this value, a (g,,-,/I,), equal to 18.33 V-' was

obtained, which resulted in a minimum source-drain current of around

2 1.44 pA for the transconductance level needed. In this case, sufficient

voltage gain and low flicker noise were achieved using a minimum length

transistor (2 pm), which implied a width of 1800 pm. The

transconductance finally achieved was 420 pa-' (the source-drain

current was adjusted to 22.91 pA).

2.3.2 Current source transistors M3a - M3f

The sizing of these transistors was based on the CMRR requirement.

In section 1.1, the requirement specified a total CMRR higher than 90 dB

@ 250 Hz. A s it is known, two types of CMRRs are present in any

amplifier, namely the systematic and random CMRR. The former

exclusively depends on design parameters, whereas the later one

depends on mismatches between transistors. A good design must

guarantee that the systematic component is negligible with respect to the

random one. Based on the requirement of 90 dB, a 110 dB systematic

CMRR was derived as a requirement, which implies an order of

magnitude higher systematic component.

Equations 2.3.a and 2.3.b were used for the sizing of transistors M 3 a

- M3f. The former equation presents the expression of the preamplifier

systematic CMRR [Gregorian and Temes 19861, where rO3 and r,,

represent the output impedance of the cascode current source M3e - M3f

and the input transistor M1 respectively. The later equation presents the

output impedance rO3 in terms of parameters of transistor M3f, assuming

that transistor M3e is designed identical to transistor M3f.

Now, having sized transistor M1 and using the fact that the ratio

was chosen equal to 3 for noise reduction, an output impedance rO3 equal

to 15.4 MR was determined from equation 2.3.a. Since transistors M3a -

M3f form current sources they have to be biased near the strong

inversion region. The (&/I,),, was chosen equal to 6 V-l, which together

with a source-drain current equal to 45.82 pA (twice the current through

the input transistors MI), determined a transconductance &,, equal to

275 pD1. Substituting this value, and the 15.4 MR found above, in

equation 2.3.b resulted in an output impedance r,,, equal to 236.6 kR.

With this value, and using the expression that relates the Early Voltage,

the transistor length and the source-drain current, a minimum length of

5.4 pm was determined for transistor M3f. The transistor length was

finally selected equal to 6 pm, which resulted in a transistor width of 360

pm. Transistors M3f, M3e, M3d and M3c were implemented as four equal

transistors in parallel of 90 pm in width, whereas transistors M3b and

M3a were each implemented as one of these transistors.

2.3.3 Transistors M4 of the active load

As mentioned before, for noise reduction, the transconductance of

these transistors was chosen one-third that of the input transistors MI.

The current through them is twice the one through transistors MI, since

transistors M2 contribute the same amount. Therefore, the (&/I& is

defined and equal to 3.05 V-I (deep in the strong inversion region). From

this value, the W/L was obtained as explained in section 1.4. In order to

improve the output impedance of the active load and minimize flicker

noise a length of 20 pm was chosen, determining a width of 95 pm.

2.3.4 Output stage

The output stage was designed based on the excursion expected at

the preamplifier output. Amplified EMG signals caused by mismatches in

the nerve cuff electrode, as well as preamplifier random offset, were

taken into account. The estimated total maximum voltage at the input of

the preamplifier was 10 mV,,&. This translated in a maximum output

current needed of (10 mV x 24)/ (R, + R2)min.

From the noise level assigned in section 2.3, R, was implemented

using one square of n-well resistance, which represents a minimum

resistor of 750 Q. Consequently, R1 was implemented using 23 squares of

n-well resistance, resulting in a (R, + R,)min of 18 kS1. Using the formula in

the last paragraph, this gives a maximum output current of around

13.33 pA.

In order to ensure proper operation of the output stage, independently

of the output current sinked/sourced, the source-drain current of

transistor M3h was selected ten times higher than the maximum output

current found above7. Transistor M3h was consequently implemented as

eleven transistors M 3 a in parallel, which together with the Early Voltage

effect, determined a current close to the 133 pA desired.

From this total output stage current, 2 1 pA was determined as the

minimum source-drain current allowed through transistor M6 in order

for the base current of transistor Q1 to be negligible with respect to it.

With this value in mind, and assuming a VBEl of 0.7 V, a maximum

resistor RD of 14.4 kR was determined and implemented using 8 strips of

p+ sheet resistance, each one of 43.6 pm in length and 3.2 pm wide (this

is equivalent to 150 squares). This resulted in a minimum source-drain

current through transistor M6 of approximately 48.6 pA, which is more

than two times higher than the 21 pA minimum calculated before.

The size of transistor M6 was calculated as a trade-off between size

and maximum source-gate voltage. The size of such transistor affects the

parasitic capacitance C2 (see Figure 2.6), which directly influences the

frequency response of the preamplifier. On the other hand, the source-

gate voltage of transistor M6 directly affects the drain-source voltage of

transistor M5, which has to be always in the saturated region for the

second stage to work properly. Based on these two constraints, the

(g,.,-,/ID), was chosen equal to 6 V-', which together with a typical source-

drain current of 58.33 pA, led to a W/L of 77. Minimum length was

selected, which led to a width of 154 pm. Finally, transistor Q1 was

selected minimum, with an emitter area of 6.4 x 9.6 pm2.

7 ~ h i s is a conservative approach. The output stage would also work with less source- drain current through transistor M3h, which was implemented in the second generation.

2.3.5 Second stage

In order to design the second stage, three constraints had to be taken

into account:

i) To have a reasonable phase margin of 60" in an amplifier, the ratio

between the non-dominant pole and the unity gain frequency is generally

chosen equal to 2.2.

ii) Due to the fact that transistors M4 resulted deep in strong

inversion, (&/ID), had to be chosen equal to (&/ID), to minimize the

systematic offset [Gray and Meyer 19821.

iii) To place the zero in the left half-plane, the nulling resistor RMl has

to be chosen equal or greater than 1 /&, [Gray and Meyer 19821.

These first, second and third constraints translate into conditions 2.4,

2.5 and 2.6 respectively.

C, - 2.2 (c, + c , ) y ' gm~

In equation 2.4, parasitic capacitor C1 actually depends on the size of

transistor M5, which makes the equation non-linear. By using these

three equations, also keeping in mind reasonable sizes for CM1 and RMl,

as well as low drain-source current for transistor M5, I was able to

determine all the components of the second stage. Capacitor CM1 resulted

in a value of 4 pF, and was implemented as a polyl-poly2 capacitor of 80

pm x 80 pm. Resistor RMl was chosen equal to RD, whereas transistor M5

was selected with a width of 43 pm and a length of 12 pm. Usually the

length of transistor M5 is chosen equal to that of transistor M4 [Gray and

Meyer 19821. This was not needed in this case.

The drain-source current of transistor M5 resulted equal to three

times IBIAs (see Figure 2.6). Consequently, transistor M3g was

implemented as three transistors M3a in parallel.

2.3.6 PSRR improvement

As shown by Sackinger et al. [Sackinger et al. 199 I], there is a

constraint for the simultaneous improvement of the CMRR and PSRR of

the simple operational amplifier (the same applies to a DDA). Basically,

the common-mode gain, the gain from the positive power supply V,, and

the one from the negative power supply (in this case ground) sum to

unity. In practice, this implies that at least one of the gains from the

power supplies is in the order of magnitude of unity. Ripple or other

parasitic signals at this supply terminal are, at mid-frequencies, fully

transferred to the output through the integrator capacitor (in this case

CMl).

In a single-ended output amplifier, the constraint can be easily

relaxed by adding a supplementary input terminal to the amplifier

circuit, with unity gain to the output. In this way, the remaining three

parasitic gains mentioned in the last paragraph add to zero, which is the

necessary condition that these gains become zero individually. If such

supplementary input terminal is connected to a "quiet" voltage reference,

the PSRR of the amplifier is consequently improved without altering its

frequency response.

In the case of the DDA shown in Figure 2.6, the extra capacitor CM1

connected between the gates of transistors M4 and VBIA, implements such

concept for PSRR improvement. It is worth mentioning that the classical

"cascode" remedy to improve PSRR is just a special realization of the

concept presented in this section and that, as it was shown in [Sackinger

et al. 19911, this alternative gives better results.

2.3.7 Determination of the voltage reference VBIAs and minimum VDD

To guarantee the correct biasing of all the branches in the

preamplifier, conditions 2.7 and 2.8 shall be met at all times.

Worst-cases for the source-gate and saturation voltages determined a

voltage reference V,,,, between 1.88 V and VDD - 2.68 V. This implied that

VDD had to be chosen equal or higher than 4.56 V. I selected VDD equal to

the standard 5 V. Consequently, the voltage reference was selected equal

to 2.12 V, which is close to the mean of the two limits (this selection

accommodates the maximum output excursion of 0.24 V, see section

2.3.4).

2.3.8 Generation of the current ZBIAs

In order to generate the biasing current IBIAS, a self-starting, power-

supply independent, classical cascode CMOS current source [Vittoz and

Fellrath 19771 was implemented. Figure 2.8 shows the schematic of such

current source, denominated in this project the "high current reference".

Figure 2.8: Generation of the current IBIAS

It can be easily shown that if transistors M1 and M2 are biased in the

weak inversion region, the current through resistor RREF meets equation

2.9, where factors I,, and IO2 depend on the transistor sizes and process

parameters.

The circuit is self-starting, provided transistor M1 is wider than

transistor M2. In this case I implemented transistor M 1 as two

transistors M2 in parallel, which translates in an Iol/Io2 equal to 2. The

dependence of the current on UT usually turns out to be an advantage

since it compensates the temperature dependence of the

transconductance in weak inversion.

The sizes of the transistors present in the high current reference are

summarized in Table 2.1.

Table 2.1: Transistor sizes of the high current reference I I I

Using ~ s ~ i c e @ simulation to account for Early Voltage effects in the

current generation, I,,,, was adjusted close to the desired value of 1 1.45

ju4 (see section 2.3.2) using a standard resistor RREF equal to 12 kR.

The simulation, layout and test of the preamplifier will be presented

later on. The next chapter presents the design of the two identical high-

pass filters (see Figure 2.7).

MS, M l O 10 18 x 6

Chapter 3

High-Pass Filter

This chapter presents the design of the high-pass filter. Two of these

high-pass filters (see Figure 2.7) set the low frequency pole of the

recording band specified in section 1.1. Full integration and low power

consumption were considered as restrictions in the design.

3.1 Selection of the high-pass filter configuration

A low frequency pole of 850 Hz f 15% was specified in section 1.1.

Assuming a reasonable maximum integrated capacitor of 30 pF, I would

need a resistor of around 6.24 MR to implement such pole. A resistor of

that value cannot be integrated using a resistive layer since it would

occupy an unreasonable large area. Instead, I implemented the high-pass

filter using a transconductance that emulates the high-value resistor.

Figure 3.1 shows the schematic of the high-pass filter implemented.

p D

CHPF Mla Mlb

VBIAS I I

M2a M2b

Figure 3.1: High-pass filter implemented

The next section details the high-pass filter design to the transistor

level.

3.2 High-pass filter design

The design started by selecting a maximum reasonable capacitor CwF

in the order of 30 pF. I implemented such capacitor as four polyl-poly2

capacitors in parallel of 103.6 pm x 105.6 pm. This gives a typical total

capacitor of around 27.57 pF. In order to set the pole at 850 Hz with this

capacitor, the transconductance level needed results equal to 147 nR-l.

To achieve such small transconductance, the biasing current IBrASl was

chosen equal to 22 nA, which implies only 11 nA per input transistor M1

(see Figure 3.1). An IC of 1 was selected for these input transistors, to

have a reasonable linear range, which led to a minimum width of 4 pm

and a length of 16 pm.

A similar approach was taken for the sizing of the load transistors M2.

Since offset was not a tight requirement for these high-pass filters (see

section 1.3), these transistors were also biased in the moderate inversion

region, to allow a reasonable size. A (&/I& equal to 13 V-I was chosen,

which led to a minimum width of 4 pm and a length of 126 pm.

The current IBIASl was generated using a similar current source as the

one described in section 2.3.8. Figure 3.2 shows the schematic of such

current source, denominated in this project the "low current reference".

Figure 3.2: Generation of the current I B I A ~ ~

The sizes of the transistors present in the low current reference are

summarized in Table 3.1.

Table 3.1: Transistor sizes of the low current reference I I

Resistor RREFl was selected equal to 470 kR, which determined a

simulated typical current IBIASl equal to 22.04 nA.

The simulation, layout and test of the high-pass filter will be

presented later on. The next chapter presents the design of the non-

inverting, low-pass amplifier (see Figure 2.7).

Chapter 4

Non-inverting, Low-pass Amplifier

This chapter presents the design of the non-inverting, low-pass

amplifier. Two of these amplifiers provide the remaining gain needed and

set the high frequency pole of the recording band as specified in section

1.1. Full integration, low power and low input capacitance were

considered as restrictions in the design.

4.1 Selection of the non-inverting, low-pass amplifier

configuration

The simplest way to implement the necessary extra gain while

providing the low-pass filter characteristic needed was to take advantage

of the dominant pole in a resistor fed-back amplifier. It is well known

that the closed-loop gain @ DC A,,,, the dominant pole paMP and the

unity-gain frequency f,,, of such amplifier meet equation 4.1 as a first-

order approximation.

In this case, the typical paMPwas set equal to the high frequency pole

of 9 kHz (see section 1. I), whereas the minimum gain needed AcAMP @ 3

kHz was determined from condition 4.2.

In order to account for the drop in the gain @ 3 kHz, I selected the

closed-loop gain @ DC A,,,, equal to 38. This value, together with the 9

kHz dominant pole p,,,, determined a unity-gain frequency fMMp equal to

342 kHz.

Figure 4.1 shows the schematic of the amplifier implemented. This is

a Miller-type amplifier with a Darlington output stage that provides low-

output impedance. The Darlington transistors Q6 and Q8 obtain their

biasing current from transistors M7 and M9 respectively, which also

carry signal current, making the amplifier a class AB. This saves power

consumption since it avoids the need of extra transistors to provide the

biasing of the Darlington ones. Resistors Rj and % provide the necessary

feedback for closed-loop operation.

Figure 4.1 : Non-inverting, low-pass amplifier implemented

The next section details the design of the non-inverting, low-pass

amplifier to the transistor level.

4.2 Non-inverting, lo w-pass amp lifier design

Due to its position in the signal processing path (see Figure 2.7), this

amplifier neither had low noise or offset as a main requirement. The

main two characteristics needed in it were low input capacitance

(compared to the value of CHPF) and full integration. The former was a

critical requirement since this amplifier follows the high-pass filter

described in chapter 3. In this way, the low frequency pole determined by

the high-pass filter is not affected by the input capacitance of the non-

inverting, low-pass amplifier. Finally, full integration implied a high

output current level. Consequently, biasing current IBlAS2 was generated

from the high current reference (see section 2.3.8).

4.2.1 Input transistors MI and biasing transistors M3

Based on the statement of the last paragraph, the input transistors

M 1 were biased in the moderate inversion region with a (g,,,/ID), equal to

15 V-l. To have a small transistor size, its source-drain current was

chosen equal to half the current through resistor RREF (see section 2.3.8),

which is approximately 0.93 pA. This led to a W/L equal to 14.4. A length

of 5 pm and a width of 72 pm were selected for M 1. Transistor M 3 came

from the high current reference, with a width of 115 pm and a length of

20 pm.

4.2.2 Transistors M2 of the active load

Since neither noise nor offset were main requirements for this

amplifier, transistors M2 were biased at the start of the strong inversion

region with a equal to 8 V-'. This value, together with a typical

drain-source current of 0.93 pA, led to a W/L equal to 1.44. A length of

12 pm and a width of 17 pm were selected, which gives a ratio close to

1.44.

4.2.3 Second stage

Generally, the (&/ID),is chosen equal to the (&/ID), in order to

minimize the systematic component of the total input offset [Gray and

Meyer 19821. This constraint was previously used in section 2.3.5, for the

design of the second stage of the preamplifier. Hence, (&/ID), resulted

equal to 8 V".

The second constraint in the design of the second stage was the

achievement of a reasonable phase margin necessary for closed-loop

operation. Based on several ~ s ~ i c e " iterations performed to minimize

power consumption, it was sufficient to select the transconductance of

transistor M4 equal to approximately four times that of the input

transistors M 18. This, together with the value of (&/ID), equal to 8 V-', led

to a W/L close to 5. A length of 4 pm and a width of 20 pm were selected

for such transistor. It is worth pointing out that the need for a base

current in transistor Q6 created a positive typical systematic offset of 0.2

mV. Fortunately, this systematic offset had opposite sign with respect to

the -1.8 mV of the high-pass filter, therefore reducing the equivalent

total input offset amplified by the circuit being disclosed in this chapter.

Transistor M 5 was consequently implemented as four transistors M3

in parallel, to provide the necessary biasing current to transistor M4.

Finally, capacitor CM2 was estimated from the unity-gain frequency

fa,, needed of 342 kHz using the formula CM2 = &,/ (2 71: faMP). This

This was possible because the amplifier is being used with a known closed-loop fmed gain of 38, which eases the requirements with respect to phase margin.

resulted in a capacitor CMz equal to 6.5 pF. Based on ~ s ~ i c e @ simulations

of the complete band-pass amplifying circuit it was later adjusted to 10

pF9.

4.2.4 Output stage

As in the output stage of the preamplifier (see section 2.3.4), the

output stage of the non-inverting, low-pass amplifier was designed based

on the excursion expected. The feedback resistors in this case were

selected keeping in mind the trade-off between die area and power

consumption. I found that the maximum reasonable resistor was equal

to 150 squares of n-well resistance. Consequently, resistor R4 resulted

equal to 150 squares138 r 4 squares, whereas resistor R3 resulted equal

to 37 x 4 squares = 148 squares. In the technology used, the n-well layer

has a minimum resistivity of 0.75 kQ/O, which gives a resistor (R3 + R4)min

equal to 114 kQ.

Once the resistors were selected, the maximum output voltage was

estimated. Of the two non-inverting, low-pass amplifiers present in

Figure 2.7, the last one in the cascade provides the final gain of the

band-pass amplifying circuit. Hence, its maximum output voltage can be

estimated as 24 x (38)2 x 15 pVpeak z 0.52 Vpeak. Adding amplified noise

and offset to this value gives a total estimated output voltage of 0.57

V,,,. This value, together with the minimum resistor of 114 kR, gives a

maximum output current of 5 pA. Consequently, the current through

transistor M9 was selected higher than 50 pA. This was achieved by

implementing transistor M9 as seven transistors M4 in parallel.

With these capacitor values, capacitor C M ~ placed to increase the PSRR slightly affects the frequency response.

Transistor M7 of the Darlington output stage was dimensioned taking

into account the base current of transistor Q8. In order to minimize the

effect of such current, the minimum drain-source current of transistor

M7 was selected equal to (10 IDs9)/Pmin = 10.43 pA1O. Hence, transistor M7

was implemented as two transistors M4 in parallel, which gives a current

of 14.91 pA.

Finally, transistors Q6 and Q8 were selected minimum, with an

emitter area of 6.4 x 9.6 pm2.

This chapter concludes the presentation of the design of the first

generation of the band-pass amplifying circuit. The next chapter presents

the ~ s ~ i c e @ simulations performed as well as the layout of the circuit.

Pmin is the minimum current gain factor of the bipolar transistor, which for the present technology is equal to 50.

Chapter 5

~ s ~ i c e " Simulations and Layout of the Band-Pass

Amplifying Circuit - First Generation

This chapter presents the Hspicea simulations and layout of the first

generation of the band-pass amplifying circuit. Minor adjustments to the

transistor sizes were performed to allow implementation in the

technology used. These final transistor sizes are presented together with

the layout.

5.1 Simu Zations

Hspicea simulations using fast, typical and slow models of the

technology used were performed immediately after the design of each

building block to confirm performance. After all the individual building

blocks were simulated, the cascade (see Figure 2.7) was finally simulated

to verify that the requirements set in section 1.1 were achieved.

Following this verification, the circuit was laid out, extracted and re-

simulated to confirm that the extra parasitic capacitances did not affect

the behavior of the circuit.

Table 5.1 and Figure 5.1 summarize the final typical simulation

results of the extracted circuit, including the pads.

Table 5.1: spice@ typical simulation results of the band-pass amplifying extracted circuit (first generation)

Gain @, 3 kHz Low-Frequency Pole High-Frequency Pole

Equivalent Input Noise Power Consumption

Systematic CMRR @ 250 Hz

PSRR @, 3 kHz

l 1 This specification was derived from the one in section 1.1 (see section 2.3.2 for the explanation).

1 Systematic Output Offset I NA

Specified > 87 dB

850 Hz f 15% 9 kHz f 15% < 1.50 pVrms

NA

110 dB11

NA -60.8 m V

Simulated 87.7 dB 846 Hz

9020 Hz 1.16 pVrms 2.13 m W

114.3 dB

67.7 dB

As it can be seen, all the requirements were met with very little power

consumption. In order to be able to compare this first generation with

other recently published amplifiers for ENG recording using nerve cuff

electrodes, we can use the "Noise Efficiency Factor" (NEF) concept

introduced by Steyaert et al. in 1987 [Steyaert et al. 19871. The NEF

factor is given by equation 5.1. It basically describes how many times the

noise of a system (V,, ,), with the same current drain (I,,,) and

bandwidth (BW), is higher compared to an ideal Bipolar transistor with

only thermal noise and no base resistance.

The NEF of this first generation of the band-pass amplifying circuit is

equal to 10. This value is two times smaller than the 20 NEF of the

implantable, single-channel, cuff-recording system fabricated using

discrete components and presented by Donaldson et al. in 2000

[Donaldson et al. 20001. Furthermore, this first generation of the band-

pass amplifying circuit has similar performance as the best one

presented in [Steyaert et al. 19871, which was implemented using Bipolar

discrete components.

With respect to the PSRR, there was no initial specification. The PSRR

@ 3 kHz finally achieved by simulation is almost 5 dB higher than the

lowest one presented by the AMPOI@ instrumentation amplifier from

Analog Devices Inc. One of such low noise, precision instrumentation

amplifiers was used as the preamplifier by Donaldson et al. in their

design [Donaldson et al. 20001. Hence, the PSRR value achieved is more

than acceptable for the present applicationl2.

Finally, the simulated systematic output offset of -60.8 mV translates

into an equivalent offset at the input of the second non-inverting, low-

pass amplifier of -60.8 mV/38 = -1.6 mV, which confirms what was early

mentioned in section 4.2.3.

The next sections detail the implementation of the layout as well as

showing pictures of the first generation fabricated.

5.2 Layout

5.2.1 Preamplifier

Each of the input transistors MI and M2 (see Figure 2.6) were

implemented as 36 transistors in parallel of width 50 pm and length 2

pm. A common-centroid, cross-coupled structure was used to arrange

the transistors in parallel. This improves the matching between the input

transistors. The rest of the transistors were implemented as single units.

Wide transistors were implemented using "S" shaped configurations in

order to reduce die area. Dummy transistors were drawn together with

transistors M3e and M3f. This improves the matching between the

current through transistors MI and M2, a crucial factor for the

successful performance of the preamplifier. Table 5.2 shows the final

sizes drawn.

l2 It is worth pointing out that the PSRR was incremented more than 12 dB by the simple technique described in section 2.3.6.

Table 5.2: Final sizes drawn for the preamplifier transistors I I I

5.2.2 High current reference

Transistors M1 to M4 (see Figure 2.8) were implemented as the

parallel of unit transistors with a width of 36.8 pm and a length of 4 pm.

An interdigitized layout was used to arrange the transistors in parallel.

Dummy transistors were drawn next to transistor M5b and to transistors

M 13 and M 14, to improve matching of the IBIAS2 currents. Table 5.3 shows

the final sizes drawn.

Q1 6.4 x 9.6 pm2 emitter area

Table 5.3: Final sizes drawn for the high current reference transistors

5.2.3 High-pass filter

The transistors of the high-pass filter (see Figure 3.1) were laid out as

single units. Transistors M2 were laid out using an "S" shaped

configuration to reduce die area. Dummy transistors were placed in the

current mirror formed by them to improve matching. Table 5.4 shows the

M8, M l O

final sizes drawn. , Table 5.4: Fin

w (elm)

36.8 x 20

36.8 x 10

M l

M 2 - M 4

L ( P I 4

4

10

Capacitor C,,, was implemented as four capacitors in parallel, in a

common-centroid configuration.

5.2.4 Low current reference

The transistors of the low current reference were laid out exactly as

dimensioned in section 3.2. Dummy transistors were placed next to

transistors M5b and M6b to improve matching of the I,,,,, currents.

1 8 x 6

1 sizes drawn for the high-pass filter transistors

L (pm) w (Pd

5.2.5 Nun-in verting, low-pass amplifier

The transistors of the non-inverting, low-pass amplifier were laid out

as single units. Table 5.5 shows the final sizes drawn.

Table 5.5: Final sizes drawn for the transistors of the non-inverting, low-pass amplifier

5.2.6 Layout photograph

Figures 5.2.a and 5.2.b show the layout and a photograph of the first

generation fabricated respectively. The layout was carried out using the

cadenceB design environment from S.F.U. The PFWR indicated in the

picture will be described in the next chapter.

I

Q6, QS

M7

M9

w (Crm) 72

17.2

115.2

20

115.2 x 4

M1

M2

M3

M4

M5

L (Crm)

5.2

12

20

4

20

6.4 x 9.6 ym2 emitter area

4

4

20 x 2

20 x 7

Figure 5.2.a: Layout of the first generation (die area 2.2 x 2.2 mm)

Figure 5.2.b: Photograph of the first generation

Chapter 6

Precision Full-Wave Rectifier

This chapter presents the design of the continuous-time PFWR.

Several configurations were studied and are presented, before selecting

the most appropriate for the present application. The circuit finally

selected and designed minimizes power consumption and area since it

requires no external components to achieve rectification. This makes the

circuit suitable for a high-density, low-power implantable medical device.

6.1 Selection of the con,guration

As explained in section 1.1, it is preferable to do analog rectification of

the band-passed, amplified signal. Therefore, the circuit to be designed

has to be in continuous time. It is desirable for this circuit to present

high input impedance, so it can be connected to the output of the band-

pass amplifying circuit without loading it.

A classical implementation of a high-impedance, continuous-time

PFWR is shown in Figure 6.1. Such circuit is based on the idea of using

operational amplifiers with diodes within the feedback path to provide

the necessary non-inverting gain for positive input signals and inverting

gain for negative ones.

Figure 6.1: Classical precision full-wave rectifier based on operational amplifiers

This classical circuit presents many drawbacks that prevent its use in a

multi-channel, low-power, closed-loop FES implantable device:

i) It presents distortion due to the fact that the diode Dl feedback

path becomes open circuit around the zero crossing, resulting in a

missing segment in the output waveform for a time interval td [Hayatleh

et al. 19951.

ii) When i) occurs, the input is not driven sufficiently strong to

achieve the slew rate of A l , and so A1 operates in the linear region,

typically resulting in a value of td about an order of magnitude higher.

Amplifier A 1 is consequently consuming unnecessary power.

iii) If resistors R were fully integrated, they would have to be large in

order to keep the power consumption low. This would occupy a large die

area.

iv) Two operational amplifiers are needed.

In prior art, two different circuits that overcame some of the

limitations mentioned above were disclosed by Kimura in 1994 [Kimura

19941 and by Arnaud et al. in 1998 [Arnaud et al. 19981. For example,

Figure 6.2 shows the second embodiment disclosed by Kimura.

Figure 6.2: Second embodiment disclosed by Kimura in U. S. patent no. 5,306,968

The circuit comprises a polarity judgment circuit C, a gain control

circuit 20, a first amplifier 2 1, and a second amplifier 22. The signal to

be rectified V,, is inputted to the polarity judgment circuit C and the first

amplifier 2 1. According to the output of C, the gain-control circuit 20

outputs two DC signals, namely VH and V,, which are provided to the

second amplifier 22. These DC signals control the gain of amplifier 22,

which outputs an amplified and rectified version VoUT of the input V,,.

Two main disadvantages of the embodiments disclosed by Kimura are

that several auxiliary DC voltages are needed to achieve rectification and

that the gain of the rectifier circuit is highly dependent on process

parameters.

Figure 6.3 shows the circuit disclosed by Arnaud et al. [Arnaud et al.

* Figure 6.3: Precision full-wave rectifier disclosed by Arnaud et al. [Arnaud et al. 19981

The idea is similar to the one proposed by Kimura. Here, the signal from

the polarity judgment circuit C (in this case a comparator) is used to

change the configuration of amplifier A from inverting amplifier to

follower and vice-versa according to the polarity of the input V,,, using

the switches 30 and the inverter I. A main disadvantage of this circuit,

that prevents implementation in a multi-channel, low-power FES device,

is that it requires two resistors R, which need to be external in order for

power consumption to be minimized. Another important disadvantage is

that the circuit does not present sufficiently high input impedance if

resistors R are integrated.

In this project I chose a different approach. Instead of switching the

configuration of an amplifier, I decided to switch the connection to the

inputs of an amplifier permanently connected as a voltage inverter,

according to the sign of the input signal with respect to the voltage

reference VBIAS. I based the voltage inverter amplifier on a DDA (see

section 2.2), which automatically provides high input impedance (its

inputs are the gates of CMOS transistors). Four analog switches,

controlled by the output of a comparator and its complementary signal,

are used in such connection scheme. With this approach, no external

components are needed and power consumption is kept at a minimum.

Figure 6.4 shows the schematic of the PFWR implemented in this project.

Figure 6.4: Precision full-wave rectifier implemented in this project

The circuit works in the following way: when the input signal VIN is

greater than the reference voltage VBIAS, the output 41 results in a low

logical level. This means transistors M2a and M 1 b are turned on,

whereas transistors M l a and M2b are turned off. Consequently, the

input signal VIN is connected to the inverting input of the first differential

pair 42 of the DDA, and the reference voltage VBIAS is connected to the

non-inverting input of such differential pair 42. On the other hand, VOLJT

and VBlAS are permanently connected to the inverting and non-inverting

inputs respectively of the second differential pair 43 of the DDA. Hence,

based on the DDA equation, VoUT results equal to VIN. When the input

signal VIN is lower than the voltage reference VBIAs, the symmetric

condition to the one described above happens, resulting in VouT equal to -

V,,. This proves that the output signal Vo,, is the positive rectified version

of the input VIN. Alternatively, if a negative rectified output is desired, the

inputs to the comparator C can be switched.

The next sections present the design of the different components

found in Figure 6.4.

6.2 Design of the voltage inverter DDA

I selected a basic CMOS DDA for the voltage inverter. Figure 6.5

shows such circuit.

Figure 6.5: Differential difference amplifier of the precision full-wave rectifier implemented

As explained in section 2.2, the current sources (transistors M3) of the

input transistors M 1 were also implemented using the cascode technique

[Gregorian and Temes 19861. This provides good matching between the

input transistors MI. The second stage, composed by transistors M4 and

M5, and by capacitor CM3, is the classical Miller integrator. This proved to

be enough for the stability of the DDA, since the input transistors M1

resulted of reasonable size. The DDA also proved to be able to drive the

pad capacitance without problem.

The next sections present the sizing of the transistors present in

Figure 6.5.

6.2.1 Input transistors MI and current source transistors M3

Using the typical simulated gain of 87.7 dB from Table 5.1, and the

maximum input signal of 15 pVp,, (see section 1. I), the maximum

rectifier input voltage resulted approximately equal to 0.36 V,,,. After

amplified noise and offset were added, the maximum rectifier input

voltage resulted equal to 0.4 Vpeak. Therefore, the input transistors M1

needed to be designed to handle this range without major distortion. This

was achieved by imposing equation 6.1 [Huang et al. 19931.

This equation translated in an IC equal to 19.79 (strong inversion). In

order to have a reasonable input transistor size, the current I,,, was

selected equal to I,,,,/2 (an extra branch was added in the high current

reference in order to bias this DDA). This selection resulted in a W/L

equal to 1.2. A length of 10 pm, which provides a reasonable gain, and a

width of 12 pm were selected.

As mentioned above, the biasing current of the DDA was generated in

the high current reference, which means transistors M 3 have a width of

1 15.2 pm and a length of 20 pm (see section 5.2.2).

6.2.2 Transistors M2 of the active load

Since the input to the PFWR is in the hundred of mV, noise was not a

major concern. Hence, I selected a (&/I,), equal to 4 V-', which is only

around 1.5 times less than (remember that in the preamplifier

this ratio was 6). This selection, together with a drain-source current

equal to I,,,,2, gives a W/L of 0.33. A length of 12 pm, to improve output

impedance, and a width of 4 pm were selected.

6.2.3 Second stage

Once again, two constraints were taken into account in the design of

this second stage. The first one is the fact that the (&/ID), had to be

chosen equal to the (&/ID), in order to minimize systematic offset [Gray

and Meyer 19821. The second requires that the unity-gain frequency of

all the amplifiers present in the rectifier be much higher than the

maximum frequency of operation in order to allow sufficient high-

frequency harmonics to be present within the output waveform so as not

to degrade the performance excessively [Hayatleh et al. 19951. In this

case it was enough to select a 300 kHz unity-gain frequency for the DDA.

This value, together with the transconductance value of transistor M 1,

determined a compensation capacitor CMJ equal to 2.9 pF. It was

implemented as a polyl-poly2 capacitor of 68 pm x 68 pm.

Transistor M4 was dimensioned using the same procedure as the one

in section 4.2.3, except that the transconductance of transistor M4 was

chosen five times that of the input transistors MI. This selection,

together with a defined (&/I& of 4 V1, gave a W/L equal to 1.33. The

length was chosen equal to that of transistor M2 [Gray and Meyer 19821,

which resulted in a width of 16 pm. Biasing transistor M5 was

implemented as four M 3 transistors in parallel.

6.2.4 Tweaking of the DDA systematic offset

The signal coming out of the PFWR is usually fed to an integrator,

which provides a smooth profile of the sensed activity. This implies that

the band-passed amplified and rectified noise appears as an "offset" at

the integrator output. Consequently, it was useful in this case to try to

compensate such "averaged" noise with offset. I did this by imposing a

systematic offset of the same value as the expected nominal random

offset, which was estimated in 2 mV. In this way, if the random and

systematic offset have opposite signs they cancel each other, whereas if

they have the same sign they both compensate part of the integrated

noise. This tweaking of the DDA systematic offset was achieved by

selecting a width for transistor M4 equal to 6 pm (it was verified by

simulation that the stability of the DDA was not compromised).

The next section presents the design of the comparator to the

transistor level.

6.3 Design of the comparator

The comparator was based on an uncompensated, two-stage Miller-

type amplifier. Figure 6.6 shows the schematic of such circuit.

Figure 6.6: Comparator of the precision full-wave rectifier implemented

This configuration provided a reasonable gain, slew rate and low offset

for the present application.

The next sections present the sizing of the transistors present in

Figure 6.6.

6.3.1 Input transistors MI and current source transistors M3

Transistors M 1 were biased in the moderate inversion region to have a

good trade-off between low offset and transistor area. The (&/ID), was

chosen equal to 15 V-', and the current through it equal to 1,,,,,13 (this

provides a reasonable transistor size and reasonable slew rate). This led

to a W/L equal to 28.8. A length of 3 pm provided sufficient gain for this

first stage, which determined a width of 86 pm.

Biasing transistor M 3 a could have been chosen identical to the one in

section 6.2.1 (same biasing current), but in order to reduce parasitic

capacitance at V,,, it was chosen with a length of 10 pm and a width of

47 pm. Transistor M3b was implemented as two transistors M3a in

parallel.

6.3.2 Transistors M2 of the active load

In order to reduce systematic offset, transistors M2 were biased in the

strong inversion region. A (&/ID), equal to 6 V-' was chosen. This led to a

W/L equal to 0.76. A length of 10 pm, to improve output impedance, and

a width of 8 pm were chosen.

6.3.3 Second stage

As explained before, the (&/ID), had to be chosen equal to the (g,/ID),

in order to minimize systematic offset [Gray and Meyer 19821. The

l3 As in the case of the DDA, an extra branch was added in the high current reference to provide such biasing.

biasing current of the second stage was chosen six times IBIAS2 for the

comparator to have its non-dominant pole far away from the dominant

one, increasing speed [Bani et al. 19981. These selections determined a

transistor M4 with a length of 10 pm (same as transistor M2) and a width

of 48 pm. Using Hspicem, the width was later adjusted to 39 pm to

minimize systematic offset. Finally, transistor M5 was implemented as

six transistors M 3 a in parallel.

6.4 Input switches and inverter

The PMOS input switches, as well as the NMOS transistor of the

CMOS inverter I (see Figure 6.4), were chosen of minimum width (4 pm)

and a length of 4 pm. The PMOS transistor of the inverter I was chosen

with a width of 12.8 pm and a length of 4 pm, to provide similar rising

and falling delays.

The next chapter presents the ~ s ~ i c e ' simulations performed for the

PFWR circuit and the layout.

Chapter 7

~ s ~ i c e " Simulations and Layout of the Precision Full-Wave

Rectifier Circuit

This chapter presents the spice@ simulations and layout of the

PFWR circuit. Minor adjustments to the transistor sizes were performed

to allow implementation in the technology used. These final transistor

sizes are presented. The layout picture was previously shown in Figure

5.2.

7.1 Simu Zations

~ s ~ i c e @ simulations using fast, typical and slow models of the

technology used were performed immediately after the design of each

building block to confirm performance. After all the individual building

blocks were simulated, the complete PFWR (see Figure 6.4) was

simulated. Following this verification, the circuit was laid out, extracted

and re-simulated to confirm that the extra parasitic capacitances did not

affect the behavior of the circuit.

The simulated systematic offset varied between 1.9 mV (fast model)

and 2.1 mV (slow model), with a typical value of 2 mV. The total power

consumption is 153 pW @ 5 V.

Figure 7.1 shows the simulated DC transfer characteristic of the

negative PFWR implemented.

Figure 7.1: Simulated DC transfer characteristic of the negative precision full-wave rectifier implemented

It verified that the slope is equal to 1. On the other hand, Figure 7.2

shows the dynamic response of the rectifier to a 3 kHz sinusoidal input

signal of 0.4 V,,,. As it can be seen in such figure, there is minimum

lagging behind of the rectified output V,,, with respect to the input V,,.

This minimizes distortion or equivalently "energy loss" of the signal being

recorded (measurements of this parameter are presented in chapter 10).

The next section details the implementation of the layout, which was

previously shown in Figure 5.2.

Figure 7.2: Simulated dynamic response of the negative precision full-wave rectifier implemented to a 3 kHz sinusoidal input signal of 0.4 Vpe&

7.2 Layout

All of the transistors, but the comparator input ones MI, were laid out

as single units. These transistors M1 were laid out using an "S" shaped

configuration instead.

Dummy transistors were drawn together with the transistors M3 of

the DDA. This improves the matching between the currents through

transistors M 1, a crucial factor for the successful performance of the

DDA. The DDA transistors were laid out exactly as dimensioned in

section 6.2.

In the case of the comparator, Table 7.1 shows the final transistor

sizes drawn.

Table 7.1: Final sizes drawn for the comparator transistors I I I

The next chapter presents the bench and in vivo testing results of the

first generation fabricated. Based on them, the band-pass amplifying

circuit requirements detailed in section 1.1 were modified to improve the

SIN. This new set of requirements is also presented at the end of the

next chapter. They were achieved by a re-design of the preamplifier,

which will be presented in chapter 9.

Chapter 8

First Generation Testing Results

This chapter presents the bench and in vivo testing results of the chip

first generation (refer to the Appendix for a detailed description of the

bench testing protocol). A feline model was used for the recording of ENG

signals. Based on the testing results, the requirements of section 1.1

were modified to improve the SIN. This new set of requirements is

presented at the end of this chapter.

8.1 Band-pass amp Zifying circuit

The prototypes fabricated had available the following building blocks

for independent testing: low current reference, high current reference,

preamplifier, and a cascade high-pass filterlnon-inverting, low-pass

amplifier. The last one was routed in this way since the high-pass filter

designed in chapter 3 is not meant to drive a pad capacitance.

All of the circuits mentioned above performed as expected, except for

the preamplifier gain. The average measured gain in the band of interest

was 14.5 when it was designed to be 24 (see section 2.3). This was

consistent in the five prototypes tested so the discrepancy was surely

caused by a problem in the layout of resistors R1 and R2.

Figure 8.1 shows the layout of such feedback resistors. As it can be

seen, even though R, was designed to be one square (see section 2.3.4),

there is some contribution of the resistor endings that is not negligible.

From the measured preamplifier gain of 14.5 and assuming R1 is equal to

the designed 23 squares, the contribution results equal to 0.7 squares.

This is in agreement with values reported elsewhere [Grebene 19841,

[Chapman 19991. It was consequently corrected in the second

generation.

t

Figure 8.1: Layout of the feedback resistors R1 and R2

Following the testing of all the individual building blocks, two

cascades (see Figure 2.7) were assembled and tested. One of them was

later encapsulated and implanted in an animal research subject for a

month, which allowed to record stable ENG signals throughout such

period. Table 8.1 summarizes the measured characteristics of the two

cascades tested, whereas Figure 8.2 presents the measured frequency

response of the two cascades superimposed.

Table 8.1: Measured characteristics of the first generation circuits # 1 and #2

Low-Frequency Pole High-Frequency Pole

Figure 8.2: Measured frequency responses of the two band-pass amplifying circuits # 1 and #2 tested

Circuit #2 84.3 dB Gain @, 3 kHz

Equivalent Input Noise14 Power Consumption

CMRR @, 250 Hz

Besides verifying the correct behavior of the first generation, the

bench testing confirmed that the noise models provided by the Foundry

were very accurate. Using the measured run parameters provided by

them, I obtained a simulated equivalent input noise of 1.38 pV,,. This is

Circuit #1 84.3 dB 840 Hz

7900 Hz

l4 It was calculated as the rms output voltage divided by the gain when both inputs are connected to VBIAS.

855 Hz 8050 Hz

1.64 pV,, 1.93 mW 91.1 dB

1.64 pV,, 1.99 mW 94.9 dB

pretty close to the measured value of 1.64 pV,,, considering the run

parameters did not include flicker noise values.

The average CMRR measured of 93 dB also confirmed that the

process-related random errors were sufficiently reduced by the large area

of the common-centroid, cross-coupled input transistors of the

preamplifier. This guaranteed that the second generation would have the

same or a better CMRR since the input transistors of the new

preamplifier would even be bigger than that of the first generation (less

noise needed).

The next section presents the measurements performed on the PFWR.

8.2 Precision full- wave rectifier

Out of the two PFWR tested, one presented an offset of 1.8 mV and

the other 1.4 mV. A statistic of the offset will be presented later on with

the results from the second generation, but at least this showed the

tendency of the offset towards 2 mV, which was imposed as described in

section 6.2.4. The average measured power consumption was 164 pW,

which is pretty close to the simulated value of 153 pW presented in

section 7.1.

Figure 8.3 presents the measured DC transfer characteristic of one of

the PFWR tested. This verified that the slope was equal to 1 as designed.

TeK Run: lO.okS/s

, ,. ? x.

, , . /- VBIAS - 0.2 I%, #

./- .'-.. ./

,.i VBIAs - 0.3 V '%. '. /"

/' k, x..

,T .. VBIAS - 0.4 V *?\

~p ~

VsIAs - 0.5 V

VBlAs - 0.6 V

).5V -0.4V -0.3V -0.2V -0.1V OV 0.1V 0.2V 0.3V 0.4V 0.5V b

VIN (0.1 Vldiv)

Figure 8.3: Measured DC transfer characteristic of the negative precision full-wave rectifier implemented

On the other hand, Figure 8.4 presents the measured dynamic response

to a 3 kHz sinusoidal input signal of 0.4 V,,,. It confirmed the minimum

lagging behind of the rectified output V,, with respect to the input V,,.

Time (0.1 msldiv)

Figure 8.4: Measured dynamic response of the negative precision full-wave rectifier implemented to a 3 kHz sinusoidal input signal of 0.4 Vp*

Finally, Figure 8.5 presents a zoom in of the switching region indicated in

Figure 8.4. In the former figure it can be seen that it takes only 8.4 ps for

the output signal Vo,, to "catch up and follow" the input signal V,,.

Figure 8.5: Zoom in of the switching region of Figure 8.4

The next section presents the in vivo testing results.

8.3 In vivo testing resu 2ts

Raw ENG signals recorded from the implanted animal research

subject under anesthesia are shown in Figure 8.6 (see Kallesae 1998 for

a description of the recording setup). The upper signal was recorded

using the first generation, whereas the lower one was recorded with

discrete amplifiers from the NeuroKinesiology Laboratory at S.F.U.

Figure 8.6: In vivo ENG signals recorded from the animal research subject under anesthesia

15 I I I I I I

It can be easily observed that the zone and features of interest, which

with further signal processing will be used in the closed-loop feedback

control, stand out from the background activity and noise more clearly in

the discrete amplifiers. The reason is that these amplifiers presented an

equivalent input noise of 0.86 w,,, when the first generation presented

a noise of 1.56 pVm,15. However, the discrete amplifiers used consumed

720 mW of power, which is 360 times more than the 2 mW consumed by

the first generation.

Another in vivo test performed with the first generation was the

measurement of the recovery time of such circuit from a stimulus

10

-

l5 Noise was sampled and the rms value calculated with MATLAB@. The value obtained is pretty close to the 1.64 pVms measured before with the oscilloscope.

Izone of irkerest I f l p e a k Lab Discrete Amplifier f -

I I. ,C,,_,, .... ,.... ,... .A.

0 t .

s I

-5

-rn

1 '

- $. ...... r r , +*=.== ...... :.* I

- -

1 0.86 pv,, - 720 m~ Features of interest 1

I I I I I I I

artifact. Because the band-pass amplifying circuit has a large differential

gain, the differential voltage due to such artifact caused the circuit to

operate abnormally. It is not uncommon to see in some amplifiers

excessive ringing and long settling times after the recording of a stimulus

artifact. Channel 4 of Figure 8.7 shows the recording of a stimulation

artifact in the sciatic nerve of the animal research subject implanted,

which was elicited by electrical stimulation using a cuff electrode in the

tibial nerve (see Kalles~re 1998 for a description of the setup). There it can

be seen that the band-pass amplifying circuit recovers in about 0.6 ms

from such overload.

Tek Run: 250kS/s

Time (0.2 msldiv)

Figure 8.7: Recorded stimulus artifact on sciatic nerve

Despite the noise level, the in vivo testing confirmed that the first

generation fabricated was suitable for the intended application. Now, the

noise needed to be reduced at the expense of extra power consumption.

Using the fact that noise is inversely proportional to the square root of

the biasing current, a quick-hand calculation gives that in order to have

an equivalent input noise of around 0.6 pVm,16, the power consumption

needs to be boosted to around 13.5 mW. It is worth pointing out that

since the product VrmS,, x z remains constant, the NEF of this new

band-pass amplifying circuit will still be close to 10 (see section 5.1).

Finally, based on these in vivo experiments, I found that there is

negligible neural information beyond 6 kHz, so I decided to reduce the

recording band to 850 - 6000 Hz, maximizing the S I N . The peak of the

neural activity falls in the band 2100 - 2300 Hz. Due to a time-to-market

constraint17, only the preamplifier was re-designed to reduce the

equivalent input noise. For the band reduction, discrete components

were used as shown in Figure 8.8 (in the conclusions and future work

chapter 1 1 a fully-integrated solution is proposed).

Figure 8.8: Proposed solution for the recording band reduction

l6 Based on equivalent input noise achieved in reference [26].

7 ~ h e second generation was embedded in NeuroStream Technologies' first clinical FES implantable prototype, which contains two recording channels.

The 100 pF capacitor and the 3.3 MR resistor form a high-pass filter with

a cutoff frequency of 482 Hz. Such high-pass filter compensates the

offset of the amplified ENG signal before being fed to the PFWR. A

~ ~ ~ 6 0 6 1 ~ (low-power CMOS amplifier) from Analog Devices was used as

a buffer to separate the mentioned high-pass filter from the low-pass

filter formed by the 100 WZ resistor and the 390 pF capacitor. Such low-

pass filter places a pole at around 4080 Hz, which combined with the 9

kHz poles from the band-pass amplifying circuit, allows to adjust the -6

dB gain drop at 6 kHzl8.

The PFWR was also tested in vivo with successful results. Since no

modifications were necessary, such results will be presented together

with the testing of the second generation.

The next section summarizes the new set of requirements for the

second generation of the band-pass amplifying circuit.

8.4 Requirements for the second generation of the band-pass

amplifying circuit

The new electrical requirements (at ambient temperature) chosen for

the second generation of the band-pass amplifying circuit were the

following:

Second order or higher band-pass amplifier. The low frequency - 6 dB

gain drop shall be @ 850 Hz + 5%. The high frequency - 6 dB gain

drop shall be @ 6 kHz + 5%;

l8 The 6 H z is adjusted as if the band-pass amplifying circuit were a second order filter.

Note: The band-pass can be adjusted, with negligible change in power

consumption, modifying resistor R~ml for the low pole and the 390 pF

capacitor for the high pole (see section 3.2 and Figure 8.8 respectively).

Band-pass gain @ 2.2 kHz shall be higher than 87 dB;

Equivalent input noise level @ 2.2 kHz shall be lower than 0.6 pVm,;

Total power consumption @ 5 V shall be lower than 13.5 mW.

CMRR @ 250 Hz shall be higher than 85 dB.

Rationale: This was modified from the previous requirement based on the

following reasoning: I found that the largest biopotential that interferes uith

the ENG is in the order of 3 mV. Considering that the smallest recordable

ENG signal is in the order of 3 pV, and being desirable at the amplifier

output to have ten times higher ENG signal than the interfering one, we

have that the minimum CMRR is given by equation 8.1. Hence, I selected 85

dB as the new minimum CMRR needed (this will provide a better yield

compared to the 90 dB specification of the first generation).

- [vcM in)[vd#ouf ) = ( 3 v ) I = 0, 000 = 80 dB ( 8 1) CMRR = - - - - AM V d in V C M , ~ ~ ~ 3 PV

The next chapter presents the preamplifier re-design in order to

achieve the lower noise requirement.

Chapter 9

Preamplifier Re-design

This chapter presents the preamplifier re-design in order to achieve

the lower noise requirement set in section 8.4. The new preamplifier is

based on a two-stage, folded-cascode [Alvarez 19931 DDA, instead of one

based on two common-source stages. This allowed avoiding the flicker

noise contribution of the NMOS transistors M4 (see Figure 2.6) that

convert into a single-ended current the differential currents from the two

input pairs.

9.1 Configuration selected

Let us go back to the first preamplifier configuration shown in Figure

2.6. A quick re-simulation using MATLAB@, as done in section 2.3,

revealed that at this sub-micron noise level it was imperative to minimize

the flicker noise component of the transistors M4 of the active load.

Consequently, I first tried to re-design the DDA replacing such NMOS

transistors with Bipolar ones with emitter degeneration [Alvarez 1 9 9 3 1 ~ ~ .

This proved not to work due to offset problems, which brought the

systematic CMRR to 70 dB @ 250 Hz, even though base-current

compensated current mirrors were used [Grebene 19841.

I chose instead a two-stage, folded-cascode configuration with Bipolar

transistors as cascode transistors and drain resistors as biasing sources.

Figure 9.1 shows such configuration.

l9 I also replaced transistor M 5 with Bipolar ones.

- 81 -

OUT

Figure 9.1 : Preamplifier second generation

As it can be seen, the differential current generated by the transistors M1

is converted to a single-ended current by the transistors M2 and Q3.

Resistors RA supply the biasing current for the common-base transistors

Q3. Even though this first stage has more components than the one used

in Figure 2.6, it presents much less flicker noise since the current mirror

M2 is implemented using PMOS transistors.

An advantage of a folded-cascode amplifier is that the compensation

capacitor is generally the same as the load capacitor [Alvarez 19931. In

this case, however, the sub-micron low noise imposed extremely wide

transistors M1 that translated in a large parasitic capacitance at the

emitters of the transistors Q3. This created a non-dominant pole lower

than the unity-gain frequency of the first stage. Consequently,

compensation was needed. It was achieved with the capacitor CMl and

the nulling resistor R,, placed in the second stage formed by transistors

MI0 and M11.

This second stage also provides further open-loop gain for the DDA,

but on the other hand, it reduces the good PSRR of the first stage [Gray

and Meyer 19821. However, I was again able to get a good PSRR using the

technique described in section 2.3.6, which in this case is implemented

by the capacitor CM1 connected between the gates of the upper transistors

M2 of the cascode current mirror of the first stage and the voltage

reference VBIAS.

Finally, the output stage configuration is the same as the one used in

the first preamplifier design (see Figure 2.6).

The next section presents the dimensioning of the components

present in Figure 9.1.

9.2 Dimensioning of components

9.2.1 Input transistors MI

The design started once again by assigning thermal noise levels for

the major noise contributors. For these four input transistors M 1,

2 n VWHZ was assigned per transistor. An identical sizing procedure as

the one described in section 2.3.1 was followed (except for the fact that

an IC of 1 was chosen), which led to a source-drain current for each

transistor equal to approximately 177 pA and a width and length of 8942

pm and 2 pm respectively. A s anticipated before, the input transistors

resulted extremely wide.

9.2.2 Transistors M2 of the cascode current mirror

In a folded-cascode amplifying stage, it is usually common to use

cascode current mirrors to significantly increase the output impedance

for obtaining higher gains. The high-swing, cascode current mirror

implemented in Figure 9.1 by transistors M2 provides one of the highest

output impedances among current mirrors [Tanno et al. 19991. It is also

suitable for low voltage operation, which eased the biasing task.

The current through these transistors M2 is generally chosen equal to

that of the input transistors M1 due to a slew-rate vs. power

consumption compromise [Iberchip Course 19971. On the other hand, an

IC of 60 was selected for these transistors, which together with the

current of 177 pA led to a W/L equal to 74.5. A length of 4 pm was

chosen, which determined a width of 298 pm.

9.2.3 Biasing resistors RA and transistors Q3

The conditions 9.1 and 9.2 were considered in the sizing of the

biasing resistors RA.

The first condition guarantees the correct biasing of the folded-cascode

stage. The second one is a requirement for the correct functioning of

such stage. After substituting values in both conditions, I found that the

resistor RA needed to be always higher than 1518 f2 and lower or equal

than 5028 R20. I chose the lower limit since this minimizes the

equivalent input noise. Resistor RA was implemented as a p+ sheet

resistor of 65.6 pm in length and 3.2 pm wide. This gives a typical

resistor RA of around 2250 R.

20 In a conservative approach, the V C E ~ ~ ~ J was chosen equal to VBE~ 4 0.7 V. Also, in condition 9.2, the "much higher than 1" requirement was modified into an "equal to 10" one.

Transistors Q3 were again chosen with minimum emitter area.

9.2.4 Current source transistors M4 and M5

These transistors were dimensioned using the same approach as in

section 2.3.2, except that the (g,,JI,),was chosen equal to 4 V-' instead of

6 V-I (higher current level). This value, together with a defined source-

drain current through such transistor M5 equal to 354 pA, led to a

minimum needed length of 9.2 pm and a width of 1864 pm. Transistor

M5 was implemented as ten transistors in parallel of 186.4 pm in width

and 9.2 pm in length.

To have a reasonable current copy ratio, transistor M4 was chosen as

a single transistor of 186.4 pm in width and 9.2 pm in length. This

selection implied that the new current IBIAs (see Figure 9.1) had to be

chosen equal to 35.40 pA. A minor modification in the high current

reference of Figure 2.8 allowed the supply of such biasing current.

9.2.5 Biasing branch given by resistor RR

The biasing branch given by resistor RR sets the base voltage of the

cascode transistors Q3. If we choose the current through such resistor

equal to I,,,,, which is actually the minimum current circulating through

any branch in the preamplifier, the resistors RR and RA meet equation 9.3

(assuming almost same V,, for all the transistors Q3).

This implied resistor RR was implemented as five resistors R, in series.

9.2.6 Biasing transistors M6 and M7

These transistors provide the necessary gate voltage biasing for the

high-swing, cascode current mirror presented in section 9.2.2. The

voltage V,, needed for such purpose (see Figure 9.1) had to guarantee the

correct biasing of all four transistors M2 of the current mirror. This

translated into the conditions 9.4 and 9.5.

The first condition guarantees the correct biasing of the transistors M2a,

whereas the second one does the same for the transistors M2b. After

substituting values in both conditions, I found that the biasing reference

Vref needed to be between 1.84 V and 2.45 V. I chose 2.14 V, which is the

average between the two limits.

The simplest solution was to provide such biasing reference using two

diode-connected transistors M6, each one with a typical source-gate

voltage close to 1.07 V. In this case, I found that the best compromise

between source-gate voltage and transistor size was achieved for a

(&/I,), equal to 6 V-', which led to a typical source-gate voltage of 1.18 V.

If we once again choose a biasing current equal to I,,,, for this branch,

based on the argument of section 9.2.5, a transistor M6 with a W/L

equal to 46.7 is determined. A length of 4 pm was selected, which

resulted in a width of 186.8 pm.

In the sizing of transistor M7, it was taken into account the fact that

the second stage gets its biasing from such transistors, through

transistor M10. This means the drain-source saturation voltage of

transistor M 7 (which is equal to that of transistor M10) will take part in a

constraint identical to that of condition 2.8. Hence, transistors M7

needed to be biased somewhere between the moderate and strong

inversion regions, to have a reasonable trade-off between proper

matching and low drain-source saturation voltage. An IC of 5 was chosen

for such transistors, which resulted in a W/L equal to 55.6. A length of 4

pm was selected, which determined a width of 1 1 1.2 x 2 pm (this

selection, instead of 222.4 pm, will become evident in section 9.2.8).

9.2.7 Output stage

A similar approach as the one described in section 2.3.4 was used for

the sizing of the output stage. First, based on the re-simulation using

MATLAB@ mentioned in section 9.1, resistor R2 was decreased from a

typical value of 1500 i2 to 100 0. It was implemented using a poly 1

resistor of 12 pm in length and 4 pm wide. Second, based on the same

re-simulation, the gain of the preamplifier AcDDA was increased from 24 to

40, to further decrease the noise contribution of the first high-pass filter

following the preamplifier (see equation 2.2).

Following the feedback resistors dimensioning, the maximum voltage

at the input of the preamplifier was re-evaluated21. Based on the first

generation measurements, such maximum voltage resulted equal to 5

mV,,, (this includes offset and interfering biopotentials). This value,

together with a gain of 40 and a resistor (R, + R2),i, equal to 283 1 SZ,

determined a maximum output current of 70.65 pA. The source-drain

21 The initial estimation for the design of the first generation was 10 mVped (see section 2.3.4).

current of transistor M 8 was then selected seven times higher than this

maximum current in order to ensure proper operation of the output

stage independently of the output current22. Transistor M 8 was

implemented as 14 transistors M4 in parallel.

From the total output stage current, 82.60 pA was determined as the

minimum source-drain current allowed through transistor M9 in order

for the base current of transistor Q12 to be negligible with respect to it.

With this value in mind, and assuming a VBE12 of 0.7 V, a maximum

resistor RD of 8475 C2 was determined and implemented using 3 strips of

p+ sheet resistance, each one of 65.6 pm in length and 3.2 pm wide. This

resulted in a minimum source-drain current through transistor M9 of

approximately 86.33 pA, which is higher than the 82.60 pA minimum

calculated before.

A s in the design of the first generation, the (&/ID), was selected equal

to 6 V-' (in such design the equivalent transistor was M6, see section

2.3.4). This value, together with a typical source-drain current of 99.50

pA, determined a W/L equal to 13 1.2. Minimum length was selected,

which led to a width of 262.4 pm. Finally, transistor Q12 was selected

minimum, with an emitter area of 6.4 x 9.6 pm2.

9.2.8 Second stage

This stage was designed considering the same constraints presented

in the design of the second stage of the preamplifier first generation (see

section 2.3.5). Resistor RM1 was chosen equal to resistor R,, whereas

capacitor CMl was chosen equal to 10 pF (same as the one of the non-

22 This is a less conservative approach than the one used in the design of the first generation (see section 2.3.4)

inverting, low-pass amplifier, see section 4.2.3). Based on the former

selection, the transconductance G~~ resulted equal 177.6 pW, which is

the inverse value of R,,,,,. This transconductance value, together with a

(g,,,/ID),, = (&/ID), = 3.43 V-' (see equation 2.5), determined a source-drain

current for transistor M l 1 equal to 51.78 pA, which is close to 1.5 times

IBus. Consequently, transistor MI0 was implemented as a transistor of

11 1.2 x 3 pm in width and 4 pm in length. Such transistor is matched

with transistor M7 (see section 9.2.6).

The above selection of transistor M 10 determined a source-drain

current through transistor M 1 1 equal to 53.10 pA (1.5 times IBIAS), which

led to a transistor M l 1 of 89.2 pm in width and 4 pm large (same length

as transistor M2).

9.2.9 Determination of the new voltage reference VBHs

To guarantee the correct biasing of all the branches in the re-designed

preamplifier, conditions 9.6 and 9.7 shall be met at all times.

> 0 'BIAS - 'SG9 - 'DSsat 10 -

Worst-cases for the source-gate and saturation voltages determined a

new voltage reference VBwS between 1.48 V and 2 V. I selected the

standard 1.8 V as the new value.

This concludes the presentation of the preamplifier re-design. The

next chapter presents the ~ s ~ i c e @ simulations, the bench and in vivo

testing results, and the layout of the second and final generation

fabricated.

Chapter 10

spice@ Simulations, Layout and Testing Results of the

Second Generation

This chapter presents the ~ s ~ i c e @ simulations, layout and testing

results of the second and final chip generation fabricated. This second

generation forms part of the first closed-loop FES implantable prototype

of Neurostream Technologies Inc., which is scheduled to go into human

trials in the first quarter of 2003.

1 0.1 Simulations

Table 10.1 summarizes the final typical simulation results of the

extracted circuit. It was also verified that the worst-case met the

requirements set in section 8.4.

Table 10.1: spice@ typical simulation results of the band-pass amplifying extracted circuit (second generation) -

Gain @, 2.2 kHz Low-Frequency Pole High-Frequency Pole

Equivalent Input Noise Power Consumption

Svstematic CMRR @, 250 Hz

The higher systematic CMRR achieved does not translate into a higher

total CMRR since this parameter is basically governed by random

mismatches. Since the input transistors M 1 of the re-designed

preamplifier are almost five times bigger in area than the ones of the first

PSRR @, 2.2 kHz

Specified > 87 dB

850 Hz f 5% 6kHz+5%

< 0.60 pVrms < 13.50 mW

110 dB

Simulated - 91.7 dB - 855 Hz 6020 Hz -

0.46 pvrrns - 10.51 mW 149.8 dB

NA 76 dB

generation, the expected total CMRR of the second generation will be of

the same order of magnitude as the one achieved in the first generation.

The next section presents the implementation of the layout as well as

pictures of the second generation fabricated.

10.2 Layout

10.2.1 Re-designed preamplifier

The layout of the second generation included all the building blocks of

the first generation except for the preamplifier. The layout of the re-

designed preamplifier was carried out following the same guidelines used

in the first generation (see section 5.2.1). Table 10.2 shows the final sizes

drawn.

I M l O I 4 I 55.6 x 6 1

Table 10.2: Final sizes drawn for the re-designed preamplifier transistors

L (w) w (elm)

Q3, Q12 6.4 x 9.6 pm2 emitter area

A careful layout analysis was carried out to guarantee that noise due

to the connections and gate resistances resulted negligible compared to

the main sources [Jindal 19841. This was achieved by increasing the

width of the poly 1 that formed the different transistors M2, and also by

short-circuiting both ends of each of such transistors M2.

10.2.2 Layout photograph

Figures 10.1 .a and 10.1 .b show the layout and photograph of the

second generation respectively. The layout was carried out using the

Tanner ~ o o l s @ design environment from Neurostream Technologies Inc.

Figure 10.l.a: Layout of the second generation (die area 2.2 x 2.2 mm)

Figure 10.l.b: Photograph of the second generation

The next section presents the bench and in vivo testing results of the

second generation fabricated.

1 0.3 Testing results

Up to date, more than 170 prototypes have been fabricated in two

different runs. Each of the dies was encapsulated in a 14-lead SOIC

package and embedded onto the same PCB with the rest of the circuitry

that forms Neurostream's first closed-loop FES implantable prototype.

This second generation behaved as expected, with a yield over 90 %23.

Table 10.3 summarizes the final specifications of the second generation

once embedded in Neurostream's first prototype.

23 Around 10% of the units did not achieve the minimum required CMRR of 85 dB (see section 8.4).

- 93 -

As it can be seen in Table 10.3, the maximum input noise requirement

Table 10.3: Second generation final specifications once embedded in Neurostream's first prototype

was increased from 0.6 &, (see section 8.4) to 0.7 pV,,. This is

Gain @, 2.2 kHz Low-Frequency Pole High-Frequency Pole

Equivalent Input Noise Power Consumption

CMRR @, 250 Hz

because extra circuitry was placed at the inputs of the recording circuit

90.5 + 0.5 dB 850 Hz + 5% 6kHz+5%

< 0.70 pVrms < 12 mW > 85 dB

to disconnect it when a stimulation pulse is delivered (the voltage

reference VBIAs is disconnected as well). This extra circuitry, together with

the remaining components on the PCB, added the extra 0.1 pV,,. The

measured mean input noise was 0.59 pV,,, with a standard deviation of

0.02 pVm,24. Considering a confidence interval of 3 o, the equivalent

input noise is guaranteed to be always less than 0.65 pV,,.

The distortion or equivalent "energy loss" was also measured in the

second generation. A 2.2 kHz sinusoidal signal of 10 pV,,, was applied to

the circuit, which emulates the maximum expected level of ENG

activity25. At the band-pass amplifying circuit output, the distortion or

energy loss is equal to around 2 %, whereas at the PFWR output is equal

to 5 %. This is more than acceptable for the present application.

24 Only the circuitry that disconnects the inputs was included in these measurements.

25 Actually, this is assuming that all the ENG activity is concentrated around the same frequency, which is a worst case since such activity is spread over the range 850 Hz - 6 kHz.

The bench testing concluded with the measurement of the PFWR

output offset. The mean value resulted equal to 3.5 mV, and the

standard deviation equal to 5.6 mV. This confirmed the positive offset

displacement introduced in section 6.2.4.

Figure 10.2 shows a 6 ms-bin-integrated ENG signal processed on-

line from a recording using the second generation in the animal research

subject walking on a treadmill.

Time I 1 s I - 1

Figure 10.2: 6 ms-bin-integrated ENG signal processed on-line from the animal research subject walking on a treadmill, recorded using the second generation

Using a simple signal-processing algorithm, such bin integrated signal is

used for closed-loop control of the FES prototype. In this application, it is

sufficient to sample the activity every 15 ms or 20 ms and still get the

profile shown in Figure 10.2. Thus, further power consumption reduction

can be achieved if the recording circuit is turned off during the non-

sensing periods. In this case it was not possible to switch on/off the

power supply VDD since this causes a long output transitory (80 ms) due

to saturation caused by the extremely high closed-loop gain of the band-

pass amplifying circuit. Instead, a 2.2 MR resistor in parallel with a

switch implemented with a discrete NMOS transistor was placed in series

with the biasing resistor RRE, of the high current reference (see section

2.3.8). This allowed to reduce the total current of the recording circuit to

less than 10 pA (or equivalently 0.05 mW) when the circuit is disabled,

and still recover in a few ms after the NMOS switch is turned on to short-

circuit the 2.2 MR resistor.

This section concludes the report on the design, fabrication and

testing of a custom ASIC for the recording of ENG activity using nerve

cuff electrodes. The next chapter presents the conclusions and future

work, especially with respect to new possible generations to further

reduce the area and power consumption.

Chapter 11

Conclusions and Future Work

1 1.1 Conclusions

I presented the design, fabrication and testing of two generations of a

custom ASIC for the recording of ENG activity using nerve cuff

electrodes. Each circuit consists of a low-noise, high CMRRIPSRR band-

pass amplifying circuit, followed by a diode/resistorless precision full-

wave rectifier. This is the first chip of its kind that combines

amplification, filtering and rectification, all integrated monolithically on a

single chip, with low noise and extremely low-power consumption. These

characteristics make the circuit suitable for the development of multi-

channel, closed-loop FES devices.

The uniqueness of the research performed here allowed the

submission on November 200 1 of Canadian, European and U.S. Patents

to protect the design of the band-pass amplifying circuit. Another patent

is currently being filed to protect the design of the diode/resistorless

PFRW. The patent landscape around this amplifier technology was not

only investigated by Neurostream Technologies Inc., the assignee, but

also by a well-recognized Canadian independent source hired exclusively

for this analysis.

Two of these recording channels have been integrated in

Neurostrearn's first FES implantable prototype scheduled to go into

human trials in the first quarter of 2003. Despite this accomplishment,

further steps can be taken to improve the performance of the circuit.

Such steps are detailed in the next section.

11.2 Future work

I envision three possible improvements to the present design:

i) Integration of two or more recording channels onto the same

substrate.

ii) Integration of the discrete solution for the recording band

reduction (see Figure 8.8).

iii) Reduction in the power supply voltage VDD.

With i), the final PCB area of the implant can be reduced since two or

more recording channels share the same encapsulation package (the

minimum SOIC package can still be used for two channels). This

capability is present in other general-purpose instrumentation amplifiers

like the AMPO1•‹ from Analog Devices Inc. However, it has to be

guaranteed by layout that the cross-talk between these two channels is

negligible.

Improvement ii) would substantially reduce the area occupied by each

recording channel since it would avoid the use of several discrete

components for the implementation of the recording band reduction

(remembering that the high frequency pole was reduced from 9 kHz to 6

kHz; see section 8.3). After studying several different integrated

solutions, the one shown in Figure 11.1 seems to be the best choice for

the implementation of the band reduction scheme.

Buffer 4080 Hz

Figure 11.1: Proposed integrated solution for the recording band reduction

The "buffer 4080 HZ" would replace the low-pass filter implemented by

the discrete 100 kR resistor and 390 pF capacitor present in Figure 8.8.

Such buffer has a -3 dB gain drop around 4080 Hz. The integrator

implemented by the "CMOS Op-amp" sets a low cutoff frequency and

cancels offset. Such low cutoff frequency can be set equal to the one

imposed by the discrete 100 pF capacitor and 3.3 MR resistor in Figure

8.8. The capacitor COFF can be integrated (and be equal to CHPF, see

section 3.2), whereas the resistor RoFF has to be external (around 12 MR).

Despite the fact that two external resistors would be needed in this

solution26, it is preferred over a G-C high-pass filter due to offset

problems.

I have already designed and simulated the "Buffer 4080 Hz", which is

based on the classic two-stage Miller-type amplifier (similar to the one in

Figure 4.1 but without the output stage). It typically consumes only 334

26 A second resistor would be needed to independently adjust the pole introduced by the "Buffer 4080 Hz".

nW @ 5 V. I have also designed the "CMOS Op-amp7', which is based on

the same amplifier configuration as the "Buffer 4080 Hz". Such "CMOS

Op-amp" has a typical unity-gain frequency of 725 kHz and consumes

only 67.8 pW @ 5 V.

The DDA has not been designed yet. It is clear however that neither of

the previous DDAs can be re-used due to distortion problems. This new

DDA would need to have low distortion, since the discrete solution of

Figure 8.8 does not introduce any distortion. This can be achieved by

biasing input PMOS transistors deep in strong inversion, at the expense

of higher power consumption.

The final envisioned improvement iii) deals with the reduction in the

power supply voltage VDD to further reduce the total power consumption

of the circuit. In order to achieve this, the use of cascode current sources

has to be eliminated, but keeping the same CMRR achieved with them.

This seems to be possible using the "yield modeling technique"

introduced by Guardiani et al. in 1992 [Guardiani et al. 19921. Basically,

this technique is based on the assumption that it is possible to model,

using response surface methods [Box and Draper 19871, the

fundamental performance of an analog IC through simple analytical

functions of a set of design parameters and a set of statistical variables

representing the effect of the process randomness. Process parameters

and mismatches are assumed to be independent random variables with

truncated Gaussian distributions that reproduce the data collected in the

fabrication pilot line. A high CMRR DDA based on this technique was

successfully implemented in [Nicollini and Guardiani 19931.

Abbreviations

ASIC - Application Specific Integrated Circuit.

CMOS - Complementary Metal Oxide Semiconductor.

CMRR - Common Mode Rejection Ratio.

DC - Direct Current.

DDA - Differential Difference Amplifier.

EMG - Electromyographic.

ENG - Electroneurographic.

FES - Functional Electrical Stimulation.

IC - Inversion Coefficient.

L - Length of the MOS transistor.

MOSFET (MOS) - Metal-Oxide-Semiconductor Field Effect

Transistor.

NEF - Noise Efficiency Factor.

NMOS - n-channel-type MOS transistor.

PCB - Printed Circuit Board.

PFWR - Precision Full-Wave Rectifier.

PMOS - p-channel-type MOS transistor.

PSRR - Power Supply Rejection Ratio.

S/N - Signal-to-Noise ratio.

W - Width of the MOS transistor.

Appendix

Bench Testing Protocol Description

Note: The supply voltage to the ASIC was 5 V f I %. This supply voltage

was applied in the following way: 1.8 V between pins VBIAS and GND

(lower power supply) and 3.2 V between pins VDD and VBL~S (upper power

supply).

1) Measurement of the gain @ 3 kHz (2.2 kHz for the second

generation):

I turned on the power by enabling the lower power supply first, followed

by the upper power supply. Using a HP 33 120 signal generator, I injected

a 100 mVpp, 3 kHz (2.2 kHz) sinusoidal signal as described in the figure

below (the resistors were measured).

ASIC 100kc2 -

*,signal Generator Ground

I measured the averaged peak-to-peak voltage VouTpp at the output of the

band-pass amplifying circuit, using a nominal TDS 420 oscilloscope

setting of 200 mV/ div and 1 ms/div. I calculated the gain as VOUTpp/VINpp,

being the nominal VINpp = (22 R x 100 mVp,)/ (22 R x 100 kR) (the

measured resistor values were used). I turned off the power by disabling

the upper power supply first, followed by the lower power supply.

2) Lower - 6 dB gain drop:

Using the same setup as in test I), I found the lower - 6 dB gain drop.

The nominal oscilloscope setting was: 100 mV/div and 2 ms/div.

3) Upper - 6 dB gain drop:

Using the same setup as in test I), I found the upper - 6 dB gain drop.

The nominal oscilloscope setting was: 100 mV/div and 400 ps/div.

4) Equivalent input noise:

I short-circuited the inputs to V,,,,. I turned on the power by enabling the

lower power supply first, followed by the upper power supply. Using the

oscilloscope, I measured the rms voltage at the output V,,, of the band-

pass amplifying circuit, using a nominal oscilloscope setting of 50

mV/div and 20 ms/div. I calculated the equivalent input noise as the

ratio between the rms voltage at V,,, and the gain obtained in test 1). I

turned off the power by disabling the upper power supply first, followed

by the lower power supply.

5) Power consumption:

Using the same setup as in test 4), I connected a 100 SZ (10 SZ for the

second generation) resistor as described in the figure below (the resistor

was measured)

GND

Supply Voltage Ground

I turned on the power by enabling the lower power supply first, followed

by the upper power supply. I measured the DC voltage drop across the

100 R (10 R) resistor using a general purpose multi-meter. I calculated

the power consumption as the voltage read times 5 V divided by the

measured resistor value.

6) CMRR @ 250 Hz:

First, using the same setup as in test I), I injected a 250 Hz sinusoidal

signal of 2 V,,, and calculated the differential gain as the ratio of

VouTpp/V,,pp, being the nominal V,,,, = (22 SZ x 2 Vpp)/(22 R x 100 kR) (the

measured resistor values were used). The nominal oscilloscope setting for

this measurement was: 200 mV/div and 4 ms/div.

Second, using a signal generator, I injected a 200 mV,,, 250 Hz

sinusoidal signal as described in the figure below.

9% Signal Generator Ground

With a time scale setting of 4 ms/div, and using the oscilloscope average

function, I measured the rms value of the output VouT of the band-pass

amplifying circuit in a 20 mV/div scale. The Sync output of the signal

generator was used as a triggering source (the nominal setting for this

triggering channel was 2 V/div).

I calculated the common-mode gain @ 250 Hz as Ac = (V,, x n)/200

mV,,. I calculated the CMRR @ 250 Hz as the ratio between the

differential and the common-mode gains at such frequency.

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