1

Eclipse Ser ies

RF Technology

rfinfo@rftechnology.com.au

August, 2003

Revision 2

T50 TransmitterOperation and Maintenance Manual

This manual is produced by RF Technology Pty Ltd

10/8 Leighton Place, Hornsby NSW 2077 Australia

Copyright © 2001 RF Technology

2

Contents1 Operating Instructions 5

1.1 Front Panel Controls and Indicators 5

1.1.1 PTT 51.1.2 Line 51.1.3 POWER LED 61.1.4 TX LED 61.1.5 ALARM LED 6

2 Transmitter Internal Jumper Options 6

2.1 Serial I/O Parameters 62.2 Line Terminations 72.3 Exciter Low Battery Level 72.4 External PA Parameters 72.5 Generate Loop 72.6 External Tone Input 72.7 External Tone, High Pass Filter Bypass 72.8 Transmit Time 72.9 Channel Select Override 72.10 CWID Start Delay 72.11 CWID Period 82.11 CWID Message 82.9 Channel Selectable Parameters 8

3 Transmitter I/O Connections 8

3.1 25 Pin Connector 83.2 9 Pin Front Panel Connector 9

4 Channel and Tone Frequency Programming 9

5 Circuit Description 10

5.1 T50 Master Schematic (Sheet 1) 105.2 Microprocessor (Sheet 2) 105.3 Audio Processing Section (Sheet 3) 135.4 Line Input Processing Section (Sheet 4) 145.5 Tone Generation Section (Sheet 5) 155.6 Frequency Synthesiser (Sheet 6) 165.7 Voltage Controlled Oscillators (Sheet 7) 185.8 1W Broadband HF Power Amplifier (Sheet 8) 205.9 Power Generation Section (Sheet 9) 20

6 Field Alignment Procedure 21

6.1 Standard Test Equipment 216.2 Invoking the Calibration Procedure Manually 21

6.2.1 The “Miscellaneous” Calibration Procedure 226.2.2 The “Reference” Calibration Procedure 226.2.3 The “Deviation” Calibration Procedure 246.2.4 The “Tone Deviation” Calibration Procedure 256.2.5 The “Line” Calibration Procedure 256.2.6 The “Power” Calibration Procedure 26

7 Specifications 28

3

7.1 Overall Descr iption 28

7.1.1 Channel Capacity 287.1.2 CTCSS 287.1.3 Channel Programming 287.1.4 Channel Selection 297.1.5 Microprocessor 29

7.2 Physical Configuration 29

7.3 Front Panel Controls, Indicators and Test Points 29

7.3.1 Controls 297.3.2 Indicators 297.3.3 Test Points 29

7.4 Electrical Specifications 29

7.4.1 Power Requirements 297.4.2 Frequency Range and Channel Spacing 297.4.3 Frequency Synthesizer Step Size 307.4.4 Frequency Stability 307.4.5 Number of Channels 307.4.6 Output Power 307.4.7 Transmit Duty Cycle 307.4.8 Spurious and Harmonics 307.4.9 Carrier and Modulation Attack Time 307.4.10 Modulation 307.4.11 Distortion 307.4.12 Residual Modulation and Noise 307.4.13 600Ω Line Input Sensitivity 307.4.14 Test Microphone Input 307.4.15 External Tone Input 307.4.16 T/R Relay Driver 317.4.17 Channel Select Input / Output 317.4.18 DC Remote Keying 317.4.19 PTT in 317.4.20 Programmable No-Tone Period 317.4.21 Firmware Timers 317.4.22 CTCSS 327.4.23 DCS Codes 327.4.24 CWID 32

7.5 Connectors 32

7.5.1 RF Output Connector 327.5.2 Power and I/O Connector 327.5.3 External Reference Connector (optional) 32

A Engineering Diagrams 33

A.1 Block Diagram 33A.2 Circuit Diagrams 33A.3 Component Overlay Diagrams 33

B T50 Parts List (Rev. 4) 34

C T50 Parts List (Rev. 3) 46

D EIA CTCSS Tones 48

4

1 Operating Instructions

1.1 Front Panel Controls and Indicator s1.1.1 PTTA front-panel push-to-talk (PTT) button is provided to facilitate bench and field testsand adjustments. The button is a momentary action type. When keyed, audio from theline input is disabled so that a carrier with subtone is transmitted. The front-panelmicrophone input is not enabled in this mode, but it is enabled when the PTT line onthat socket is pulled to ground.

The PTT button has another function when transmission is keyed up, and the TX LEDlight is showing. If there is a “forward power low” alarm (the ALARM LED flashesthree times, then pauses), pressing this will cause the ALARM LED to flash 6, 7, 8, or 9times before the pause (see Table 2). This will indicate what has caused the low poweralarm.

1.1.2 LineThe LINE trimpot is accessible by means of a small screwdriver from the front panel ofthe module. It is used to set the correct sensitivity of either line input or the directaudio input. It is factory preset to give 60% of rated deviation with an input of 0dBm(1mW on 600Ω, equivalent to 775mV RMS or about 2.2V peak-to-peak) at 1kHz. Bythis means an input sensitivity from approximately -12dBm to +12dBm may beestablished.

An internal, software selectable, option, provides an extra gain step of 20dB. This,effectively changes the input sensitivity to –32 to –8dBm.

LED Flash Cadence Fault Condition

9 flashes, pause External PA failure – reason unknown

8 flashes, pause Low dc supply on External PA

7 flashes, pause External PA Over Current Condition

6 flashes, pause External PA Over Temperature

5 flashes, pause One or both synthesizers could not lock.

WARNINGChanges or modifications not expressly approved by RFTechnology could void your authority to operate thisequipment. Specifications may vary from those given in thisdocument in accordance with requirements of local authorities.RF Technology equipment is subject to continual improvementand RF Technology reserves the right to change performanceand specification without further notice.

5

4 flashes, pause Either PLL is near its operational limit

3 flashes, pause Unable to communicate with the External PA.

2 flashes, pause The current channel is not programmed or the channelfrequency is out of range.

1 flash, pause Low dc supply voltage

LED ON continuously Transmitter timed out

Table 1: Interpretations of LED flash cadence (TX LED Off)

LED Flash Cadence Fault Condition

9 flashes, pause External PA failure (if PTT is pressed)

8 flashes, pause Low dc supply on External PA (if PTT is pressed)

7 flashes, pause External PA Over Current Condition(if PTT is pressed)

6 flashes, pause External PA Over Temperature(if PTT is pressed)

3 flashes, pause Forward Power Out of Range(if PTT is not pressed)

2 flashes, pause Reverse Power ratio exceeded.

1 flash, pause Low dc supply voltage

LED ON continuously Transmitter timed out

Table 2: Interpretations of LED flash cadence (TX LED On)

1.1.3 POWER LEDThe PWR LED shows that the dc supply is connected to the receiver and that themicroprocessor is not being held in a RESET state.

1.1.4 TX LEDThe TX LED illuminates when the transmitter is keyed. It will not illuminate (and anALARM cadence will be shown) if the synthesizer becomes unlocked, or the outputamplifier supply is interrupted by the microprocessor.

1.1.5 ALARM LEDThe Alarm LED can indicate several fault conditions if they are detected by the self testprogram. The alarm indicator shows the highest priority fault present. See Tables 1and 2.

2 Transmitter OptionsThere are NO internal jumpers in the T50.

There are many software selectable options. Some options are selected on a per channelbasis, and some are defined globally (i.e. the parameter is fixed irrespective of whichchannel is selected). Below is a description of these global parameters

2.1 Ser ial I/O Parameter sThere are two serial ports. There is the main serial port which is brought out to the frontpanel connector. This is referred to as PORT0. There is another serial port which is forfactory use only. It is referred to as PORT1.

The baud rate, can be defined for PORT0. PORT0 is set by default to 57.6Kbps, withNo parity.

6

2.2 LINE TerminationsThere are two main audio inputs, plus a direct audio (TONE) input. The direct audioinput is a High Impedance Balanced DC input, but the two audio inputs are AC coupled(> 10Hz) inputs which can be High Impedance(HiZ), or 600 ohm inputs. Each inputcan be software selected to be HiZ, or 600 ohms.

2.3 Exciter Low Battery LevelThis is factory set to 24.0V, and defines the level of the DC supply that will cause anExciter dc supply low alarm.

2.4 External PA Parameter sThere are several user definable parameters associated with the external PA providedwith each exciter.

These are the PA low battery alarm level (default is 26V), the PA Set Forward PowerLevel (defaults to 100W), the Forward Power Low Alarm Level (defaults to 90%), andthe Reverse Power Alarm Level (defaults to 25% - corresponding to a VSWR of 3:1).

2.5 Generate LOOPNormally the transmitter will key up if dc current is sensed flowing in either directionbetween Line1+ and Line1- (>=1mA). If the LOOP_VOLTS option is set to its non-default setting, then a 12Vdc supply is applied to the pair through 660 ohms of sourceimpedance. (It would be expected, normally, that if this option is selected, then theoption to remove the 600 terminator from Line1, would also be selected). If dc currentflows from having applied this potential, then the transmitter will key up.

2.6 External TONE InputNormally any signal applied to the TONE+/TONE- pair is ignored. If this option isselected, then a Direct Audio input will be mixed with any audio received on either ofthe other two lines, and with any CTCSS tones, or DCS codes being generated.

2.7 External Tone High Pass Filter BypassNormally the Direct Audio, and the CTCSS/DCS outputs are passed through a 250Hz,low pass filter. This filter can be bypassed by selecting this option.

2.8 Transmit TimeThis parameter defines a maximum time limit for continuous transmission. It isexpressed in seconds and can be arbitrarily large (months in fact). If it is set to zeroseconds, then the transmitter can stay keyed up permanently.

2.9 Channel Select Over r ideThis parameter allows the user to override the channel number that is read in viaconnector P3. Normally it is InActive, but if it is set to a value from 0 to 255, then theexciter will behave as though that channel was hard-wired at the rear.

2.10 CWID Star t DelayIf CWID (Continuous Wave Identification) is enabled, then this value indicates the timein tenths of a second, from keying up an exciter to when the first station identication

7

message is sent. If this timer value is negative, then CWID transmission is disabled.This feature is only available on models from Rev. 4.

2.11 CWID Per iodIf CWID (Continuous Wave Identification) is enabled, then this value indicates the timein tenths of a second from one transmission to the next. If the value is zero, then theCWID message is transmitted only once. This feature is only available on models fromRev. 4.

2.12 CWID MessageThis parameter allows the user to specify the message string to be transmitted as thestation ID. This feature is only available on models from Rev. 4.

2.13 Channel Selectable Parameter sEach channel defines two complete set of parameters. One set of parameters is usedwhen a transmitter keys up from the PTT-in input, and the other set is used when thetransmitter keys up from the LOOP-in, the PTT switch, or the microphone PTT input.

Each set defines what frequency to use, what CTCSS sub-tone (if any) to use, whatmaximum line deviation to use, what tone deviation to use, what transmit delay (a delayapplied from PTT-in or LOOP-in to transmission), what transmit tail (delay from PTT-in, or LOOP-in, to transmission being stopped, and No-TONE period (a period of extratransmission in which No Tone is applied after PTT-in or LOOP-in has been released.

As well as these parameters, which Line (or Lines) can be selected, and whether thelines should have flat frequency response or have pre-emphasis applied. Also, it canenable or disable, the extra 20dB gain pad.

Note that both Line1 and Line 2 can be selected (each with or without pre-emphasis),and if so, then the two signals will be mixed, and the Line potentiometer will adjust thelevel of them both.

3 Transmitter I/O Connections

3.1 25 Pin ConnectorThe female D-shell, 25 pin, connector is the main interface to the transmitter. The pinconnections are described in table 3.

Function Signal Pins Specification

dc power +28Vdc(in)

0 Vdc

+5Vdc(out)

+12Vdc(out)

Vref

13, 25

1, 14

17

15

4

+24 to 32 Vdc

Common Voltage

Output for external Logic(100mA)

Output for an external relay(120mA)

Reference voltage for Tests

SerialCommunications

SCLK

MOSI

CH_EN

PA_CS

12

6

18

24

Serial Clock

Bi-directional Data Pin

Enables Channel Select Shift Register

Enables PA A/D chip

8

SPARE_SEL 5 Spare Select (for future use)

600Ω/HiZ Line Line1+

Line1-

8

19

Transformer Isolated Balanced 0dBmInput

600Ω/HiZ Line Line2+

Line2-

10

22

Transformer Isolated Balanced 0dBmInput

Direct PTT input 11 Ground to key PTT

T/R Relay driveroutput

23 Open collector, 250mA /12V

Sub-Audible ToneInput

Tone+

Tone-

9

21>10kΩ, dc coupled

Table 3: Pin connections and explanations for the main 25-pin, D connector.

3.2 9 Pin Front Panel ConnectorThe female D-shell, 9 pin, front panel connector is an RS232 interface for serialcommunications to a terminal, a terminal emulator, or to a computer. The pinconnections are described in table 4.

Function Pins Specification Pin name on IBM PC

TXD 2 Transmit Data (Output) RxD

RXD 3 Receive Data (Input) TxD

RTS 8 Request To Send (Output) CTS

CTS 7 Clear To Send (Input) RTS

DTR 6 Data Terminal Ready(Output) DSR

DSR 1 Data Set Ready (Input) DCD

GND 5 GND GND

Table 4: Pin connections for the front panel 9 pin D connector.

The pinout for the connector has been chosen so that a straight-through BD9 male toDB9 female cable can connect the transmitter to any male DB9 serial port on an IBMPC compatible computer.

Note that for connection to a modem, a cross-over cable will be required.

4 Channel Programming and Option SelectionChannel and tone frequency programming is most easily accomplished with RFTechnology WinTekHelp software. This software can be run on an IBM compatible PCand can be used to calibrate a T50, R50, and PA50 as well as program channelinformation. See the WinTekHelp manual for further information.

9

5 Circuit Descr iptionThe following descriptions should be read as an aid to understanding the block andschematic diagrams given in the appendix of this manual.

There are 9 sheets in the schematic in all.

5.1 T50 Master Schematic (Sheet 1)Sheet 1, referred to as the “T50 Master Schematic”, is a top level sheet, showing fivecircuit blocks, and their interconnection with each other, as well as the interconnectionwith all connectors and external switches.

JP12 is the connector, on the printed circuit board, for the microphone input.

P3 represents the rear female DB25 connector.

J1 is the nominal 1W RF output (BNC) connector, which is used to connect to theExternal Power Amplifier.

J4 is an optional BNC connector for an external reference clock. If an externalreference clock, with power level from +5 to +26dBm is attached here, the firmwarewill automatically track the channel VCO to the reference.

Note that the external reference frequency is limited to:

500kHz, or any multiple

any multiple of 128KHz greater than or equal to 512kHz

any multiple of 160KHz greater than or equal to 480kHz

and cannot be greater than 10MHz in Rev 4 or older versions. In Rev 5, the externalfrequency can be as high as 20MHz.

P1 is the front panel DB9 RS-232 connector for attachment to a terminal, a terminalemulator, or to an IBM PC running the WinTekHelp software.

JP2 is for the attachment of an LCD display module. This has been included for laterdevelopment. This connector, is not normally fitted

JP3, and JP4 are specialised connectors for test and factory configuration use only.

RV100 represents the front panel LINE potentiometer.

SW1 represents the PTT test pin.

D102, D103, and D104 represent the three front panel LEDs.

5.2 Microprocessor (Sheet 2)Sheet 2 describes the basic microprocessor circuitry.

The core CPU is the Motorola XC68HC12A0. It is configured in 8 bit data widthmode.

The CPU is clocked by a 14.7456MHz crystal oscillator circuit (top left) comprising theJFET Q202, and two switching transistors Q203 and Q204.

The CPU contains an 8 channel A/D converter whose inputs are identified as AN0,AN1, …, AN7.

AN7 and AN6 are used as LOCK detect inputs from the two Phase Locked Loop (PLL)circuits (see 5.6)

AN5 is used to sense whether or not the dc supply is within spec or not.

10

AN4 is multiplexed between the LINE control potentiometer and the Channel referencecrystal’s temperature sense. Which analogue input drives this analogue input, is definedby the state of TEMP_LEVEL_IN which is a CPU output signal.

AN3 and AN1 are inputs from the PLL circuits that sense the bias voltage on the VCOcontrol varactor for each VCO.

AN2 is used to sense the average peak voltage of the audio input.

AN0 is used to sense the average peak voltage of the RF output.

FRDY is an output from the flash. It goes low when the Flash starts to write a byte ofdata, or erase a block, or erase the whole chip, and it returns to its default high statewhen the action requested has completed.

FPSW1 is the switch input from the PTT Test pin.

FPSW2, and FPSW3 are two pins that have been reserved for future use as switchinputs.

LOOP/VOLTS_SEL is a CPU output that when high applies 12V of dc feed to theaudio output.

TONE_DEV_U/D and TONE_DEV_INC are CPU outputs that are used to control thedigital potentiometer that sets the TONE deviation level. (see 5.5)

EXT_TONE_SEL is a CPU output that when low enables differential analogue inputfrom the TONE+/TONE- pair. (see 5.5)

LINEINP_ADSEL is a serial bus select pin. It selects the quad Digital to Analogueconverter (DAC) that sets the levels for the two Line input Voltage ControlledAmplifiers, the output RF power amplifier bias voltage, and the LCD bias circuit. (see5.4)

LINEINP_DSEL is also a serial bus select pin. It is used to select the shift register thatis used to control most of the analogue switches in the audio Line input circuitry, aswell as the digital POT used to set the maximum deviation level. (See 5.4)

PWR_CNTRL_HIGH is a CPU output that can be low, tri-state, or high. This adjusts,slightly, the range of the power amplifier bias circuitry allowing finer control of theoutput power level. (see 5.4 and 5.8)

CTCSS_SEL is a serial bus select pin. It is used to select the FX805 chip(U500), whichis used to generate CTCSS tones. (see 5.5)

CHAN_PLL_SEL is a serial bus select pin. It is used to select the PLL chip in theChannel PLL circuit (U604). (See 5.6)

SIGGEN_ADSEL is a serial bus select pin. It is used to select the quad DAC in the RFarea. This DAC controls the reference oscillator bias voltages, and the BALANCEvoltage controlled amplifier. (See 5.6)

CHAN_VCO_EN is a CPU output that enables (when high) the Channel VCO. (See 5.6and 5.7)

EXT_REF_DIV is a CPU timer input. It is the output of the external reference clockdivided by 3200. The software can measure what the reference frequency is, and thenuse this input to calculate the frequency error of the channel PLL reference oscillator. Itcan then adjust the channel reference oscillator to reduce this error to less than 0.3ppm.(See 5.6)

SPARE_SEL is a serial bus select. It has been reserved for future use, and has beenbrought out to the rear DB25 connector. (see 5.1)

11

CH_EN is a serial bus select. It is brought out to the rear panel and is used to interfaceto the channel encoder on the rear daughter-board. (See 5.1)

Any GPS pulses are isolated from the on-board electronics by the opto-isolator U212.The output of that opto-isolator is then connected to the GPS timer input of the CPU.This has been included for future use to be able to auto-adjust the reference oscillatorfrequencies to low, or high frequency clock pulses from an external clock reference of aGPS receiver.

TERM_EN2 and TERM_EN1 are used to enable (when low) 600 ohm termination ofLine2, and Line1 respectively. (See 5.3)

The Fo outputs from the Modulation PLL and the Channel PLL are divided by two, andthese are called FO_MOD_2 and FO_CHAN_2 respectively. They should be 200Hzsquare waves, except for brief periods when frequencies are being changed. (See 5.6)

ECLK is a pin that at start-up only, should have the CPU system clock of 7.3728MHzon it.

TX_LED, ALARM_LED, are CPU outputs that drive (when low) the TX LED, and theALARM LED on.

T/R_RELAY_H, when high, drives the T/R RELAY output low, and also enables theRF power amplifier. The T/R RELAY output can activate at least one conventional12V relay. (See 5.1)

SCLK, and MOSI are used as the core of a serial bus. SCLK is a clock pin, and MOSIis a bi-directional data pin.

PA_CS is a serial select pin. It is passed, via the rear DB25 connector to the ExternalPower Amplifier (PA). (See 5.1)

DBGTX_TTL, DBGRX_TTL are RS232 transmit and receive (TTL) data pins whichare connected to the debug port after conversion to/from RS232 compatible voltagelevels by U202 and U201.

TXD_TTL, RXD_TTL, RTS_TTL, CTS_TTL, DTR_TTL, DSR_TTL, are RS232 datapins which are connected to the main front panel serial port after conversion to/fromRS232 compatible voltage levels by U202 and U201.

PTT_uPHONE is a CPU input and it reflects the state of the PTT pin on the microphonehandset.

TONE_INT is a CPU input that comes from the FX805 (U500). This pin is used toindicate when a Tone has been decoded, or there is some other need to service theFX805. As yet, this pin is not used in the T50. (See 5.5)

LOOP_DET is a CPU pin that is asserted low if there is dc loop current detectedthrough the centre tap input of Line2. (See 5.3)

FILTER_OFF is a CPU output that is used to by-pass, when low, the low pass filter inthe Tone Input Circuitry. (See 5.5)

PTT-in is an input from the rear DB25 connector that causes the INT pin of the CPU tobe asserted (low) when 1mA of current is drawn via that pin. If PTT-in is pulled toground, through a resistance of at most 3.9kohms, it will cause INT to be asserted. If itis pulled low via a 2K2 resistor, and as many as three diodes in series, it will still causethe INT pin to be asserted. This latter example shows that quite complex diode logiccan be used on this pin.

BKGD is a bi-directional I/O pin used to communicate with the core of the CPU. It isconnected to the debug port and is utilised by specialised hardware to control the CPUexternally, even without any firmware being present in the Flash.

12

MORSE is a CPU output that can be used to generate a CWID (Continuous WaveIdentification) code. This is a 1028Hz tone which is keyed on and off in a Morse codeas a staion identifier. (See 5.4)

The RESET pin is both a low active input and a low active output to the CPU. Ifgenerated externally to the CPU, it forces the CPU into reset, and if the CPU executes aRESET instruction, this pin will be driven low by the CPU.

Whenever there is insufficient volts (< 4.65V) on pin 2 of the MC33064D (U203), itwill keep its RES output low. After the voltage has met the right level it will assert itsoutput low for another 200 milliseconds. Thus the CPU will be held in reset until VCCis at the correct level. Thus the PWR_OK LED will only light when VCC is withinspecification, and RESET has been released.

S200 is a momentary push-button switch that, when pressed, will cause the CPU to bereset.

MOD_PLL_SEL is a serial bus select pin. It is used to select the Modulation PLL chip(U602). (See 5.6)

LCD_DB7, LCD_RS, LCD_R/W, and LCD_E are reserved for interfacing to an LCDdisplay module. Note that this feature has not been implemented.

U205 is used to select whether the Flash or RAM is to be read or written.

U207 is a single supply, 5V, TSOP40 Flash chip of size 8, 16, or 32 Megabits, and isused to store the firmware.

U208 is a 1, or 4, Megabit Static RAM in an SOP-32 package, and is used for both codeand data. The code in the RAM is copied from the Flash, at start-up.

5.3 Audio Processing Section (Sheet 3)Sheet 3 is a schematic, which itself refers to two other sheets.

Sheet 3 shows how the two Line inputs go to audio transformers T300 and T301, arethen optionally terminated by analogue switches U301B, and U301C, before beingpassed to the audio input stages described by Sheet 4.

It also shows how the Direct Audio (TONE) signal is passed to the Tone circuitry (sheet5).

It also shows how dc current in Line1 will cause the opto-isolator (U300) to generatethe CPU input LOOP_DET.

Relay RL300 is used to drive current back through an externally generated dc loop,when the CPU output LOOP/VOLTS_SEL is high.

The output of the Tone circuitry and the Audio circuitry are mixed (summed) andamplified by U302. It is then passed through a high order low pass filter (3.1kHz),before being attenuated by digital POT U303.

U403D adds an extra 1.8% gain of the summed modulation signal. It effectively addsanother bit of control to the maximum deviation level.

The Digital POT (U303), in conjunction with U403D, set the Maximum deviation.

U302C then adds 6dB of gain before sending the audio to the modulator.

R317, D307, and C304, act as an average peak detector. This enables the CPU todetermine the size of signals being handled by the audio section.

13

Note that the Line inputs, and the TONE input, are protected by transils and fusesagainst accidental connection to damaging voltages. The fuses (F300, F301, and F302)are not user replaceable. They are surface mount devices and must be replaced byauthorised service personnel.

5.4 Line Input Processing Section (Sheet 4)The two audio inputs are passed, after transformer coupling, to sheet 4.

In Sheet 4, the two Line Inputs are input to a transconductance amplifier (U402A, andU402B). A transconductance amplifier is a current controlled, current amplifier, i.e. itamplifies input current, but its level of amplification is controlled by the level of currentthat is injected into pin1 (or pin16). By converting a DAC output into a current, andconverting the input voltage into an input current, U402A and U402B are converted intoVoltage Controlled, Amplifiers(VCAs).

Two of the DAC outputs are converted to currents by U400B, U400C, Q401, and Q400,and these currents are used to control the gain of the transconductance amplifiers.

The input voltages are converted to current by the input load resistors R402, and R403.

The output currents are converted to voltages by resistors R420 and R424.

The outputs of the transconductance amplifiers are buffered by the darlington buffersprovided with the amplifiers (U402C, and U402D).

The output of each VCA is then amplified by U405B and U405C respectively.

The level of amplification of each VCA is adjusted in software in accordance with anyadjustments made to the LINE POT. The software converts the linear range of theLINE POT into a logarithmic scale, such that if the LINE POT is wound down to zero,the amplification of each VCA is reduced by 12db relative to its centre position.Similarly if the POT is wound to its maximum position, both amplifiers increase theirgain by 12dB.

The outputs of these amplification stages are then attenuated. Analogue switchesU404A and U404Bare used to select which attenuation circuit is used for Line 2, andU404D and U404C are used to select which attenuation circuit is used for Line 1.

If the resistive divider formed by R425, R426, and R439 is selected then the Line 2audio signal frequency response is unaffected (it is Flat). If the reactive divider definedby C402, R431, and R439 is selected, then higher frequencies of the Line 2 audio signalare attenuated less than lower frequencies, i.e. Pre-emphasis is applied to the audiosignal.

Line 1 has an identical circuit.

The outputs of these pre-emphasis/flat frequency response attenuators are then bufferedby U405A, and U405D respectively.

The microphone input is amplified by U400D, after being limited by D400. It is passedthrough a pre-emphasis network (defined by C404, R433, and R436), and is enabled, ordisabled by switch U403A.

The outputs of the Line 1 conditioning circuit, the Line 2 conditioning circuit, and themicrophone input amplifier, are then mixed (summed) and amplified by U407A. Itsoutput is, in turn, amplified by U407B, but the gain of U407B is either 2.7 or 27depending on the state of analogue switch U403B.

The CPU is capable of injecting a signal into the audio path. This can be achieved viathe MORSE output. This is partially filtered by R446 and C421. C420 provides DC

14

isolation, and R446, and R448 set the level to be approximately 30% of maximumdeviation.

The output of U407B is passed (signal LINE_INP) to the Line Level Sense circuitry(sheet 3) so that the CPU can determine the input line level.

U407B’s output is also passed to the limiter defined by D402, and D401. ResistorsR442, and R444 are used to “soften” the clipping, i.e. to “round off” the edges as thevoltage hits the clipping levels. This reduces the level of the lower order harmonicsproduced.

U407C then buffers the output for mixing with the tone output circuitry.

The PWR_CNTRL_RAW DAC output is used to control the bias to the on-board RFamplifier (see Sheet 8). The CPU output pin PWR_CNTRL_HIGH is effectivelysummed with the DAC output to define three control ranges:

State of PWR_CNTRL_HIGH PWRCNTRL Voltage Range

TriState 2.98 – 5.86

Low (0V) 0.6 – 3.0

High (5V) 3.55 - 5.96

Table 9: Power Control Ranges.

Note that in practice only the first two power ranges are used.

U401 is an octal shift register and octal latch combined. When there is a rising edge onLINEINP_DEN, the 8 shift register outputs are latched into the octal latch. The outputsof the octal latch are the outputs Q0 to Q7. Thus the last 8 data bits clocked onto MOSI,by SCLK, before LINEINP_DEN is clocked high, will appear on Q0 to Q7.

U406 is a quad 8 bit DAC. The CPU communicates with the DAC via SCLK, MOSI,and the select signal LINEINP_ADSEL, which is low when the DAC is selected.

U302B is used to convert the DAC output into a bias level for the LCD. Note that, atthis stage, the LCD display option is not developed.

5.5 Tone Generation Section (Sheet 5)U500 is a CTCSS tone encoder and decoder. The integrated circuit is also capable ofgenerating DCS signals.

The CPU accesses U500 via the serial bus using MOSI, SCLK, and the low activeSelect signal CTCSS_SEL.

The output of the tone generator is mixed (summed) with any signals that are allowedthrough analogue switch U301D.

U502 is set up as a balanced differential amplifier. The resistors R530, R531, R508,R509, R510, R532, R533, and R511, are precision resistors to improve the CMRR ofthe differential amplifier.

U502A amplifies, as well as mixes, the two audio inputs, and its output is either passedthrough a low pass filter (at 250Hz), or not, depending on the state of analogue switchU301A.

The output of U502C is then attenuated by a digital POT, before being buffered byU502D.

15

The digital POT performs two functions. It is used to help set the maximum CTCSStone deviation. It does this in conjunction with U500, as it is also possible for theCTCSS tones that are launched by U500 to be adjusted using software.

The second function of the digital POTs is enabled when U301D is enabled. The levelof attenuation by the digital POT is adjusted as part of the calibration procedure to setthe tone deviation caused when a signal is applied to the tone input.

R526, D502, and D503, form a limiter, that prevents any signal arriving from the TONEpair from ever exceeding 3kHz deviation.

5.6 Frequency Synthesiser (Sheet 6)This circuit also includes Sheet 7 as a block diagram. Sheet 7 contains the schematicfor the two Voltage Controlled Oscillators.

There are two complete Phase Locked Loops. One is called the Modulation PLL, andthe other is referred to as the Channel PLL.

The Modulation PLL does change frequencies slightly, but by less than +/- 240kHz.

The Channel PLL is the principal PLL that changes frequencies when the exciterchanges frequency.

As its name suggests, modulation is performed on the Modulation PLL.

The modulation is a conventional 2 point FM modulation. Modulation by signals,whose frequency components are well below the PLL loop frequency, is effected bymodulating the reference oscillator of the Modulation PLL. Frequencies well above thePLL loop frequency are effected by modulating the Modulation VCO directly, andfrequencies in the cross-over region are a combination of the two.

The heart of this schematic are the two PLL chips U602, and U604.

Each is, in fact, a dual PLL chip, but only one PLL, in each, is used. All that is used ofthe second PLL chip is its dividers. The outputs of these dividers can be switched to theFoLD output pin, which is then converted to a square wave by a further division of 2 byU606A and U606B.

By using the second PLL’s dividers it is possible to divide the reference oscillator, andthe VCO output down to frequencies that can be handled by the Timer inputs of theCPU, without causing excessive interrupt load to the CPU.

5.6.1 The Modulation PLLU602 and the Modulation VCO (see Sheet 7) form the modulation PLL. U602 acts asits own crystal oscillator for its reference oscillator. X600 is a 5ppm, 12MHz, crystal.Its resonant point is adjusted by the bias applied to varactor D600.

The bias applied to varactor D600 is a combination of the potentials at two DACoutputs (MOD_ADJ and MOD_ADJ_FINE), plus the modulating signal arriving atMOD_IN (which is the same signal as MOD_OUT in Sheet 3).

The summing of these three voltages is performed by U607.

The Phase detector output of the PLL chip is then passed through the loop filter networkdefined by C612, R618, C625, R617, C613, and C718 (see Sheet 7). L713 is used tofilter out any residual noise (outside of the audio bandwidth), including the phasedetector frequency, and/or any switch-mode noise from the dc voltage rails.

The loop filter signal is then fed as a control voltage to the Modulation VCO(MOD_PLL_IN).

16

The output of the Modulation VCO is connected back to the PLL for phase detection viasignal path MOD_VCO_OUT.

The phase detector output is also buffered and attenuated for the analogue input of theCPU. This is the function of U600, R622, and R625. In this way the CPU can monitorthe VCO bias to ensure that it is within specification (>0.5V, and < 4.5V).

The FoLD pin, of U602, can be used for many purposes. It can be connected to theoutput of any of the 4 internal dividers, or be used as a LOCK-DETECT monitor, or asa user programmable output pin. In this circuit it is used as a LOCK-DETECT outputwhen the frequency is being changed, but otherwise it is connected internally to theunused reference divider of U602, to deliver a 400Hz pulse train to FoLD.

U602 is set up with a phase detector frequency of 20kHz.

5.6.2 The Channel PLLU604 and the Channel VCO (see Sheet 7) form the Channel PLL. U604 acts as its owncrystal oscillator for its reference oscillator. X601 is a 5ppm, 12MHz, crystal. Itsresonant point is adjusted by the bias applied to varactor D601.

The bias applied to varactor D601 is adjusted by the CHAN_ADJ DAC output.

The Phase detector output of U604 is then passed through the loop filter networkdefined by C622, R620, C626, R619, C623, and C725 (see Sheet 7). L718 is used tofilter out any residual noise (outside of the audio bandwidth), including the phasedetector frequency, and/or any switch-mode noise from the dc voltage rails.

The loop filter signal is then fed as a control voltage to the Channel VCO(CHAN_PLL_IN).

The output of the Channel VCO is connected back to the PLL for phase detection viasignal path CHAN_VCO_OUT.

The phase detector output is also buffered and attenuated for the analogue input of theCPU. This is the function of U608, R623, and R624. In this way the CPU can monitorthe VCO bias to ensure that it is within specification (>0.5V, and < 4.5V).

The FoLD pin, of U604, can be used for many purposes. It can be connected to theoutput of any of the 4 internal dividers, or be used as a LOCK-DETECT monitor, or asa user programmable output pin. In this circuit it is used as a LOCK-DETECT outputwhen the frequency is being changed, but otherwise it is connected internally to theunused reference divider of U604, to deliver a 400Hz pulse train to FoLD.

U604 is set up with a phase detector frequency of 31.25kHz.

The signal CHAN_VCO_EN is an output from the CPU that is used to turn on (whenHigh) or turn off (when low) the Channel VCO.

5.6.3 The External Reference DividerThe external Reference Input (EXT_REF_IN) is buffered by an attenuator networkformed by R628,R633, and R630 in parallel with R635. This also forms a 50 ohmtermination network for the reference input.

R628 is a 1 watt resistor, and so, in theory levels as high as +30dBm can be accepted.To be safe, though, the largest signal that is approved to be accepted is +26dBm.

Q600 is set up as a switching transistor, and with a sufficiently high input signal level (>+5dBm), it will clock U605.

U605 is set up as a divide by 128 circuit, and its output is then divided by U606 by 25.

17

The two unused, divide by two, stages of U606 are then used to convert the 400HzFoLD pulse trains into 200Hz square waves for the Timer inputs of the CPU.

5.6.4 The DACU601 is a quad DAC. It is programmed by the CPU via the serial bus (SCLK andMOSI). It is selected by the low active signal SIGGEN_ADSEL.

Three of its outputs are used to adjust the reference oscillators.

In the presence of an external reference oscillator, the software will automatically trackthe channel VCO to the external clock.

The modulation reference oscillator is always tracked as closely as possible to theChannel reference oscillator. Because of this need for very close tracking, two DACoutputs are summed. In this way, the CPU is given coarse, as well as fine control.

The CPU can sense a phase difference of 136ns in 4 seconds, i.e. as little as 0.034ppmbetween the two PLL reference oscillators. Each step of the MOD_ADJ_FINE DACoutput will move the frequency about 2% of this amount.

The other DAC output (BALANCE) is used to adjust the BALANCE VCA (see sheet7).

The user programmable digital output of the DAC (MOD_VCO_EN) is used to enablethe modulation VCO (when High)

5.6.5 The VCOs and the RF OutputThese are more closely described in 5.7, but it is worth noting that there are threeprimary outputs of the VCOs. There is each VCO output itself, but also the signalVCO_OUT. This is the difference frequency between them.

Generally the modulation VCO is set to oscillate at 320MHz. To get an output of40MHz, the Channel VCO is set to 280MHz.

But if you wanted an output frequency of, for example, 40.00125MHz, then themodulation VCO would change to 319.78125 MHz (i.e. it drops by 218.75kHz), and theChannel VCO would become 279.78MHz (i.e. dropping by 220kHz).

By such small changes in the modulation VCO (maximum delta is +/- 240kHz), eachmultiple of 1250Hz can be accommodated, without any need to ever change the twophase detector frequencies.

5.7 Voltage Controlled Oscillator s (Sheet 7)JFETS Q704, and Q705 are the heart of two Colpitts oscillators.

The capacitor feedback divider for Q704 (modulation VCO) is defined by C732 andC733, and this shapes the negative impedance looking into the drain of Q704.

In the Channel VCO, C740 is effectively in series with Cgs of Q705. These, then definethe negative impedance looking into the drain of Q705.

L716, in parallel with L726 forms the tank coil for the modulation oscillator, and theresonant capacitance is defined by the series combination of C750 and the capacitanceacross D701. L712 has +ve reactance and it acts to reduce the minimum effectivecapacitance seen back through C750, thereby increasing the tuning range slightly.

Similarly, L719 is the tank coil for the channel oscillator, and the resonant capacitanceis defined by the series combination of C751 and the capacitance across D704. L717has +ve reactance and it acts to reduce the minimum effective capacitance seen backthrough C751, thereby increasing the tuning range slightly.

18

The VCO frequencies are controlled by the bias applied to D701 and D704 respectively,which is set by signals MOD_PLL_IN and CHAN_PLL_IN. These signals are thephase detector outputs from the Modulation PLL and the Channel VCO respectively(see Sheet 6).

Diodes D700 and D703 are used to provide some AGC for the JFETs. These Schottkydiodes will increase the –ve bias on the gate of the JFETs (thereby decreasing the drain

current) if the oscillation level should increase, and similarly the gate bias will reduce ifthe –ve peaks of the oscillation should reduce.

The Modulation bias is also adjusted by the modulation input (MOD_IN). This signal isamplified by a VCA. The BALANCE DAC output is converted to a current by U707and Q700, and that then is used to set the gain of the VCA. The output of the VCA isthen attenuated by R725/R729, and this bias is then applied to varactor D701. Note thatthe modulation bias is in anti-phase to the PLL bias.

Each VCO has its own gyrator feed circuit (Q707 and Q702). This is done to removeany possible noise on the voltage rails from modulating either VCO.

The drain current of each VCO can be switched off or on by MOSFETs Q701 andQ703. Q701 is switched on when MOD_VCO_EN is high. MOD_VCO_EN is the userprogrammable digital output from DAC U601 (see Sheet 6). Q703 is switched on whenthe CPU output CHAN_VCO_EN (see Sheet 2) is high.

The output of each VCO is “sniffed”, by a high impedance attenuator. In themodulation VCO, R737 in series with the 50 ohm input impedance of U702 forms thisattenuator. In the Channel VCO, R745, R736, and the input impedance of U706 formone such attenuator, and R741 in series with the input impedance of U703 forms theother. Note that there is a low pass filter in the front of U702, and U706 to reduce thelevel of spurious signals generated by intermod in these two amplifiers,

U702 amplifies the modulation VCO signal, which is then amplified again by U701,then filtered to reduce harmonics, before arriving at the LO input of MX700 at a level ofaround +5 - +7dBm. The output of U702 also has a low pass filter to reduce the level ofharmonics arriving at the mixer.

The output of the MOD VCO is also attenuated by R733, and then re-amplified beforebecoming MOD_VCO_OUT. MOD_VCO_OUT is then passed to the Modulation PLL(U602, see Sheet 6).

U705’s primary role is to ensure that noise that becomes coupled by the PLL chip, backonto its VCO input, does not couple back into the path to the mixer. If this isn’t done,then the mixer’s LO input contains many harmonics of the reference oscillator.

U703 performs both an amplification role, and an isolation role similar to U703’s. Itsoutput (CHAN_VCO__OUT) is fed back to the Channel PLL (U604, see Sheet 6).

The output of U706 is attenuated by the network R714, R742, and R724, and it isfiltered to reduce harmonics as much as possible. This filtered VCO output is thenbrought to the RF pin of the mixer at a level of about –19dBm.

The output of the mixer is then run through a low pass filter to remove frequencies otherthan (Fmod - Fvco). U700 then amplifies this signal to a level of about –6 to –8dBm.

The external output signal of T/R_RELAY, which is asserted low whenever the exciteris keyed up, is used to switch MOSFET Q706 off. When Q706 is off, amplifier U700 isenabled. When T/R_RELAY is high, then U700 is deprived of bias current andVCO_OUT is then completely disabled.

19

5.8 1W Broadband HF/VHF Power Amplifier (Sheet 8)The RF output of Sheet 7 (VCO_OUT) becomes the primary input to this circuit(RF_IN).

This RF input is first amplified to a level of about +2 to +4dBm by U800, then it isamplified by Q801 to about +20dBm (with full bias), and then it is amplified by Q804and Q805 to +30dBm. The output stage gain is less above about 42MHz, so that thepeak output power falls to about +26dBm at 50MHz.

The effective gain of Q801 is controlled by adjusting the bias level (PWRCNTRL).This can vary from 0.6V to nearly 6V, and is adjusted by a DAC output and a CPUdigital output, in Sheet 4.

The software monitors the forward power sense in the External Power Amplifier(PA) aswell as the Reverse Power, temperatures, drain currents etc. It does this via the serialbus (formed by SCLK and MOSI) and the select pin for the ADC converter on theExternal PA (PA_CS).

The software then automatically adjusts the PWRCNTRL bias to:

1) Keep the forward power at the level defined by parameter PA_SET_FWD_PWR(see 4.1), unless,

2) If the reverse power is > PA_SET_FWD_PWR*REV_PWR_ALARM/100.0then the forward power is reduced until the reverse power stops exceeding thislimit, or,

3) The temperature of the PA output stage FETs exceeds 120C, in which caseforward power is reduced until this stops occurring.

5.9 Power Generation Section (Sheet 9)There are three switch mode dc-dc converters in the board. These use monolithicconverters based on the National LM2595. Two of the converters are 12V convertersand one is a 5V converter.

The power in to the whole exciter is the voltage rail 28V.

U907 converts this down to 12V.

U908 is set up as an inverter, and uses the 12V rail to create –12V.

U909 converts the +12V rail to +5V for all the digital circuitry.

The +12V rail is used to power the on-board relay, as well as up to one extra off-boardrelay. It is also dropped, via a linear regulator (U910) to produce the +10V rail, whichin turn is dropped by another linear regulator U911 to produce +5Q, which, in turn, isdropped by a further linear regulator (U912) to produce +2.5V.

Similarly U913, U914, and U915 are linear regulators that produce –10V, -5V, and –2.5V from the –12V output of U908.

+10, +5Q, and +2.5V, -10V, -5V, and –2.5V rails are used in the audio and RF sections.

D911 is a 4.096V (3%) reference diode. Its output is buffered by U906 which thenproduces a reference voltage rail Vref, which is used by the CPU’s A/D converter, andthe DACs, and also in the voltage to current converters of the VCAs (see Sheet 4, andSheet 7).

20

6 FIELD ALIGNMENT PROCEDURE

6.1 Standard Test EquipmentSome, or all of the following equipment will be required:

• AF signal generator, 75 - 3000Hz frequency range, with output level set to 387mVRMS and, if the microphone input is to be tested, 10mV rms output.

• Power supply set to 28Vdc, with current >10A.

• RF 50Ω load(s), 250W rated, return loss <-20dB, and total attenuation of 50dB

• Reference Clock. At least +6dBm output.

The external reference frequency is limited to:

500kHz, or any multiple,

any multiple of 128KHz greater than or equal to 512kHz,

any multiple of 160KHz greater than or equal to 480kHz

In Rev 4 or earlier revision systems, the external reference clock is limited to 10MHz.In Rev 5 or later systems, the external reference clock can be as high as 24 MHz, andcan have an output level as low as 0dBm. The accuracy should be at least 0.5ppm,preferably 0.1ppm

• RF Peak Deviation Meter

• True RMS AC voltmeter, and a DC voltmeter.

• RF Power Meter (accurate to 2%, i.e. 0.17dB)

• Some means of measuring Reverse Power, and a known 3:1 mismatched load.

6.2 Invoking the Calibration Procedure ManuallyFrom Version 4 of the firmware, and version 1.4 of WinTekHelp, the calibrationprocedure can be performed through a Windows front end program. This isdocumented in the WinTekHelp manual.

As well as the Windows based calibration procedure, the firmware still supports theolder command prompt method, which is described in this section.

The T50 has in-built firmware to perform calibration. This firmware requests the userfor information as to meter readings, and/or to attach or adjust an AF signal generator.

The firmware based calibration program can be accessed from a terminal, a terminalemulator, or the WinTekHelp terminal emulator.

If the user selects the “Go to the Prompt Window” option from the main menu, they canmanually type commands to invoke the calibration procedure. When the exciter isready to accept commands it echoes the following prompt:

T50>

Via a terminal, or a terminal emulator, a user can type various commands in. The basiccommand to start the calibration procedure is:

T50> cal calibration_type

Where “calibration_type” is one of:

a) misc: Miscellaneous parameters are defined and calibrated

21

b) dev: Maximum deviations are set (automatically forces a “cal line” and a “caltone”)

c) line: Line1, Line 2, Dir Aud (Tone), and microphone inputs are tested andcalibrated.

d) pwr: The External PA attached to this unit is calibrated.e) ref: The reference oscillators are adjusted and calibratedf) tone: The maximum tone deviations are calibrated

6.2.1 The “ Miscellaneous” Calibration ProcedureT50> cal misc

This procedure should not normally be invoked as part of any field maintenance.

The program will print out the Model Name and Serial Number of the exciter. If theseparameters haven’t already been defined (e.g. at an initial calibration, at the factory, theservice personnel will be prompted to enter these values).

Then it will ask the operator to enter the value of Vref (as measured at TP913, see 5.9).

Measure the voltage, at TP913 (Vref)and type it on the command line...

Unless the reference diode D911 has been replaced, this should not be done. The usershould simply hit the Enter key to bypass this operation. If, though, D911 has beenreplaced for some reason, then, the reference voltage can be measured either on TP913or pin 4 of P3.

Then the exciter low battery alarm level will be asked for. If the current value isacceptable, the User need only hit the Enter key on the keyboard. If another value ispreferred, then that value can be typed in.

For example:

The Exciter's Low Battery Alarm is 24VIf this is correct enter <RET>,else enter the new value: 26

In this example, the low Battery Alarm level is changed to 26V.

Then the user will be prompted for serial port baud rates, parities etc. At present onlyNo parity and No flow control are supported. The WinTekHelp software will expect57600 BPS, and No Parity, and No Flow Control. Note well, that if you do change anyof these, the change will not take effect until you power down the exciter and thenpower it up again. (As an alternative to power cycling the exciter, and if the cover is offthe exciter, you may simply press the momentary push-button switch S200 (see 5.2).

The next thing the calibration program tests is the state of the LINE pot. The programwill ask the user to adjust this pot. If the Potentiometer is below centre, it will ask theuser to adjust it up (i.e. adjust it clockwise). If it is above centre, it will ask the user toadjust it down (i.e. adjust it counter clockwise). When the POT has been centred, or,the User hits the Enter key, the program will terminate.

This last step is normally only done as part of a factory install, and it is done to ensurethat the POT is centred before being shipped to customers. For field maintenancepurposes, the step should be skipped in order to leave the LINE POT at the settingformerly desired.

6.2.2 The “ Reference” Calibration ProcedureT50> cal ref

22

To compensate for crystal ageing and other component parameters that drift over time,the following procedure should be performed approximately once per year.

If your exciter is fitted with the external reference option (an extra BNC connector onthe rear panel), the user can connect an external reference directly to the rear BNCconnector. If the exciter does not have this option, then the top cover of the exciter

should be removed and an external reference oscillator should be connected via a 50ohm probe to J4 (just to the right of the DC voltage regulators and converters).

The external reference clock, should have a power level from +6 to +26dBm and anyfrequency that meets the following criteria:

500kHz, or any multiple, or,any multiple of 128KHz, greater than or equal to 512kHz, or,any multiple of 160KHz, greater than or equal to 480kHz.

The frequency should be 10MHz or less in Rev 4 or older versions. In Rev 5, and laterversions the frequency can be as high as 24MHz, and at power levels as low as 0dBm.

No User input is required, except to hit the Enter key when the external reference isconnected. The firmware will automatically adjust both reference oscillators, and savethe new DAC adjustments in FLASH (as parameters) to be used to centre the oscillatorseach time the unit powers up.

The user should see the following output. (Note that the temperatures, frequencies,error values, serial number, etc, indicated are examples only)

Connect an external reference input or the clock outputfrom a GPS receiver to the GPS input.Enter <RET> when this has been done.

External Reference is 10.0MHz

Ensure that the displayed reference frequency (10.0MHz in the above example) is thesame as the frequency of your oscillator.

Waiting for a GPS clock.. . . . . .

The system waits here for a GPS reference to be seen. At this stage, this method ofcalibrating the clocks has not been validated by RFT Engineering, so do not attempt touse this option.

Then the firmware continues.

Have not observed a GPS clockSystem Frequency relative to external clock is 7372654.32The crystal temperature is 32C.Waiting up to 1 minute for clocks to stabilise.. . . . . .

The crystal temperature is 32 CThe channel ref error = 1 cnts or, 1.63 HzThe mod ref error = 1 cnts or, 1.63Hz

The user may see the following error message.

The Model Name is T50_REV4and the Serial Number is RT11500Please take note of the Model, DAC values, serial number andcrystal temperature, and report this problem to RFT Engineering.

23

If a message, similar to this is seen, it indicates a potential fault condition. If the finaltext indicates that the channel and mod reference errors are within specification (the lasttext output), then the unit is able to be used, but nonetheless, it is advisable that an e-mail be sent to RF Technology indicating the problem. Such a problem may be causedby a crystal having aged to such an extent, that it is getting close to the region where itmay soon, no longer be adjusted, or that, with further degradation, the low frequencyperformance may be compromised.

As no other calibration procedure requires the top cover to be removed, you shouldreplace the cover, should you have had to remove it for this procedure.

6.2.3 The “ Deviation” Calibration ProcedureT50> cal dev

This procedure should not normally be invoked as part of any field maintenance. Theonly conceivable time that it might ever be used, would be if a non standard maximumdeviation was required.

Note that the nominal output power of the exciter’s output is 1W. Whilst the powerlevel is not set to the maximum level, the deviation meter should either have an inputpower rating of at least +30dBm, or suitable attenuation is required between the exciterand the deviation meter. Note that for this test the nominal RF output frequency is37.5MHz.

The first stage begins with the following message:

This procedure sets the Balance and Max Deviation LevelsConnect an audio signal generator to the External Tone inputSet the output to be a sine wave, 3.87 V rms and 120HzDisconnect the RF connection to the PAand connect a deviation meter to the exciter's BNC output,and use a CRO to monitor the Audio output from the deviation meter.The Channel VCO Bias is 2.5VThe Modulation VCO Bias is 2.3V.

Enter + or – to increase or decrease the Balance, until theCRO signal is as symmetric as possible.

?

Here the user can hit the +, p, or P, keys to increase the Balance, or -, m, or M keys todecrease it. In response, the firmware, which has opened up the maximum deviationdigital POT (U303) to maximum gain, will adjusted the Balance VCA accordingly.

This test applies a very high level to the External Tone Input which becomes “saturated”by the limiter for the Tone input. The result is a square wave with a slight ring on theedges. The ringing is caused by the elliptical filter used as a 3kHz low pass filter.

If the modulation balance is not working properly, the top edges of the resultingmodulated signal will be slewed.

Then the firmware will make the following request.

change the signal input to Line 1, and adjust the frequency till thedeviation peaks

When this has been done, the User needs to hit the Enter key, and the following willappear again.

Enter + or - to increase or decrease the deviation,and <RET> when the deviation is 5kHz

24

?

In response to the +, or – keys (or m, p, M, or P), the firmware adjusts the deviationdigital POT. The user should do this until the deviation is about 200Hz below the valueshown.

The firmware will now repeat this for the following standard deviations, 5.0kHz,4.5kHz, 4.0kHz, 3.5kHz, 3.0kHz, 2.5kHz, 2.0kHz, and 1.5kHz.

6.2.4 The “ Tone Deviation” Calibration ProcedureT50> cal tone

This procedure should not normally be invoked as part of any field maintenance.

Note that if the deviations are calibrated, then this procedure will be automaticallyinvoked.

This procedure is similar to the maximum deviation procedure (See 6.5). The Line 1and Line 2 audio paths are turned off for this procedure, as is the Direct Audio (TONE)input. The only signal sent to the modulator is a tone of 107.2Hz.

The program starts off, with the following message:

This procedure sets the maximum tone deviations for aMax Deviation of 5kHz. Note that the actual maximumtone deviations automatically scale with the Max Deviation.eg a 500Hz tone deviation would be a 250Hz tone deviationwhen a 2.5kHz Max Deviation was chosen.Disconnect the RF connection to the PA,and connect a deviation meter to the exciter's BNC output.The audio is being switched off, and 107.2Hz tone generated

Thence a procedure that is almost identical to that used for setting maximum deviationsis used to set these tone deviations. There is one significant difference, though, and thatis, as well as using + (or p, or P), and – (or m, or M) keys to step the deviation up ordown, one can also use the < key, or the > key. These last two keys will step down, orup, the level of signal transmitted by U500, whereas the other keys will modify thesetting of the digital POT U503 (see 5.5).

This procedure is used to set tone deviations of 750Hz, 700Hz, 650Hz, 600Hz, 550Hz,500Hz, etc down to 150Hz.

6.2.5 The “ Line” Calibration ProcedureT50> cal line

This procedure should not be used as part of any usual field maintenance, unless anycomponent has been replaced that might affect the gain of any of the audio inputs.

Note that if the deviations are calibrated, then this procedure will be automaticallyinvoked.

The program begins:

Calibrating Line 1 and Line 2 audio levelsAttach an audio signal generator to Line 1Set the output to be a sine wave, 388mV rms and 1kHzDisconnect the RF connection to the PAand connect a deviation meter to the exciter's BNC output.Enter + or - to increase or decrease the deviation,and <RET> when the deviation is 3kHz.

?

25

This is the same mechanism that is used in 6.5 and 6.6. The user enters +, p, or P toincrease the Line 1 gain, to increase the deviation, or, -, m, or M to decrease the gain.The user hits the Enter key when the desired deviation is set.

Now attach the audio signal generator to Line 2Enter + or - to increase or decrease the deviation,and <RET> when the deviation is 3kHz

?

Again the user enters +, p, or P to increase the Line 2 gain, or, -, m, or M to decrease thegain. The user hits the Enter key when the desired deviation is set.

The firmware goes on to open the microphone audio path (note that the microphonePTT switch does not need to be depressed for this). Note also that the application of a10mV test input is a factory only test. An adequate test in field testing, would be tospeak into the microphone and see that the deviation meter responded accordingly.

Testing the microphone input.Attach an audio signal generator to the microphone input.Set the output to be a sine wave, 10mV rms and 1kHz.Ensure that the deviation is between 2.7 and 3.3kHzEnter <RET> when measurement complete.Alert Engineering if there is a failure.

Then the Direct Audio input (with the low pass filter off) is tested.

Testing the Tone input.Attach an audio signal generator to the Tone input.Set the output to be a sine wave, 129mV rms, and 1kHz.Enter + or - to increase or decrease the deviation,and <RET> when the deviation is 1kHz

?

And then user then follows the same procedure as defined for setting the Line 1 andLine 2 gains.

6.2.6 The “ Power” Calibration ProcedureT50> cal pwr

All Power Amplifiers are calibrated ex-factory. All the important parameters, such asthe forward and reverse power sense adjustment, and drain bias settings are notdependent on the exciter, and thus any factory calibrated PA50 power amplifier can beconnected to, and work correctly with any T50 exciter. The frequency range of theamplifier is defined by three jumper settings on the external PA, which the CPU can

detect. Thus the CPU knows (on power up) what frequencies are, or are not, possible tobe used with the PA.

The exciter may store some PA specific parameters, such as the Serial Number of thePA, and also some offset values for the pre-amp drain current, and the output stagedrain current. These latter offsets improve the accuracy of the over current alarmtesting, (but are not strictly necessary). In order to set these parameters, it is advisedthat this procedure be performed every time an exciter is used with a new ExternalPower Amplifier. Note that many of the stages can be skipped if they have beenperformed before.

The program begins:

26

This procedure is used to calibrate an External Power Amplifier.The existing PA's SERIAL NO is: 002356Enter the new PA serial no:

Simply hit the Enter key here if the Serial Number is correct.

Take the lid off a PA, and set all threebias Pots (R238,R239, and R240) fully clockwise.Enter <RET> when done.Now we will set the Bias currents in the PA.Attach power to the PA.Each mV read across TP100(+ve lead), and TP101(-ve lead),corresponds to 1mA of 1st stage Bias current.For power control in the range 50 - 150W,set the 1st stage bias to 35 - 40mA.For power control in the range 20 - 60W, use a bias of 15 - 20mA.Attach the millivoltmeter, andadjust R238 for the bias required.

Unless one of the RF power transistors has been replaced, the user should simply skipthese last four stages by hitting the Enter key four times.

Attach the Power Amplifier to the Exciter,and ensure the PA is powered up.Attach the PA output to a reflectometer, the reflectometer to a 50dB(nominal) attenuator, and the attenuator to a calibrated powermeterEnter <RET> when this has been doneAdjust C209 in the Power Amplifieruntil there is a minimum in the dc voltage measured at TP204Enter <RET> when done.Adjust the Forward Power Sense POT (R228) untitthe measured output power (adjusted for the attenuator andreflectometer losses) is equal to the Preset Forward Power.Enter <RET> when done.

Unless something has been modified in the power sense circuits, these last three stagesshould be skipped by simply hitting the Enter key three times.

This next step allows the firmware to compute an offset in the output stage draincurrent, so that the exciter’s ability to measure the output stage drain current issignificantly more accurate.

Measure the voltage across TP102(+ve lead)and TP103(-ve lead), and enter the value measured

This next step allows the firmware to compute an offset in the pre-amp stage draincurrent, so that the exciter’s ability to measure the pre-amp stage drain current issignificantly more accurate.

Measure the voltage across TP100(+ve lead)and TP101(-ve lead), and enter the value measured

The next two stages can be skipped by simply hitting the Enter key twice.

Attach the reflectometer to an open circuitEnter <RET> when this has been doneAdjust the Reverse Power Sense POT (R227) until

27

the displayed reverse power equals 50W.Enter <RET> when this has been done.

This then completes all the calibration procedures.

7 SPECIFICATIONS

7.1 Overall Descr iptionThe transmitter is a frequency synthesized, narrow band, HF/VHF, FM unit, used todrive an external 120 watt amplifier. All necessary control and 600 Ω line interfacecircuitry is included.

7.1.1 Channel CapacityAlthough most applications are single channel, the T50 can be programmed for up to256 channels, numbered 0-255. This allows a network administrator to program everyexciter, in every site, the same way. By setting each site up to select which of the 256channels is appropriate, any exciter can be plugged into any position, in any site,without the need to perform on-site re-programming. This can be convenient inmaintenance situations.

Channel information consists of two independent and complete sets of information,which may differ or be the same. One set defines the parameters to be used, if the unitis keyed up from PTT-in being “grounded”, and the other set defines the parameters tobe used if the unit is keyed up for any reason other than PTT-in being “grounded”.

The parameters that can be defined on a per channel basis are:

a) The frequency

b) The CTCSS tone (if any) to be generated, or, the DCS code (if any) to begenerated.

c) The delay from the initiation of the exciter to RF output being generated(Is specified in hundredths of a second, 0 – 999)

d) The transmit tail; the length of time after the exciter is released beforetransmission stops. (Is specified in seconds 0 – 999).

e) The No Tone period; a length of time after the expiry of (d) in whichtransmission continues, but with no tone being generated. (Is specified intenths of a second, 0 –999)

f) Whether audio from Line 1, or Line 2, or both, (or neither!) is enabled,and whether or not Pre-emphasis is required, or not, on each line, andwhether or not an extra gain pad (of 20dB) is required.

g) What Nominal Tone Deviation, and Maximum Deviation should be used(See Tables 7 and 8)

7.1.2 CTCSSFull EIA subtone Capability is built into the modules. The CTCSS tone can beprogrammed for each channel. This means that each channel number can represent aunique RF and tone frequency combination.

7.1.3 DCSFrom Rev. 4 hardware and Rev. 4 firmware, support for DCS codes is supported. DCScode generation can be enabled on a per channel basis. If enabled, the 23 bit Golay

28

code containing the selected DCS code word will be generated continuously after theexciter is keyed up.

7.1.4 Channel ProgrammingThe channel information is stored in non-volatile memory and can be programmed viathe front panel connector using a PC, and/or RF Technology software.

7.1.5 Channel SelectionChannel selection is by eight channel select lines connected to the rear panel thatmounts on the rear DB25 female connector.

A BCD active high code applied to the lines selects the required channel. This can besupplied by pre-wiring the rack connector so that each rack position is dedicated to afixed channel. Alternatively, thumb-wheel switch panels are available.

By redefining “illegal” BCD codes, users can also encode channels from 100 – 255.

7.1.6 MicroprocessorA microprocessor is used to control the synthesizer, tone squelch, PTT functions,external reference monitoring, calibration, fault monitoring and reporting, output powerlevel control, volume adjustment, line selection, option setting, and facilitate channelfrequency programming.

7.2 Physical ConfigurationThe transmitter is designed to fit in a 19 inch rack mounted sub-frame. The installedheight is 4 RU (178 mm) and the depth is 350 mm. The transmitter is 63.5 mm or twoEclipse modules wide.

7.3 Front Panel Controls, Indicators, and Test Points7.3.1 ControlsTransmitter Key - Momentary Contact Push Button

Line Input Level - screwdriver adjust multi-turn pot

7.3.2 IndicatorsPower ON - Green LED

Tx Indicator - Yellow LED

Fault Indicator - Flashing Red LED

7.3.3 Test PointsThere are no front panel test points. All important test points are monitored by thefirmware.

7.4 Electr ical Specifications7.4.1 Power RequirementsOperating Voltage - 16 to 32 Vdc

Current Drain – 0.33A Maximum, typically 0.32A Standby

Polarity - Negative Ground

29

7.4.2 Frequency Range and Channel SpacingThe T50, as a single model, covers the full band, and all channel spacing.

Frequency 25 kHz 20kHz 15kHz 12.5 kHz 10 kHz 7.5 kHz 6.25 kHz

25 - 50 MHz T50 T50 T50 T50 T50 T50 T50

7.4.3 Frequency Synthesizer Step SizeThe specified frequency can be any multiple of 1250Hz.

7.4.4 Frequency Stability±5 ppm over 0 to +60 C, standard

±12 ppm over -30 to +60 C.

7.4.5 Number of Channels256, numbered 00 - 255

7.4.6 Output powerThe T50 needs an external PA50 power amplifier.

The output power is factory set to 100W by default, the reverse power level is set tofold back the output power when the PA50 sees a load with VSWR of 3:1 or higher (i.e.when the reverse power is 25% or more of the forward power).

7.4.7 Transmit Duty Cycle100%

7.4.8 Spurious and HarmonicsLess than 0.25µW, when connected to a PA50 operating at an output power level of100W.

7.4.9 Carrier and Modulation Attack TimeLess than 36ms (Rev 3 and Rev 4).

Less than 20ms (Rev 5 or higher).

7.4.10 ModulationType - Two point direct FM with optional pre-emphasis

Frequency Response - ±1 dB of the selected characteristic from 300-3000Hz

Maximum Deviation - Maximum deviation set on a per channel basis to 1.5, 2.0, 2.5,3.0, 3.5, 4.0, 4.5, or 5.0 kHz.

7.4.11 DistortionModulation distortion is less than 3% at 1 kHz and 60% of rated system deviation.

7.4.12 Residual Modulation and NoiseThe residual modulation and noise in the range 300 - 3000 Hz is typically less than -50dB with 5kHz maximum deviation (i.e. a test level of 3kHz).

7.4.13 600Ω Line Input SensitivityAdjustable from -32 to +12 dBm for rated deviation on two symmetric, independent,transformer coupled Line inputs.

30

7.4.14 Test Microphone Input200Ω dynamic, with PTT

7.4.15 External Tone InputCompatible with all RF Technology receivers. Each unit is factory configured to give20% of maximum deviation for an external tone input of 129mV.

7.4.16 T/R Relay DriverAn open drain MOSFET output is provided to operate an antenna change over relay orsolid state switch. The transistor can sink up to 250mA. A 1W flywheel diode connectsto the 12V rail to prevent damage to the FET from inductive kick from a relay coil.

7.4.17 Channel Select Input/OutputCoding - 8 lines, BCD coded 00 – 99; illegal BCD codes used to encode channels100 – 255.

If the MSN (Most Significant Nibble) is greater than 9, then the channel number isdefined by the formula:

16*MSN + LSN;

where the LSN is the Least Significant Nibble.

If the MSN is less than 9, but the LSN is greater than 9, then the channel number isdefined by the formula:

10*LSN+MSN;

Logic Input Levels - High for <1.5V, Low for >3.5V

Internal pull up resistors select channel 00 when all inputs are O/C.

7.4.18 DC Remote KeyingAn opto-coupler input is provided to enable dc loop keying over balanced lines or localconnections. The circuit can be connected to operate through the 600Ω line.

7.4.19 PTT inAn external input that when “grounded” with at least 1mA of current, will cause theexciter to key up. The current is drawn from the PTT in input which attempts to “pullup” anything that “grounds” it. It can be “grounded” with a short to 0V, or anyresistance up to 3.9k ohm. If the resistance of the “ground connection” is less than 2.2kohms, then up to three diodes in series can be part of the grounding path. This allowssystems installers to use quite complex diode logic to enable or disable exciters.

It would normally be “grounded” by the COS output of a receiver.

7.4.20 Programmable No-Tone PeriodA No-Tone period can be appended to the end of each transmission to aid in eliminatingsquelch tail noise which may be heard in mobiles with slow turn off decoders. The No-Tone period can be set from 0-99.9 seconds in 0.1 second increments.

7.4.21 Firmware TimersThe controller firmware includes some programmable timer functions.

Repeater Hang Time(Transmit Tail) - A short delay or ``Hang Time'' can beprogrammed to be added to the end of transmissions. This is usually used in talkthrough repeater applications to prevent the repeater from dropping out between mobile

31

transmissions. The Hang Time can be individually set on each channel for 0 - 999seconds.

Time Out Timer - A time-out or transmission time limit can be programmed toautomatically turn the transmitter off. The time limit can be set from 0-10millionseconds. The timer is automatically reset when the PTT input is released. Zero secondsdisables the timer, and allows continuous transmission.

7.4.22 CTCSSCTCSS tones can be provided by an internal encoder or by an external source connectedto the external tone input. The internal CTCSS encoding provides programmableencoding of any tone, accurate to 0.1Hz, including all EIA tones, from 67.0Hz to257Hz.

7.4.23 DCS codesDCS codes can be generated. The 9 bit DCS codes can be specified as a 3 digit octalnumber and individual codes can be assigned to each channel. The exciter computes the23 bit golay code for each DCS code, which is then continuously transmitted as NRZdata at a bit rate of 134.4 bits per second when the exciter has keyed up. This feature isonly available from Rev. 4 units or later revisions.

7.4.24 CWIDCWID messages are transmitted as Morse Code streams. The transmit rate is a nominal20 words per minute. Each “dot” is a burst of 1028Hz tone at a deviation level of1.5kHz for 60ms. Each “dash” is the same tone, at the same level for 180ms.

7.5 Connectors7.5.1 RF Output ConnectorBNC connector on the module rear panel.

7.5.2 Power & I/O Connector25-pin “D” Female Mounted at the top of the rear panel

7.5.3 External Reference Connector (optional)BNC connector mounted in the middle of the rear panel connector.

32

A Engineering DiagramsThere is only one printed circuit board covering all models of the T50. There is onlyone option for this product, which is the external reference clock option. That optionadds a rear connector, and a small length of coaxial cable and a fixed coaxial cablemount to the parts list.

Unlike other products in the Eclipse range, CTCSS is no longer an option. All unitshave the ability to transmit CTCSS tones, and from Rev. 4, DCS codes.

A.1 Block DiagramFigure 1 shows the block signal flow diagram.

A.2 Circuit DiagramsFigure 2 shows the detailed circuit diagram with component numbers and values for themain (exciter) PCB. Figure 3 shows the detailed circuit diagram with componentnumbers and values for the higher-power PA variation. Figure 4 shows the detailedcircuit diagram with component numbers and values for the lower-power PA variation.

A.3 Component Over lay DiagramsFigure 5 shows the PCB overlay guide with component positions for the main (exciter)PCB. Figure 6 shows the detailed circuit diagram with component numbers and valuesfor the higher-power PA variation. Figure 7 shows the detailed circuit diagram withcomponent numbers and values for the lower power PA variation.

33

B T50 Parts List (Rev 4)

Ref Descr iption Par t #C100 Four EMI filters in a 1206 package, 100pF 34/NFA3/1100C101 Four EMI filters in a 1206 package, 100pF 34/NFA3/1100C102 Four EMI filters in a 1206 package, 100pF 34/NFA3/1100C103 Four EMI filters in a 1206 package, 100pF 34/NFA3/1100C201 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC202 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC203 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC204 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC205 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC206 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC207 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC208 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC209 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC210 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC211 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC214 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC215 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC216 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC217 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC219 3u3F SMD, Electrolytic cap, A body, 10% 42/STA1/03U3C220 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC221 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC222 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC224 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC225 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC226 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC227 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC300 22uF Electrolytic Capacitor, 35V, Bipolar 41/BP01/022UC301 22uF Electrolytic Capacitor, 35V, Bipolar 41/BP01/022UC302 2n2F Cer. Cap, NPO, 1206, 5% 46/26N1/02N2C304 3u3F SMD, Electrolytic cap, A body, 10% 42/STA1/03U3C305 10nF Cer. Cap, NPO, 1206, 5% 46/26N1/010NC306 120pF Cer. Cap, NPO, 0603, 5% 46/63N1/120PC307 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC308 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC309 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC310 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC311 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC312 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C400 15uF SMD, low ESR Electrolytic cap, C body 41/SELC/015UC401 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC402 3n3F Cer. Cap, NPO, 1206, 5% 46/26N1/03N3C403 3n3F Cer. Cap, NPO, 1206, 5% 46/26N1/03N3C404 3n3F Cer. Cap, NPO, 1206, 5% 46/26N1/03N3C405 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC406 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC407 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC408 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC409 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC410 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC411 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC412 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC413 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC414 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC415 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC416 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC417 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC418 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC419 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC420 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC421 1nF, 25V, X7R, 0603 46/63X1/001N

34

C422 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC423 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C425 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C426 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC427 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC428 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C500 22pF Cer. Cap, NPO, 0603, 5% 46/63N1/022PC501 22pF Cer. Cap, NPO, 0603, 5% 46/63N1/022PC502 Ceramic Capacitor, 16V, 1uF, X7R 45/X7R1/1U16C503 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC506 100pF Cer. Cap, NPO, 0603, 5% 46/63N1/100PC507 100pF Cer. Cap, NPO, 0603, 5% 46/63N1/100PC508 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC509 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C510 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC511 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC512 15uF SMD, low ESR Electrolytic cap, C body 41/SELC/015UC513 15uF SMD, low ESR Electrolytic cap, C body 41/SELC/015UC514 Ceramic Capacitor, 16V, 22nF, X7R,10% 45/X7R1/022NC515 100nF, 50V, NPO, TH, 5mm 47/2007/100NC516 1n2F Cer. Cap, NPO, 1206, 5% 46/26N1/01N2C600 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC601 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC602 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC603 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC604 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C605 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC606 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC607 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C608 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C609 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC610 470pF Cer. Cap, NPO, 0603, 5% 46/63N1/470PC611 1nF Cer. Cap, X7R, 0603, 10% 46/63X1/001NC612 470nF, 25V, Y5V, decoupler, 0603 46/63Y1/470NC613 Ceramic Capacitor, 16V, 220nF, X7R, 10% 45/X7R1/220NC614 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015PC615 3p3F Cer. Cap, NPO, 0603, 5% 46/63N1/03P3C616 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC617 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC619 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C620 33pF Cer. Cap, NPO, 0603, 5% 46/63N1/033PC621 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C622 470nF, 25V, Y5V, decoupler, 0603 46/63Y1/470NC623 Ceramic Capacitor, 16V, 220nF, X7R, 10% 45/X7R1/220NC624 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C625 3u3F SMD, Electrolytic cap, A body, 10% 42/STA1/03U3C626 3u3F SMD, Electrolytic cap, A body, 10% 42/STA1/03U3C627 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC628 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC629 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C630 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C631 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC634 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC635 8p2F Cer. Cap, NPO, 0603, 5% 46/63N1/08P2C636 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC637 56pF Cer. Cap, NPO, 0603, 5% 46/63N1/056PC638 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC639 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC640 8p2F Cer. Cap, NPO, 0603, 5% 46/63N1/08P2C641 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC642 100pF Cer. Cap, NPO, 0603, 5% 46/63N1/100PC643 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC644 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC645 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C646 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C649 10pF Cer. Cap, NPO, 0603, 5% 46/63N1/010PC650 10pF Cer. Cap, NPO, 0603, 5% 46/63N1/010P

35

C651 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC652 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC700 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC701 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC702 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC703 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC704 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220PC705 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220PC706 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC707 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220PC708 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220PC709 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220PC710 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC711 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC712 3u3F SMD, Electrolytic cap, A body, 10% 42/STA1/03U3C713 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC714 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC715 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC716 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220PC718 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC719 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C720 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC721 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC722 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC723 3u3F SMD, Electrolytic cap, A body, 10% 42/STA1/03U3C724 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC725 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC726 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012PC727 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012PC728 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012PC729 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015PC730 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC731 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015PC732 5p6F Cer. Cap, NPO, 0603, 5% 46/63N1/05P6C733 3p3F Cer. Cap, NPO, 0603, 5% 46/63N1/03P3C734 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012PC735 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012PC736 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC737 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC738 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC739 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC740 4p7F Cer. Cap, NPO, 0603, 5% 46/63N1/04P7C742 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC743 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC744 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012PC745 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC746 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC747 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC748 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC749 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC750 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015PC751 33pF Cer. Cap, NPO, 0603, 5% 46/63N1/033PC752 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012PC753 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC754 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC755 22pF Cer. Cap, NPO, 0603, 5% 46/63N1/022PC756 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012PC757 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047PC758 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047PC759 22pF Cer. Cap, NPO, 0603, 5% 46/63N1/022PC760 15uF SMD, low ESR Electrolytic cap, C body 41/SELC/015UC761 22pF Cer. Cap, NPO, 0603, 5% 46/63N1/022PC762 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC763 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC764 6p8F Cer. Cap, NPO, 0603, 5% 46/63N1/06P8C765 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/068PC766 10pF Cer. Cap, NPO, 0603, 5% 46/63N1/010P

36

C767 12pF Cer. Cap, NPO, 0603, 5% 46/63N1/012PC768 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015PC769 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/068PC770 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC771 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC772 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC773 Ceramic Capacitor, 16V, 1uF, Y5V 45/Y5X7/1U16C775 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC776 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC801 100nF Cer. Cap, X7R, 1206, 10% 46/3310/100NC802 1n2F Cer. Cap, X7R, 0603, 10% 46/63X1/01N2C803 1nF Cer. Cap, NPO, 0603, 5% 46/63N1/01N0C804 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/068PC805 470pF Cer. Cap, X7R, 0603, 10% 46/63X1/470PC806 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC807 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC810 100nF Cer. Cap, X7R, 1206, 10% 46/3310/100NC811 100uF Electrolytic Capacitor, 35V 41/2001/100UC820 470pF Cer. Cap, NPO, 0603, 5% 46/63N1/470PC821 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC822 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC823 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC824 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC825 220pF Cer. Cap, NPO, 0603, 5% 46/63N1/220PC826 3u3F SMD, Electrolytic cap, A body, 10% 42/STA1/03U3C827 10 uF Electrolytic capacitor 41/2001/010UC828 150pF Cer. Cap, NPO, 0603, 5% 46/63N1/150PC829 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC830 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/068PC901 100uF SMD, low ESR Electrolytic cap, D body 41/SELD/100UC902 470uF Electrolytic Capacitor, Low ESR, 35V 41/200L/470UC903 33uF SMD, low ESR Electrolytic cap, C body 41/SELC/033UC904 3u3F SMD, Electrolytic cap, A body, 10% 42/STA1/03U3C915 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC920 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC923 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC924 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC925 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC926 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC927 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC928 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC929 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC930 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC931 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC932 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC933 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC934 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC935 470uF Electrolytic Capacitor, Low ESR, 35V 41/200L/470UC936 33uF SMD, low ESR Electrolytic cap, C body 41/SELC/033UC937 100uF SMD, low ESR Electrolytic cap, D body 41/SELD/100UC938 100uF SMD, low ESR Electrolytic cap, D body 41/SELD/100UC939 100uF SMD, low ESR Electrolytic cap, D body 41/SELD/100UC940 33uF SMD, low ESR Electrolytic cap, C body 41/SELC/033UC941 33uF SMD, low ESR Electrolytic cap, C body 41/SELC/033UC942 33uF SMD, low ESR Electrolytic cap, C body 41/SELC/033UC943 33uF SMD, low ESR Electrolytic cap, C body 41/SELC/033UC944 33uF SMD, low ESR Electrolytic cap, C body 41/SELC/033UC945 33uF SMD, low ESR Electrolytic cap, C body 41/SELC/033UD102 Radially mounted LED 21/1010/LEDRD103 Radially mounted LED 21/1010/LEDYD104 Radially mounted LED 21/1010/LEDGD200 Dual Series Diode 21/3010/AV99D202 Gen. Purpose 1N4004 diode in SMD pkg 24/SMA1/4004D203 Zener Diode 21/1040/C3V3D300 Bi-directional Transil 24/TRSL/012VD301 Bidirectional Transil 24/TRSL/012VD302 Bidirectional Transil 24/TRSL/012V

37

D303 Dual Series Diode 21/3010/AV99D304 Dual Series Diode 21/3010/AV99D305 Dual Series Diode 21/3010/AV99D306 Gen. Purpose 1N4004 diode in SMD pkg 24/SMA1/4004D307 Dual Schottky, Comm. Cathode, Diode 24/3BAT/54C1D400 Dual Series Diode 21/3010/AV99D401 Dual Series Diode 21/3010/AV99D402 Dual Series Diode 21/3010/AV99D403 Dual Series Diode 21/3010/AV99D500 Dual Series Diode 21/3010/AV99D501 Dual Series Diode 21/3010/AV99D502 Dual Series Diode 21/3010/AV99D503 Dual Series Diode 21/3010/AV99D600 Varactor 21/3060/V109D601 Varactor 21/3060/V109D700 Schottky diode 21/3030/0017D701 Varactor 21/3060/V109D703 Schottky diode 21/3030/0017D704 Varactor 21/3060/V109D800 Dual Schottky, Comm. Cathode, Diode 24/3BAT/54C1D906 Power Fast Schottky diode 24/BRM1/40T3D907 Power Fast Schottky diode 24/BRM1/40T3D908 Power Fast Schottky diode 24/BRM1/40T3D909 Power Fast Schottky diode 24/BRM1/40T3D910 Gen. Purpose 1N4004 diode in SMD pkg 24/SMA1/4004D911 4.096V Reference Diode 29/VREF/0001F300 SMD (1206 pkg), 125mA fuse 39/1206/A125F301 SMD (1206 pkg), 125mA fuse 39/1206/A125F302 SMD (1206 pkg), 125mA fuse 39/1206/A125

J1 BNC Connector 35/5BNC/RA01JP12 4 Pin SIL Header 35/2501/0004JP2 14 Pin SIL Header 35/2501/0014JP3 10 pin DIL Header 35/7026/0010JP4 10 pin DIL Header 35/7026/0010

L100 Ferrite, 1206 pkg, 120 ohm, 3A 37/P034/0001L101 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L102 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L104 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L200 220uH Choke 37/3320/P103L202 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L203 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L204 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L205 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L500 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L600 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L700 27nH Inductor 37/8551/027NL701 33nH Inductor 37/8551/033NL702 27nH Inductor 37/8551/027NL703 27nH Inductor 37/8551/027NL704 47nH Inductor 37/8551/047NL705 27nH Inductor 37/8551/027NL706 330nH Inductor 37/3320/330NL708 330nH Inductor 37/3320/330NL709 330nH Inductor 37/3320/330NL710 330nH Inductor 37/3320/330NL711 330nH Inductor 37/3320/330NL712 220nH Inductor 37/8551/220NL713 1206 47R resistor 51/3380/047RL714 330nH Inductor 37/3320/330NL715 330nH Inductor 37/3320/330NL716 Inductor - Air Core, 12.5nH 37/AC51/12N5L717 100nH Inductor 37/8551/100NL719 Inductor - Air Core, 18.5nH 37/AC51/18N5L720 24nH Inductor 37/6351/024NL721 24nH Inductor 37/6351/024NL722 24nH Inductor 37/6351/024NL723 330nH Inductor 37/3320/330N

38

L724 330nH Inductor 37/3320/330NL725 3u3H Choke 37/3320/P101L726 33nH Inductor 37/8551/082NL800 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L801 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L803 Inductor - Air Core, 538nH 37/AC52/558NL804 Inductor - Air Core, 538nH 37/AC52/558NL807 220uH Choke 37/3320/P103L808 3u3H Choke 37/3320/P101L809 180nH Inductor 37/8551/180NL810 1uH Choke 37/3320/P200L811 3u3H Choke 37/3320/P101L812 150nH Inductor 37/3320/150NL813 150nH Inductor 37/3320/150NL901 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L902 SMD High Current, Shielded, 330uH Choke 37/MSP1/330UL903 SMD High Current, Shielded, 470uH Choke 37/MSP1/470UL904 SMD High Current, Shielded, 330uH Choke 37/MSP1/330UL905 Ferrite, 1206 pkg, 600 ohm, 200mA 37/P033/0001L906 Ferrite, 1206 pkg, 120 ohm, 3A 37/P034/0001L907 Ferrite, 1206 pkg, 120 ohm, 3A 37/P034/0001L908 Ferrite, 1206 pkg, 120 ohm, 3A 37/P034/0001L909 Ferrite, 1206 pkg, 120 ohm, 3A 37/P034/0001

LC700 70MHz SMD Filter, 0805 pkg 37/85LC/0135LC701 70MHz SMD Filter, 0805 pkg 37/85LC/0135LC702 70MHz SMD Filter, 0805 pkg 37/85LC/0135

M1 Tinned BeCu, used as RF screen. 94/BECU/24XHM1C RF Screen Cover (Small) 80/9209/0001M2 Conductive Foam Inserts 83/0001/0000

MX700 +7dBm0 Mixer, Surface Mount 37/MIXR/P028P1 DB9 Female with filtered pins 35/5012/009FP3 DB25 Female with filtered pins 35/5012/025F

Q200 Gen. Purpose NPN transistor in SOT-23 27/3020/3904Q201 N channel, Enhancement Mode MOSFET 27/30B5/5138Q202 N Channel Junction FET(low Freq) 27/3020/5484Q203 NPN Switching transistor in SOT-23 27/3020/2369Q204 NPN Switching transistor in SOT-23 27/3020/2369Q205 Gen. Purpose PNP transistor in SOT-23 27/3010/3906Q206 Gen. Purpose NPN transistor in SOT-23 27/3020/3904Q300 N channel, Enhancement Mode MOSFET 27/30B5/5138Q301 Gen. Purpose PNP transistor in SOT-23 27/3010/3906Q302 Gen. Purpose PNP transistor in SOT-23 27/3010/3906Q400 Gen. Purpose PNP transistor in SOT-23 27/3010/3906Q401 Gen. Purpose PNP transistor in SOT-23 27/3010/3906Q500 Gen. Purpose PNP transistor in SOT-23 27/3010/3906Q501 Gen. Purpose PNP transistor in SOT-23 27/3010/3906Q600 Gen. Purpose NPN transistor in SOT-23 27/3020/3904Q700 Gen. Purpose PNP transistor in SOT-23 27/3010/3906Q701 N channel, Enhancement Mode MOSFET 27/30B5/5138Q702 Gen. Purpose NPN transistor in SOT-23 27/3020/3904Q703 N channel, Enhancement Mode MOSFET 27/30B5/5138Q704 N Channel Junction FET(UHF) 27/3030/J309Q705 N Channel Junction FET(UHF) 27/3030/J309Q706 N channel, Enhancement Mode MOSFET 27/30B5/5138Q707 Gen. Purpose NPN transistor in SOT-23 27/3020/3904Q801 SOD-89A RF Transistor(1W) 27/300B/FQ17Q804 SOD-89A RF Transistor(1W) 27/300B/FQ17Q805 SOD-89A RF Transistor(1W) 27/300B/FQ17R100 0805, 1%, 4K7 resistor 51/8511/04K7R101 0805, 1%, 4K7 resistor 51/8511/04K7R102 0805, 1%, 4K7 resistor 51/8511/04K7R103 1206 180R resistor 51/3380/0180R104 1206 270R resistor 51/3380/0270R105 0805, 1%, 4K7 resistor 51/8511/04K7R201 0805, 1%, 10K resistor 51/8511/010KR202 0805, 1%, 10K resistor 51/8511/010KR203 0805, 1%, 10K resistor 51/8511/010K

39

R204 0805, 1%, 10K resistor 51/8511/010KR205 0805, 1%, 2K2 resistor 51/8511/02K2R206 0805, 1%, 2K2 resistor 51/8511/02K2R207 0805, 1%, 68K resistor 51/8511/068KR208 0805, 1%, 22K resistor 51/8511/022KR209 0805, 1%, 330R resistor 51/8511/330RR210 0805, 1%, 10K resistor 51/8511/010KR211 0805, 1%, 220R resistor 51/8511/220RR212 0805, 1%, 220R resistor 51/8511/220RR213 0805, 1%, 1M resistor 51/8511/01M0R214 1206 180R resistor 51/3380/0180R215 0805, 1%, 120R resistor 51/8511/120RR216 0805, 1%, 1K resistor 51/8511/01K0R217 0805, 1%, 10K resistor 51/8511/010KR218 0805, 1%, 10K resistor 51/8511/010KR219 0805, 1%, 10K resistor 51/8511/010KR220 0805, 1%, 10K resistor 51/8511/010KR221 0805, 1%, 560R resistor 51/8511/560RR222 0805, 1%, 1K resistor 51/8511/01K0R223 0805, 1%, 10K resistor 51/8511/010KR224 0805, 1%, 10K resistor 51/8511/010KR225 0805, 1%, 10K resistor 51/8511/010KR226 1206 180R resistor 51/3380/0180R227 0805, 1%, 56R resistor 51/8511/056RR228 0805, 1%, 10K resistor 51/8511/010KR229 0805, 1%, 10K resistor 51/8511/010KR230 0805, 1%, 120R resistor 51/8511/120RR231 0805, 1%, 120R resistor 51/8511/120RR232 0805, 1%, 560R resistor 51/8511/560RR233 0805, 1%, 22K resistor 51/8511/022KR234 0805, 1%, 1K resistor 51/8511/01K0R235 0805, 1%, 4K7 resistor 51/8511/04K7R236 0805, 1%, 22K resistor 51/8511/022KR237 0805, 1%, 47K resistor 51/8511/047KR238 0805, 1%, 1K resistor 51/8511/01K0R239 0805, 1%, 1K resistor 51/8511/01K0R240 0805, 1%, 10K resistor 51/8511/010KR241 0805, 1%, 47R resistor 51/8511/047RR242 0805, 1%, 47K resistor 51/8511/047KR243 0805, 1%, 220R resistor 51/8511/220RR244 0805, 1%, 10R resistor 51/8511/010RR245 0805, 1%, 10K resistor 51/8511/010KR300 0805, 1%, 27R resistor 51/8511/027RR301 0805, 1%, 27R resistor 51/8511/027RR302 0805, 1%, 27R resistor 51/8511/027RR303 0805, 1%, 27R resistor 51/8511/027RR304 0805, 1%, 330R resistor 51/8511/330RR305 0805, 1%, 330R resistor 51/8511/330RR306 0805, 1%, 10R resistor 51/8511/010RR307 0805, 1%, 4K7 resistor 51/8511/04K7R308 0805, 1%, 2K2 resistor 51/8511/02K2R309 0805, 1%, 560R resistor 51/8511/560RR310 0805, 1%, 560R resistor 51/8511/560RR311 0805, 1%, 22K resistor 51/8511/022KR312 0805, 1%, 22K resistor 51/8511/022KR313 0805, 1%, 22K resistor 51/8511/022KR314 0805, 1%, 1K resistor 51/8511/010KR315 0805, 1%, 22K resistor 51/8511/022KR316 0805, 1%, 1K resistor 51/8511/010KR317 0805, 1%, 1K resistor 51/8511/01K0R318 0805, 1%, 120K resistor 51/8511/120KR319 0805, 1%, 120K resistor 51/8511/120KR320 0805, 1%, 120K resistor 51/8511/120KR321 0805, 1%, 68K resistor 51/8511/068KR322 0805, 1%, 68K resistor 51/8511/068KR323 0805, 1%, 68K resistor 51/8511/068KR324 0805, 1%, 1K resistor 51/8511/01K0

40

R325 0805, 1%, 47K resistor 51/8511/047KR326 0805, 1%, 47K resistor 51/8511/047KR327 0805, 1%, 47K resistor 51/8511/047KR328 0805, 1%, 10K resistor 51/8511/010KR329 0805, 1%, 10K resistor 51/8511/010KR330 0805, 1%, 47K resistor 51/8511/047KR331 0805, 1%, 47K resistor 51/8511/047KR332 0805, 1%, 68K resistor 51/8511/068KR333 0805, 1%, 1K resistor 51/8511/01K0R335 0805, 1%, 22K resistor 51/8511/022KR336 0805, 1%, 22K resistor 51/8511/022KR337 0805, 1%, 1K8 resistor 51/8511/01K8R400 0805, 1%, 330R resistor 51/8511/330RR401 0805, 1%, 270R resistor 51/8511/270RR402 0805, 1%, 22K resistor 51/8511/022KR403 0805, 1%, 22K resistor 51/8511/022KR404 0805, 1%, 12K resistor 51/8511/012KR405 0805, 1%, 5K6 resistor 51/8511/05K6R406 0805, 1%, 10K resistor 51/8511/010KR407 0805, 1%, 10K resistor 51/8511/010KR408 0805, 1%, 5K6 resistor 51/8511/05K6R409 0805, 1%, 56K resistor 51/8511/056KR410 0805, 1%, 47K resistor 51/8511/047KR411 0805, 1%, 47K resistor 51/8511/047KR412 0805, 1%, 10K resistor 51/8511/010KR413 0805, 1%, 1K resistor 51/8511/01K0R414 0805, 1%, 560R resistor 51/8511/560RR415 0805, 1%, 560R resistor 51/8511/560RR416 0805, 1%, 560R resistor 51/8511/560RR417 0805, 1%, 560R resistor 51/8511/560RR418 0805, 1%, 2K2 resistor 51/8511/02K2R419 0805, 1%, 22K resistor 51/8511/022KR420 0805, 1%, 120K resistor 51/8511/120KR421 0805, 1%, 22K resistor 51/8511/022KR422 0805, 1%, 120K resistor 51/8511/120KR423 0805, 1%, 10K resistor 51/8511/010KR424 0805, 1%, 10K resistor 51/8511/010KR425 0805, 1%, 22K resistor 51/8511/022KR426 0805, 1%, 22K resistor 51/8511/022KR427 0805, 1%, 47K resistor 51/8511/047KR428 0805, 1%, 22K resistor 51/8511/022KR429 0805, 1%, 22K resistor 51/8511/022KR430 0805, 1%, 47K resistor 51/8511/047KR433 0805, 1%, 270K resistor 51/8511/270KR434 0805, 1%, 4K7 resistor 51/8511/04K7R435 0805, 1%, 1K resistor 51/8511/01K0R436 0805, 1%, 4K7 resistor 51/8511/04K7R437 0805, 1%, 47K resistor 51/8511/047KR438 0805, 1%, 47K resistor 51/8511/047KR439 0805, 1%, 4K7 resistor 51/8511/04K7R440 0805, 1%, 4K7 resistor 51/8511/04K7R442 0805, 1%, 4K7 resistor 51/8511/04K7R443 0805, 1%, 4K7 resistor 51/8511/04K7R444 0805, 1%, 4K7 resistor 51/8511/04K7R445 0805, 1%, 47K resistor 51/8511/047KR446 0805, 1%, 100K resistor 51/8511/100KR447 0805, 1%, 47K resistor 51/8511/047KR448 0805, 1%, 270K resistor 51/8511/270KR449 0805, 1%, 220R resistor 51/8511/220RR450 0805, 1%, 56K resistor 51/8511/56KR451 0805, 1%, 47K resistor 51/8511/047KR453 0805, 1%, 10K resistor 51/8511/010KR454 0805, 1%, 10K resistor 51/8511/010KR455 0805, 1%, 10K resistor 51/8511/010KR456 0805, 1%, 47K resistor 51/8511/047KR457 0805, 1%, 22K resistor 51/8511/022KR458 0805, 1%, 4K7 resistor 51/8511/04K7

41

R459 0805, 1%, 4K7 resistor 51/8511/04K7R460 0805, 1%, 4K7 resistor 51/8511/04K7R461 0805, 1%, 56K resistor 51/8511/056KR462 0805, 1%, 22K resistor 51/8511/022KR463 0805, 1%, 56K resistor 51/8511/056KR464 0805, 1%, 270K resistor 51/8511/270KR465 0805, 1%, 22K resistor 51/8511/022KR466 0805, 1%, 2K2 resistor 51/8511/02K2R467 0805, 1%, 4K7 resistor 51/8511/04K7R500 0805, 1%, 47K resistor 51/8511/047KR501 0805, 1%, 47K resistor 51/8511/047KR502 0805, 1%, 47K resistor 51/8511/047KR503 0805, 1%, 22K resistor 51/8511/022KR504 0805, 1%,1K resistor 51/8511/01K0R505 0805, 1%, 10K resistor 51/8511/010KR506 0805, 1%, 10K resistor 51/8511/010KR507 0805, 1%, 1M resistor 51/8511/01M0R508 0805, 0.5%, 50ppm,15K resistor 51/85P1/015KR509 0805, 0.5%, 50ppm,15K resistor 51/85P1/015KR510 0805, 0.5%, 50ppm,15K resistor 51/85P1/015KR511 0805, 0.5%, 50ppm,15K resistor 51/85P1/015KR512 0805, 1%, 10K resistor 51/8511/010KR513 0805, 1%, 10K resistor 51/8511/010KR514 0805, 1%, 15K resistor 51/8511/015KR515 0805, 1%, 330K resistor 51/8511/330KR516 0805, 1%, 680R resistor 51/8511/680RR517 0805, 1%, 47K resistor 51/8511/047KR518 0805, 1%, 47K resistor 51/8511/047KR519 0805, 1%, 47K resistor 51/8511/047KR520 0805, 1%, 47K resistor 51/8511/047KR521 0805, 1%, 47K resistor 51/8511/047KR522 0805, 1%, 270K resistor 51/8511/270KR523 0805, 1%, 1K resistor 51/8511/01K0R525 0805, 1%, 10K resistor 51/8511/010KR526 0805, 1%, 2K2 resistor 51/8511/02K2R527 0805, 1%, 47K resistor 51/8511/047KR528 0805, 1%, 47K resistor 51/8511/047KR529 0805, 1%, 47K resistor 51/8511/047KR530 0805, 0.5%, 50ppm,15K resistor 51/85P1/015KR531 0805, 0.5%, 50ppm,15K resistor 51/85P1/015KR532 0805, 0.5%, 50ppm,15K resistor 51/85P1/015KR533 0805, 0.5%, 50ppm,15K resistor 51/85P1/015KR534 0805, 1%, 5K6 resistor 51/8511/05K6R535 0805, 1%, 100K resistor 51/8511/100KR536 0805, 1%, 10K resistor 51/8511/10KR537 0805, 1%, 100K resistor 51/8511/100KR602 0805, 1%, 10K resistor 51/8511/010KR603 0805, 1%, 10K resistor 51/8511/010KR604 0805, 1%, 10K resistor 51/8511/010KR605 0805, 1%, 15K resistor 51/8511/015KR606 0805, 1%, 5K6 resistor 51/8511/05K6R607 0805, 1%, 5K6 resistor 51/8511/05K6R608 0805, 1%, 2K2 resistor 51/8511/02K2R609 0805, 1%, 10K resistor 51/8511/010KR610 0805, 1%, 10K resistor 51/8511/010KR611 0805, 1%, 10K resistor 51/8511/010KR612 0805, 1%, 10K resistor 51/8511/010KR613 0805, 1%, 47R resistor 51/8511/047RR614 0805, 1%, 47R resistor 51/8511/047RR615 0805, 1%, 47R resistor 51/8511/047RR616 0805, 1%, 47R resistor 51/8511/047RR617 0805, 1%, 1K resistor 51/8511/01K0R618 0805, 1%, 1K resistor 51/8511/01K0R620 0805, 1%, 1K2 resistor 51/8511/1K2R622 0805, 1%, 5K6 resistor 51/8511/05K6R623 0805, 1%, 5K6 resistor 51/8511/05K6R624 0805, 1%, 22K resistor 51/8511/022K

42

R625 0805, 1%, 22K resistor 51/8511/022KR626 0805, 1%, 2K2 resistor 51/8511/02K2R627 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150R628 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150R629 0805, 1%, 270K resistor 51/8511/270KR630 1206, 1%, 120R resistor 51/3380/120RR631 0805, 1%, 47R resistor 51/8511/047RR632 0805, 1%, 47R resistor 51/8511/047RR633 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150R634 1206, 1%, 120R resistor 51/3380/120RR635 0805, 1%, 560R resistor 51/8511/560RR636 0805, 1%, 220R resistor 51/8511/220RR637 0805, 1%, 5K6 resistor 51/8511/05K6R638 0805, 1%, 5K6 resistor 51/8511/05K6R639 0805, 1%, 10K resistor 51/8511/010KR640 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150R646 0805, 1%, 4K7 resistor 51/8511/04K7R647 0805, 1%, 10K resistor 51/8511/010KR648 0805, 1%, 4K7 resistor 51/8511/04K7R649 0805, 1%, 10K resistor 51/8511/010KR650 0805, 1%, 5K6 resistor 51/8511/05K6R700 0805, 1%, 120R resistor 51/8511/120RR701 0805, 1%, 100R resistor 51/8511/047RR702 0805, 1%, 100R resistor 51/8511/120RR703 0805, 1%, 100R resistor 51/8511/120RR704 0805, 1%, 100R resistor 51/8511/120RR705 0805, 1%, 100R resistor 51/8511/220RR706 0805, 1%, 220R resistor 51/8511/220RR707 0805, 1%, 100R resistor 51/8511/220RR708 0805, 1%, 4K7 resistor 51/8511/04K7R709 0805, 1%, 10K resistor 51/8511/010KR710 0805, 1%, 2K2 resistor 51/8511/02K2R711 0805, 1%, 10R resistor 51/8511/010RR712 0805, 1%, 56R resistor 51/8511/056RR713 0805, 1%, 10K resistor 51/8511/010KR714 0805, 1%, 56R resistor 51/8511/056RR715 0805, 1%, 10K resistor 51/8511/010KR716 0805, 1%, 47R resistor 51/8511/047RR717 0805, 1%, 10K resistor 51/8511/010KR718 0805, 1%, 100R resistor 51/8511/120RR719 0805, 1%, 10K resistor 51/8511/010KR720 0805, 1%, 100K resistor 51/8511/100KR721 0805, 1%, 330R resistor 51/8511/330RR722 0805, 1%, 22K resistor 51/8511/022KR723 0805, 1%, 10K resistor 51/8511/010KR724 0805, 1%, 56R resistor 51/8511/056RR725 0805, 1%, 5K6 resistor 51/8511/05K6R726 0805, 1%, 47R resistor 51/8511/047RR727 0805, 1%, 22K resistor 51/8511/022KR729 0805, 1%, 10R resistor 51/8511/010RR730 0805, 1%, 100R resistor 51/8511/100RR731 0805, 1%, 560R resistor 51/8511/560RR732 0805, 1%, 22K resistor 51/8511/022KR733 0805, 1%, 1K resistor 51/8511/01K0R734 0805, 1%, 4K7 resistor 51/8511/04K7R735 0805, 1%, 22K resistor 51/8511/022KR736 0805, 1%, 56R resistor 51/8511/056RR737 0805, 1%, 330R resistor 51/8511/330RR738 0805, 1%, 100R resistor 51/8511/100RR739 0805, 1%, 10K resistor 51/8511/010KR740 0805, 1%, 100R resistor 51/8511/100RR741 0805, 1%, 1K resistor 51/8511/01K0R742 0805, 1%, 220R resistor 51/8511/220RR743 0805, 1%, 560R resistor 51/8511/560RR745 0805, 1%, 330R resistor 51/8511/330RR801 0805, 1%, 12K resistor 51/8511/012KR802 0805, 1%, 100R resistor 51/8511/100R

43

R803 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150R804 1206 10R resistor 51/3380/0010R805 1206 10R resistor 51/3380/0010R806 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150R808 0805, 1%, 10R resistor 51/8511/010RR809 0805, 1%, 27R resistor 51/8511/027RR810 0805, 1%, 10R resistor 51/8511/010RR811 0805, 1%, 27R resistor 51/8511/027RR812 0805, 1%, 100R resistor 51/8511/100RR813 1218, 5%, 150R, 1W, SMD resistor 51/2851/0150R814 0805, 1%, 10R resistor 51/8511/010RR815 0805, 1%, 1K resistor 51/8511/01K0R816 0805, 1%, 10K resistor 51/8511/010KR819 7W Axial 68R resistor 55/5W51/068RR823 0805, 1%, 4K7 resistor 51/8511/04K7R918 0805, 1%, 47K resistor 51/8511/047KR919 0805, 1%, 47K resistor 51/8511/047KR920 0805, 1%, 1K resistor 51/8511/01K0R921 0805, 1%, 560R resistor 51/8511/560RR922 0805, 1%, 220R resistor 51/8511/220RR923 0805, 1%, 1K resistor 51/8511/01K0R924 0805, 1%, 680R resistor 51/8511/680RR925 0805, 1%, 220R resistor 51/8511/220RR926 0805, 1%, 2K2 resistor 51/8511/02K2R927 0805, 1%, 220R resistor 51/8511/220RR928 0805, 1%, 220R resistor 51/8511/220RR929 0805, 1%, 220R resistor 51/8511/220RR930 0805, 1%, 220R resistor 51/8511/220RR931 0805, 1%, 220R resistor 51/8511/220RR932 0805, 1%, 220R resistor 51/8511/220RR933 0805, 1%, 560R resistor 51/8511/560RR934 0805, 1%, 560R resistor 51/8511/560RR935 0805, 1%, 120R resistor 51/8511/120RR936 0805, 1%, 120R resistor 51/8511/120R

RL300 12V Telecommunications DPDT Relay 96/2000/012VRV100 100K, 11 turn, linear Pot. 53/THH1/100KS200 4mm SMD PB switch 31/SMPB/0001SW1 Omron-6x6-RA switch 31/0005/E121T300 High Isolation Audio Transformer 37/2040/5065T301 High Isolation Audio Transformer 37/2040/5065U201 Quad CMOS RS232 Driver SMD (SO-14) 29/14C8/9A01U202 Quad CMOS RS232 Driver SMD (SO-14) 29/14C8/8001U203 Under-voltage sensor and Reset Generator 29/MC33/064DU204 Motorola Embedded 8/16 bit microcontroller 29/68HC/12A0U205 One of 8 Selector 29/2030/C138U207 4 Megabyte TSOP (Std.) 5V (only) Flash 29/P006/0001U208 1,2,4 Megabit RAM in SOP package 29/SRAM/P013U212 Hi Speed, TTL compatible, opto-isolator 26/N137/0001U300 Opto-isolator with Darlington Output 25/1010/4N33U301 Quad SPST Analog Switch - low Rds On 29/00DG/411CU302 Low Power Quad Operational Amplifier 29/000L/M224U303 32 position digital pot. 29/MAX5/161LU400 Low Power Quad Operational Amplifier 29/000L/M224U401 8-bit Shift reg. with output latch 29/2030/C595U402 Transconductance Amplifier 29/0LM1/3700U403 Quad SPST Analog Switch - low Rds On 29/00DG/411CU404 Quad SPST Analog Switch - low Rds On 29/00DG/411CU405 Low Power Quad Operational Amplifier 29/000L/M224U406 Voltage Output, Quad 8 bit DAC 29/00MA/X534U407 Low Power Quad Operational Amplifier 29/000L/M224U500 CTCSS and DCS encoder/decoder 29/00FX/805LU502 Low Power Quad Operational Amplifier 29/000L/M224U503 32 position digital pot. 29/MAX5/161LU600 Gen. Purp. R2R Op. Amp. 29/1M55/P021U601 Voltage Output, Quad 8 bit DAC 29/00MA/X534U602 Dual PLL 29/LMX2/335LU603 Temperature Sensor 29/0001/LM61

44

U604 Dual PLL 29/LMX2/335LU605 Dual, Ripple Carry, 4 bit binary counter 29/2030/C393U606 Dual 4 bit, ripple carry, decade counters 29/2030/C390U607 Gen. Purp. R2R Op. Amp. 29/1M55/P021U608 Gen. Purp. R2R Op. Amp. 29/1M55/P021U700 MMIC Amplifier 24/3010/VAM6U701 MMIC Amplifier 24/3010/211LU702 MMIC Amplifier 24/3010/211LU703 MMIC Amplifier 24/3010/211LU704 Transconductance Amplifier 29/0LM1/3700U705 MMIC Amplifier 24/3010/211LU706 MMIC Amplifier 24/3010/211LU707 Gen. Purp. R2R Op. Amp. 29/1M55/P021U800 MMIC Amplifier 24/3010/211LU906 Gen. Purp. R2R Op. Amp. 29/1M55/P021U907 Simple (Buck) Switcher, 5V, 1A output 29/REG1/0N12U908 Simple (Buck) Switcher, 5V, 1A output 29/REG1/0N12U909 Simple (Buck) Switcher, 5V, 1A output 29/REG2/00N5U910 LDO Adjustable Positive Voltage Regulator 29/00LM/1117U911 Positive Adjustable Voltage Reg. in SO8 package 29/000L/M317U912 Positive Adjustable Voltage Reg. in SO8 package 29/000L/M317U913 Negative Adjustable Voltage Reg. in SO8 29/000L/M337U914 Negative Adjustable Voltage Reg. in SO8 29/000L/M337U915 Negative Adjustable Voltage Reg. in SO8 29/000L/M337X200 14.7456 MHz Crystal, 30ppm, SMD 33/14M7/0001X500 4.0 MHz Crystal 32/2049/04M0X600 12.0 MHz Crystal, 5ppm, SMD 33/12M0/0001X601 12.0 MHz Crystal, 5ppm, SMD 33/12M0/0001

45

C T50 Parts List (Rev 3) The following table highlights those components in Rev. 3 exciters, that differ from theparts in Rev. 4. The values indicated are the values used in Rev.3

Ref Descr iption Par t #C212 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC420 NFC421 NFC502 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC512 NFC513 Ceramic Capacitor, 16V, 1uF, X7R, 1206 45/X7R1/1U16C611 10nF Cer. Cap, X7R, 0603, 10% 46/63X1/010NC612 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC622 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC645 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC646 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC719 100nF, 25V, Y5V, decoupler, 0603 46/63Y1/100NC726 3p9F Cer. Cap, NPO, 0603, 5% 46/63N1/03P9C727 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015PC728 15pF Cer. Cap, NPO, 0603, 5% 46/63N1/015PC729 1p8F Cer. Cap, NPO, 0603, 5% 46/63N1/01P8C731 NFC734 3p9F Cer. Cap, NPO, 0603, 5% 46/63N1/03P9C735 2p2F Cer. Cap, NPO, 0603, 5% 46/63N1/02P2C744 NFC752 NFC755 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047PC756 4p7F Cer. Cap, NPO, 0603, 5% 46/63N1/04P7C757 120pF Cer. Cap, NPO, 0603, 5% 46/63N1/120PC758 120pF Cer. Cap, NPO, 0603, 5% 46/63N1/120PC759 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047PC760 NFC765 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047PC766 NFC767 NFC768 NFC769 NFC804 18pF Cer. Cap, NPO, 0603, 5% 46/63N1/018PC808 1p8F Cer. Cap, NPO, 0603, 5% 46/63N1/01P8C809 NFC812 1p8F Cer. Cap, NPO, 0603, 5% 46/63N1/01P8C813 100pF Cer. Cap, NPO, 0603, 5% 46/63N1/100PC815 56pF Cer. Cap, NPO, 0603, 5% 46/63N1/056PC816 33pF Cer. Cap, NPO, 0603, 5% 46/63N1/033PC818 10pF Cer. Cap, NPO, 0603, 5% 46/63N1/010PC819 68pF Cer. Cap, NPO, 0603, 5% 46/63N1/01P8C828 47pF Cer. Cap, NPO, 0603, 5% 46/63N1/047PC830 NFD503 NF

J4 NFJP4 NF

L701 39nH Inductor 37/8551/039NL703 NFL704 NFL705 NFL713 220uH Choke 37/3320/P103L720 220nH Inductor 37/3320/220NL721 270nH Inductor 37/3320/270NL722 220nH Inductor 37/3320/220NL726 82nH Inductor 37/8551/082NL805 120nH, air core 37/AC52/120NL806 169nH, air core 37/MAXI/169NL812 270nH Inductor 37/3320/270NL813 NF

LC700 NF

46

LC701 NFLC702 NFQ402 Gen. Purpose PNP transistor in SOT-23 27/3010/3906R313 0805, 1%, 120K resistor 51/8511/120KR314 0805, 1%, 22K resistor 51/8511/022KR315 0805, 1%, 100K resistor 51/8511/100KR316 0805, 1%, 22K resistor 51/8511/022KR332 0805, 1%, 180K resistor 51/8511/180KR333 0805, 1%, 1K resistor 51/8511/01K0R337 NFR404 0805, 1%, 10K resistor 51/8511/010KR446 0805, 1%, 10K resistor 51/8511/010KR448 0805, 1%,10K resistor 51/8511/010KR451 0805, 1%, 47K resistor 51/8511/047KR452 0805, 1%,10K resistor 51/8511/010KR464 0805, 1%, 330K resistor 51/8511/330KR514 0805, 1%, 22K resistor 51/8511/022KR515 NFR522 0805, 1%, 68K resistor 51/8511/068KR534 NFR535 NFR536 NFR537 NFR600 0805, 1%, 4K7 resistor 51/8511/04K7R602 0805, 1%, 27K resistor 51/8511/027KR603 0805, 1%, 27K resistor 51/8511/027KR604 0805, 1%, 100K resistor 51/8511/100KR605 0805, 1%, 18K resistor 51/8511/018KR609 0805, 1%, 22K resistor 51/8511/022KR610 0805, 1%, 47K resistor 51/8511/047KR612 0805, 1%, 100K resistor 51/8511/100KR617 0805, 1%, 560R resistor 51/8511/560RR619 0805, 1%, 680R resistor 51/8511/680RR620 0805, 1%, 680R resistor 51/8511/680RR621 0805, 1%, 4K7 resistor 51/8511/04K7R626 0805, 1%, 4K7 resistor 51/8511/04K7R627 NFR628 1218, 5%, 68R, 1W, SMD resistor 51/2851/0068R633 1206, 1%, 120R resistor 51/3380/120RR634 1206, 1%, 120R resistor 51/8511/120RR640 NFR701 0805, 1%, 47R resistor 51/8511/047RR702 0805, 1%, 120R resistor 51/8511/120RR703 0805, 1%, 120R resistor 51/8511/120RR705 0805, 1%, 220R resistor 51/8511/220RR711 0805, 1%, 56R resistor 51/8511/056RR712 NFR713 0805, 1%, 100K resistor 51/8511/100KR714 0805, 1%, 120R resistor 51/8511/120RR721 NFR725 0805, 1%, 22K resistor 51/8511/022KR733 0805, 1%, 330R resistor 51/8511/330RR736 0805, 1%, 220R resistor 51/8511/220RR737 0805, 1%, 1K resistor 51/8511/01K0R738 0805, 1%, 220R resistor 51/8511/220RR740 0805, 1%, 120R resistor 51/8511/120RR741 0805, 1%, 4K7 resistor 51/8511/04K7R742 0805, 1%, 180R resistor 51/8511/180RR745 0805, 1%, 220R resistor 51/8511/220RR801 0805, 1%, 22K resistor 51/8511/022KR803 1218, 5%, 100R, 1W, SMD resistor 51/2851/0100R806 1218, 5%, 100R, 1W, SMD resistor 51/2851/0100R807 1218, 5%, 100R, 1W, SMD resistor 51/2851/0100R813 1218, 5%, 100R, 1W, SMD resistor 51/2851/0100R814 NFR815 NF

47

D EIA CTCSS TONESFrequency EIA NumberNo Tone

67.0 A171.9 B174.4 C177.0 A279.7 C282.5 B285.4 C388.5 A391.5 C494.8 B3

100.0 A4103.5 B4107.2 A5110.9 B5114.8 A6118.8 B6123.0 A7127.3 B7131.8 A8136.5 B8141.3 A9146.2 B9151.4 A10156.7 B10162.2 A11167.9 B11173.8 A12179.9 B12186.2 A13192.8 B13203.5 A14210.7 B14218.1 A15225.7 B15233.6 A16241.8 B16250.3 A17

11

Blo

ck F

low

Dia

gram

of A

udio

and

RF

sign

als

in 9

154(

T50)

05/9

A

8-A

pr-2

003

10:2

8:51

D:\P

rote

l File

s\C

opie

s fr

om C

roco

dile

\t50_

4.dd

b - I

ssue

4\B

LOC

K_D

IAG

RA

M.S

ch

Title

Size

:N

umbe

r:

Prin

t Dat

e:

File

:

Rev

isio

n:

Shee

tof

A4

RF

Tech

nolo

gy P

ty L

tdU

nit 1

0, 8

Lei

ghto

n Pl

ace

Hor

nsby

, NSW

207

7A

ustra

liaR

ev. R

elea

se D

ate:

O

rigin

ator

:

Tone

+

Tone

-

Low

Pas

sFi

lter (

250H

z)

Lim

iter

Dig

ital

Pote

ntio

met

erB

uffe

r

Sum

min

gA

mpl

ifier

Buf

fer

Line

2+

Line

2-

T300

Line

2+

Line

2-

T301

VC

A

VC

A

Pre-

emph

asis

Flat

Sum

min

gA

mpl

ifier

Pre-

emph

asis

Flat

Pre-

emph

asis

Mic

roph

one

inpu

t

Am

plifi

er20

dB g

ain

Lim

iter

Sum

min

gA

mpl

ifier

Low

Pas

sFi

lter (

3kH

z)

Dig

ital

Pote

ntio

met

er

Buf

fer

Am

plifi

er6d

B g

ain

Loop

Det

ect

Mod

ulat

ion

PLL

Mod

ulat

ion

Ref

eren

ceO

scill

ator

VC

O

Cha

nnel

PLL

Ref

eren

ceO

scill

ator

VC

OR

FA

mpl

ifier

Vol

tage

Con

trolle

d

RF

Am

plifi

erR

FA

mpl

ifier

RF

Am

plifi

er

RF

Am

plifi

er

Low

Pas

sFi

lter (

350M

Hz)

Low

Pas

sFi

lter (

300M

Hz)

Pass

ive

Mix

erLo

w P

ass

Filte

r (55

MH

z)Lo

w P

ass

Filte

r (55

MH

z)

RF

Out

put

RF

Am

plifi

er

RF

Am

plifi

er

3200

Exte

rnal

Ref

eren

ceIn

put

uP

uP

uP

uP

uP

uPuPuPuPuPuP

uP

uP

uP uP

uP

uP

uP

uP

Set S

ynth

esis

erD

ivid

ers

Cen

tre F

requ

ency

Adj

ustm

ent

Set S

ynth

esis

erD

ivid

ers

Cen

tre F

requ

ency

Adj

ustm

ent

Lock

Det

ect a

ndR

efer

ence

Osc

. Det

ect

Lock

Det

ect a

ndR

efer

ence

Osc

. Det

ect

uP uP

+12V

uP

Loop

/Vol

tsSe

lect

Max

imum

Dev

iatio

nSe

tting

VC

AuP

Bal

ance

Line

1

Line

2

Max

imum

Ton

e D

evia

tion

Setti

ng

uP

Bal

ance

d D

iffer

entia

lA

mpl

ifier

CTC

SSG

ener

ator

uP

uP uP

Dev

iatio

nC

ontro

l

Dev

iatio

nC

ontro

l

and

Dir.

Aud

. (To

ne IN

) Dev

iatio

nC

ontro

l

Var

acto

rB

ias

uP

Var

acto

rB

ias

uP

Line

Pote

ntio

met

eruP

Vre

f

Line

Lev

el In

Exte

rnal

Ref

. Div

.

Peak

Det

ecto

r

uPLi

ne L

evel

Sen

se

Hig

h Sp

eed

Cou

pler

GPS

GPS

+

GPS

-uP

Tem

p. S

enso

r

uPTe

mp.

VC

A: V

olta

ge C

ontro

lled

Am

plifi

er

VC

O: V

olta

ge C

ontro

lled

Osc

illat

or

uP: M

icro

proc

esso

r Inp

ut o

r Out

put

PLL:

Pha

se L

ocke

d Lo

op

12

34

56

78

ABCD

87

65

43

21

D C B A

11

Rea

r Pan

el B

oard

for 9

154

(T50

) and

915

5 (R

50)

05/9

160

R7

1

16-A

ug-2

002

09:5

6:54

F:\O

bsol

eted

File

s\O

ld F

iles

Bac

kup\

916x

.ddb

- T5

0_R

50_r

ear_

pane

l.Sch

Title

Size

:N

umbe

r:

Prin

t Dat

e:

File

:

Rev

isio

n:

Shee

tof

A3

RF

Tech

nolo

gy P

ty L

tdU

nit 1

0, 8

Lei

ghto

n Pl

ace

Hor

nsby

, NSW

207

7A

ustra

liaR

ev. R

elea

se D

ate:

O

rigin

ator

:

Rev

No.

ECO

No.

Des

crip

tion

of C

hang

e

VCC16 GND 8

I76

I65

I54

I43

I314

I213

I112

I011

SI10

C2

C15

Q7

PL1

Q9

U1

74H

C16

5R

2

47K

R1

47K

C1

100n

F

Q1

BSS

138

D9

BA

W56

MO

SI

SCLK

+5V

R3

100K

R4

100K

R5

100K

R6

100K

R7

100K

R8

100K

R9

100K

R10

100K

CH

1C

H2

CH

4C

H8

CH

10C

H20

CH

40C

H80

PTT_

INT/

R_R

ELA

YLI

NE2

+LI

NE2

-TO

NE+

TON

E-LI

NE-

LIN

E+

GPS

+G

PS-

CH

_EN

CS2

+5V

PA_C

S

+28V

11421531641751861972082192210231124122513

J1 DB

25

GN

D

R11

47K

R12

47K

R13

47K

R14

47K

R15

47K

R16

47K

R17

47K

R18

47K

+12V

R19

22R

Vre

f

D4 BAV99

D5 BAV99

D6 BAV99

D7 BAV99

D3 BAV99

D2 BAV99

D1 BAV99

D8 BAV99

R20

180R

R25

180R

R24

180R

R23

180R

R21

180R

R22

180R

D10

BA

V99

GN

D

5V_P

RO

T

D11

BA

V99

GN

D

5V_P

RO

T

D12

BA

V99

GN

D

5V_P

RO

T

D13

BZX

84C

5V6

GN

D

5V_P

RO

T

R26

180R

D14

BA

V99

GN

D

5V_P

RO

T

FD1

FID

UC

IAL

FD2

FID

UC

IAL

LK1

JUM

PER

LK2

JUM

PER

LK3

JUM

PER

LK4

JUM

PER

5X2

Hea

der1

2 3 4 5 6 7 8 910

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

5 9

Tone Generation Section

9154 B

20-Feb-2002 23:41:52

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - tonetx.sch

Title

Size: Number:

Print Date:

File:

Revision:

Sheet of

A3RF Technology Pty Ltd

Unit 10, 8 Leighton PlaceHornsby, NSW 2077

AustraliaRev. Release Date: Originator:

Rev No. ECO No. Description of Change

TONEP+

TONEP-

TONE_DEV_U/D

CTCSS_SEL

SCLKMOSI

EXT_TONE_SEL

TONE_OUTTONE_OUT

R52268K

R50147K

R509

7K5

R50047K

R508

7K5

C506100pF

C507100pF

GND

5

67

U502B

LM224

R5117K5

R510

7K5

GND

2

31

U502A

LM224

R504

560R

GND

R514

10K

R503

22K

C501

22pF

C500

22pF

C513

1uF

C509

1uFC508

100nF

+5V

R5071M

X5004MHz

GND

CTCSS_SEL

MOSISCLK

CTCSS_OUT

GND

GND

R516680R

16

15 14

U301D

DG411

R50247K

-10V

TONE_DEV_INC

R517

47K

R518

47K

R519

47K

C51422nF

C515100nF

C516

1n2F

9

108

U502C

LM224

GND GND

2

1

VD

D6

GN

D3

INC5

U/D4

U503

MAX5161L

-2.5V

V+

4V

-11

U502ELM224

-10V

+10V

R5231K

R524NF

+2.5V14

13

12U502D

LM224

GNDQ500

MMBT3906

Q501

MMBT3906

R505

10K

R506

10K

R52047K

-2.5V

+2.5V

+2.5V

R52147K

-2.5V

(NPO)(X7R - 10%)

1

2 3U301A

DG411

FILTER_OFFFILTER_OFF

R530, R531, R508, R509, R532, R533, R510, AND R511Should be 0.25%, 50ppm TC or better

(NPO)

C510

100nF

C511

100nF

TP501TONE_IN

TP500TONE+CTCSS

GND

GND

D500

BAV99

D501BAV99

-10V

+10V

+10V

VC

C24

GN

D12

XTAL1

XTAL/CLK2

CS7

ADDR3

SCLK5

Din6

Dout8

IRQ4

AUDIO_IN10

RX_IN+14

RX_SUB_IN16

TONE_OUT9

AUDIO_OUT11

COMP-19

NO_TONE22

Vbi

as18

RX_IN-13

RX_OUT15

RX_SUB_OUT17

COMP+20

WA

KE

23

COMP_OUT21

U500

FX805

R51210K

+5V

C503

100nF

C502

100nF

TONE_INT

R51310K

+5V

R525

10K

L500

BLM31A601

+5TONE

R526

2K2 D503

BAV99

R52747K

R52847K

-10V

-10V

R52947K

-10VR531

7K5

R530

7K5

R5337K5

R532

7K5

R534NF

D502

BAV99

GND GND

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

6 9

Frequency Synthesiser

9154 B

20-Feb-2002 23:40:44

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - siggen.sch

Title

Size: Number:

Print Date:

File:

Revision:

Sheet of

A3RF Technology Pty Ltd

Unit 10, 8 Leighton PlaceHornsby, NSW 2077

AustraliaRev. Release Date: Originator:

Rev No. ECO No. Description of Change

MOD_IN

MOSISCLK

MOD_PLL_SENSE

SIGGEN_ADSEL

R609

10K

R608

2K2

D600

MMBV109

-5V

C611

10nF

R602

27K

R604100K

C605

10nF

CHAN_VCO_OUTMOD_VCO_OUT

MOD_PLL_IN

CHAN_PLL_IN

VCO_OUT

MOD_VCO_EN

2PORT_MOD

BALANCE

CHAN_VCO_EN

T/R_RELAY

VCO Sectionvco.sch

GND

GND

C620

33pF

C614

15pF

R603

27KC610

470pF

GND

C615

15pF

2

31

U400A

LM224

R605

27K

C601

100nF

GND

R606

5K6

R6181K

R617

1K

C612

100nF

C613

220nF

GND

GND

R620680R

R619

680R

C622

100nF

C623

220nF

GND

R6214K7

+5V

+5Q

GND

RESET

SCLK

MOD_ADJ

CHAN_ADJ

C602

10nF

MOD_PLL_SENSE

CHAN_PLL_SEL

RESET

SIGGEN_ADSEL

R611

2K2

R6075K6

Vref

GND

R622

5K6

R623

5K6

R62422K

R62522K

GND

MOD_BIAS

R629

270K

CHAN_BIAS

VC

C1

1

VC

C2

16

Vp1

2

GN

D4

GN

D13

DO13

DO214

FoLD8

Fin15

Fin212

Xin6

Xout7

LE11

CLK9

DATA10

Vp2

15

U602LMX2335L

+5Q

VC

C1

1

VC

C2

16

Vp1

2

GN

D4

GN

D13

DO13

DO214

FoLD8

Fin15

Fin212

Xin6

Xout7

LE11

CLK9

DATA10

Vp2

15

U604LMX2335L

GND

GND

SCLKMOSI

SCLKMOSI

MOD_PLL_SEL

R6004K7

CHAN_PLL_SENSECHAN_PLL_SENSE

C637

56pF

C63610nF

GND

C600

10nF

C617

100nF

GND

D601

MMBV109-5V

R612

100K

C638

10nF

R61047K

C639

100nF

GND

C640

8p2F

R613

47R

GND

R614

47R

+5Q

C616

10nF

GND

GND

R61647R

+5Q

C609

10nF

+5Q

+5Q

+5V

R61547R

+5Q

EXT_REF_IN

R62868R

R630120R

GND

+5V

C641

100nF

R633

120R

C643

100nF

GND

Q600

MMBT3904

R635560R

R636220R

R634

120R

C642100pF

EXT_REF_DIV

PDOUT_MOD

PDOUT_CHAN

MOD_VCO_EN

GND

QA3

QB4

QC5

1A1

QD6

R2

U605A

74HC393

QA11

QB10

QC9

1A13

QD8

R12

U605B74HC393

QA3

QB5

QC6

1A1

QD7

R2

1B4

U606A

74HC390

GND

Vcc

14G

nd7

U605C

74H

C39

3

Vcc

16G

nd8

U606C

74H

C39

0

GND

C606

100nF

C644

100nF

GND GND

GND

GND

Divide by 128

Divide by 25

CS9

SCLK10

Din11

AG

ND

14

DG

ND

12V

CC

13

Vre

f3

CLR7

LDAC6

PDE5

OUTA2

OUTB1

OUTC16

OUTD15

Dout8

UPO4

U601

MAX534

Vref

R650

5K6

BALANCE

MOD_ADJ_FINE

VCO_OUT

R648

4K7

Fo_MOD

Fo_MODFo_CHAN

Fo_CHAN_2

Fo_MOD_2Fo_MOD_2

Fo_CHAN_2QA

13

QB11

QC10

1A15

QD9

R14

1B12

U606B

74HC390

R646

4K7

C645

100nF

GND

C646

100nF

GND

R64910K

R64710K

Fo_CHAN

MOD_IN

MOD_INC648

100nF

* C613 AND C623 CAN BE X7R(10%)

C647

NF

L600BLM31A601

MOSI

+C626

3u3F

C618

NF

** C625 and C626 should be 10% Tantalums

C635

8p2F

X600

12M

X601

12M

C624

1uF

C629

1uF

C649

10pF

C650

10pF

GND

GND

R631

47R C631

10nF

GND+5Q

GND

C630

1uF

C621

1uF

C604

1uF

C634

10nF

C607

1uF

C603

10nF

C619

1uF

C608

1uF

R632

47R

+C625

3u3FR6375K6

GN

D3

V+

1

Vo2

U603 LM61

GND

+5Q

R638

5K6

C651

100nFR639

10K

Vt

*

*

**

**

Case Size ATEMP

TEMPPlaced near X601

4

31

25

U607

TS971LT

-5V

+5Q

MOD_PLL_SEL

CHAN_PLL_SEL

C652

10nF

GND

4

31

25

U600

TS971LT

-5V

+5Q

4

31

25

U608

TS971LT

-5V

+5Q

GND

CHAN_BIAS

MOD_BIAS

CHAN_VCO_EN

T/R_RELAY

C628

100nF

C627

100nF

L713

220uH

L718

220uH

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

9 9

Power Generation Section

9154 B

20-Feb-2002 23:40:01

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - power.sch

Title

Size: Number:

Print Date:

File:

Revision:

Sheet of

A3RF Technology Pty Ltd

Unit 10, 8 Leighton PlaceHornsby, NSW 2077

AustraliaRev. Release Date: Originator:

Rev No. ECO No. Description of Change

28V

GND

+10V

+5V

-5V-10V

+2.5V

-2.5V

+C941

33uF

+C945

33uF

C928

100nF

C925

100nF R936120R

R928220R

+C944

33uF

C924

100nF

R933560R

+C943

33uF

+5Q

C930

100nF

R927220R

+C942

33uF

D909

MBRM140T3

L904

DS5022P-224

GND

+ C939

100uF

+ C936

33uF

12V

Tantalum, ESR <= 0.3 ohms

Output Current is 750mA (max)

R925220R

R9201K

GND

R921560R

+10V

+5V

R9231K

R930220R

R929220R

R934560R

R924560R

R922220R

+C902

470uF

Tantalum, ESR <= 0.3 ohms

+2.5V

-2.5V

C932

100nF

GND

D911

ZRC400F01

R926

2K2

GND

C929

100nF

Vref+10V

Vref

+ C940

33uF

GND

TP911

-10VTP914-5V

TP912

+5V

TP916+2.5V

TP913Vref

TP910+10V

TP915

GND

TP917

-2.5V

R935120R

R932220R

12V

D907

MBRM140T3

L902

DS5022P-224

GND

+ C938

100uF

Tantalum, ESR <= 0.3 ohms

Max output current is 1A

12V

TP909

12V

GN

D3

GN

D6

Vout1

EN5

Vin2

FB4

U909LM2595S-5

GN

D3

GN

D6

Vout1

EN5

Vin2

FB4

U907LM2595S-12

+C935

470uF

D908

MBRM140T3

L903

DS5022P-334+ C937

100uF

Tantalum, ESR <= 0.3 ohms

-12V

GN

D3

GN

D6

Vout1

EN5

Vin2

FB4

U908LM2595S-12

D906

MBRM140T3

R91947K

R918

47K

C915

100nF

12V

D910SM4004

GND

-Vin2

-Vout1

AD

J4

-Vin3

-Vin7

-Vin6

NC5

NC8

U913LM337LM

-Vin2

-Vout1

AD

J4

-Vin3

-Vin7

-Vin6

NC5

NC8

U915LM337LM

-Vin2

-Vout1

AD

J4

-Vin3

-Vin7

-Vin6

NC5

NC8

U914LM337LM

Vout2

Vin1

AD

J4

Vout3

Vout7

Vout6

NC5

NC8

U911LM317LM

Vout2

Vin1

AD

J4

Vout3

Vout7

Vout6

NC5

NC8

U912LM317LM

GND

GND

GND

GND

GND

GND

-5V

R931220R

GND

C923

100nF

C934

100nF

GND

GND

-10V

GND

C926

100nFC931

100nF

C920

100nF

C927

100nF

C933

100nF

GNDGND

GNDGND

+5Q

Low Impedance Type35V, 10mm dia

-10V

+10V

ADJ1

Vin3

Vo4

Vo2

U910LM1117DTX-ADJ

L901

33uH+ C903

33uF

L905

220uH

+C901100uF

L906

BLM31P121SG

L907

BLM31P121SG

L908

BLM31P121SG

+5D1

+5D2

+5D3

L909

BLM31P121SG

TP908+5Q

4

31

25

U906

TS971LT

+5Q

+C904

3u3F

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

8 9

Broadband Power Amplifier

9154 B

20-Feb-2002 23:39:04

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - pa.sch

Title

Size: Number:

Print Date:

File:

Revision:

Sheet of

A3RF Technology Pty Ltd

Unit 10, 8 Leighton PlaceHornsby, NSW 2077

AustraliaRev. Release Date: Originator:

Rev No. ECO No. Description of Change

RF_out

RF_in

LOC_FWD_PWR

C807

1n2F

C806

10nF

RF_out

C810

100nF

GND

R80510R

28V

L801

BLM31A601L803558nH

Coilcraft Maxi Spring Coils

Murata FerriteSMD Choke

L800

BLM31A601C801

100nF

GND GND

R81610K

R8234K7

D800BAT54C

GND

C803

1nF

L804558nH

R80410R

PWRCNTRL

+C811100uF

GND

R810

10R

C814

NF

C816

33pF

C818

10pF

C813

100pF

C809

NF

L805

120nH

L806

169nH

GND

C81556pF

C817NF

C819

68pF

C8121p8F

C8081p8F

R819

68R

R811

27R

C802

1n2F

Q804

BFQ17

Q805

BFQ17Q801BFQ17

L808

3u3H

L8101uH

L809

180nH

R806100R

C805

470pFC820

470pF

R803100R

35V

C821

100nF

C822

10nF

R808

10R

R807100R

R813

100R+C827

10uF

+C826

3u3F

GND

GND

L807

220uH

+10V

C825

220pF

GND

L8113u3H

R812220R

R80247R

42

1 3

U800MSA0311

GND

C823

100nF

C824

100nF

GND

GND

35V

C829

100nF

R809

27R

C804

47pF

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

2 9

Microprocessor

9154 B

20-Feb-2002 23:32:55

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - micro.sch

Title

Size: Number:

Print Date:

File:

Revision:

Sheet of

A3RF Technology Pty Ltd

Unit 10, 8 Leighton PlaceHornsby, NSW 2077

AustraliaRev. Release Date: Originator:

Rev No. ECO No. Description of Change

MOD_PLL_SEL

RXDATA

PE448

SS104

SCK103

PF169

CSP073

PF674

CSD72

CSO68

R/W38

A1916

A1813

A1712

A1611

A1567

A1466

A1365

A1264

A1163

A1062

A961

A860

A759

A658

A557

A456

A355

A254

A153

D735

D634

D533

D432

D331

D230

D129

D028

VC

C2

VC

C14

VC

C42

Vdd

pll

43

VC

C79

VC

C95

Vre

f85

GN

D1

GN

D15

GN

D41

GN

Dpl

l45

GN

D80

GN

D96

GN

Dre

f86

A052

AN794

AN693

AN592

AN491

AN390

AN289

AN188

AN087

PJ710

PJ69

PJ47

PJ36

PJ25

PJ58

PJ14

MODB50

RESET40

MODA49

PE751

PE339

IRQ37

XIRQ36

PJ03

PH784

PH683

PH582

PH481

PH378

PH277

PH176

PH075

PF371

PF270

A2118

A1917

PD727

PD626

PD525

PD424

PD323

PD222

PD121

PD020

MOSI102

MISO101

TxD1100

RxD199

TxD098

RxD097

PT7112

PT6111

PT5110

PT4109

PT3108

PT2107

PT1106

PT0105

EXTAL46

XTAL47

XFC44

BKGD19

U204

MC68HC812A0

TXDATA

RESET12

RY/BY36

CE9

WE38

OE37

A2139

A2040

A191

A182

A173

A164

A155

A146

A137

A128

A1113

A1014

A915

A816

A717

A618

A519

A420

A321

A222

A123

A024

GN

D29

VC

C10

D025

D735

D634

D533

D432

D328

D227

D126

VC

C31

GN

D30

NC

11

U207

29F032

EN16

EN2A4

EN2B5

S23

S12

S01

VC

C16

GN

D8

Y77

Y69

Y510

Y411

Y312

Y213

Y114

Y015

U205

74HC138

LOC_FWD_PWR

VC

C32

GN

D16

CS22

OE24

WE29

A111

A181

A1730

A162

A1531

A143

A1328

A124

A1125

A1023

A926

A827

A75

A66

A57

A48

A39

A210

D721

D620

D519

D418

D317

D215

D114

D013

A012

U208

K6T4008

MOD_PLL_SENSE

PTT_IN

LOOP_DET

T/R_RELAY

RESET

TERM_EN1

GND

+5D1

TERM_EN2

TONE_DEV_U/D

GND

ALARM_LED

TX_LED

LINEINP_ADSEL

SCLKMOSI

PTT_uPHONE

CHAN_PLL_SEL

RTS

FPSW1

DTR

CTS

CTCSS_SEL

EXT_TONE_SEL

LINEINP_DSEL

C206

100nF

C205

100nF

C204

100nF

LINE_LEVEL_SENSE

C207

100nF

CHAN_VCO_EN

LOOP/VOLTS_SEL

GND

SIGGEN_ADSEL

TONE_DEV_INC

MOD_BIAS

GND

R/WCS0

CSD

FWTFRD

RAMRDRAMWT

VC

C20

GN

D10

C11

E1

O72

O619

O55

O416

O36

O215

O19

O012

I73

I618

I54

I417

I37

I214

I18

I013

U209

74HC374

GND

+5D2

D7D6D5D4D3D2D1D0

LCD_DB0LCD_DB1LCD_DB2LCD_DB3LCD_DB4LCD_DB5

A21A20

LCD_DB6

A19A18

LCD_DB7

A17

LCD_R/W

A16

LCD_RS

A15

LCD_E

A14A13A12A11A10

FRDY

A9A8A7A6A5A4A3A2A1A0

C212

100nF

D7

C208100nF

D6D5

GND

D4

GND

D3D2

R21810K

D1

R22010K

D0

R21710K

R21910K

+5D3

+5D1

+5D1

C226

100nF

FPSW2FPSW3

R22310K

R22410K

R22510K

+5LCD

GND

DSR

RES1

GN

D4

VC

C2

NC3

NC5

NC6

NC7

NC8

U203

MC33064D

GND

LCD_DB7

+5D3

LCD_DB6LCD_DB5LCD_DB4

R20410K

LCD_DB3

R20310K

LCD_DB2

S2007914G

LCD_DB1LCD_DB0

A21

MOD_PLL_SEL

A20A19

LCD_E

A18A17

LCD_RS

A16A15

LCD_R/W

A14A13A12

12V

A11

R209

330R

A10

-12V

A9

R2052K2

A8A7A6A5

+C219

3u3F

A4A3

GND

A2

C202

100nF

A1A0

+5D1

C222

100nF

+5D3

C220

100nF

R235

4K7

R20768K

R202

10K

28V

GND

A18A17A16

C203

100nF

A15A14A13A12A11

L202BLM31A601

A10A9

+5D1

A8A7A6A5A4A3A2A1A0

L205

BLM31A601

L203BLM31A601

D7

L204BLM31A601

D6D5D4

+5D1

D3D2D1D0

+5D2

R212

220R

DBGTX

D7

DBGRX

D6D5D4D3D2

BKGD

D1D0

CTS_TTL

C211

100nF

DSR_TTL

C210

100nF

RTS_TTL

GND

Vref

DTR_TTL

GND

R245

10K

R232

560R

RESET

FILTER_OFF

CSP0

C209

10nF

C214100nF

FRDY

R221

560R

RESET

GND

D200

BAV99

+5D1

C225

100nF

R2221K

+5V

+5D3

LINE_LEVEL_IN

+5D2

TONE_INT

CH_ENSPARE_SEL

R229

10K

LINE_LEVEL_IN

R2131M

R2062K2

Q206MMBT3904

Q205MMBT3906

C216

100nF

PA_CS

R210

10K

GND

Fo_MOD_2Fo_CHAN_2

EXT_REF_DIV

R2161K

Fo_MOD_2

R22810K

TEMP_LEVEL_IN

Fo_CHAN_2

GND

+5D3

9

10 11

U403C

DG411

PWR_CNTRL_HIGH

+5TONE

R211220R

GPS-

MOSISCLK

CH_EN

GPS+

R231120R

R230120R

R214

180R

R215120R

PWR_OK

Q200MMBT3904

R226

180R

GND

GPS

ECLKLCD_DB7

A[0..21]

D[0..7]DEV_H_L

TX_LED

PA_CS

TERM_EN2TERM_EN1

SPARE_SEL

CHAN_BIAS

V+

14G

nd7

U201E

14C89A

V+

14G

nd7

V-

1

U202E 14C88

+5D3

SCKSD

DBGTX_TTL

TXD_TTLDBGRX_TTL

GND

C201

100nF

C224

100nF

RXD_TTL

LOOP_DET

C215

100nF

TONE_INT

GND

PTT_uPHONE

GND

GND

GND

C227

100nF

INT

C217

100nF

BKGD_ISO

CHAN_PLL_SENSE

ALARM_LEDRESET

X20014M7456

R2341K FILTER_OFF

R23322K

GND

GND

Q201

BSS138

1112

13

U202D

14C88

T/R_RELAY_H6

4

C5

U201B

14C89A

89

10

U202C14C88

K3

NC4

VC

C8

Ve7

Vo6

A2

NC1

GN

D5 U212

6N137

11

C12

13 U201D

14C89A

8

C9

10

U201C14C89A

3 2

U202A14C88

64

5

U202B

14C88

31

C2

U201A14C89A

D203BZX84C3V3

R227

56R

D202

SM4004

12V

GND

R244

10R

R241

47R

TONE_DEV_U/DTONE_DEV_INC

R242

47K

EXT_TONE_SEL

R20822K

LOC_FWD_PWR

CHAN_BIAS

MOD_BIAS

LINE_LEVEL_SENSE

CHAN_PLL_SELSIGGEN_ADSEL

LINEINP_ADSELLINEINP_DSEL

R243220R

CTCSS_SEL

LOOP/VOLTS_SEL

EXT_REF_DIV

FPSW3

Q204

MMBT2369

FPSW2

R24010K

FPSW1

R239

1K

VIN_SENSE

+5D2

CHAN_PLL_SENSE

GND

T/R_RELAY_H

C221

100nF

CHAN_VCO_EN

MOD_PLL_SENSE

R2381K

R23622K

R23747K

Q203MMBT2369

TEMPQ202MMBF5484

GND

L200220uH

GND

TEMP

PWR_CNTRL_HIGH

DEV_H_L

R201

10K

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

1 9

T50 Master Schematic

9154 B

20-Feb-2002 23:28:58

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - Master.sch

Title

Size: Number:

Print Date:

File:

Revision:

Sheet of

A3RF Technology Pty Ltd

Unit 10, 8 Leighton PlaceHornsby, NSW 2077

AustraliaRev. Release Date: Originator:

Rev No. ECO No. Description of Change

162738495

P1 DB9

D104 GREEN

D103 AMBER

D102 RED

POWER OK

ALARM

Tx Data

1234

JP12

4 HEADER

GND

28V

T/R_RELAYHiZ+HiZ-TONE+TONE-LINE_I/P4

LINE_I/P1

MOSI

PTT_IN

TONE-

TERM_EN2TERM_EN1

L2-L2+

L1-

L1+

uPHONE_IN

MOD_OUT

LOOP_DET

LOOP/VOLTS_SEL

TONE+

LINEINP_DSEL

MOSISCLK

CTCSS_SEL

LINEINP_ADSEL

EXT_TONE_SEL

RESET

TONE_DEV_U/D

TONE_DEV_INC

LCD_BIAS

LINE_LEVEL_SENSE

FILTER_OFF

PWRCNTRL

TONE_INT

PWR_CNTRL_HIGH

DEV_H_L

AUDIO PROCESSING SECTIONaudio.sch

28V

GND

+10V

+5V

-5V

-10V

+2.5V

-2.5V

Vref

12V

+5Q

POWER SECTIONpower.sch

VCO_out

MOD_IN

MOSISCLK

Fo_MOD_2Fo_CHAN_2

MOD_PLL_SENSE

SIGGEN_ADSEL

MOD_PLL_SEL

RESET

CHAN_BIAS

MOD_BIAS

CHAN_PLL_SEL

CHAN_PLL_SENSE

EXT_REF_INEXT_REF_DIV

TEMP

71

CHAN_VCO_EN

T/R_RELAY

RF SIGNAL GENERATORsiggen.sch

RXDATA

TXDATALOC_FWD_PWR

MOD_PLL_SENSE

Fo_MOD_2Fo_CHAN_2

T/R_RELAY

PTT_IN

LOOP_DET

RESET

TONE_DEV_U/D

TERM_EN1TERM_EN2

LINEINP_ADSEL

ALARM_LED

TX_LED

FPSW1

SCLKCTCSS_SEL

MOSI

EXT_TONE_SEL

LINEINP_DSEL

PTT_uPHONE

RTS

DTR

CTS

LINE_LEVEL_SENSE

CHAN_VCO_EN

LOOP/VOLTS_SEL

SIGGEN_ADSEL

MOD_PLL_SEL

TONE_DEV_INC

CHAN_BIAS

LCD_DB7LCD_DB6

LCD_DB4LCD_DB5

LCD_DB3LCD_DB2LCD_DB1LCD_DB0

LCD_ELCD_R/W

LCD_RS

FPSW2

FPSW3

DSR

MOD_BIAS

GPS+

BKGD

DBGTXDBGRX

GPS-

FILTER_OFF

PA_CS

PWR_OK

CHAN_PLL_SEL

CHAN_PLL_SENSE

TONE_INT

EXT_REF_DIV

CH_ENSPARE_SEL

LINE_LEVEL_IN

PWR_CNTRL_HIGH

DEV_H_L

TEMP

MICROPROCESSOR CONTROL SECTIONmicro.sch

GND

28V

-5V

+5V

+10V

RF_outRF_in

LOC_FWD_PWRPWRCNTRL

POWER AMPLIFIERpa.sch

GND

PTT_uPHONE

PTT_IN

T/R_RELAY

GPS+GPS-CH_ENSPARE_SEL

RXDATA

TXDATALOC_FWD_PWR

RTS

CTS

DTR

-10V

R104270R

R103180R

+5D3

+2.5V

-2.5V

uPHONE_IN

1234567891011121314

JP2

HEADER 14

GND

+5D1

LCD_BIAS

LCD_BIAS

DSRDSR

RXDRTS

TXDCTS

DTRRI

SG

DCD

Vref

SCLKPA_CS

12345678910

JP3

CON10GND

+5D3

RESET Debug/Monitor Port

GPS+GPS-

NB: connector signals reversedso that straight through cable can be used to PC

DBGTXDBGRX

L100BLM31P121SG

PA_CS

J1

BNC Right Angle - Low Profile

GND

RESET

J4

BNC-2

GND

MOSISCLK

12V

+5Q

MOD_PLL_SENSE

CHAN_PLL_SENSE

MOD_PLL_SELMOD_BIAS

CHAN_PLL_SELCHAN_BIAS

Fo_CHAN_2Fo_MOD_2

PWRCNTRL

SIGGEN_ADSEL

EXT_REF_DIV

BKGD

R1024K7

R1014K7

R1004K7

+5V

CH_ENSPARE_SEL

L104

BLM31A601

L102

BLM31A601

+5LCD

C103

NFA31CC102

C102NFA31CC102

C101NFA31CC102

C100NFA31CC102

GND L101

BLM31A601

TP102

28V

RV100100K

Vref

GND

R105

4K7

GND

11421531641751861972082192210231124122513

P3

DB25RA/F

12V

L2+L2-

L1+

L1-

T/R_RELAY

Vref

33

22

SW1

C&K_PB

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

4 9

Line Input Processing Section

9154 B

20-Feb-2002 23:31:21

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - lineinp.sch

Title

Size: Number:

Print Date:

File:

Revision:

Sheet of

A3RF Technology Pty Ltd

Unit 10, 8 Leighton PlaceHornsby, NSW 2077

AustraliaRev. Release Date: Originator:

Rev No. ECO No. Description of Change

LINE_IN1

LINE_IN2

uPHONE_IN

2

31

U407A

LM224 5

67

U407B

LM224

3

4

1

52

116

A

U402A

LM13700

7

8

VCC

U402C

14

13

16

1215B

U402B

LM13700

10

9

VCC

U402D

R402

22K

R414560R

R403

22K

R417560R

R415560R

R416560R

+10V

-10V

+10dBm max input => |Vin| < 3.46VFor peak distortion of 0.3%max input to transimpedance

amplifier is 100mV => need 25dB attenuation

R40610K

Io = Is(2Iabc/Id) : Io= Vo/Rl ; Is = Vs/Rs; Iabc = Vabc/Rabc; Id = Vd/Rd=> Vo/Vs = 2*Rl*Rd*Vabc/(Rs*Rabc*Vd) = Vabc*0.11

NB: Is max (3.46/18) is less than Id/2 (0.5ma)

R407

10K

+10V

R420120K

R422120K

GND

GNDGND

LINE2_GAIN

LINE1_GAIN

=> +10dBm peak voltage is transformed to 1.57V(max) to 6.15mV(min) (8 bit DAC, 4V reference)

R400

330R

R401

270R

C401

10nF

GNDGND

R404

56K

9

10 11

U404C

DG411

8

7 6

U404B

DG411

16

15 14

U404D

DG411

1

2 3

U404A

DG411

C423

1uF

C402

3n3F

R425

22K

C425

1uF

C403

3n3F

R426

22K

PRE_EMPH2

PRE_EMPH1

FLAT1

FLAT2

R4394K7

R4404K7

GND

GND

R434

4K7

R460

4K7

R42822K

R42922K

GND

GN

D5

VL

12

V+

13V

-4

U404EDG411

GND

+5V +10V

-10VC407

100nF

16

15 14

U403D

DG411C4043n3F

EN_uPHONE

R436

4K7

R447

47K

GND

R464

270K

R45647K

GND

R443

4K7

D402

BAV99

+2.5V

-2.5V

D401

BAV99

R4444K7

R442

4K7

9

108

U407CLM224

R433

270K

R432

270K

R431

270K

AUDIO_OUT

MOSI

SCLK

LINEINP_DEN

RESET

GND

G13

RCK12

Din14

SRCLR10

SRCK11

Q015

Q11

Q22

Q33

Q44

Q55

Q66

Q77

Dout9

VC

C16

GN

D8

U401

74HC595A

+5V

PRE_EMPH2FLAT2

PRE_EMPH1FLAT1

EN_uPHONE

GN

D5

VL

12

V+

13V

-4

U403EDG411

+10V+5V

GND-10V

AUDIO_DEV_INCAUDIO_DEV_U/D

CS9

SCLK10

Din11

AG

ND

14

DG

ND

12V

CC

13

Vre

f3

CLR7

LDAC6

PDE5

OUTA2

OUTB1

OUTC16

OUTD15

Dout8

UPO4

U406

MAX534

+5V

GND

MOSI

SCLKRESET

LINEINP_DEN

RESETSCLKMOSI

LINEINP_ADSELLINEINP_ADSEL

LINE1_GAIN

LINE2_GAIN

LINE_IN2

LINE_IN1

D400BAV99

1

2 3U403A

DG411

8

7 6

U403B

DG411

R448

10K

R449

5k6

+2.5V

-2.5V

TEST_DEVHIGH_GAIN

TEST_DEV

DEV_H_L

5

67

U302B

LM224

R41210K

R454

10K

+5V

LCD_BIAS

LINE_INP

C408

100nF

GND

V+

4V

-11

U407E

LM224

+10V

-10V

(NPO)

(NPO)

(NPO)

C413

100nF

C414

100nF

C416100nF

C409

100nF

C410

100nF

C415

100nF

GND

GND

GND

GND

GND GND

C412

100nF

GND

C411

100nF

GND

PWRCNTRL14

13

12

U407D

LM224

R455

10K

R413

1KR4085K6

PWR_CNTRL_RAW

R42310K

-10V

R42410K

-10V

C417100nF

C418100nF

GND

C419

100nF

GNDC422

100nF

GND

LCD_BIAS_RAW

5

67

U405B

LM224

R450

120K

R457

10K

9

108

U405C

LM224

R463

120K

R409120K

GND

2

31

U405ALM224

1413

12

U405DLM224

R405

5K6

R458

4K7

R459

4K7

R4351K

R465

100K

R461120K

GND

R462

10K

C428

1uF

V+

4V

-11

U405E

LM224

C426

100nF

C427

100nF

GND

GND

+

C400

33uF

AUDIO_OUT

AUDIO_DEV_INCAUDIO_DEV_U/D

R41047K

R41147K

-10V

-10V

R42747K

R43747K

R43047K

R44547K

-10V

-10V

-10V

-10V

R43847K

-10V

R42122K

R41922K

9

108

U400C

LM224

5

67

U400B

LM224

1413

12

U400D

LM224

V+

4V

-11

U400E

LM224

+2.5V

+5V

Vref

Q400MMBT3906

Q401MMBT3906

C405

100nF

C406

100nF

+10V

-10V

GND

GND

R45147K

-10V

R453

10K

PWR_CNTRL_HIGH

GND

Q402MMBT3906

R446

10k

R45210k HIGH_GAIN

R4185k6

DEV_H_L

R466

2K2

PWR_CNTRL_HIGHPWR_CNTRL_HIGH

R4674K7

+5D1

D403

BAV99

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

3 9

Audio Processing Section

9154 B

20-Feb-2002 23:30:34

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - audio.sch

Title

Size: Number:

Print Date:

File:

Revision:

Sheet of

A3RF Technology Pty Ltd

Unit 10, 8 Leighton PlaceHornsby, NSW 2077

AustraliaRev. Release Date: Originator:

Rev No. ECO No. Description of Change

TONE+

TONE-

CTCSS_SEL

TONE_DEV_INC

EXT_TONE_SEL

TONE_DEV_U/D

L2-

L2+

L1+

L1-

uPHONE_IN

MOD_OUT

LOOP_DET

LOOP/VOLTS_SEL

T301AUDIO_XFRMR

12 3

45 6

78

RL300

MR62-12

12V

GND

C30122uF

D303BAV99

D304

BAV99

R305330R

R304330R

K2

NC3

B6

C5

E4

A1

U300

4N32

R3082K2

+5D3

GND

T300

AUDIO_XFRMR

GND

R307

4K7

Q300BSS138

R306

10R

R31122K

GND

C300

22uF

* C300, and C301 are Bipolar electrolytic capacitors

9

10 11U301C

DG411

8

7 6U301B

DG411

R309560R

R310560R

TERM_EN2

TERM_EN1

LOOP/VOLTS_SEL

GND

GND

R300

27R

R301

27R

D3001.5KE11CA

D3011.5KE11CA

GND

F300

120mA

R302

27R

F301

120mA

R303

27R

LOOP_DET

LINE_IN1

LINE_IN2

uPHONE_IN

AUDIO_OUTMOSISCLKLINEINP_DEN

RESET

LINEINP_ADSEL

LCD_BIAS

LINE_INP

PWRCNTRL

AUDIO_DEV_INCAUDIO_DEV_U/D

DEV_H_L

PWR_CNTRL_HIGH

Line Input Processing Sectionlineinp.sch

TONEP+

TONEP-

TONE_DEV_INC

CTCSS_SELSCLKMOSI

EXT_TONE_SEL

TONE_OUT

TONE_DEV_U/D

TONE_INT

FILTER_OFF

TONE GENERATION SECTIONtonetx.sch

SCLKMOSI

GND

D3021.5KE11CA

F302

120mA

R31322K

R31410K

2

31

U302A

LM224

R315

22K

R31610K

GND

R321

68K

R322

68K

R323

68KC302

2n2F

C305

10nF

C306

120pF

1413

12U302D

LM224

GND GND

R318

120K

R319

120K

R320

120K

MOD_OUT

LINEINP_ADSELLINEINP_DSEL

RESET

TERM_EN2

TERM_EN1

GN

D5

VL

12

V+

13V

-4

U301EDG411

GND-10V

+10V+5V

LCD_BIAS

LINE_LEVEL_SENSE

R317

1K

GND

D307BAT54C

+ C304

3u3F

+5V

D305

BAV99

R31222K

R324

1k

D306

SM4004

V+

4V

-11

U302ELM224

+10V

-10V

(NPO) (NPO) (NPO)

TP300LINE_IN2

TP301LINE_IN1

C307

100nF

C308

100nF

GND

GND

TP305MOD_OUT

C309

100nF

C310

100nF

C311

100nF

GND GND

GND

PWRCNTRL

TONE_INT

PWRCNTRL

LINE_INP

FILTER_OFF

C312

1uF

LCD_BIAS

TO

NE

_OU

T

R33522K

R336

22K

AUDIO_DEV_INC

AUDIO_DEV_U/D

R332

68K

2

1

VD

D6

GN

D3

INC5

U/D4

U303

MAX5161L

-2.5V

R333

1K R334NF

+2.5V

9

108

U302C

LM224

GND

Q301

MMBT3906

Q302

MMBT3906

R328

10K

R329

10K

R33047K

-2.5V

+2.5V

+2.5V

R33147K

-2.5V

AUDIO_DEV_INCAUDIO_DEV_U/D

R32547K

-10V

-10V

R32647K

R32747K

-10V

*

*

DEV_H_L

PWR_CNTRL_HIGH

TP302

AUDIO_OUT

TP303

TONE_OUT

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

7 9

Voltage Controlled Oscillators

9154 B

20-Feb-2002 23:42:46

C:\Program Files\Design Explorer 99 SE\rft\t50\t50.Ddb - vco.sch

Title

Size: Number:

Print Date:

File:

Revision:

Sheet of

A3RF Technology Pty Ltd

Unit 10, 8 Leighton PlaceHornsby, NSW 2077

AustraliaRev. Release Date: Originator:

Rev No. ECO No. Description of Change

MOD_PLL_IN

CHAN_PLL_IN

CHAN_VCO_OUT

MOD_VCO_OUTC732

5p6F

C733

12pF

C737

10nF

+10V

GND

C750

22pF

GND

-5V

C718

100nF

GND

R711100K

C719

100nF

GND

L71612n5H

D701

MMBV109D702NF

R737

1K

C715

100nF

GND

R729

10R

L709

330nH

C702

10nF

C727

15pF

L701

39nH

GND

C734

3p9F

R701

47R

C705

22pF

L708330nH

C704

22pF

VCO_OUT

L700

27nH

L702

27nH

C728

15pF

C721

100nF

R71456R

R730

220RC722

100nF

R740

120R

CHAN_VCO_EN

Q704

MMBFJ309

D700BAT17 R709

10K

C739

10nF

Q703BSS138

R708

4K7

R73222K

L714330nH

R716

47RC748

10nF

GND

R717

10K

C724

10nF

Q707MMBT3904

GND

L724330nH

C743

10nF

GND

+10V

42

13U702

MSA0611

42

13

U701MSA0311

GND

GND

R703120R

R738220R

C770

100nF

C772

100nF

C736

100nF

LO6

RF3

GN

D1

GN

D4

GN

D5

IF2

MX700MIXER

L720

220nH

L721

270nH

L722

220nH

C760

1uF

C761

22pF

C762

10nF

C759

47pF

C758

120pF

C757

120pF

C755

47pF

+10V

C700

100nFL7253u3H

R700

120R

C714

150pF

R706

220R

42

13U700

MSA0611

GND

C713

100nF

GND

C740

4p7F

C741

NF

C738

10nF

+10V

GND

C751

33pF

GND

-5V

C725

100nF

GND

R713100K

C711

10nF

GND

L71918n5H

D704

MMBV109

D705

NF

R7361K

R744

10K

R72456R

C701

10nF

C731

15pF

L704

47nH

GND

C735

3p9F

C707

22pF

L710330nH

C716

22pF

L703

27nH

L705

27nH

C729

15pF

R718

120R

Q705MMBFJ309

D703BAT17

R739

10K

C747

10nF

L715330nH

R726

47RC730

10nF

GND

R719

10K

C720

10nF

Q702MMBT3904

GND

L723330nH

C742

10nF

GND

+10V

42

13

U706

MSA0611

GND

GND

R704

120R

R707

220RC771

100nF

C703

100nF

GND

CHAN_VCO_EN

GND

R72522K

2PORT_MOD

BALANCE

C763

10nF

C717

3p9F

C726

3p9F

C709

22pF

C746

10nF

C773

1uF

C752

1uF

R742

820R

R741

4K7

C754

100nF

C753

100nF

3

4

1

5 2

116

A

U704A

LM13700

7

8

VCC

U704CR727

22K

R743560R

R731560R

+10V

-10V

R723

10K

R720100K

GND GND

R72222K

BALANCE

C774

100nF

R71510K

-10V

C776

100nF

C775

100nF

GND

14

13

16

12 15B

U704B

LM13700

GND

Q700

MMBT3906

Vref

-10V

M1

RFSCREEN1

+C7233u3F

+

C7123u3F

R733

330R

L711330nH

C708

22pF

42

13U705

MSA0611

R702

120RR705220R

C710

100nF

C706

100nF

GND

GND

+10V

A05T

42

13U703

MSA0611

L706330nH

L717

100nH

L712

220nH

+10V

GND

+10V

GND

GND

GND

GND

GND

GND

A04T

L707NF

L72682nH

GND

R745220R

Q701BSS138

R734

4K7

R73522K

GND

C745

100nF

MOD_VCO_EN4

31

25

U707

TS971LT

+5Q

-5V

Q706BSS138

R710

2K2

C749

10nF

GND

GND

GND

T/R_RELAY

C756

10pF

C764

6p8F

C765

56pF