Maestro-2E PCI Audio Accelerator Data Sheet

ESS Technology, Inc. SAM0151-091198 1

Maestro-2ETM

PCI Audio AcceleratorData Sheet

DESCRIPTION

The Maestro-2ETM PCI audio accelerator, a high-performance 500-MIPS-equivalent PCI audio processor,uses the high-bandwidth PCI bus and an AC’97 CODECto deliver advanced PC audio features. These featuresinclude HRTF 3-D positional audio, high-quality64-channel wavetable music synthesis with downloadablewavetable samples, and DVD AC-3 5.1-to-2 speakervirtualization.

The Maestro-2E implements multi-stream DirectSoundand DirectSound3D acceleration and Windows 95 andWindows 98 stream acceleration with digital mixing andsample rate conversion. The Maestro-2E maintains fullDOS legacy audio compatibility over a standard PCI 2.1bus. The Maestro-2E is designed for high-performanceconsumer multimedia PC, notebook PC, and add-in cardapplications.

The Maestro-2E, based on a dual-engine, 64-channel,pipelined Wave Processor and a programmable audiosignal processor, provides simultaneous support formultiple audio streams of different types. Its corearchitecture is designed to handle complex signalprocessing tasks with a bus-mastering PCI interface andbuilt-in dedicated DMA engine supporting a DSP core.The support functions ensure efficient transfer of audiodata streams to and from system memory buffers,providing a system solution with maximum performanceand minimal host CPU loading. The architecture enablesimplementation of communications over the Internet frommultiple sources.

The Maestro-2E has a variety of audio interfaces. It hastwo 20-bit AC’97 CODEC interfaces that can be enabledsimultaneously for notebook docking implementation. Thesecondary AC’97 CODEC interface can be programmed tohandle multiple serial CODEC interfaces which, togetherwith the primary AC’97 CODEC, can provide full-featuredAC-3 speaker outputs. The Maestro-2E also supports aconsumer IEC958 S/PDIF output that provides high-quality digital audio and MIDI.

The Maestro-2E, which operates at 3.3 volts, has severalspecial features for notebook operation. It is compliantwith the Advanced Power Management (APM) 1.2,Advanced Configuration and Power Interface (ACPI) 1.0,and PCI Power Management Interface (PPMI) 1.0. It hasmultiple power-saving modes (D0, D1, D2, and D3) forpower-efficiency when the audio system is both active andidle. It provides a high-quality docking solution that isbackward compatible to the ES978 docking station

interface, and also supports an AC-link based digitaldocking solution with its secondary 20-bit AC-link.CLKRUN# pin support can be used to stop the PCIinterface clock. This helps achieve the lowest powerconsumption in D3hot mode.

The Maestro-2E supports full DOS game compatibility forboth PC motherboard and add-in card solutions throughthree hardware implementations: PC/PCI, DistributedDMA (DDMA), and Transparent DMA (TDMA). While PC/PCI and DDMA are industry-standard protocols for legacysupport, ESS’ TDMA technology implements DOS gamecompatibility over the standard PCI 2.1 bus withoutadditional sideband signals.

The Maestro-2E PCI audio accelerator is pin-to-pincompatible to the Maestro-2, and is available in anindustry-standard 100-pin Thin Quad Flat Package(TQFP).

FEATURES

High-Performance PCI Audio Acceleration • 500-MIPS-equivalent dual-engine PCI audio accelerator

• 64-Channel wavetable synthesis

• HRTF 3-D positional audio acceleration

• Multi-Stream DirectSound and DirectSound3D acceleration

• Hardware acceleration for DirectMusic, ActiveMovie, and DirectInput API

• DVD AC-3 speaker virtualization

• Enhanced effects (reverb, chorus, flange, treble, bass, and 3D stereo expander)

• Advanced platform for interactive 3-D gaming, DVD movie playback, and Internet communications

Legacy DOS Game Support • Full DOS game compatibility through three hardware

implementations: PC/PCI, DDMA, and TDMA

• TDMA needs no sideband signals, full DOS game compatibility achieved in standard PCI 2.1 bus

• Serial IRQ support

Complete Audio Solution for Notebook PCs • Compliance with APM 1.2, ACPI 1.0, and PPMI 1.0

• Compliance with Intel’s “Mobile Power Guideline”

• 3.3 volt operation with multiple power-saving modes

4 SAM0151-091198 ESS Technology, Inc.

MAESTRO-2E DATA SHEET

MAESTRO-2E BLOCK DIAGRAMS

MAESTRO-2E BLOCK DIAGRAMS

Figure 1 Maestro-2E Block Diagram

SystemDRAM Chipset CPU

3.3 V PCImaster

SB Prolegacyaudio

64-ChannelWave

Processor

Effect synth

HRTF 3-Dpositional

audio

Audiosignal

processor

ROM SRAM

20-Bit AC-Link #2/

MPU-401

HW volume

Game port

I2S/ZV

DSP interface

AC-Link #1

ACPI 1.0PPMI 1.0

WaveCache

PCI BUS

RIN

G B

US

Maestro-2E

AC’97 CODEC

Mic inLine inAux 1 (CD audio)Aux 2 (DVD)Aux 3 (digital TV)PhoneLine outHeadset outMono_out

AC-Link

DSP serial interface

MPEG audio

Analog/digital joystick

Vol up, vol down, mute

MIDI keyboard

C24

Multiple serialCODEC interface

APM 1.2

20-Bit

S/PDIF output Digital audio output

EEPROM interface EEPROM for device I/O customization

ES978 digital I/F ES978 docking interface



DOCKING APPLICATIONS

Figure 2 Wave Processor Portion

DOCKING APPLICATIONS

Figure 3 Docking Interface – Backward Compatible to the ES978

Figure 4 Digital Docking Interface

EffectsFilterEnvelopeSum

WaveCache

Multi-stream

Interface

PCIInterface

WaveLooping

CommandFIFO

CODECInterface

Source64

64 Streams

Maestro-2E 20-Bit AC-link

ES978Digital Interface

AC’97CODEC Differential

Transceiver

DigitalController

ES978Mic inLine in

CD audio

Line out

CD

Aux B

Line in

Mic

Hardware Volume

GPIOJoystick

MIDI

I2S Zoomed Video

XSCXSD

XA1,XA3

XA0,XA2

5

2

2

2

Portable Unit Docking Unit

Mode-3Line out

Aux 2 (L,R)

AC’97CODEC

Maestro-2E 20-Bit AC-link #1

AC’97CODEC

5

Portable Unit Docking Unit

ES978Digital Interface

20-Bit AC-link #2

5

ES9782

Line out

Line in

Mic in

CD audioMIDIGPIOAnalog joystickHardware volumeI2S Zoomed Video

ext. 1.03/2.00

ext. 2.00



PINOUT

PINOUT

Figure 5 Maestro-2E Pinout

1

G P I O 5 / V O L U P / R 1 #G P I O 4 / V O L D N / G S 1G P I O 3 / I L R / S P D I F OG P I O 2 / I D I / R 0 #G P I O 1 / I D O / G S 0G P I O 0 / I S C L KG N DC L K R U N # / E C SP M E #G N DA D 0A D 1A D 2A D 3A D 4A D 5A D 6A D 7V C CC / B E 0 #

X S D / R x DG N DC 2 4

R S T #I N T #V C C

P C I C L KG N D

G N T #R E Q #

G N DA D 3 1A D 3 0A D 2 9A D 2 8A D 2 7A D 2 6A D 2 5A D 2 4V C C

GP

IO1

0 /

PC

RE

Q#

GP

IO1

1 /

SIR

Q#

/ S

PD

IFO

GN

DO

SC

IO

SC

OV

CC

GD

0G

D1

GD

2G

D3

GD

4G

D5

/ E

DO

UT

GD

6 /

VO

LU

P /

ED

ING

D7

/ V

OL

DN

/ E

CL

KG

ND

S C L K 1S D F S 1

S D I 1S D O 1

X S C / T x D

GP

IO6

/ I

SC

LK

(I2

SC

LK

)G

PIO

7 /

IL

R (

I2S

LR

)G

PIO

8 /

ID

AT

A (

I2S

DA

TA

)V

CC

SD

O2

SD

I2S

DF

S2

SD

FS

3 /

DO

CK

ED

SC

LK

2G

PIO

9 /

PC

GN

T#

Maestro-2E

25

PA

RL

OC

K#

ST

OP

#D

EV

SE

L#

TR

DY

#IR

DY

#F

RA

ME

#C

/BE

2#

VC

CA

D1

6A

D1

7A

D1

8A

D1

9A

D2

0A

D2

1A

D2

2A

D2

3G

ND

IDS

EL

C/B

E3

#

A D 8A D 9A D 1 0A D 11A D 1 2

AD

13

AD

14

AD

15

GN

DC

/BE

1#

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

75 5174 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

100

76

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

26

50

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

100-Pin TQFP



PIN DESCRIPTION

PIN DESCRIPTION

Name Number I/O Definition

C/BE[3:0]# 1,13,21,31 I/O Multiplexed command/byte enable. These pins indicate cycle type during the address phase of a transaction. They indicate active-low byte enable information for the current data phase during the data phases of a transaction. These pins are inputs during slave operation and outputs dur-ing bus mastering operation.

IDSEL 2 I ID select, active-high. This pin is used as a chip select during PCI configuration read and write cycles.

AD[31:0] 92:99,4:11, 23:30,33:40

I/O Multiplexed address and data lines.

FRAME# 14 I/O Cycle frame, active-low. The current PCI bus master drives this pin to indicate the beginning and duration of a transaction.

IRDY# 15 I/O Initiator ready, active-low. The current PCI bus master drives this pin to indicate that as the initi-ator it is ready to transmit or receive data (and complete the current data phase).

TRDY# 16 I/O Target ready, active-low. The current PCI bus master drives this pin to indicate that as the target device it is ready to transmit or receive data (and complete the current data phase).

DEVSEL# 17 I/O Device select, active-low. The PCI bus target device drives this pin to indicate that it has decoded the address of the current transaction as its own chip select range.

STOP# 18 I/O Stop transaction, active-low. The current PCI bus target drives this pin active to indicate a request to the master to stop the current transaction.

LOCK# 19 I/O Lock.

PAR 20 I/O Parity, active-high. This pin indicates even parity across AD[31:0] and C/BE[3:0]# for both address and data phases. The signal is delayed one PCI clock from either the address or data phase for which parity is generated.

PME# 42 O Power management enable interrupt output to wake up the system.

CLKRUN#43

I/O Dual-purpose pin. CLKRUN# is an input for clock status and an output to start/speed-up clock.

ECS O ECS# is the EEPROM chip select. ECS is active during power-on reset; turned off after reset.

GPIO0

45

I/O Dual-purpose pin. GPIO0 is general purpose input/output 0. Selected by Maestro2E_Base+68h[11:0].

ISCLKI ISCLK is the serial shift clock for the DSP serial interface. Selected by setting PCI 52h[4] = 1 and

Maestro2E_Base+36h[15] = 1.

GPIO1

46

I/O Multi-purpose pin. GPIO1 is general purpose input/output 1. Selected by Maestro2E_Base+68h[11:0].

Strap pin:1 = TDMA mode for 440LX chipset (default).0 = PC/PCI mode for 440LX chipset.

IDOO IDO is the serial data output for the DSP serial interface. Selected by

setting PCI 52h[4] = 1 and Maestro2E_Base+36h[15] = 1.

GS0 O GS0 is PCI bus grant select 0. Selected by setting PCI 58h[0] = 1.

GPIO2

47


IDII IDI is the serial data input for the DSP serial interface. Selected by setting PCI 52h[4] = 1 and


R0# I R0# is PCI bus request 0. Selected by setting PCI 58h[0] = 1.

GPIO3

48


ILRI ILR is the frame sync signal for the DSP serial interface. Selected by setting PCI 52h[4] = 1 and


SPDIFOO SPDIFO is the S/PDIF output. Selected by setting PCI 53h[0] = 1 and PCI 58h[1] = 0. Alterna-

tively, the SPDIFO at pin 62 may be used. SPDIFO at pin 48 is the default.



PIN DESCRIPTION

GPIO4

49


Strap pin:1 = Subsystem ID[0] = 0.0 = Subsystem ID[0] =1.

VOLDNI VOLDN is a volume decrease input. Selected by setting PCI 52h[7:5]

to 1x0. Alternatively, the VOLUP/VOLDN pair at pins 73 and 74 may be used.

GS1 O GS1 is PCI bus grant select 1. Selected by setting PCI 58h[0] = 1.

GPIO5

50


VOLUPI VOLUP is a volume increase input. Selected by setting PCI 52h[7:5] to 1x0. Alternatively, the

VOLUP/VOLDN pair at pins 73 and 74 may be used.

R1# I R1# is PCI bus request 1. Selected by setting PCI 58h[0] = 1.

GPIO6

51


ISCLK (I2SCLK)

I ISCLK (I2SCLK) is the I2S serial clock. Selected by setting Maestro2E_Base+36h[15] = 1.

GPIO752


ILR (I2SLR)

I ILR (I2SLR) is the I2S frame sync. Selected by setting Maestro2E_Base+36h[15] = 1.

GPIO853


IDATA (I2SDATA)

I IDATA (I2SDATA) is the I2S data input pin. Selected by setting Maestro2E_Base+36h[15] = 1.

SDO2 55 I/O Serial data out.

SDI2 56 I Serial data in.

SDFS2 57 O Serial data frame sync. Strap pin in combination with strap pin 77. See the description for pin 77.

SDFS358

O Dual-purpose pin. SDFS3 is the serial data frame sync.

DOCKEDI DOCKED, when active-high, indicates that the unit is docked to an AC’97 CODEC with docking

station support. Internal 2.2k pull-down to digital ground.

SCLK2 59 I/O Serial data clock. Output pin when the multi-CODEC interface is used. Input pin when the AC-link #2 interface is used.

GPIO960


PCGNT# I PCGNT# is the PC/PCI grant input. Selected by setting PCI 50h[10:8] = 010.

GPIO1061


PCREQ# O PCREQ# is the PC/PCI request output. Selected by setting PCI 50h[10:8] = 010.

GPIO11

62


SIRQ# I/O SIRQ# is the serial interrupt request. Selected by setting PCI 40h[14] = 1.

SPDIFOO SPDIFO is the S/PDIF output. Selected by setting PCI 53h[0] = 1 and PCI 58h[1] = 1. Alterna-

tively, the SPDIFO at pin 48 may be used. SPDIFO at pin 48 is the default.

OSCI 64 I 49.152 MHz crystal input. Refer to the Maestro-2 reference design for an update.

OSCO 65 O 49.152 MHz crystal output. Refer to the Maestro-2 reference design for an update.

GD[3:0] 70:67 I/O Game port data. Joystick timer.

GD4 71 I Game port data. Joystick switch.




PIN DESCRIPTION

GD572

I Dual-purpose pin. GD5 is a game port data input pin.

EDOUT O EDOUT is EEPROM data output. EDOUT is active during power-on reset; turned off after reset.

GD6

73


VOLUPI VOLUP is a volume increase input. Selected by setting PCI 52h[7:5] = 1x1. Alternatively, the

VOLDN/VOLUP pair at pins 49 and 50 may be used.

EDIN I EDIN is EEPROM data input. EDIN is active during power-on reset; turned off after reset.

GD7

74


VOLDNI VOLDN is a volume decrease input. Selected by setting PCI 52h[7:5] = 1x1. Alternatively, the

VOLDN/VOLUP pair at pins 49 and 50 may be used.

ECLK O ECLK is the EEPROM clock output. ECLK is active during power-on reset; turned off after reset.

SCLK1 76 I Serial clock. In AC’97 configuration, this pin is an input which drives the timing for the AC’97 interface.

SDFS1 77 O Serial data frame sync. In AC’97 configurations, this strap pin is an output which indicates the framing for the AC’97 link with pin 57.

SDI1 78 I Serial audio data input.

SDO1 79 O Serial audio data out.

TxD80

O Dual-purpose pin. TxD is MIDI transmit data.

XSCO XSC is the ES978 Expansion Audio Mixer serial clock. Selected by setting PCI 58h[2] = 1 while

the DOCKED pin is high.

RxD

81

I Dual-purpose pin. RxD is MIDI receive data.

XSDI/O XSD is the ES978 Expansion Audio Mixer serial data input/output. Selected by setting PCI

58h[2] = 1 while the DOCKED pin is high.

C24 83 O 24.576 MHz clock output. For CODEC clock source.

RST# 84 I Reset.

INT# 85 O Interrupt request, active-low. This pin is the level triggered interrupt pin dedicated to servicing internal device interrupt sources.

PCICLK 87 I PCI bus clock. This clock times all PCI transactions. All PCI synchronous signals are generated and sampled relative to the rising edge of this clock.

GNT# 89 I Bus master grant, active-low. The system arbiter drives this pin to indicate to the device that access to the PCI bus has been granted.

REQ# 90 O Bus master request, active-low tri-state output. This pin indicates to the system arbiter that this device is requesting access to the PCI bus. This pin must be tri-stated when RST# is active.

VCC 12,32,54, 66,86,100

Pwr +3.3 volts.

GND 3,22,41,44, 63,75,88,91

Pwr Ground.


Pin 57 Pin 77 Option

0 0 Reserved.

0 1 Reserved.

1 0 Multi-CODEC pinout at pins 59:55.

1 1 AC-Link#2 pinout at pins 57:55, and 59.



STRAP SELECTED OPTION

STRAP SELECTED OPTION

MULTI-FUNCTION PIN ASSIGNMENT

Pin Name Pin Number Default State at Reset Condition Description

SDFS2 57 Pull-up See Description

In AC’97 configurations, this strap pin is an output which indicates the framing for the AC’97 link with pin 57.

SDFS1 77 Pull-up See Description

See description of pin 57.

GPIO1 46 Pull-up Low PC/PCI system configuration is detected.

High No PC/PCI system configuration is detected. TDMA mode for 440LX chipset.

GPIO4 49 Pull-up Low Bit 0 of PCI Configuration register 2Eh =1.

High Bit 0 of PCI Configuration register 2Eh =0.

Pin 57 Pin 77 Option

0 0 Reserved.

0 1 Reserved.

1 0 Multi-CODEC pinout at pins 59:55.

1 1 AC-Link#2 pinout at pins 57:55, and 59.

Function Pin Names Pin Numbers Selection Settings

DSP Serial Interface ISCLK,IDO,IDI,ILR 48:45 PCI 52h[4] = 1 and Maestro2E_Base+36h[15]=1

EEPROM Interface ECS#,EDOUT, EDIN,ECLK

43,74:72 Active during power-on reset. Turned off after reset.

ES978 Mixer Expansion Interface XSC,XSD 81:80 PCI 58h[2] = 1 and DOCKED pin high

General-Purpose Interface GPIO[11:0] 62:60,53:45 Maestro2E_Base+68h[11:0]

Hardware Volume Control VOLUP,VOLDN 50,49 PCI 52h[7:5] = 1x0

VOLUP,VOLDN 73,74 PCI 52h[7:5] = 1x1

I2S Interface ISCLK,ILR,IDATA 53:51 Maestro2E_Base+36h[15] = 1

Legacy Audio Interface PCGNT#,PCREQ# 61:60 PCI 50h [10:8] = 010

SIRQ# 62 PCI 40h[14] = 1

Multiple PCI Master Interface R[1:0]#,GS[1:0] 47,50,46,49 PCI 58h[0] = 1

Secondary AC’97 Interface(AC’97 Extension 2.00)

SCLK2,SDFS2, SDI2,SDO2

59, 57:55 Strap pin 57 high; strap pin 77 high

Serial CODEC Interface SCLK2,SDFS3, SDFS2,SDI2,SDO2

59:55 Strap pin 57 high; strap pin 77 low

S/PDIF Output SPDIFO 48 (default) PCI 53h[0] = 1 and PCI 58[1] = 0

62 PCI 53h[0] = 1 and PCI 58h[1] = 1



FUNCTIONAL PIN GROUPING

FUNCTIONAL PIN GROUPING

Function Pins Pin Number

ACPI Pin PME# 42

CODEC #1 Interface SCLK1 76

SDFS1 77

SDI1 78

SDO1 79

Clocks OSCI 64

OSCO 65

C24 83

Docking Station Interface Pin DOCKED * 58

DSP Serial Interface ISCLK * 45

IDO * 46

IDI * 47

ILR * 48

EEPROM Interface Pins ECS * 43

ECLK * 74

EDOUT * 72

EDIN * 73

ES978 Mixer Expansion Interface Pins

XSC * 80

XSD * 81

Game Port Interface GD[3:0] 70:67

GD4 71

GD5 * 72

GD6 * 73

GD7 * 74

General-Purpose I/O Pins GPIO0 * 45

GPIO1 * 46

GPIO2 * 47

GPIO3 * 48

GPIO4 * 49

GPIO5 * 50

GPIO6 * 51

GPIO7 * 52

GPIO8 * 53

GPIO9 * 60

GPIO10 * 61

GPIO11 * 62

Hardware Volume Control Pins VOLDN * 49,74

VOLUP * 50,73

I2S Interface ISCLK (I2SCLK) *

51

ILR (I2SLR) *

52

IDATA (I2SDATA) *

53

Legacy Audio Interface PCGNT# * 60

PCREQ# * 61

SIRQ# * 62

MPU-401 Interface TxD * 80

RxD * 81

Multiple PCI Master Interface R0# * 47

R1# * 50

GS0 * 46

GS1 * 49

PCI Bus Pins IDSEL 2

AD[31:0] 92:99,4:11, 23:30,33:40

C/BE[3:0]# 1,13,21,31

FRAME# 14

IRDY# 15

TRDY# 16

DEVSEL# 17

STOP# 18

LOCK# 19

PAR 20

CLKRUN# 43

RST# 84

INT# 85

PCICLK 87

GNT# 89

REQ# 90

Serial CODEC Interface / Secondary AC’97 Interface

SDO2 55

SDI2 56

SDFS2 57

SDFS3 * 58

SCLK2 59

S/PDIF Output SPDIFO * 48, 62

Power Pins VCC 100,86,66, 54,32,12

GND 91,88,75,63,44,41,22,3

* These pins share more than one function.

Function Pins Pin Number



POWER MANAGEMENT

POWER MANAGEMENT

The Maestro-2E is a high-performance device with lowpower consumption. Besides the low-power CMOStechnology used to process the Maestro-2E, variousfeatures are designed into the device to provide benefitsfrom popular power-saving techniques. These featuresand techniques are discussed in this section.

CLKRUN Protocol

The PCI CLKRUN feature is one of the primary methodsof power management on the PCI bus interface of theMaestro-2E for the notebook computer. Since somechipsets do not implement CLKRUN, this is not alwaysavailable to the system designer, and alternate power-saving features are provided.

PCI Power Management Interface (PPMI)

The PCI Power Management Interface (PPMI)specification establishes the infrastructure required to letthe operating system control the power of PCI functions.This is done by defining a standard PCI interface andoperations to manage the power of PCI functions on thebus. The PCI functions can be assigned one of five powermanagement states that result in varying levels of powersavings.

The five power-management states of PCI functions are:

• D0 – full power

• D1 and D2 – intermediate states

• D3 hot – off state; power supply is on

• D3 cold – off state; power supply is off

For the operating system to manage the device powerstates on the PCI bus, the PCI function should support fourpower-management operations:

– capabilities reporting

– power status reporting

– setting the power state

– system wake-up

The operating system identifies the capabilities of the PCIfunction by traversing the new capabilities list. Thepresence of new capabilities is indicated by setting bit [4]in the PCI Status register and providing access through acapabilities pointer to a capabilities list.

The capabilities pointer provides access to the first item inthe linked list of capabilities. For the Maestro-2E, thecapabilities pointer is mapped to an offset, C0h, indicatedin the PCI Configuration register at 34h. The first byte ofeach capability register block is required to be a unique IDof the capability. PCI power management has beenassigned an ID of 01h. The next byte is a pointer to thenext pointer item in the list of capabilities. There are nomore items in the list, so the next item pointer is set to zero.The registers following the next item pointer are specific tothat function’s capability. The PPMI capability implementsthe register block outlined in Table 1.

The Power-Management Capabilities register (PCIConfiguration register C2h in the Maestro-2E) is a staticread-only register that provides information on thecapabilities of the functions related to power-management. The Power-Management Control/Statusregister enables control of power-management states andenables and monitors power-management events. TheData register is an optional register that displays state-dependent power measurements such as powerconsumed or heat dissipation.

Table 1 Power-Management RegistersRegister Name Offset

Power-Management capabilities Next-Item pointer Capability ID 0

Data PMCSR bridge support extensions Power-Management control status (CSR) 4



DISABLING MAESTRO-2E AUDIO

ACPI Transition Diagram

Figure 6 ACPI Transition Diagram

DISABLING MAESTRO-2E AUDIO

To disable Maestro-2E audio in both notebook andmotherboard implementations:

1. Set PCI 04h[2:0] = 000.

This disables Maestro-2E response to all inputs andoutputs and Bus Master cycles.

2. Set PCI 41h[7] = 1.

This disables Maestro-2E response to all legacy audiofunctions.

D3hot

D3cold

D2

D1

D0active

power-on reset

PCI reset

VCC remove

d

timer expires

soft resetpower down

resume (0 m

s,100 ms)

pause

pause

D0uninitia-

lized

resume (200 µs, 100 ms)


PRELIMINARY

ES1921AC ‘97 Rev 2.1 Audio CODEC

Data Sheet

DESCRIPTION

The ES1921 CODEC is a general-purpose 18-bit stereo, fullduplex, audio codec that conforms to the analog componentspecification of the Rev 2.1 AC'97 (Audio Codec 97)Component Specification.

The ES1921 implements a high-performance accelerated PCIaudio solution when used with the ESS Maestro™ PCI DigitalAudio Controller. The ES1921 is equipped with a stereo 18-bitDAC, a stereo 18-bit ADC, 6 line-level inputs (4 stereo and 2mono), 3 outputs (2 stereo and 1 mono), and a Time DivisionMultiplexed (TDM) serial AC-Link to a Maestro or other digitalcontroller.

The ES1921 may be used as a primary or secondary CODEC inmultiple codec configurations conforming to the AC'97 Rev. 2.1specification.

The ES1921 audio CODEC can record and play back voice,sound, and music at 48 kHz sample rate. The playback mixer has4 stereo inputs (Line, CD, Video, Aux, and PCM digital audio)and 2 mono inputs (Mic and Phone, plus PC beep). The recordmultiplexer has 5 stereo inputs (Line, CD, Video, Aux, Mixer)and 3 mono inputs (Mic, Phone, and Mono mix). The mixer has3 outputs (Line, True Line Level, and Mono). Line out can beused for stereo output to multimedia speakers while Mono outcan be used to output to a telephony subsystem or down-linephone.

The ES1921 can be used on motherboards, add-on cards, orPCMCIA cards. The ES1921 is available in an industry-standard 48-pin Thin Quad Flat Pack (TQFP).

APPLICATIONS

FEATURES

• Single, high-performance, mixed-signal, 18-bit stereo VLSI chip

• Meets or exceeds Audio CODEC ’97 Rev. 2.1 performance specifications

• Supports 2-CODEC architecture for configuration with one ES1921 in notebook and one in docking station

• AC-Link digital serial interface (TDM format) to a Maestro or other digital controller

Record and Playback Features • Full-duplex stereo operation for simultaneous record and

playback

• 18-bit stereo ADC and DAC; 3rd 18-bit ADC for mic input

• 48 kHz playback and record sample rate

Inputs/Outputs • 4 stereo inputs for line-in, CD, video, and auxiliary line-in

• 2 selectable mono inputs for microphone sharing a single mixer input and 1 mono input for phone

• PC speaker input

• 2 stereo outputs for line-out (for example, multimedia speakers and DVD Pure Audio)

Power • Advanced Configuration and Power Interface (ACPI) support.

• EAPD - External Amplifier Power Down Control

• 3.3 V or 5.0 V digital and 5.0 V analog power supply (AVDD >= DVDD)

Compatibility • Meets Microsoft PC98 and PC99 1.0 specifications for

Baseline and Advanced Audio with FAQ updates

• Meets Intel’s Audio CODEC ’97 Rev 2.1 specifications

• Multimedia PCs • Business Audio

• 3-D PC Games • Audio Conferencing

DigitalInterface

SYNC

BIT_CLK

RESET#

SDATA_OUT

SDATA_IN

DAC

DAC

ADC

ADC

RegisterSet

Mixer

PC Beep

Phone

Line

CD

Video

Aux

Mic1Mic2Mux

Analog Mixing

and

Volume Control

Mono Out

Line Out

ES1921L

R

L

R

True Line Out

+20 dB


ES1921 DATA SHEET

PINOUT

PRELIMINARY

PINOUT

Figure 1 ES1921 48-Pin Pinout

ES1921

1

MONO_OUT

AVDD2

LNLVL_OUT_L

NC

LNLVL_OUT_R

AVSS2

NC

NC

ID0

ID1

EAPD

NC

DV

DD

1

XT

L_I

N

XT

L_O

UT

DV

SS1

SDA

TA

_OU

T

BIT

_CL

K

DV

SS2

SDA

TA

_IN

DV

DD

2

SYN

C

RE

SET

#

PC

_BE

EP

LIN

E_O

UT

_R

LIN

E_O

UT

_L

AN

TI_

PO

P

CA

P3

CA

P2

CA

P1

AF

ILT

2

AF

ILT

1

VR

EFO

UT

VR

EF

AV

SS1

AV

DD

1

LINE_IN_R

LINE_IN_L

MIC2

MIC1

CD_R

CD_GND

CD_L

VIDEO_R

VIDEO_L

AUX_R

AUX_L

PHONE

2 3 4 5 6 7 8 9 10 11

14

23

22

21

20

19

18

17

16

15

24252627282930313233343536

37

38

39

40

41

42

43

44

45

46

47

48 13

12

48-PIN TQFP


ES1921 DATA SHEET

PIN DESCRIPTION

PRELIMINARY

PIN DESCRIPTION

Name Number I/O Description

DVDD1 1 PWR Digital VDD

XTL_IN 2 I Oscillator input (24.576 MHz)

XTL_OUT 3 I Oscillator output

DVSS1 4 DGND Digital ground

SDATA_OUT 5 I AC ‘97 Serial data in

BIT_CLK 6 O Serial data clock (12.288 MHz)

DVSS2 7 DGND Digital ground

SDATA_IN 8 O AC ‘97 Serial data out

DVDD2 9 PWR Digital VDD

SYNC 10 I Fixed rate sample sync (48 kHz).

RESET # 11 I Hardware reset

PC_BEEP 12 I PC speaker out

PHONE 13 I Telephone speaker input

AUX_L 14 I Aux left channel input

AUX_R 15 I Aux right channel input

VIDEO_L 16 I Video left channel input

VIDEO_R 17 I Video right channel input

CD_L 18 I CD left channel input

CD_GND 19 I CD ground

CD_R 20 I CD right channel input

MIC1 21 I First microphone input

MIC2 22 I Second microphone input

LINE_IN_L 23 I Line-in left channel input

LINE_IN_R 24 I Line-in right channel input

AVDD1 25 PWR Analog VDD

AVSS1 26 AGND Analog ground

VREF 27 I DAC reference voltage filter capacitor

VREFOUT 28 O Mic reference voltage output (2.5 V, 1.25 mA)

AFILT1 29 O Anti-Aliasing Filter Cap - ADC channel

AFILT2 30 O Anti-Aliasing Filter Cap - ADC channel

CAP1 31 O Analog output hold-off delay

CAP2 32 O ADC Reference Capacitor

CAP3 33 O Anti-Pop Power Sustain Delay

ANTI_POP 34 O Anti-Pop Output Ground Shunt Control

LINE_OUT_L 35 O Line Out Left Channel

LINE_OUT_R 36 O Line Out Right Channel

MONO_OUT 37 O Mono out

AVDD2 38 PWR Analog VDD

LNLVL_OUT_L 39 O True Line Level Output Left Channel

NC 40 NC No connect

LNLVL_OUT_R 41 O True Line Level Output Right Channel

AVSS2 42 AGND Analog ground

NC 43, 44, 48 NC No connect

ID0 45 I Multi-CODEC ID select - bit 0

ID1 46 I Multi-CODEC ID select - bit 1


ES1921 DATA SHEET

FUNCTIONAL DESCRIPTION

PRELIMINARY


This section shows the overall structure of the ES1921 anddiscusses its major functional subunits.

The major subunits of the ES1921 are shown in Figure 2 anddescribed briefly in the following paragraphs.

Figure 2 ES1921 Block Diagram

A simplified ES1921 block diagram is given in Figure 2. TheES1921 performs fixed 48K sample rate D-A and A-Dconversion, mixing, and analog processing. Its digital interfacecommunicates with the AC'97 digital controller, such as an ESSMaestro™ PCI Digital Audio controller, via the five-wire AC-Link. Two fixed 48Ks/s DACs support two stereo PCM-outchannels. The digital mix of all sources, including the internalsynthesizer and any other digital sources, is performed in thedigital controller. The Mixer block mixes the PCM_OUT withany analog sources, then outputs to LINE_OUT andLNLVL_OUT. The MONO_OUT delivers either mic only or amono mix of sources from the mixer. The two fixed 48Ks/s

ADCs take any mix of mono or stereo sources and convert it toa stereo PCM-in signal. All ADCs and DACs operate at 18-bitresolution.

EAPD 47 O External Amplifier Power Down

Name Number I/O Description

LINE_OUT

LINE_IN

AVDD

AVSS

MIC2

CD

RESET#

XTL_IN XTL_OUT

REF GEN

VIDEO

DVDDDVSS

AUX

AFILT[1:0]

PREAMP/MIC BOOST MIC1

RECORD

SOURCE

PLAYBACK

MIXER

SDATA_IN

BIT_CLK

SYNC

AC-LINK

SDATA_OUTMONO_OUT

PHONE

PC_BEEP

VREFVREFOUT

ID[1:0]

LNLVL

MASTERVOL

CTRL

MASTERVOL

CTRL

MONOVOL

CTRLLeft

Right

Left

RIght

EAPD

STEREO DAC18-BIT

FILTER ADC18-BIT

FILTER ADC18-BIT

STEREO DAC18-BIT

DAC

DAC

ANTI_POP

PCM-out DACs

PCM-in ADCs

POWER MGMT


ES1921 DATA SHEET


PRELIMINARY

Digital Subsystems

• AC-Link – a four line serial link between the ES1921 and a Maestro or other digital controller. The fifth line, RESET#, is linked directly to the host or to the Maestro. This link is the control interface for the ES1921. It also carries audio data between the ES1921 and its digital controller.

Analog Subsystems

• Playback Mixer – eight input stereo mixer. All inputs can be muted. Each of the following inputs has a 5-bit volume control:

– PCM Out (digital audio from the Maestro digital control-ler)

– Line In

– CD audio In

– Video Audio In

– Auxiliary In

– Phone In

– Mic1 or Mic2 Mono In

This input has a 4-bit volume control:

– PC Beep Throughput

• 18-Bit stereo DAC – for audio playback of digital audio from the Maestro digital controller.

• 18-Bit stereo ADC – for audio record. Audio is returned to the host via the AC-Link and the digital controller.

• Record source and input volume control – input source and volume control for recording. The Mic source can be mixed post input volume with its own independent input volume control. The recording source can be selected from one of eight choices:

– Line In

– CD Audio In

– Auxiliary In

– Video Audio In

– Stereo mix

– Mono mix

– Mic In

– Phone

• Output volume and mute – The output master volume supports 5 bits per channel plus mute. There are separate volume controls for mono out and stereo outs.

• Reference generator – analog reference voltage generator.

• Pre-amp – 20 dB microphone pre-amplifier with bypass.

Mixer

The ES1921 mixer is designed to the AC'97 specification tomanage the playback and record of all digital and analog audiosources in the PC environment. These include:

• System Audio: digital PCM input and output for business, games and multimedia

• CD/DVD: analog CD/DVD-ROM Redbook audio with internal connections to Codec mixer

• Mono microphone: choice of desktop mic, with programmable boost and gain

• Speakerphone: use of system mic and speakers for telephone, DSVD, and video conferencing

• Video: TV tuner or video capture card with internal connections to Codec mixer

• AUX/synth: analog FM or wavetable synthesizer, or other internal source

Mixer InputThe mixer provides recording and playback of any audiosources or output mix of all sources. The ES1921 supports thefollowing input sources:

• any mono or stereo source

• mono or stereo mix of all sources

• 2-channel input w/mono output reference (mic + stereo mix)

Note: any unused input pins should have a capacitor (1 uFsuggested) to ground.

Mixer OutputThe mixer generates two distinct outputs:

• a stereo mix of all sources for output to the LINE_OUT

• a stereo mix of all sources for output to the LNLVL_OUT

• a mono, mic only or mix of all sources for MONO_OUT

NOTE: Mono output of stereo mix is attenuated by -6 dB .

PC Beep ImplementationPC Beep is active on power up and defaults to an unmuted state.The user should mute this input before using any other mixerinput because the PC Beep input can contribute noise to thelineout during normal operation.


ES1921 DATA SHEET

MIXER SCHEMATIC BLOCK DIAGRAM

PRELIMINARY

MIXER SCHEMATIC BLOCK DIAGRAM

ADC

PCM indigital audio

PCM outDAC

digital audio

MIC1

LINE IN

CD

VIDEO

Line out

OutputVolume

Record

Record

MasterVolume

Source

Volume

Mono outMono

Volume

MIC2

PHONE

PC BEEP

AUX

Preamp

Σ

stereo line

mono line

MonoSelect

MicSelect

LNLVLout

PlaybackMixer

Line LevelVolume

Bypass

andMute

Σ

-6 dB

-6 dB

Table 1 Mixer Functional ConnectionsSOURCE FUNCTION CONNECTION

PC_Beep PC beep pass thru from PC beeper output

PHONE speakerphone or DLP in from telephony subsystem

MIC1 desktop microphone from mic jack

MIC2 second microphone from second mic jack

LINE_IN external audio source from line-in jack

CD audio from CD-ROM cable from CD-ROM

VIDEO audio from TV tuner or video camera cable from TV or VidCap card

AUX upgrade synth or other external source internal connector

PCM out digital audio output from AC'97 digital controller AC-Link

LINE_OUT stereo mix of all sources To output jack

LNLVL_OUT Additional stereo mix of all sources To output jack

MONO_OUT mic or mix for speakerphone or DLP out to telephony subsystem

PCM in digital audio input to AC'97 digital controller AC-Link


ES1921 DATA SHEET

TYPICAL APPLICATION (PRIMARY CODEC CONFIGURATION)

PRELIMINARY

TYPICAL APPLICATION (PRIMARY CODEC CONFIGURATION)

Aux In Left

Aux In Right

Line In Left

Line In Right

AUX_R

AUX_L

AVDD1

RESET#

SDATA_IN

SDATA_OUT

BIT_CLK

SYNC

DVDD1

LINE_IN_R

LINE_IN_L

ES1921

SDFS1

SCLK1

SDO1

SDI1

GPO0

Maestro

XTL_IN

XTL_OUT

Video In LeftVIDEO_L

Video In RightVIDEO_R

CD_L

CD_RCD In Left

CD In Right

LINE_OUT_R

MONO_OUT

To Stereo

Amplifier

LINE_OUT_L

PHONE Phone In

CDGND CD Ground

AVSS1

AVSS2

DVSS1

DVSS2

VREF

VREFOUT

DVDD2

AVDD2

AFILT1

AFILT2

MIC1 Mic1 In

MIC2 Mic2 In

PC_BEEP PC Beep In

Digital Controller

LNLV_L

LNLV_R

CAP2

True LevelLine Out

ID0

ID1

C24

EAPD

0.1 µF10 µF

10 µF 0.1 µF

560 to 1000 pF

5.0 V ± 5% 1 uF

.1 uF

.1 uF

10 uF

.1 uF

.1 uF

3.3 V ± 5%or 5.0 V ± 5%

ANTI_POP

560 to 1000 pF

CAP110 µF10 µF

Optional

CAP322 µF

Optional

0.1


ES1921 DATA SHEET

ANALOG DESIGN CONSIDERATIONS

PRELIMINARY

ANALOG DESIGN CONSIDERATIONS

This section describes design considerations related to inputsand outputs of analog signals and related pins on the chip.

Reference Generator

Reference generator pins VREF , VREF Out, and CAP2 areshown below.

Figure 3 Reference Generator Pin Diagram

Anti-Aliasing Filter

The filter pins AFILT1 and AFILT2 are shown in Figure 4.

Figure 4 Anti-Aliasing Filter Pin Diagram

Power Connection

The recommended power connection is shown below. Analog/Digital power sequencing order is not critical and the chipdesign avoids latch-up.

Figure 5 Recommended Power Connection

ES1921VREF

10 µF

0.1 µF

VREF OUT

CAP2 10 µF

0.1 µF

ES1921

AFILT1

560 to 1000 pF

AFILT2

560 to 1000 pF

ES1921

DVDD

AVDD

3.3 V or 5.0 V

5.0 V


ES1921 DATA SHEET

AC-LINK CLOCK AND RESET

PRELIMINARY


Figure 6 shows the AC-Link serial interface and the clockinglink between the ES1921 and its Maestro digital controller. Alldigital audio streams and command/status information arecommunicated over the AC-Link. See “Digital Interface” onpage 13 for details. AC-Link is described in the Intel AudioCodec ‘97 Specification, which is available for download fromIntel at its web site:http://developer.intel.com/pc-supp/platform/ac97

Figure 6 ES1921's AC-Link to the Maestro Digital Controller

Clocking

The beginning of all audio frames transferred over the AC-Linkis synchronized to the rising edge of the SYNC signal driven bythe Maestro or other digital controller. Data is transmittedthrough the AC-Link on every rising edge of BIT_CLK, andsubsequently sampled by the receiving side on eachimmediately following falling edge of BIT_CLK.

There are three different clock inputs available to the ES1921.The potential inputs are a Maestro digital controller, an externalcrystal, and a master ES1921.

Maestro Digital Controller as SourceThe ES1921 can derive its clock internally from the Maestrodigital controller through the XTAL_IN pin. See Figure 6. Thiseliminates the need for an extra component. Synchronizationwith the Maestro digital controller is achieved through theBIT_CLK pin at 12.288 MHz (half of crystal frequency).

External CrystalThe clocking for the ES1921 can be derived from a 24.576 MHzexternal crystal connected to the XTAL_IN and XTAL_OUTpins. See Figure 7.

Master CODEC as SourceIn cases where the ES1921 is a slave CODEC and can’t bedriven by the Maestro digital controller, its internal clocking isderived by doubling the BIT_CLK input. The BIT_CLK inputreceived from master CODEC synchronizes the AC-link and

determines the clocking for the slave CODEC. If there is noBIT_CLK input, the slave CODEC stays dead. For discussion ofthis, see “Master-Slave Operation” below.

Figure 7 ES1921's clocking from an external crystal

Reset

There are 3 types of resets as detailed under “TimingCharacteristics”.

• a “cold” reset where all ES1921 logic including registers is initialized to its default state

• a “warm” reset where the contents of the ES1921 register set are left unaltered

• a “register” reset which only initializes the ES1921 registers to their default states

After signaling a reset to the ES1921, the AC'97 digitalcontroller should not attempt to play or capture audio data untilit has sampled a “Codec Ready” indication (bit 15 Slot 0) viaregister 26h from the ES1921.

For proper reset operation SDATA_OUT should be “0” during“cold” reset. See “Testability” section for more information.

Master-Slave Operation

Certain applications require multiple CODECs supporting asingle digital controller. For example, a notebook computer andits docking station is such an application. In this example, adigital controller and CODEC reside in the notebook while anadditional CODEC is in the docking station. The docking stationCODEC provides access to the audio resources available to thedocking station. These two CODECs are in a master-slaverelationship.

The master CODEC generates BIT_CLK for both the Maestrodigital controller and the slave CODEC. This ensures that allthree chips are in sync. In addition, internal chip clocking for theslave CODEC is derived by doubling the BIT_CLK input fromthe master CODEC.

The master and slave CODECs are determined by the status ofthe ID pins. If either of the two ID pins is tied low, the CODECis a slave.

ES1921DigitalController

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

MaestroRESET#

XTAL_IN

ES1921

XTAL_OUT

XTAL_IN


ES1921 DATA SHEET


PRELIMINARY

Table 2 CODEC Master-Slave Relationship (External Pins)

The Maestro-2E digital controller provides for two CODECinterfaces. For an example, see Figure 8 below.

Table 3 Maestro-2E/ES1921 Pin Assignments

Figure 8 Example of Dual CODEC Design

ID0 ID1 CODEC Relationship

DVDD or Floating DVDD or Floating Master

GND DVDD or Floating

SlaveDVDD or Floating GND

GND GND

InterfaceMaestro-2E

Master ES1921

Pin Name Pin Name

Master CODEC

GPO0 RESET#

SCLK1 BIT_CLK

SDFS1 SYNC

SDI1 SDATA_IN

SDO1 SDATA_OUT

C24 XTAL_IN

InterfaceMaestro-2E Slave ES1921

Pin Name Pin Name

Slave CODEC

GPO3 RESET#

SDI2 SDATA_IN

SDO2 SDATA_OUT

SDFS2 SYNC

SCLK2 BIT_CLK

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

XTAL_INSDFS1

SCLK1

SDO1

SDI1

XTAL_IN

C24

ID0

ID1

ID0

ID1

Maestro-2E

Maestro-2E and Dual ES1921s for Notebook Plus Docking Station Configuration

Docking Station ES1921 (Slave)

Notebook ES1921 (Master)

RESET#

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

GPO0

SDFS2

SDO2

SDI2

GPO3

SCCK2

Documents

Maestro-2E PCI Audio Accelerator Data Sheet