M11 8085 Programming

7/31/2019 M11 8085 Programming

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EE 201 : Digital Circuits andMicroprocessors

Dr. Amit Sethi

Room 303, EEE Dept.

2529, amitsethi


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Objectives for this session Introduce the 8085 Microprocessor

Introduction to 8085 programming model

Introduction to 8085 instruction set


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Computer: Basic definitions Computer is a machine that

sequentially and automaticallycarries out a sequence ofarithmetic or logical operationsgiven as instructions in form of aprogram, which can be changed

readily, allowing the computer tosolve more than one kind ofproblem

Data and programs can be read

from memories, storage or inputdevices

Data can be written into memory,storage and output devices


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All computers are based on the TuringMachine concept

In 1937, Alan Turing described this

abstract idea of a computer Turing Machines consist of:A tape of infinite length with symbols printed in cells

A read-write head that can move along the tape to read andwrite symbols

A state from a finite set stored inside the machine

A finite set of instructions that translate the current state and the

read symbol into an action which can be: Change to another state Move to another place on the tape

Write a symbol on the tape


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Von Neumann Architecture

Based on TM concept

Employs a single data bus to fetch both the instruction and the data

Has a CPU with a control unit, an Arithmetic and Logic Unit (ALU) and

registers to temporarily store data for the two to use Memory and I/O are addressed by a separate address bus


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8085 has become a popular microprocessorfor teaching

A simple 8-bit design, introduced by Intel in

1977 compatible with the more-famous Intel8080

Relatively easy to study and operate: Required less supporting hardware than 8080

"5" is for +5-volt (V) power supply rather than the+5V, -5V and +12V supplies the 8080 needed

Had a long life as a microcontroller (with addedperipherals)

Its actual name is 8085A, and it is NMOS devicecontaining ~6,500 transistors and 40 pins


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80

85Architecture


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Another View


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80

85Pin

Diagram


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16-bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

8-bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

A Accumulator S Z 0 AC 0 P 1 CY F

BC B CDE D E

HL H L

PC PC

SP SP

8085 Programming Model There are 6 general purpose

registers, 8-bits wide eachB, C, D, E, H, and L

They are used as needed.

Can be used as 16-bit register pairs: BC, DE, HL The accumulator is technically part of the ALU It is 8-bits wide

It is one of the inputs to every ALU operation

The result of any operation is always stored in it

It is known as Register A

Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan


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The 8085 Programming Model The ALU includes five flag

flip-flops that are set orreset after an operation:They are Z (zero), CY (carry), S

(sign), P (parity) and AC(Auxiliary Carry)

These flags are used when themicroprocessor tests for data

conditionsThese make up the Flags

Register


8-bit data bus 16-bit address bus

16-bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

8-bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0


BC B C

DE D E

HL H L

PC PC

SP SP


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The 8085 Instructions

Since the 8085 is an 8-bit device it can have up to 28 (256)instructions

However, the 8085 only uses 246 combinations thatrepresent a total of 74 instructions Most of the instructions have more than one format

These instructions can be grouped into five differentgroups:Data Transfer Operations

Arithmetic Operations

Logic OperationsBranch Operations

Control Operations



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Instruction and Data Formats

Each instruction can have two parts, e.g. ADDB:The first part is the task or operation to be

performed This part is called the opcode (operation code) This part is essential for all instructions

In 8085, all opcodes are 8-bits wideThe second part is the data to be operated on

Called the operand



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Operand Types There are different ways for specifying the operand:

There may not be an operand (implied operand) CMA

The operand may be an 8-bit number (immediate data) ADI 4FH

The operand may be an internal register (register) SUB B

The operand may be a 16-bit address (memory address) LDA 4000H



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Instruction Size Depending on the operand type, the instruction may

have different sizes. It will occupy a different number ofmemory bytes: Instructions with implied operand occupy one byte

Instruction that contains immediate data or a memory addressoccupy 2 or 3 bytes:

Instructions that include immediate data use two bytes:

One for the opcode and the other for the 8-bit data.

Instructions that include a memory address occupy three bytes:

One for the opcode, and the other two for the 16-bit address.



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Instruction with Immediate Data Operation: Load an 8-bit number into the

accumulator

MVI A, 32 Operation: MVI A Operand: The number 32

Binary Code (Hex code):

0011 1110 3E 1st byte.

0011 0010 32 2nd byte.



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Instruction with a Memory Address Operation: go to address 2085

Instruction: JMP 2085 Opcode: JMP Operand: 2085 Binary code (Hex code):

1100 0011 C3 1st byte.1000 0101 85 2nd byte0010 0000 20 3rd byte

Note: Error in book on page 146.



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Addressing Modes

The microprocessor has different ways ofspecifying the data for the instruction. These

are called addressing modes: The 8085 has four addressing modes:

Implied CMAImmediate MVI B, 45

Direct LDA 4000

Indirect LDAX B Load the accumulator with the contents of the memory

location whose address is stored in the register pair

BC).Source: 7305862-Introduction-to-8085-Instructions.ppt by Dr. Bassel Soudan


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A simple program

Objective: Add 3216 and 4816

Notice that: Possible instructions are defined by the programming model

There is a 1-to-1 relation between an instruction in English, its mnemonic,Hex and binary. In the lab, you will get a handout for this

Step English Mnemonic

(Assembly)

Memory

Address

Hex Binary

(Machine)

1 Load 3216 intoaccumulator

MVI A,32H C000C001

3E

32

0011 1110

0011 0010

2 Load 4816 intoregister B

MVI B,48H C002C003

06

48

0000 0110

0100 1000

3 Add B to A ADD B C004 80 1000 0000

4 Halt HLT C005 76 0111 0110


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Revision: 8085 Programming Model Can address 64K 8-bit wide locations

Has 6 general purpose

registers, 8-bits wide each B, C, D, E, H, and L

They are used as needed. Can be used as 16-bit register pairs:

BC, DE, HL

The accumulator (or A) is part of the ALU

It is 8-bits wide It is one of the inputs to every ALU operation

The result of any operation is always stored in it

Flag register contains the following bits: Z (zero), CY (carry), S (sign), P (parity) and AC (Auxiliary Carry)

Program counter (also called the instruction pointer) indicates thememory address of the instruction to be executed

Stack pointer points to top of the (subroutine) call stack


8-bit data bus 16-bit address bus

16-bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

8-bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0


BC B C

DE D E

HL H L

PC PC

SP SP


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8085 Addressable Locations

8085 is an 8-bit P All calculations manipulate 8-bits of

data

Operations and data with more bits is

broken down into 8-bits It can handle 16-bit memory

Memory has 64k addressable locations

These locations are divided into:

User addressable (stored in a RAM) EEPROM

I/O ports (connected to devices)

Bi-directional8-bit data bus

1 byte word

Unidirection

al16bitaddressbus(lower8

multiplexedwithdatab

us)

64Klocations(2byteaddress)

8085 addressablelocations


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The 8085 Instructions

Since the 8085 is an 8-bit device it can have up to 28 (256)instructions

However, the 8085 only uses 246 combinations thatrepresent a total of 74 instructions Most of the instructions have more than one format

These instructions can be grouped into five differentgroups:Data Transfer Operations

Arithmetic Operations

Logic OperationsBranch Operations

Control Operations



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Data Transfer Operations These operations simply COPY the data from the

source to the destination MOV, MVI, LDA, and STA

They transfer:Data between registersData Byte to a register or memory location

Data between a memory location and a register

Data between an I/O Device and accumulator

The data in the source is not changed.



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Arithmetic Operations Addition (ADD, ADI):

Any 8-bit number.

The contents of a register.

The contents of a memory location.

Can be added to the contents of the accumulator and the result isstored in the accumulator.

Subtraction (SUB, SUI): Any 8-bit number

The contents of a register

The contents of a memory location

Can be subtracted from the contents of the accumulator. The result isstored in the accumulator



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Arithmetic Operations Increment (INR) and Decrement (DCR):

The 8-bit contents of any memory location or anyregister can be directly incremented ordecremented by 1

No need to disturb the contents of theaccumulator



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Logic Operations These instructions perform logic operations on

the contents of the accumulator ANA, ANI, ORA, ORI, XRA and XRI

Source: Accumulator and An 8-bit number

The contents of a register

The contents of a memory location

Destination: AccumulatorANA R/M AND Accumulator With Reg/Mem

ANI # AND Accumulator With an 8-bit number

ORA R/M OR Accumulator With Reg/Mem

ORI # OR Accumulator With an 8-bit number

XRA R/M XOR Accumulator With Reg/Mem

XRI # XOR Accumulator With an 8-bit number

Complement:1s complement of the contents of the accumulator

CMA No operand



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Unconditional Branch JMP Address

Jump to the address specified (Go to)

CALL Address Jump to the address specified but treat it as a subroutine

RET Return from a subroutine

The addresses supplied to all branch operations must be16-bits



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Conditional Branch Go to new location if a specified condition is met

JZ Address (Jump on Zero) Go to address specified if the Zero flag is set

JNZ Address (Jump on NOT Zero) Go to address specified if the Zero flag is not set

JC Address (Jump on Carry)

Go to the address specified if the Carry flag is set

JNC Address (Jump on No Carry) Go to the address specified if the Carry flag is not set

JP Address (Jump on Plus)

Go to the address specified if the Sign flag is not set JM Address (Jump on Minus)

Go to the address specified if the Sign flag is set



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Machine Control HLT

Stop executing the program NOP

No operation

Exactly as it says, do nothing

Usually used for delay or to replace instructions

during debugging



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Program 1: Read a 16-bit number from memory, take its

1s complement and store it back in memoryStep English Mnemonic

(Assembly)

Memory

Address

Hex Binary

(Machine)

1 Load number pointer of

lower 8-bits to H

LXI H,C050 C000

C001C002

21

50C0

0010 0001

0101 00001100 0000

2 Move lower 8-bits to A MOV A,M C003 7E 0111 1110

3 Complement A CMA C004 2F 0010 1111

4 Write A to C052 STA C052 C005C006C007

3252

C0

0011 00100101 0010

1100 0000

5 Increment H INX H C008 23 0010 0011

6 Move upper 8-bits to A MOV A,M C009 7F 0111 1111

7 Complement A CMA C00A 2F 0010 1111

8 Write A to C053 STA C053 C00BC00CC00D

32

53

C0

0011 0010

0101 0011

1100 0000

9 Halt HLT C00E 76 0111 0110


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Program 2: Generate a Fibonacci sequence//Fibonacci Series Generation

//To run the Program simply load at

// memory location C050=01,C051=01

START :

MVI C,09//Counter

LXI H,C050 //Memory Pointer

X :

MOV A,MINX H

MOV B,M

INX H

ADD B

DAAMOV M,A

DCX H

DCR C

JNZ X

HLT


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Objectives for this session Understand the Memory Map

Learn about interfacing with I/O devices

Note: The following slides have been adapted from works of others, primarily:

8085architecturememoryinterfacing1-100523023313-phpapp01.ppt by Pratik Amlani and

1204-ppi-8255-100523023201-phpapp02.ppt by Unknown


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Memory map: 64K memory device Address lines required: 16 (A0 A15)

Memory map: 0000H - FFFFH

Memory map: 32K memory device Address lines required: 15 (A0 A14)

Memory map: depends on how address line A15is connected


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U1

8085

36

1

2

5

6

9

8

7

1011

29

33

39

35

12

13

14

15

16

1718

19

21

22

23

2425

26

27

28

30

31

32

34

3

37

4

38

RST-IN

X1

X2

SID

TRAP

RST 5.5

RST 6.5

RST 7.5

INTR

INTA

S0

S1

HOLD

READY

AD0

AD1

AD2

AD3

AD4AD5

AD6

AD7

A8

A9

A10

A11

A12

A13

A14

A15

ALE

WR RD

IO/M

RST-OT

CLKO

SOD

HLDA

U2

74LS373

3

4

7

8

13

1417

18

111

2

5

6

9

12

1516

19

D0

D1

D2

D3

D4D5

D6

D7

OCG

Q0

Q1

Q2

Q3

Q4Q5

Q6

Q7

U4

27C256

10

9

8

7

6

54

3

25

24

21

232

26

27

20

22

1

11

12

13

15

1617

18

19

A0

A1

A2

A3

A4A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

CE

OEVPP

O0

O1

O2

O3O4

O5

O6

O7

U5A

74LS32

1

2

3

Memory device is selected only if IO/M = 0 & A15 = 0

You can do other things with A15=1, such as communicate with devices

RAM


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So the memory map of the RAM in the

previous slide is

0 0 0 0

A11 to A0A15 A14 A13 A12

0. 0 0 = 0000H

0 1 1 1

A11 to A0A15 A14 A13 A12

1. 111 = 7FFFH

to


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Interfacing I/O Devices Using I/O devices data can be transferred

between the microprocessor and the outsideworld.

This can be done in groups of 8 bits using the

entire data bus. This is called parallel I/O.

The other method is serial I/O where one bit is

transferred at a time using the SI and SO pinson the Microprocessor.


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Interfacing I/O devices with 8085

8085

I/O

Interface

I/O

Devices

MemoryInterface

MemoryDevices

System Bus


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8085 Communication with I/O devices Involves the following three steps:

1.Identify the I/O device (with address)

2.Generate Timing & Control signals

3.Data transfer takes place


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Techniques for I/O Interfacing Memory-mapped I/O

Consider them like any other memory location. They are assigned a 16-bit address within the address range of the

8085.

The exchange of data with these devices follows the transfer of datawith memory. The user uses the same instructions used for memory.

Peripheral-mapped (or I/O-mapped) I/OTreat them separately from memory:

I/O devices are assigned a port number within the 8-bit addressrange of 00H to FFH.

The user in this case would access these devices using the IN andOUT instructions only.


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1.Identify the I/O device (with address)1. Memory-mapped I/O (16-bit address)

2. Peripheral-mapped I/O (8-bit address)


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2.Generate Timing & Control Signals Memory-mapped I/O

Reading Input: IO/M = 0, RD = 0Write to Output: IO/M = 0, WR = 0

Peripheral-mapped I/OReading Input: IO/M = 1, RD = 0

Write to Output: IO/M = 1, WR = 0

3. Data transfer takes place


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Memory-mapped I/O

8085 uses its 16-bit address bus to identify a memory location

Memory address space: 0000H to FFFFH

8085 needs to identify I/O devices also I/O devices can be interfaced using addresses from memory

space

8085 treats such an I/O device as a memory location This is called Memory-mapped I/O

Same commands are used to communicate with I/O devicesthat are memory mapped, e.g. MOV

STA


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Memory-mapped I/O Instructions I/O devices are identified by 16-bit addresses

8085 communicates with an I/O device as if it wereone of the memory locations

Memory related instructions are used

For e.g. LDA, STA LDA 8000HLoads A with data read from input device with 16-bit

address 8000H

STA 8001HStores (Outputs) contents of A to output device with 16-bit

address 8001H


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Example Program WAP to read a number from input port (port address

8000H) and display it on ASCII display connected tooutput port (port address 8001H)

LDA 8000H;reads data value 03H(example) into

;accumulator, A = 03HMVI B, 30H;loads register B with 30H

ADD B ;A = 33H, ASCII code for 3

STA 8001H;display 3 on ASCII display


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Peripheral-mapped I/O 8085 has a separate 8-bit addressing scheme for I/O

devices I/O address space: 00H to FFH

This is called Peripheral-mapped I/O or I/O-

mapped I/O The chip used to interface with peripherals is 8255

also called PPI (programmable Peripheral Interface)

This uses different commands, e.g. IN

OUT


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Peripheral I/O Instructions IN Instruction

Inputs data from input device into theaccumulator

It is a 2-byte instruction

Format: IN 8-bit port addressExample: IN 01H


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Peripheral I/O Instructions OUT Instruction

Outputs the contents of accumulator to an outputdevice

It is a 2-byte instruction

Format: OUT 8-bit port addressExample: OUT 02H


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Programmable Interface Devices Used to interface a I/O device to the

microprocessor

8085Programmable

I/O

Interface

I/O

Devices

System Bus

Can be programmed/configured to performvarious I/O functions by writing softwareinstructions


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8255 A programmable parallel I/O device Designed to be compatible with 8085

It consists ofThree I/O ports

Port A

Port B

Port C

Port C can be used as two 4-bit ports

PCu (Port C upper 4 bits)

PCl (Port C lower 4 bits)


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Example of I/O Interfacing using 8255

80858255

8-bitADC

System

Bus

LEDDISPLAY

TemperatureSensor

Port A

Port Cu

Port B

Port Cl


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Problem example Let us say that we want to read an 8-bit input,

take its complement, and display the result on8 LEDs

Here are the steps to follow:

1. Configure the 8255 ports2. Write program to:

1. Read input from an 8255 port

2. Take its complement3. Write output to an 8255 port, which is connected toLEDs


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1. Configure 8255 I/O Ports

80858255

System

Bus

LEDDISPLAY

8-bit inputPort A

Port Cu

Port B

Port Cl

To configure 8255 we need to know


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To configure 8255, we need to know

its Modes of Operation Two primary modes of operation

1. Parallel I/O mode Mode 0 (Simple Input/Output)

Mode 1 (Input/Output with Handshake)

Mode 2 (Bidirectional data transfer)2. Bit Set/Reset Mode

This application uses Parallel I/O mode - Mode 0


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Control Word for 8255 8255 has a 8-bit Control word register

8255 ports can be configured for operation bywriting a appropriate control word in it

for Parallel I/O


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0 (No BSR)

0

0

0 (dont care)

1

00

1

90H


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Application Programming1. Configure 8255 I/O ports

1. MVI A, 90H2. OUT CWR

Writing value 90H in Control Word Register

of 8255 CWR represents the 8-bit port address of

Control Word Register

Application Programming


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Application Programming2. Write program:

1. MVI A, 90H2. OUT CWR

3. IN PORTA4. CMA

5. OUT PORTB

3. Note that the output will have to bebuffered, because the P output is fleeting

(remains for a very short time)

8255 Chip selection & Port Addresses


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p

8255A2A3

A4

A5

A6

A7

CS

A1

A0

A1

A0

A = 80H

B = 81H

C = 82HA1 A0 Port

0 0 A

0 1 B

1 0 C

1 1 CWR

P i ith t dd


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Programming with port addresses

OUT 83H

IN 80H OUT 81H

OUT CWR

IN PORTA OUT PORTB


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Objectives for this session Understand how interrupts work

Classification of interrupts Processing of interrupts in 8085

Using interrupts for I/O interfacing


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Definition and Classification Interrupt is a process where an external device can

get the attention of the microprocessor.The process starts from the I/O device.The process is asynchronous.

Classification of InterruptsBased on priority:

Maskable Interrupts (Can be delayed or Rejected)

Non-Maskable Interrupts (Can not be delayed or Rejected)

Based on where the interrupt service routine is: Vectored (the address of the service routine is hard-wired) Non-vectored (the address of the service routine needs to be supplied

externally by the device)

Source: www.aust.edu/cse/moinul/interrupt.pptby Moinul Hoque

What happens when an interrupt is


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pp p

generated? An interrupt is a signal that requires

microprocessors attention.The Microprocessor may respond to it as soon as possible.

What happens when P is interrupted ?

When the Microprocessor receives an interrupt signal, itsuspends the currently executing program andjumps to anInterrupt Service Routine (ISR) to respond to the incominginterrupt (if not masked).

Each interrupt will most probably have its own ISR.



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Responding to Interrupts Responding to an interrupt may be immediate or

delayed depending on whether the interrupt ismaskable or non-maskable and whether interruptsare being masked or not.

There are two ways of redirecting the execution tothe ISR depending on whether the interrupt isvectored or non-vectored.Vectored: The address of the subroutine is already known

to the Microprocessor

Non Vectored: The device will have to supply the addressof the subroutine to the Microprocessor


The 8085 Interrupts


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The 8085 Interrupts When a device interrupts, it actually wants the P to

give a service which is equivalent to asking the P tocall a subroutine. This subroutine is called ISR(Interrupt Service Routine)

The EI instruction is a one byte instruction and isused to Enable the non-maskable interrupts.

The DI instruction is a one byte instruction and isused to Disable the non-maskable interrupts.

The 8085 has a single Non-Maskable interrupt.The non-maskable interrupt is not affected by the value ofthe Interrupt Enable flip flop.


The 8085 Interrupts


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The 8085 Interrupts

The 8085 has 5 interrupt inputs.The INTR input.

The INTR input is the only non-vectored interrupt. INTR is maskable using the EI/DI instruction pair.

RST 5.5, RST 6.5, RST 7.5 are all automaticallyvectored.

RST 5.5, RST 6.5, and RST 7.5 are all maskable.

TRAP is the only non-maskable interrupt in the8085 TRAP is also automatically vectored


8085 Interrupts


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8085 Interrupts

8085

TRAP

RST7.5

RST6.5

RST 5.5

INTR

INTA

Interrupt name Maskable Vectored

INTR Yes No

RST 5.5 Yes Yes

RST 6.5 Yes Yes

RST 7.5 Yes Yes

TRAP No Yes


Interrupt Vectors and Vector Table


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Interrupt Vectors and Vector Table

An interrupt vector is a pointer to where theISR is stored in memory.

All interrupts (vectored or otherwise) aremapped onto a memory area called theInterrupt Vector Table (IVT).

The IVT is usually located in memory page 00(0000H - 00FFH).

The purpose of the IVT is to hold the vectors that

redirect the microprocessor to the right placewhen an interrupt arrives.


Example


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Example

Let , a device interrupt the Microprocessor using theRST 7.5 interrupt line.

Because the RST 7.5 interrupt is vectored, Microprocessorknows, in which memory location it has to go using a callinstruction to get the ISR address.

RST7.5 is known as Call 003CH to Microprocessor.Microprocessor goes to 003C location and will get a JMP

instruction to the actual ISR address. The Microprocessorwill then, jump to the ISR location



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The 8085 Non-Vectored Interrupt Process


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The 8085 Non Vectored Interrupt Process

6. Microprocessor Performs the ISR.

7. ISR must include the EI instruction to enable the furtherinterrupt within the program.

8. RET instruction at the end of the ISR allows the P to

retrieve the return address from the stack and theprogram is transferred back to where the program wasinterrupted.


The 8085 Non-Vectored Interrupt Process


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The 8085 Non Vectored Interrupt Process

The 8085 recognizes 8 RESTART instructions:RST0 - RST7.each of these would send the execution to a

predetermined hard-wired memory location:Restart

Instruction

Equivalent

toRST0 CALL 0000H

RST1 CALL 0008H

RST2 CALL 0010H

RST3 CALL 0018HRST4 CALL 0020H

RST5 CALL 0028H

RST6 CALL 0030H

RST7 CALL 0038HSource: www.aust.edu/cse/moinul/interrupt.pptby Moinul Hoque

Restart Sequence


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Restart Sequence

The restart sequence is made up of three

machine cyclesIn the 1st machine cycle: The microprocessor sends the INTA signal.

While INTA is active the microprocessor reads the data lines

expecting to receive, from the interrupting device, the opcode forthe specific RST instruction.

In the 2nd and 3rd machine cycles: the 16-bit address of the next instruction is saved on the stack.

Then the microprocessor jumps to the address associated withthe specified RST instruction.


Hardware Generation of RST Opcode


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a d a e Ge e at o o S Opcode

How does the external device produce

the opcode for the appropriate RSTinstruction?The opcode is simply a collection of bits.

So, the device needs to set the bits of thedata bus to the appropriate value inresponse to an INTA signal.

77



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Issues in Implementing INTR Interrupts


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p g p

How long must INTR remain high?

The microprocessor checks the INTR line one clock cycle

before the last T-state of each instruction.The INTR must remain active long enough to allow for the

longest instruction.

The longest instruction for the 8085 is the conditional CALLinstruction which requires 18 T-states.

Therefore, the INTR must remain active for 17.5 T-states.

If f= 3MHZ then T=1/f and so, INTR must remain active for [(1/3MHZ) * 17.5 5.8 micro seconds].




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p g p

How long can the INTR remain high?

The INTR line must be deactivated before the EI isexecuted. Otherwise, the microprocessor will beinterrupted again.

Once the microprocessor starts to respond to anINTR interrupt, INTA becomes active (=0).

Therefore, INTR should be turned off as soon asthe INTA signal is received.




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Can the microprocessor be interrupted again beforethe completion of the ISR?As soon as the 1st interrupt arrives, all maskable interrupts

are disabled.

They will only be enabled after the execution of the EI

instruction.

Therefore, the answer is: only if we allow it to.

If the EI instruction is placed early in the ISR, otherinterrupt may occur before the ISR is done.


Multiple Interrupts & Priorities


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How do we allow multiple devices to interrupt

using the INTR line?The microprocessor can only respond to onesignal on INTR at a time.

Therefore, we must allow the signal from only oneof the devices to reach the microprocessor.

We must assign some priority to the different

devices and allow their signals to reach themicroprocessor according to the priority.



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Multiple Interrupts & Priorities


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Note that the opcodes for the different RSTinstructions follow a set pattern. Bit D5, D4 and D3 of the opcodes change in a binary sequence

from RST 7 down to RST 0.

The other bits are always 1.

This allows the code generated by the 74366 to be used directlyto choose the appropriate RST instruction.

The one draw back to this scheme is that theonly way to change the priority of the devices

connected to the 74366 is to reconnect thehardware.



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Masking RST 5.5, RST 6.5 and RST 7.5


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These three interrupts are masked at two

levels:Through the Interrupt Enable flip flop andthe EI/DI instructions.

The Interrupt Enable flip flop controls the whole maskable

interrupt process.

Through individual mask flip flops thatcontrol the availability of the individual

interrupts. These flip flops control the interrupts individually.


The 8085 Maskable/Vectored Interrupt Process


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1. The interrupt process should be enabled using the EIinstruction.

2. The 8085 checks for an interrupt during the execution ofevery instruction.

3. If there is an interrupt, and if the interrupt is enabled

using the interrupt mask, the microprocessor willcomplete the executing instruction, and reset theinterrupt flip flop.

4. The microprocessor then executes a call instruction thatsends the execution to the appropriate location in theinterrupt vector table.



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Manipulating the Masks


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The Interrupt Enable flip flop is manipulatedusing the EI/DI instructions.

The individual masks for RST 5.5, RST 6.5 and

RST 7.5 are manipulated using the SIMinstruction.This instruction takes the bit pattern in the

Accumulator and applies it to the interrupt maskenabling and disabling the specific interrupts.



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SIM and the Interrupt Mask


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Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit 2 is themask for RST 7.5.

If the mask bit is 0, the interrupt is available.

If the mask bit is 1, the interrupt is masked.

Bit 3 (Mask Set Enable - MSE) is an enable for setting the mask.

If it is set to 0 the mask is ignored and the old settings remain.

If it is set to 1, the new setting are applied. The SIM instruction is used for multiple purposes and not only for

setting interrupt masks.

It is also used to control functionality such as Serial Data

Transmission. Therefore, bit 3 is necessary to tell the microprocessor whether ornot the interrupt masks should be modified


SIM and the Interrupt Mask


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The RST 7.5 interrupt is the only 8085 interrupt that has memory.

If a signal on RST7.5 arrives while it is masked, a flip flop will

remember the signal. When RST7.5 is unmasked, the microprocessor will be interrupted

even if the device has removed the interrupt signal.

This flip flop will be automatically reset when the microprocessor

responds to an RST 7.5 interrupt.

Bit 4 of the accumulator in the SIM instruction allows explicitlyresetting the RST 7.5 memory even if the microprocessor did not

respond to it. Bit 5 is not used by the SIM instruction


Maskable Interrupts and vector

l i


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locations

InterruptEnable

Flip Flop

INTR

RST 5.5

RST 6.5

RST 7.5

M 5.5

M 6.5

M 7.5

RST7.5 Memory



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Using the SIM Instruction to Modify the

Interrupt Masks


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Interrupt Masks Example: Set the interrupt masks so that RST5.5 is

enabled, RST6.5 is masked, and RST7.5 is enabled.

First, determine the contents of the accumulator

SD

O

SD

E

XX

X

R7.5

M

SE

M

7.5

M

6.5

M

5.5

- Enable 5.5 bit 0 = 0- Disable 6.5 bit 1 = 1- Enable 7.5 bit 2 = 0- Allow setting the masks bit 3 = 1- Dont reset the flip flop bit 4 = 0- Bit 5 is not used bit 5 = 0- Dont use serial data bit 6 = 0- Serial data is ignored bit 7 = 0

0 1 00000 1

Contents of accumulator are: 0AH

EI ; Enable interrupts including INTRMVI A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5SIM ; Apply the settings RST masks


Determining the Current Mask Settings


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RIM instruction: Read Interrupt MaskLoad the accumulator with an 8-bit pattern

showing the status of each interrupt pin andmask.

Interrupt EnableFlip Flop

RST 5.5

RST 6.5

RST 7.5

M 5.5

M 6.5

M 7.5

RST7.5 Memory

SDI

P7.5

P6.5

P5.5 IE

M7.5

M6.5

M5.5

01234567


How RIM sets the Accumulators different bits


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SD

I

P7.5

P6.5

P5.5

IE M7

.5

M6

.5

M5

.5

01234567

RST5.5 Mask

RST6.5 Mask

RST7.5 Mask} 0 - Available1 - Masked

Interrupt EnableValue of the Interrupt EnableFlip Flop

Serial Data In

RST5.5 Interrupt Pending




The RIM Instruction and the Masks


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Bits 0-2 show the current setting of the maskfor each of RST 7.5, RST 6.5 and RST 5.5

They return the contents of the three mask flip flops. They can be used by a program to read the mask settings in

order to modify only the right mask.

Bit 3 shows whether the maskable interruptprocess is enabled or not. It returns the contents of the Interrupt Enable Flip Flop.

It can be used by a program to determine whether or notinterrupts are enabled.


The RIM Instruction and the Masks


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Bits 4-6 show whether or not there arepending interrupts on RST 7.5, RST 6.5, andRST 5.5 Bits 4 and 5 return the current value of the RST5.5 and RST6.5

pins.

Bit 6 returns the current value of the RST7.5 memory flip flop.

Bit 7 is used for Serial Data Input. The RIM instruction reads the value of the SID pin on the

microprocessor and returns it in this bit.


Pending Interrupts


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Since the 8085 has five interrupt lines,interrupts may occur during an ISR and remainpending.Using the RIM instruction, it is possible to can

read the status of the interrupt lines and find ifthere are any pending interrupts.


TRAP

TRAP is the only non maskable interrupt


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TRAP is the only non-maskable interrupt.It does not need to be enabled because it cannot be

disabled.

It has the highest priority amongst interrupts.

It is edge and level sensitive.It needs to go high and stay high to be recognized.

Once it is recognized, it wont be recognized againuntil it goes low, then high again.

TRAP is usually used for power failure andemergency shutoff.


The 8085 Interrupts


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Interrupt

Name

MaskableMasking

Method

Vectored MemoryTriggering

Method

INTR Yes DI / EI No NoLevel

Sensitive

RST 5.5 /

RST 6.5 Yes

DI / EI

SIM Yes No

Level

Sensitive

RST 7.5 YesDI / EI

SIMYes Yes

Edge

Sensitive

TRAP No None Yes NoLevel &Edge

Sensitive


Stacks and Subroutines


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The Stack


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The stack is an area of memoryidentified by the programmer for

temporary storage of information. The stack is a LIFO structure.

Last In First Out.

The stack normally grows backwardsinto memory. In other words, the programmer defines

the bottom of the stack and the stackgrows up into reducing address range.

Source: Stack_and_Subroutine.pdf by Moinul Hoque

The Stack Given that the stack grows backwards into memory, it is


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Given that the stack grows backwards into memory, it iscustomary to place the bottom of the stack at the end ofmemory to keep it as far away from user programs as

possible. In the 8085, the stack is defined by setting the SP (Stack

Pointer) register. LXI SP, FFFFH

This sets the Stack Pointer to location FFFFH (end ofmemory for the 8085).

The Size of the stack is limited only by the available

memory.


Saving and retrieving information on

the Stack


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the Stack Information is saved on the stack by PUSHing

it on.

It is retrieved from the stack by POPping it off.

The 8085 provides two instructions:

PUSH for storing information on the stackPOP for retrieving it back.

Both PUSH and POP work with register pairsONLY


The PUSH Instruction


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PUSH B (1 Byte Instruction)Decrement SP

Copy the contents of register B to the memorylocation pointed to by SP

Decrement SPCopy the contents of register C to the memory

location pointed to by SP


The POP Instruction


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POP D (1 Byte Instruction)Copy the contents of the memory location pointed

to by the SP to register E

Increment SP

Copy the contents of the memory location pointedto by the SP to register D

Increment SP


Operation of the Stack


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During pushing, the stack operates in a decrementthen store style.

The stack pointer is decremented first, then theinformation is placed on the stack.

During POPping, the stack operates in a use then

increment style.The information is retrieved from the top of the stack and

then the pointer is incremented.

The SP pointer always points to the top of the stack


LIFO The order of PUSHs and POPs must be opposite of

h h i d i i f i b k i


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each other in order to retrieve information back intoits original location.

PUSH B PUSH D

...

POP D POP B

Reversing the order of the POP instructions will

result in the exchange of the contents of BC and DE


The PSW Register Pair


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The 8085 recognizes one additional register paircalled the PSW (Program Status Word).

This register pair is made up of the Accumulator and theFlags registers.

It is possible to push the PSW onto the stack, do

whatever operations are needed, then POP it off ofthe stack.The result is that the contents of the Accumulator and the

status of the Flags are returned to what they were beforethe operations were executed


Push & Pop PSW Register Pair

PUSH PSW (1 Byte Instruction)


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y Decrement SP

Copy the contents of register A to the memory location pointed to by SP

Decrement SP Copy the contents of Flag register to the memory location pointed to by S

POP PSW (1 Byte Instruction) Copy the contents of the memory location pointed to by the SP to Flag

register Increment SP

Copy the contents of the memory location pointed to by the SP to registerA

Increment S



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Subroutines

h h i i f d li i h


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The 8085 has two instructions for dealing withsubroutines.The CALL instruction is used to redirect program

execution to the subroutine.

The RET instruction is used to return the executionto the calling routine.


CALL Instruction

CALL 4000H (3 b i i )


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CALL 4000H (3 byte instruction)When CALL instruction is fetched, the MP knows

that the next two Memory location contains 16bitsubroutine address in the memory.


CALL Instruction

MP Reads the subroutine address from the next


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two memory location and stores the higher order8bit of the address in the W register and stores

the lower order 8bit of the address in the Zregister

Push the address of the instruction immediately

following the CALL onto the stack [Return address]Loads the program counter with the 16-bit

address supplied with the CALL instruction fromWZ register


RET Instruction

RET (1 b t i t ti )


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RET (1 byte instruction)Retrieve the return address from the top of the

stack

Load the program counter with the return address


Things to be considered in Subroutine

The CALL instruction places the return address at the


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The CALL instruction places the return address at thetwo memory locations immediately before where the

Stack Pointer is pointing.You must set the SP correctly BEFORE using the CALL

instruction.

The RET instruction takes the contents of the twomemory locations at the top of the stack and usesthese as the return address.

Do not modify the stack pointer in a subroutine. You willloose the return address.


Things to be considered in Subroutine

Number of PUSH and POP instruction used in


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Number of PUSH and POP instruction used inthe subroutine must be same, otherwise, RETinstruction will pick wrong value of the returnaddress from the stack and program will fail.


Conditional CALL and RTE Instructions

The 8085 supports conditional CALL and


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ppconditional RTE instructions.

The same conditions used with conditional JUMPinstructions can be used.

CC, call subroutine if Carry flag is set.

CNC, call subroutine if Carry flag is not setRC, return from subroutine if Carry flag is set

RNC, return from subroutine if Carry flag is not set

Etc.


A Proper Subroutine

According to Software Engineering practices a


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According to Software Engineering practices, aproper subroutine:

Is only entered with a CALL and exited with an RETHas a single entry point

Do not use a CALL statement to jump into different

points of the same subroutine.Has a single exit point

There should be one return statement from any

subroutine.


Program 4: Use a subroutines for bubble

sorting 5 numbers//Implementing bubble sort COMP_SWAP:


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START:

MVI D,05 //Outer loop

W:

LXI H,C020

MVI C,05 //Inner loop

X:

CALL COMP_SWAP

DCR C

JNZ X

DCR D

JNZ WHLT

_

MOV A,M

INX H

MOV B,M

CMP B

CP STORE_BACK

RET

STORE_BACK:

MOV M,A

DCX H

MOV M,B

INX H

RET

Appendix: Programming the 8255


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Interfacing of input devices

The basic concepts are similar to interfacing of


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p goutput devices.

The address lines are decoded to generate a signal that is activewhen the particular port is being accessed.

An IORD signal is generated by combining the IO/M and the RDsignals from the microprocessor.

A tri-state buffer is used to connect the input deviceto the data bus. The control (Enable) for thesebuffers is connected to the result of combining the

address signal and the signal IORD.

Examples of Interfacing I/O Devices

To illustrate the techniques of interfacing I/O


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To illustrate the techniques of interfacing I/Odevices we will design the circuits needed to

interface 8 LEDs to display the contents of theaccumulator as well as 8 switches to set thecontents of the accumulator.

Interfacing the LEDs

Lets first design the external circuit.


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gThe data on the data bus from the microprocessor stays for

an extremely short amount of time. So, in order to keep itlong enough for displaying, we will need an external latch.

We will use an 8-bit latch to hold the data we need to connect the8 LED to the latches outputs.

However, the latch will not be able to source enoughcurrent. So, we will use the inverted outputs and make it

sink the current instead.

When should the latch be enabled?

It needs to be enabled when the data is on the data


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bus.

That happens when the ALE signal is low. However, weonly want to display the data that is being sent to the I/O,we dont want to display the data being saved in memory.

So, the latch needs to be enabled only during I/O

operations. That happens when IO/M=1Finally we only want to display data intended for our port.

We must decide on a port number. Lets say FFH.

Now, we can design the control circuit.

Interfacing the LEDs (Control Circuit)

The Latch will be enabled when:


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WR = 0

IO/M = 1

The address on A8 A15 = FFH

Latch Enable

A15

A8

IO/M

WR

Interfacing the LEDs (Latch & LEDs)


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Interfacing the LEDs (the program)

When a bit on the AD bus is 1, the


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corresponding Q will be zero and the LED will

have 5 volts on the anode and 0 on thecathode. Therefore, it will be on.

Finally, to write the program:MVI A, Data ;load the data to be displayed

OUT FF ;send the data to output port FF

HLT ;End

Interfacing the switches

The binary value from the switches will have to becarried by the data bus. However, the data bus is ashared bus So the switches must be connected to


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shared bus. So, the switches must be connected tothe data bus using Tri-state buffers.

Similar to the latch, the buffers must be enabled onlyon I/O Read operation from this I/O port.

Lets choose I/O port 0FH for the switches. So, thebuffers must be enabled when:

RD = 0

IO/M = 1

A8-A15 = 0FH

Source: http://www.kulo.in/micro/8085ss/Chapter%25204.ppt

Interfacing the Switches(Control Circuit)


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IO/MRD

Buffer Enable

A8


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Documents

M11 8085 Programming