1

LTC3727/LTC3727-1

3727fc

High Efficiency, 2-PhaseSynchronous Step-Down Switching Regulators

Figure 1. High Efficiency Dual 12V/5V Step-Down Converter

■ Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 14V■ Out-of-Phase Controllers Reduce Required Input

Capacitance and Power Supply Induced Noise■ OPTI-LOOP® Compensation Minimizes COUT■ ±1% Output Voltage Accuracy■ Power Good Output Voltage Monitor■ Phase-Lockable Fixed Frequency 250kHz to 550kHz■ Latched Short-Circuit Shutdown (LTC3727 Only)■ Dual N-Channel MOSFET Synchronous Drive■ Wide VIN Range: 4V to 36V Operation■ Very Low Dropout Operation: 99% Duty Cycle■ Adjustable Soft-Start Current Ramping■ Foldback Output Current Limiting■ Output Overvoltage Protection■ Low Shutdown IQ: 20μA■ Selectable Constant Frequency or Burst Mode®

Operation■ Small 28-Lead SSOP Package■ LTC3727-1 Also Available in the 5mm × 5mm QFN

Package

The LTC®3727/LTC3727-1 are high performance dualstep-down switching regulator controllers that drive allN-channel synchronous power MOSFET stages. A con-stant frequency current mode architecture allows phase-lockable frequency of up to 550kHz. Power loss and noisedue to the ESR of the input capacitors are minimized byoperating the two controller output stages out of phase.

OPTI-LOOP compensation allows the transient responseto be optimized over a wide range of output capacitance andESR values. There is a precision 0.8V reference and a powergood output indicator. A wide 4V to 30V (36V maximum)input supply range encompasses all battery chemistries.

A RUN/SS pin for each controller provides soft-start, andon the LTC3727GN, optional timed, short-circuit shut-down. Current foldback limits MOSFET heat dissipationduring short-circuit conditions when overcurrent latchoffis disabled. Output overvoltage protection circuitry latcheson the bottom MOSFET until VOUT returns to normal. TheFCB mode pin can select among Burst Mode, constantfrequency mode and continuous inductor current mode orregulate a secondary winding.

■ Telecom Systems■ Automotive Systems■ Battery-Operated Digital Devices

+4.7μF

M2

M1

0.1μF

105k1%

1000pF

8μH

220pF

1μFCERAMIC

22μF50VCERAMIC

+ 47μF6VSP

0.015Ω

20k1% 15k

VOUT15V5A

M4

M30.1μF

280k1%

15μH

220pF

1000pF

+56μF15VSP

0.015Ω

20k1%

15k

VOUT212V4A

TG1 TG2

BOOST1 BOOST2

SW1 SW2

BG1 BG2

SGND

PGND

SENSE1+ SENSE2+

SENSE1– SENSE2–

VOSENSE1 VOSENSE2

ITH1 ITH2

VIN PGOOD INTVCC

RUN/SS1 RUN/SS2

VIN18V TO 28V

M1, M2, M3, M4: FDS6680A3727 F01

0.1μF 0.1μF

LTC3727/LTC3727-1

PLLIN

DESCRIPTIO

U

FEATURES

APPLICATIO SU

TYPICAL APPLICATIO

U

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All othertrademarks are the property of their respective owners. Protected by U.S. Patents, including5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6304066, 5705919.

2

LTC3727/LTC3727-1

3727fc

ORDER PARTNUMBER

LTC3727EGLTC3727EG-1LTC3727IG-1

Input Supply Voltage (VIN) .........................36V to –0.3VTop Side Driver Voltages(BOOST1, BOOST2) ...................................42V to –0.3VSwitch Voltage (SW1, SW2) .........................36V to –5VINTVCC, EXTVCC, (BOOST1-SW1),(BOOST2-SW2) ........................................8.5V to –0.3VRUN/SS1, RUN/SS2, PGOOD ..................... 7V to –0.3VSENSE1+, SENSE2 +, SENSE1–,SENSE2 – Voltages .....................................14V to –0.3VPLLIN, PLLFLTR, FCB Voltages ........... INTVCC to –0.3V

TJMAX = 125°C, θJA = 95°C/W

ABSOLUTE AXI U RATI GS

W WW U

PACKAGE/ORDER I FOR ATIOU UW

1

2

3

4

5

6

7

8

9

10

11

12

13

14

TOP VIEW

G PACKAGE28-LEAD PLASTIC SSOP

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS1

SENSE1+

SENSE1–

VOSENSE1

PLLFLTR

PLLIN

FCB

ITH1

SGND

3.3VOUT

ITH2

VOSENSE2

SENSE2–

SENSE2+

PGOOD

TG1

SW1

BOOST1

VIN

BG1

EXTVCC

INTVCC

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

Consult LTC Marketing for parts specified with wider operating temperature ranges.

(Note 1)

ITH1, ITH2, VOSENSE1, VOSENSE2 Voltages ...2.7V to –0.3VPeak Output Current <10μs (TG1, TG2, BG1, BG2) ... 3AINTVCC Peak Output Current ................................ 50mAOperating Temperature Range (Note 2) .. –40°C to 85°CJunction Temperature (Note 3) ............................. 125°CStorage Temperature Range ................. –65°C to 125°CLead Temperature(Soldering, 10 sec, G Package)............................. 300°CSolder Reflow Temperature (UH Package) ........... 265°C

32 31 30 29 28 27 26 25

9 10 11 12 13

TOP VIEW

33

14 15 16

17

18

19

20

21

22

23

24

8

7

6

5

4

3

2

1VOSENSE1

PLLFLTR

PLLIN

FCB

ITH1

SGND

3.3VOUT

ITH2

BOOST1

VIN

BG1

EXTVCC

INTVCC

PGND

BG2

BOOST2

NC SENS

E1–

SENS

E1+

NC RUN/

SS1

PGOO

D

TG1

SW1

V OSE

NSE2 NC

SENS

E2–

SENS

E2+

RUN/

SS2

TG2

SW2

NC

UH PACKAGE32-LEAD (5mm × 5mm) PLASTIC QFN

ORDER PARTNUMBER

LTC3727EUH-1

TJMAX = 125°C, θJA = 34°C/WEXPOSED PAD (PIN 33) IS SGND(MUST BE SOLDERED TO PCB)

UH PARTMARKING

37271

The ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.ELECTRICAL CHARACTERISTICS

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBFLead Free Part Marking: http://www.linear.com/leadfree/

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSMain Control LoopsVOSENSE1, 2 Regulated Feedback Voltage (Note 4); ITH1, 2 Voltage = 1.2V ● 0.792 0.800 0.808 VIVOSENSE1, 2 Feedback Current (Note 4) –5 – 50 nAVREFLNREG Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 4) 0.002 0.02 %/V

3

LTC3727/LTC3727-1

3727fc

The ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSVLOADREG Output Voltage Load Regulation (Note 4)

Measured in Servo Loop; ΔITH Voltage = 1.2V to 0.7V ● 0.1 0.5 %Measured in Servo Loop; ΔITH Voltage = 1.2V to 2.0V ● –0.1 –0.5 %

gm1, 2 Transconductance Amplifier gm ITH1, 2 = 1.2V; Sink/Source 5μA (Note 4) 1.3 mmhogmGBW1, 2 Transconductance Amplifier GBW ITH1, 2 = 1.2V (Note 4) 3 MHzIQ Input DC Supply Current (Note 5)

Normal Mode VIN = 15V, EXTVCC Tied to VOUT1, VOUT1 = 8.5V 670 μA Shutdown VRUN/SS1, 2 = 0V 20 35 μA

VFCB Forced Continuous Threshold ● 0.76 0.800 0.84 VIFCB Forced Continuous Pin Current VFCB = 0.85V – 0.30 – 0.18 – 0.05 μAVBINHIBIT Burst Inhibit (Constant Frequency) Measured at FCB pin 6.8 7.3 V

ThresholdUVLO Undervoltage Lockout VIN Ramping Down ● 3.5 4 VVOVL Feedback Overvoltage Lockout Measured at VOSENSE1, 2 ● 0.84 0.86 0.88 V

ISENSE Sense Pins Total Source Current (Each Channel) VSENSE1–, 2– = VSENSE1+, 2+ = 0V – 85 – 60 μA

DFMAX Maximum Duty Factor In Dropout 98 99.4 %IRUN/SS1, 2 Soft-Start Charge Current VRUN/SS1, 2 = 1.9V 0.5 1.2 μAVRUN/SS1, 2 ON RUN/SS Pin ON Threshold VRUN/SS1, VRUN/SS2 Rising 1.0 1.5 1.9 VVRUN/SS1, 2 LT RUN/SS Pin Latchoff Arming Threshold VRUN/SS1, VRUN/SS2 Rising from 3V (LTC3727 Only) 4.1 4.5 VISCL1, 2 RUN/SS Discharge Current Soft-Short Condition VOSENSE1, 2 = 0.5V, 0.5 2 4 μA

VRUN/SS1, 2 = 4.5V (LTC 3727 Only)ISDLHO Shutdown Latch Disable Current VOSENSE1, 2 = 0.5V (LTC3727 Only) 1.6 5 μAVSENSE(MAX) Maximum Current Sense Threshold VOSENSE1, 2 = 0.7V,VSENSE1–, 2– = 12V ● 105 135 165 mV

TG Transition Time: (Note 6)TG1, 2 tr Rise Time CLOAD = 3300pF 50 90 nsTG1, 2 tf Fall Time CLOAD = 3300pF 50 90 ns

BG Transition Time: (Note 6)BG1, 2 tr Rise Time CLOAD = 3300pF 40 90 nsBG1, 2 tf Fall Time CLOAD = 3300pF 40 80 nsTG/BG t1D Top Gate Off to Bottom Gate On Delay CLOAD = 3300pF Each Driver 90 ns

Synchronous Switch-On Delay TimeBG/TG t2D Bottom Gate Off to Top Gate On Delay CLOAD = 3300pF Each Driver 90 ns

Top Switch-On Delay TimetON(MIN) Minimum On-Time Tested with a Square Wave (Note 7) 180 nsINTVCC Linear RegulatorVINTVCC Internal VCC Voltage 8.5V < VIN < 30V, VEXTVCC = 6V 7.2 7.5 7.8 VVLDO INT INTVCC Load Regulation ICC = 0mA to 20mA, VEXTVCC = 6V 0.2 1.0 %VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 8.5V 70 160 mVVEXTVCC EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive ● 6.9 7.3 VVLDOHYS EXTVCC Hysteresis 0.3 VOscillator and Phase-Locked LoopfNOM Nominal Frequency VPLLFLTR = 1.2V 350 380 430 kHzfLOW Lowest Frequency VPLLFLTR = 0V 220 255 290 kHzfHIGH Highest Frequency VPLLFLTR ≥ 2.4V 460 530 580 kHz

4

LTC3727/LTC3727-1

3727fc

Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition for extended periods may affect devicereliability and lifetime.Note 2: The LTC3727E/LTC3727E-1 are guaranteed to meet performancespecifications from 0°C to 85°C. Specifications over the –40°C to 85°Coperating temperature range are assured by design, characterization andcorrelation with statistical process controls. The LTC3727IG-1 isguaranteed to meet performance specifications over the –40°C to 85°Coperating temperature range.Note 3: TJ is calculated from the ambient temperature TA and powerdissipation PD according to the following formulas:

Efficiency vs Output Currentand Mode (Figure 13)

Efficiency vs Output Current(Figure 13)

Efficiency vs Input Voltage(Figure 13)

TYPICAL PERFOR A CE CHARACTERISTICS

UW

OUTPUT CURRENT (A)0.0010

EFFI

CIEN

CY (%

)

10

30

40

50

100

70

0.01 0.1 1

3727 G01

20

80

90

60

10

FORCEDCONTINUOUSMODE

Burst ModeOPERATION

VIN = 15VVOUT = 8.5V

CONSTANTFREQUENCY(BURST DISABLE)

OUTPUT CURRENT (A)0.001

EFFI

CIEN

CY (%

)

70

80

10

3727 G02

60

500.01 0.1 1

100

90

VIN = 10VVIN = 15V

VIN = 7V

VIN = 20V

VOUT = 5V

INPUT VOLTAGE (V)5

EFFI

CIEN

CY (%

)

70

80

3727 G03

60

5015 25 35

100VOUT = 5VIOUT = 3A

90

The ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LTC3727EG/LTC3727EG-1/LTC3727IG-1: TJ = TA + (PD • 95 °C/W)LTC3727EUH-1: TJ = TA + (PD • 34 °C/W)

Note 4: The LTC3727/LTC3727-1 are tested in a feedback loop that servosVITH1, 2 to a specified voltage and measures the resultant VOSENSE1, 2.Note 5: Dynamic supply current is higher due to the gate charge beingdelivered at the switching frequency. See Applications Information.Note 6: Rise and fall times are measured using 10% and 90% levels. Delaytimes are measured using 50% levels.Note 7: The minimum on-time condition is specified for an inductorpeak-to-peak ripple current ≥40% of IMAX (see minimum on-timeconsiderations in the Applications Information section).

RPLLIN PLLIN Input Resistance 50 kΩIPLLFLTR Phase Detector Output Current

Sinking Capability fPLLIN < fOSC –15 μA

Sourcing Capability fPLLIN > fOSC 15 μA3.3V Linear RegulatorV3.3OUT 3.3V Regulator Output Voltage No Load ● 3.25 3.35 3.45 VV3.3IL 3.3V Regulator Load Regulation I3.3 = 0mA to 10mA 0.5 2.5 %V3.3VL 3.3V Regulator Line Regulation 6V < VIN < 30V (LTC3727) 0.05 0.2 %

6V < VIN < 30V (LTC3727-1) 0.05 0.3 %PGOOD OutputVPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 VIPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 μAVPG PGOOD Trip Level, Either Controller VOSENSE with Respect to Set Output Voltage

VOSENSE Ramping Negative –6 –7.5 –9.5 % VOSENSE Ramping Positive 6 7.5 9.5 %

5

LTC3727/LTC3727-1

3727fc

Maximum Current Sense Thresholdvs Duty Factor

Maximum Current Sense Thresholdvs Percent of Nominal OutputVoltage (Foldback)

Maximum Current Sense Thresholdvs VRUN/SS (Soft-Start)

Current Sense Thresholdvs ITH Voltage Load Regulation VITH vs VRUN/SS

TYPICAL PERFOR A CE CHARACTERISTICS

UW

DUTY FACTOR (%)0

0

V SEN

SE (m

V)

25

50

75

100

125

150

20 40 60 80

3727 G07

100

PERCENT OF NOMINAL OUTPUT VOLTAGE (%)0

V SEN

SE (m

V) 90

120

150

80

3727 G08

60

30

75

105

135

45

15

020 40 60 100

VRUN/SS (V)0

50

V SEN

SE (m

V)

75

100

125

150

1 2 3 4

3727 G09

5 6

VSENSE(CM) = 1.6V

VITH (V)0

V SEN

SE (m

V)

25

50

75

1.5 2.5

3727 G10

0

–25

–500.5 1.0 2.0

100

125

150

LOAD CURRENT (A)0

NORM

ALIZ

ED V

OUT

(%)

–0.2

–0.1

4

3727 G11

–0.3

–0.41 2 3 5

0.0FCB = 0VVIN = 15VFIGURE 1

VRUN/SS (V)0

0

V ITH

(V)

0.5

1.0

1.5

2.0

2.5

1 2 3 4

3727 G12

5 6

VOSENSE = 0.7V

Supply Current vs Input Voltageand Mode (Figure 13) EXTVCC Voltage Drop

INPUT VOLTAGE (V)0

0

SUPP

LY C

URRE

NT (μ

A)

400

1000

10 20

3727 G04

200

800

600

30

BOTHCONTROLLERS ON

SHUTDOWN

CURRENT (mA)0

EXTV

CC V

OLTA

GE D

ROP

(mV)

60

80

100

30 50

3727 G05

40

20

010 20 40

120

140

160VEXTVCC = 8.5V

Internal 7.5V LDO Line Regulation

INPUT VOLTAGE (V)0

6.8

INTV

CC V

OLTA

GE (V

)

6.9

7.1

7.2

7.3

20

7.7

3727 G06

7.0

105 25 3015 35

7.4

7.5

7.6ILOAD = 1mA

6

LTC3727/LTC3727-1

3727fc

Soft-Start Up (Figure 12)

IOUT*5A/DIV

VOUT5V/DIV

VRUN/SS5V/DIV

VIN = 20V 50ms/DIV 3727 G16

VOUT = 12V

Load Step (Figure 12)

VOUT200mV/DIV

IOUT*2A/DIV

VIN = 15V 50μs/DIV 3727 G17

VOUT = 12VLOAD STEP = 0A TO 3ABurst Mode OPERATION

Load Step (Figure 12)

VOUT200mV/DIV

IOUT*2A/DIV

VIN = 15V 50μs/DIV 3727 G18

VOUT = 12VLOAD STEP = 0A TO 3ACONTINUOUS MODE

Input Source/CapacitorInstantaneous Current (Figure 12)

VSW120V/DIV

VIN = 15V 1μs/DIV 3727 G19

VOUT1 = 12VVOUT2 = 5VIOUT1 = IOUT2 = 2A

Burst Mode Operation (Figure 12)

VOUT20mV/DIV

IOUT*0.5A/DIV

VIN = 15V 50μs/DIV 3727 G20

VOUT = 12VVFCB = OPENIOUT = 20mA

Constant Frequency (Burst Inhibit)Operation (Figure 12)

VOUT20mV/DIV

IOUT*0.5A/DIV

VIN = 15V 5μs/DIV 3727 G21

VOUT = 12VVFCB = 7.5VIOUT = 20mA

VSW220V/DIV

TYPICAL PERFOR A CE CHARACTERISTICS

UW

IIN1A/DIV

SENSE Pins Total Source Current

VSENSE COMMON MODE VOLTAGE (V)0

–400

I SEN

SE (μ

A)

–300

–250

–200

–150

–100

–50

5 10

3727 G13

0

50

100

–350

15

Dropout Voltage vs Output Current(Figure 13) RUN/SS Current vs Temperature

OUTPUT CURRENT (A)0

1.0

1.2

1.4

4

3727 G14

0.8

0.6

1 2 3 5

0.4

0.2

0

DROP

OUT

VOLT

AGE

(V)

VOUT = 5V

RSENSE = 0.015Ω

RSENSE = 0.010Ω

TEMPERATURE (°C)–50 –25

0

RUN/

SS C

URRE

NT (μ

A)

0.2

0.6

0.8

1.0

75 10050

1.8

3727 G15

0.4

0 25 125

1.2

1.4

1.6

*IOUT ⇒ INDUCTOR CURRENT

7

LTC3727/LTC3727-1

3727fc

Undervoltage Lockoutvs Temperature

Shutdown Latch Thresholdsvs Temperature

TYPICAL PERFOR A CE CHARACTERISTICS

UW

TEMPERATURE (°C)–50

UNDE

RVOL

TAGE

LOC

KOUT

(V)

3.40

3.45

3.50

25 75

3727 G25

3.35

3.30

–25 0 50 100 125

3.25

3.20

TEMPERATURE (°C)–50 –25

0

SHUT

DOW

N LA

TCH

THRE

SHOL

DS (V

)

0.5

1.5

2.0

2.5

75 10050

4.5

3727 G26

1.0

0 25 125

3.0

3.5

4.0 LATCH ARMING

LTC3727 ONLY

LATCHOFFTHRESHOLD

UUU

PI FU CTIO SRUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combina-tion of Soft-Start, Run Control Inputs and Short-CircuitDetection Timers (LTC3727 only). A capacitor to ground ateach of these pins sets the ramp time to full output current.Forcing either of these pins back below 1.0V causes the ICto shut down the circuitry required for that particularcontroller. Latchoff overcurrent protection is also invokedvia this pin as described in the Applications Informationsection (LTC3727 only).

SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12): The (+)Input to the Differential Current Comparators. The ITH pinvoltage and controlled offsets between the SENSE– andSENSE+ pins in conjunction with RSENSE set the currenttrip threshold.

SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11): The (–)Input to the Differential Current Comparators.

VOSENSE1, VOSENSE2 (Pins 4, 12/Pins 1, 9): Receives theremotely-sensed feedback voltage for each controller froman external resistive divider across the output.

Current Sense Pin Input Currentvs Temperature

EXTVCC Switch Resistancevs Temperature

Oscillator Frequencyvs Temperature

TEMPERATURE (°C)–50 –25

25

CURR

ENT

SENS

E IN

PUT

CURR

ENT

(μA)

29

35

0 50 75

3727 G22

27

33

31

25 100 125

VOUT = 5V

TEMPERATURE (°C)–50 –25

0

EXTV

CC S

WIT

CH R

ESIS

TANC

E (Ω

)4

10

0 50 75

3727 G23

2

8

6

25 100 125

TEMPERATURE (°C)–50

400

500

700

25 75

3727 G24

300

200

–25 0 50 100 125

100

0

600

FREQ

UENC

Y (k

Hz)

VPLLFLTR = 5V

VPLLFLTR = 1.2V

VPLLFLTR = 0V

G Package/UH Package

8

LTC3727/LTC3727-1

3727fc

PLLFLTR (Pin 5/Pin 2): The phase-locked loop’s lowpassfilter is tied to this pin. Alternatively, this pin can be drivenwith an AC or DC voltage source to vary the frequency ofthe internal oscillator.

PLLIN (Pin 6/Pin 3): External Synchronization Input toPhase Detector. This pin is internally terminated to SGNDwith 50kΩ. The phase-locked loop will force the rising topgate signal of controller 1 to be synchronized with therising edge of the PLLIN signal.

FCB (Pin 7/Pin 4): Forced Continuous Control Input. Thisinput acts on both controllers and is normally used toregulate a secondary winding. Pulling this pin below 0.8Vwill force continuous synchronous operation. Do notleave this pin floating.

ITH1, ITH2 (Pins 8, 11/Pins 5, 8): Error Amplifier Outputsand Switching Regulator Compensation Points. Each as-sociated channels’ current comparator trip point increaseswith this control voltage.

SGND (Pin 9/Pin 6): Small Signal Ground. Commonto both controllers; must be routed separately fromhigh current grounds to the common (–) terminalsof the COUT capacitors.

3.3VOUT (Pin 10/Pin 7): Linear Regulator Output. Capableof supplying 10mA DC with peak currents as high as50mA.

PGND (Pin 20/Pin 19): Driver Power Ground. Connects to thesources of bottom (synchronous) N-channel MOSFETs, an-odes of the Schottky rectifiers and the (–) terminal(s) of CIN.

INTVCC (Pin 21/Pin 20): Output of the Internal 7.5V LinearLow Dropout Regulator and the EXTVCC Switch. The driverand control circuits are powered from this voltage source.Must be decoupled to power ground with a minimum of 4.7μFtantalum or other low ESR capacitor.

UUU

PI FU CTIO SEXTVCC (Pin 22/Pin 21): External Power Input to anInternal Switch Connected to INTVCC. This switch closesand supplies VCC power, bypassing the internal low drop-out regulator, whenever EXTVCC is higher than 7.3V. SeeEXTVCC connection in Applications section. Do not exceed8.5V on this pin.

BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current GateDrives for Bottom (Synchronous) N-Channel MOSFETs.Voltage swing at these pins is from ground to INTVCC.

VIN (Pin 24/Pin 23): Main Supply Pin. A bypass capacitorshould be tied between this pin and the signal ground pin.

BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17): BootstrappedSupplies to the Top Side Floating Drivers. Capacitors areconnected between the boost and switch pins and Schot-tky diodes are tied between the boost and INTVCC pins.Voltage swing at the boost pins is from INTVCC to (VIN +INTVCC).

SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch NodeConnections to Inductors. Voltage swing at these pins isfrom a Schottky diode (external) voltage drop belowground to VIN.

TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current GateDrives for Top N-Channel MOSFETs. These are the outputsof floating drivers with a voltage swing equal to INTVCC –0.5V superimposed on the switch node voltage SW.

PGOOD (Pin 28/Pin 27): Open-Drain Logic Output. PGOODis pulled to ground when the voltage on either VOSENSE pinis not within ±7.5% of its set point.

Exposed Pad (Pin 33, UH Package): Signal Ground. Mustbe soldered to the PCB ground for electrical contact andoptimum thermal performance.

9

LTC3727/LTC3727-1

3727fc

Figure 2

FU CTIO AL DIAGRA

UU W

(Refer to Functional Diagram)OPERATIOU

Main Control Loop

The LTC3727/LTC3727-1 use a constant frequency, cur-rent mode step-down architecture with the two controllerchannels operating 180 degrees out of phase. Duringnormal operation, each top MOSFET is turned on when theclock for that channel sets the RS latch, and turned offwhen the main current comparator, I1, resets the RS latch.The peak inductor current at which I1 resets the RS latchis controlled by the voltage on the ITH pin, which is theoutput of each error amplifier EA. The VOSENSE pin receives

SWITCHLOGIC

–

+

0.8V

7.3V

7.5V

VIN

VIN

7VBINH

CLK2

CLK1

0.18μA

R6

R5

+

–

FCB

+

–

–

+

–

+

–

+ VREF

INTERNALSUPPLY

3.3VOUT

VSEC

RLP

CLP

1.5V

FCB

EXTVCC

INTVCC

SGND

+

7.5VLDOREG

SW

SHDN

0.55V

TOP

BOOST

TG CB

CIND1

DB

PGND

BOTBG

INTVCC

INTVCC

VIN

+

CSEC

COUT

VOUT

3727 F02

DSEC

RSENSE

R2

+

VOSENSE

DROPOUTDET

RUNSOFT

START

BOT

TOP ONS

R

Q

Q

OSCILLATOR

PHASE DET

PLLFLTR

PLLIN

FCB

EA

0.86V

0.80V

OV

VFB

1.2μA

6V

R1

–

+

RC

4(VFB)RST

SHDN

RUN/SS

ITHCC

CC2

CSS

+

4(VFB)0.86V

SLOPECOMP

3mV

+

–

–

+

SENSE–

SENSE+

INTVCC

50k

25k

2.4V

25k

50k

I1 I2

B

DUPLICATE FOR SECONDCONTROLLER CHANNEL

+– –+

50k

FIN

+

–

+

–

+

–

+

–

PGOODVOSENSE1

VOSENSE2

0.86V

0.74V

0.86V

0.74V

the voltage feedback signal, which is compared to theinternal reference voltage by the EA. When the load currentincreases, it causes a slight decrease in VOSENSE relative tothe 0.8V reference, which in turn causes the ITH voltage toincrease until the average inductor current matches thenew load current. After the top MOSFET has turned off, thebottom MOSFET is turned on until either the inductorcurrent starts to reverse, as indicated by current compara-tor I2, or the beginning of the next cycle.

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(Refer to Functional Diagram)

The top MOSFET drivers are biased from floating boot-strap capacitor CB, which normally is recharged duringeach off cycle through an external diode when the topMOSFET turns off. As VIN decreases to a voltage close toVOUT, the loop may enter dropout and attempt to turn onthe top MOSFET continuously. The dropout detector de-tects this and forces the top MOSFET off for about 400nsevery tenth cycle to allow CB to recharge.

The main control loop is shut down by pulling the RUN/SSpin low. Releasing RUN/SS allows an internal 1.2μAcurrent source to charge soft-start capacitor CSS. WhenCSS reaches 1.5V, the main control loop is enabled with theITH voltage clamped at approximately 30% of its maximumvalue. As CSS continues to charge, the ITH pin voltage isgradually released allowing normal, full-current opera-tion. When both RUN/SS1 and RUN/SS2 are low, allLTC3727/LTC3727-1 controller functions are shut down,including the 7.5V and 3.3V regulators.

Low Current Operation

The FCB pin is a multifunction pin providing two func-tions: 1) to provide regulation for a secondary winding bytemporarily forcing continuous PWM operation onboth controllers; and 2) to select between two modes oflow current operation. When the FCB pin voltage is below0.8V, the controller forces continuous PWM currentmode operation. In this mode, the top and bottomMOSFETs are alternately turned on to maintain the outputvoltage independent of direction of inductor current.When the FCB pin is below VINTVCC – 2V but greater than0.8V, the controller enters Burst Mode operation. BurstMode operation sets a minimum output current levelbefore inhibiting the top switch and turns off the synchro-nous MOSFET(s) when the inductor current goes nega-tive. This combination of requirements will, at low cur-rents, force the ITH pin below a voltage threshold that willtemporarily inhibit turn-on of both output MOSFETs untilthe output voltage drops. There is 60mV of hysteresis inthe burst comparator B tied to the ITH pin. This hysteresisproduces output signals to the MOSFETs that turn themon for several cycles, followed by a variable “sleep”interval depending upon the load current. The resultantoutput voltage ripple is held to a very small value by

OPERATIOU

having the hysteretic comparator follow the error ampli-fier gain block.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to besynchronized to an external source via the PLLIN pin. Theoutput of the phase detector at the PLLFLTR pin is also theDC frequency control input of the oscillator that operatesover a 250kHz to 550kHz range corresponding to a DCvoltage input from 0V to 2.4V. When locked, the PLLaligns the turn on of the top MOSFET to the rising edge ofthe synchronizing signal. When PLLIN is left open, thePLLFLTR pin goes low, forcing the oscillator to its mini-mum frequency.

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous currentoperation. This is the least efficient operating mode, butmay be desirable in certain applications. The output cansource or sink current in this mode. When sinking currentwhile in forced continuous operation, current will beforced back into the main power supply potentially boost-ing the input supply to dangerous voltage levels—BEWARE!

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and mostother internal circuitry is derived from the INTVCC pin.When the EXTVCC pin is left open, an internal 7.5V lowdropout linear regulator supplies INTVCC power. If EXTVCCis taken above 7.3V, the 7.5V regulator is turned off and aninternal switch is turned on connecting EXTVCC to INTVCC.This allows the INTVCC power to be derived from a highefficiency external source such as the output of the regu-lator itself or a secondary winding, as described in theApplications Information section.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transientovershoots (>7.5%) as well as other more serious condi-tions that may overvoltage the output. In this case, the topMOSFET is turned off and the bottom MOSFET is turned onuntil the overvoltage condition is cleared.

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Power Good (PGOOD) Pin

The PGOOD pin is connected to an open drain of an internalMOSFET. The MOSFET turns on and pulls the pin low wheneither output is not within ±7.5% of the nominal outputlevel as determined by the resistive feedback divider.When both outputs meet the ±7.5% requirement, theMOSFET is turned off within 10μs and the pin is allowed tobe pulled up by an external resistor to a source of up to 7V.

Foldback Current, Short-Circuit Detectionand Short-Circuit Latchoff (LTC3727 Only)

The RUN/SS capacitors are used initially to limit the inrushcurrent of each switching regulator. After the controllerhas been started and been given adequate time to chargeup the output capacitors and provide full load current, theRUN/SS capacitor is used in a short-circuit time-outcircuit. If the output voltage falls to less than 70% of itsnominal output voltage, the RUN/SS capacitor beginsdischarging on the assumption that the output is in anovercurrent and/or short-circuit condition. If the condi-tion lasts for a long enough period as determined by thesize of the RUN/SS capacitor, the controller will be shutdown until the RUN/SS pin(s) voltage(s) are recycled.This built-in latchoff can be overridden by providing a>5μA pull-up at a compliance of 5V to the RUN/SS pin(s).This current shortens the soft start period but also pre-vents net discharge of the RUN/SS capacitor(s) during anovercurrent and/or short-circuit condition. Foldback cur-rent limiting is also activated when the output voltage fallsbelow 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. Even if a short is presentand the short-circuit latchoff is not enabled, a safe, lowoutput current is provided due to internal current foldbackand actual power wasted is low due to the efficient natureof the current mode switching regulator.

PART NUMBER FUNCTION

LTC3727 With Latchoff Function Available

LTC3727-1 Latchoff Always Disabled

THEORY AND BENEFITS OF 2-PHASE OPERATION

The LTC3727 dual high efficiency DC/DC controller bringsthe considerable benefits of 2-phase operation to portableapplications. Notebook computers, PDAs, handheld ter-minals and automotive electronics will all benefit from thelower input filtering requirement, reduced electromag-netic interference (EMI) and increased efficiency associ-ated with 2-phase operation.

Why the need for 2-phase operation? Until recently, con-stant-frequency dual switching regulators operated bothchannels in phase (i.e., single-phase operation). Thismeans that both switches turned on at the same time,causing current pulses of up to twice the amplitude ofthose for one regulator to be drawn from the input capaci-tor and battery. These large amplitude current pulsesincreased the total RMS current flowing from the inputcapacitor, requiring the use of more expensive inputcapacitors and increasing both EMI and losses in the inputcapacitor and battery.

With 2-phase operation, the two channels of the dual-switching regulator are operated 180 degrees out ofphase. This effectively interleaves the current pulsesdrawn by the switches, greatly reducing the overlap timewhere they add together. The result is a significant reduc-tion in total RMS input current, which in turn allows lessexpensive input capacitors to be used, reduces shieldingrequirements for EMI and improves real world operatingefficiency.

Figure 3 compares the input waveforms for a representa-tive single-phase dual switching regulator to the newLTC3727 2-phase dual switching regulator. An actualmeasurement of the RMS input current under these con-ditions shows that 2-phase operation dropped the inputcurrent from 2.53ARMS to 1.55ARMS. While this is animpressive reduction in itself, remember that the powerlosses are proportional to IRMS

2, meaning that the actualpower wasted is reduced by a factor of 2.66. The reducedinput ripple voltage also means less power is lost in the

(Refer to Functional Diagram)OPERATIOU

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input power path, which could include batteries, switches,trace/connector resistances and protection circuitry. Im-provements in both conducted and radiated EMI alsodirectly accrue as a result of the reduced RMS inputcurrent and voltage.

Of course, the improvement afforded by 2-phase opera-tion is a function of the dual switching regulator’s relativeduty cycles which, in turn, are dependent upon the inputvoltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows howthe RMS input current varies for single-phase and 2-phaseoperation for 3.3V and 5V regulators over a wide inputvoltage range.

It can readily be seen that the advantages of 2-phaseoperation are not just limited to a narrow operating range,but in fact extend over a wide region. A good rule of thumbfor most applications is that 2-phase operation will reducethe input capacitor requirement to that for just one channeloperating at maximum current and 50% duty cycle.

A final question: If 2-phase operation offers such anadvantage over single-phase operation for dual switchingregulators, why hasn’t it been done before? The answer isthat, while simple in concept, it is hard to implement.Constant-frequency current mode switching regulators

require an oscillator derived “slope compensation” signalto allow stable operation of each regulator at over 50%duty cycle. This signal is relatively easy to derive in single-phase dual switching regulators, but required the develop-ment of a new and proprietary technique to allow 2-phaseoperation. In addition, isolation between the two channelsbecomes more critical with 2-phase operation becauseswitch transitions in one channel could potentially disruptthe operation of the other channel.

(b)(a)

5V SWITCH20V/DIV

3.3V SWITCH20V/DIV

INPUT CURRENT5A/DIV

INPUT VOLTAGE500mV/DIV

IIN(MEAS) = 1.55ARMS 3727 F03bIIN(MEAS) = 2.53ARMS 3727 F03a

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation forDual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced InputRipple with the LTC3727 2-Phase Regulator Allows Less Expensive Input Capacitors,Reduces Shielding Requirements for EMI and Improves Efficiency

(Refer to Functional Diagram)OPERATIOU

Figure 4. RMS Input Current Comparison

INPUT VOLTAGE (V)0

INPU

T RM

S CU

RREN

T (A

)

3.0

2.5

2.0

1.5

1.0

0.5

010 20 30 40

3727 F04

SINGLE PHASEDUAL CONTROLLER

2-PHASEDUAL CONTROLLER

VO1 = 5V/3AVO2 = 3.3V/3A

13

LTC3727/LTC3727-1

3727fc

Figure 1 on the first page is a basic LTC3727/LTC3727-1application circuit. External component selection is drivenby the load requirement, and begins with the selection ofRSENSE and the inductor value. Next, the power MOSFETsand D1 are selected. Finally, CIN and COUT are selected.The circuit shown in Figure 1 can be configured foroperation up to an input voltage of 28V (limited by theexternal MOSFETs).

RSENSE Selection For Output Current

RSENSE is chosen based on the required output current.The LTC3727 current comparator has a maximum thresh-old of 135mV/RSENSE and an input common mode rangeof SGND to 14V. The current comparator threshold setsthe peak of the inductor current, yielding a maximumaverage output current IMAX equal to the peak value lesshalf the peak-to-peak ripple current, ΔIL.

Allowing a margin for variations in the LTC3727 andexternal component values yields:

RmV

ISENSEMAX

= 90

When using the controller in very low dropout conditions,the maximum output current level will be reduced due tothe internal compensation required to meet stability crite-rion for buck regulators operating at greater than 50%duty factor. A curve is provided to estimate this reductonin peak output current level depending upon the operatingduty factor.

Operating Frequency

The LTC3727 uses a constant frequency phase-lockablearchitecture with the frequency determined by an internalcapacitor. This capacitor is charged by a fixed current plusan additional current which is proportional to the voltageapplied to the PLLFLTR pin. Refer to Phase-Locked Loopand Frequency Synchronization in the Applications Infor-mation section for additional information.

A graph for the voltage applied to the PLLFLTR pin vsfrequency is given in Figure 5. As the operating frequency

is increased the gate charge losses will be higher, reducingefficiency (see Efficiency Considerations). The maximumswitching frequency is approximately 550kHz.

Inductor Value Calculation

The operating frequency and inductor selection are inter-related in that higher operating frequencies allow the useof smaller inductor and capacitor values. So why wouldanyone ever choose to operate at lower frequencies withlarger components? The answer is efficiency. A higherfrequency generally results in lower efficiency because ofMOSFET gate charge losses. In addition to this basictrade-off, the effect of inductor value on ripple current andlow current operation must also be considered.

The inductor value has a direct effect on ripple current. Theinductor ripple current ΔIL decreases with higher induc-tance or frequency and increases with higher VIN:

ΔIf L

VVVL OUTOUT

IN= ⎛

⎝⎜⎞⎠⎟

11

( )( )–

Accepting larger values of ΔIL allows the use of lowinductances, but results in higher output voltage rippleand greater core losses. A reasonable starting point forsetting ripple current is ΔIL = 0.3(IMAX). The maximum ΔILoccurs at the maximum input voltage.

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Figure 5. PLLFLTR Pin Voltage vs Frequency

OPERATING FREQUENCY (kHz)200 250 300 350 550400 450 500

PLLF

LTR

PIN

VOLT

AGE

(V)

3727 F05

2.5

2.0

1.5

1.0

0.5

0

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LTC3727/LTC3727-1

3727fc

The inductor value also has secondary effects. The transi-tion to Burst Mode operation begins when the averageinductor current required results in a peak current below25% of the current limit determined by RSENSE. Lowerinductor values (higher ΔIL) will cause this to occur atlower load currents, which can cause a dip in efficiency inthe upper range of low current operation. In Burst Modeoperation, lower inductance values will cause the burstfrequency to decrease.

Inductor Core Selection

Once the inductance value is determined, the type ofinductor must be selected. Actual core loss is independentof core size for a fixed inductor value, but it is verydependent on inductance selected. As inductance in-creases, core losses go down. Unfortunately, increasedinductance requires more turns of wire and thereforecopper (I2R) losses will increase.

Ferrite designs have very low core loss and are preferredat high switching frequencies, so designers can concen-trate on reducing I2R loss and preventing saturation.Ferrite core material saturates “hard,” which means thatinductance collapses abruptly when the peak design cur-rent is exceeded. This results in an abrupt increase ininductor ripple current and consequent output voltageripple. Do not allow the core to saturate!

Different core materials and shapes will change the size/current and price/current relationship of an inductor.Toroid or shielded pot cores in ferrite or permalloy mate-rials are small and don’t radiate much energy, but gener-ally cost more than powdered iron core inductors withsimilar characteristics. The choice of which style inductorto use mainly depends on the price vs size requirementsand any radiated field/EMI requirements. New designs forhigh current surface mount inductors are available fromnumerous manufacturers, including Coiltronics, Vishay,TDK, Pulse, Panasonic, Wuerth, Coilcraft, Toko and Sumida.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for eachcontroller in the LTC3727: One N-channel MOSFET for thetop (main) switch, and one N-channel MOSFET for thebottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTVCCvoltage. This voltage is typically 7.5V during start-up (seeEXTVCC Pin Connection). Consequently, logic-levelthreshold MOSFETs must be used in most applications.The only exception is if low input voltage is expected(VIN < 5V); then, sub-logic level threshold MOSFETs(VGS(TH) < 3V) should be used. Pay close attention to theBVDSS specification for the MOSFETs as well; most of thelogic level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “ON”resistance RDS(ON), reverse transfer capacitance CRSS,input voltage and maximum output current. When theLTC3727 is operating in continuous mode the duty cyclesfor the top and bottom MOSFETs are given by:

Main SwitchDuty CycleVVOUT

IN=

Synchronous SwitchDuty CycleV V

VIN OUT

IN= –

The MOSFET power dissipations at maximum outputcurrent are given by:

PVV

I R

k V I C f

MAINOUT

INMAX DS ON

IN MAX RSS

= ( ) +( ) +

( ) ( )( )( )

2

2

1 δ ( )

PV V

VI RSYNC

IN OUT

INMAX DS ON= ( ) +( )–

( )2 1 δ

where δ is the temperature dependency of RDS(ON) and kis a constant inversely related to the gate drive current.

Both MOSFETs have I2R losses while the topside N-channelequation includes an additional term for transition losses,which are highest at high input voltages. For VIN < 20V thehigh current efficiency generally improves with largerMOSFETs, while for VIN > 20V the transition losses rapidlyincrease to the point that the use of a higher RDS(ON) devicewith lower CRSS actually provides higher efficiency. Thesynchronous MOSFET losses are greatest at high inputvoltage when the top switch duty factor is low or during a

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short-circuit when the synchronous switch is on close to100% of the period.

The term (1+δ) is generally given for a MOSFET in the formof a normalized RDS(ON) vs Temperature curve, butδ = 0.005/°C can be used as an approximation for lowvoltage MOSFETs. CRSS is usually specified in the MOS-FET characteristics. The constant k = 1.7 can be used toestimate the contributions of the two terms in the mainswitch dissipation equation.

The Schottky diode D1 shown in Figure 2 conducts duringthe dead-time between the conduction of the two powerMOSFETs. This prevents the body diode of the bottomMOSFET from turning on, storing charge during the dead-time and requiring a reverse recovery period that couldcost as much as 3% in efficiency at high VIN. A 1A to 3ASchottky is generally a good compromise for both regionsof operation due to the relatively small average current.Larger diodes result in additional transition losses due totheir larger junction capacitance. Schottky diodes shouldbe placed in parallel with the synchronous MOSFETs whenoperating in pulse-skip mode or in Burst Mode operation.

CIN and COUT Selection

The selection of CIN is simplified by the multiphase archi-tecture and its impact on the worst-case RMS currentdrawn through the input network (battery/fuse/capacitor).It can be shown that the worst case RMS current occurswhen only one controller is operating. The controller withthe highest (VOUT)(IOUT) product needs to be used in theformula below to determine the maximum RMS currentrequirement. Increasing the output current, drawn fromthe other out-of-phase controller, will actually decreasethe input RMS ripple current from this maximum value(see Figure 4). The out-of-phase technique typically re-duces the input capacitor’s RMS ripple current by a factorof 30% to 70% when compared to a single phase powersupply solution.

The type of input capacitor, value and ESR rating haveefficiency effects that need to be considered in the selec-tion process. The capacitance value chosen should besufficient to store adequate charge to keep high peakbattery currents down. 22μF to 47μF is usually sufficientfor a 25W output supply operating at 250kHz. The ESR of

the capacitor is important for capacitor power dissipationas well as overall battery efficiency. All of the power (RMSripple current • ESR) not only heats up the capacitor butwastes power from the battery.

Medium voltage (20V to 35V) ceramic, tantalum, OS-CONand switcher-rated electrolytic capacitors can be used asinput capacitors, but each has drawbacks: ceramic voltagecoefficients are very high and may have audible piezoelec-tric effects; tantalums need to be surge-rated; OS-CONssuffer from higher inductance, larger case size and limitedsurface-mount applicability; electrolytics’ higher ESR anddryout possibility require several to be used. Multiphasesystems allow the lowest amount of capacitance overall.As little as one 22μF or two to three 10μF ceramic capaci-tors are an ideal choice in a 20W to 35W power supply dueto their extremely low ESR. Even though the capacitanceat 20V is substantially below their rating at zero-bias, verylow ESR loss makes ceramics an ideal candidate forhighest efficiency battery operated systems. Also con-sider parallel ceramic and high quality electrolytic capaci-tors as an effective means of achieving ESR and bulkcapacitance goals.

In continuous mode, the source current of the top N-chan-nel MOSFET is a square wave of duty cycle VOUT/VIN. Toprevent large voltage transients, a low ESR input capacitorsized for the maximum RMS current of one channel mustbe used. The maximum RMS capacitor current is given by:

C quiredI IV V V

VIN RMS MAXOUT IN OUT

INRe

/

≅−( )[ ]1 2

This formula has a maximum at VIN = 2VOUT, whereIRMS = IOUT/2. This simple worst case condition is com-monly used for design because even significant deviationsdo not offer much relief. Note that capacitor manufacturer’sripple current ratings are often based on only 2000 hoursof life. This makes it advisable to further derate thecapacitor, or to choose a capacitor rated at a highertemperature than required. Several capacitors may also beparalleled to meet size or height requirements in thedesign. Always consult the manufacturer if there is anyquestion.

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The benefit of the LTC3727 multiphase can be calculatedby using the equation above for the higher power control-ler and then calculating the loss that would have resultedif both controller channels switch on at the same time. Thetotal RMS power lost is lower when both controllers areoperating due to the interleaving of current pulses throughthe input capacitor’s ESR. This is why the input capacitor’srequirement calculated above for the worst-case control-ler is adequate for the dual controller design. Rememberthat input protection fuse resistance, battery resistanceand PC board trace resistance losses are also reduced dueto the reduced peak currents in a multiphase system. Theoverall benefit of a multiphase design will only be fullyrealized when the source impedance of the power supply/battery is included in the efficiency testing. The drains ofthe two top MOSFETS should be placed within 1cm of eachother and share a common CIN(s). Separating the drainsand CIN may produce undesirable voltage and currentresonances at VIN.

The selection of COUT is driven by the required effectiveseries resistance (ESR). Typically once the ESR require-ment is satisfied the capacitance is adequate for filtering.The output ripple (ΔVOUT) is determined by:

Δ ΔV I ESRfCOUT L

OUT≅ +⎛

⎝⎜⎞⎠⎟

18

Where f = operating frequency, COUT = output capaci-tance, and ΔIL= ripple current in the inductor. The outputripple is highest at maximum input voltage since ΔILincreases with input voltage. With ΔIL = 0.3IOUT(MAX) theoutput ripple will typically be less than 50mV at max VINassuming:

COUT Recommended ESR < 2 RSENSE

and COUT > 1/(8fRSENSE)

The first condition relates to the ripple current into theESR of the output capacitance while the second termguarantees that the output capacitance does not signifi-cantly discharge during the operating frequency perioddue to ripple current. The choice of using smaller outputcapacitance increases the ripple voltage due to the

discharging term but can be compensated for by usingcapacitors of very low ESR to maintain the ripple voltageat or below 50mV. The ITH pin OPTI-LOOP compensationcomponents can be optimized to provide stable, highperformance transient response regardless of the outputcapacitors selected.

Manufacturers such as Nichicon, Nippon Chemi-Con andSanyo can be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectriccapacitor available from Sanyo has the lowest (ESR)(size)product of any aluminum electrolytic at a somewhathigher price. An additional ceramic capacitor in parallelwith OS-CON capacitors is recommended to reduce theinductance effects.

In surface mount applications multiple capacitors mayneed to be used in parallel to meet the ESR, RMS currenthandling and load step requirements of the application.Aluminum electrolytic, dry tantalum and special polymercapacitors are available in surface mount packages. Spe-cial polymer surface mount capacitors offer very low ESRbut have lower storage capacity per unit volume than othercapacitor types. These capacitors offer a very cost-effec-tive output capacitor solution and are an ideal choice whencombined with a controller having high loop bandwidth.Tantalum capacitors offer the highest capacitance densityand are often used as output capacitors for switchingregulators having controlled soft-start. Several excellentsurge-tested choices are the AVX TPS, AVX TPS Series IIIor the KEMET T510 series of surface mount tantalums,available in case heights ranging from 1.2mm to 4.1mm.Aluminum electrolytic capacitors can be used in cost-driven applications providing that consideration is givento ripple current ratings, temperature and long term reli-ability. A typical application will require several to manyaluminum electrolytic capacitors in parallel. A combina-tion of the above mentioned capacitors will often result inmaximizing performance and minimizing overall cost. Othercapacitor types include Nichicon PL series, NEC Neocap,Cornell Dubilier ESRE and Sprague 595D series. Consultmanufacturers for other specific recommendations.

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INTVCC Regulator

An internal P-channel low dropout regulator produces7.5V at the INTVCC pin from the VIN supply pin. INTVCCpowers the drivers and internal circuitry within theLTC3727. The INTVCC pin regulator can supply a peakcurrent of 50mA and must be bypassed to ground with aminimum of 4.7μF tantalum, 10μF special polymer, or lowESR type electrolytic capacitor. A 1μF ceramic capacitorplaced directly adjacent to the INTVCC and PGND IC pinsis highly recommended. Good bypassing is necessary tosupply the high transient currents required by the MOSFETgate drivers and to prevent interaction between channels.

Higher input voltage applications in which large MOSFETsare being driven at high frequencies may cause the maxi-mum junction temperature rating for the LTC3727 to beexceeded. The system supply current is normally domi-nated by the gate charge current. Additional externalloading of the INTVCC and 3.3V linear regulators alsoneeds to be taken into account for the power dissipationcalculations. The total INTVCC current can be supplied byeither the 7.5V internal linear regulator or by the EXTVCCinput pin. When the voltage applied to the EXTVCC pin isless than 7.3V, all of the INTVCC current is supplied by theinternal 7.5V linear regulator. Power dissipation for the ICin this case is highest: (VIN)(IINTVCC), and overall efficiencyis lowered. The gate charge current is dependent onoperating frequency as discussed in the Efficiency Consid-erations section. The junction temperature can be esti-mated by using the equations given in Note 2 of theElectrical Characteristics. For example, the LTC3727 VINcurrent is limited to less than 24mA from a 24V supplywhen not using the EXTVCC pin as follows:

TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C

Use of the EXTVCC input pin reduces the junction tempera-ture to:

TJ = 70°C + (24mA)(7.5V)(95°C/W) = 87°C

Dissipation should be calculated to also include any addedcurrent drawn from the internal 3.3V linear regulator. Toprevent maximum junction temperature from being ex-ceeded, the input supply current must be checked operat-ing in continuous mode at maximum VIN.

EXTVCC Connection

The LTC3727 contains an internal P-channel MOSFETswitch connected between the EXTVCC and INTVCC pins.When the voltage applied to EXTVCC rises above 7.3V, theinternal regulator is turned off and the switch closes,connecting the EXTVCC pin to the INTVCC pin therebysupplying internal power. The switch remains closed aslong as the voltage applied to EXTVCC remains above 7.0V.This allows the MOSFET driver and control power to bederived from the output during normal operation (7.2V <VOUT < 8.5V) and from the internal regulator when theoutput is out of regulation (start-up, short-circuit). If morecurrent is required through the EXTVCC switch than isspecified, an external Schottky diode can be added be-tween the EXTVCC and INTVCC pins. Do not apply greaterthan 8.5V to the EXTVCC pin and ensure that EXTVCC < VIN.

Significant efficiency gains can be realized by poweringINTVCC from the output, since the VIN current resultingfrom the driver and control currents will be scaled by afactor of (Duty Cycle)/(Efficiency). For 7.5V regulators thissupply means connecting the EXTVCC pin directly to VOUT.However, for 3.3V and other lower voltage regulators,additional circuitry is required to derive INTVCC powerfrom the output.

The following list summarizes the four possible connec-tions for EXTVCC:

1. EXTVCC Left Open (or Grounded). This will cause INTVCCto be powered from the internal 7.5V regulator resulting inan efficiency penalty of up to 10% at high input voltages.

2. EXTVCC Connected directly to VOUT. This is the normalconnection for a 7.5V regulator and provides the highestefficiency.

3. EXTVCC Connected to an External supply. If an externalsupply is available in the 7.5V to 8.5V range, it may be usedto power EXTVCC providing it is compatible with theMOSFET gate drive requirements.

4. EXTVCC Connected to an Output-Derived Boost Net-work. For 3.3V and other low voltage regulators, efficiencygains can still be realized by connecting EXTVCC to anoutput-derived voltage that has been boosted to greater

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than 7.5V. This can be done with the inductive boostwinding as shown in Figure 6.

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitors CB connected to the BOOSTpins supply the gate drive voltages for the topside MOSFETs.Capacitor CB in the functional diagram is charged thoughexternal diode DB from INTVCC when the SW pin is low.When one of the topside MOSFETs is to be turned on, thedriver places the CB voltage across the gate-source of thedesired MOSFET. This enhances the MOSFET and turns onthe topside switch. The switch node voltage, SW, rises toVIN and the BOOST pin follows. With the topside MOSFETon, the boost voltage is above the input supply: VBOOST =VIN + VINTVCC. The value of the boost capacitor CB needsto be 100 times that of the total input capacitance of thetopside MOSFET(s). The reverse breakdown of the exter-nal Schottky diode must be greater than VIN(MAX). Whenadjusting the gate drive level, the final arbiter is the totalinput current for the regulator. If a change is made and theinput current decreases, then the efficiency has improved.If there is no change in input current, then there is nochange in efficiency.

Figure 6. Secondary Output Loop & EXTVCC Connection

Output Voltage

The LTC3727 output voltages are each set by an externalfeedback resistive divider carefully placed across theoutput capacitor. The resultant feedback signal iscompared with the internal precision 0.800V voltagereference by the error amplifier. The output voltage isgiven by the equation:

V VRROUT = +⎛

⎝⎜⎞⎠⎟

0 8 121

.

where R1 and R2 are defined in Figure 2.

SENSE+/SENSE– Pins

The common mode input range of the current comparatorsense pins is from 0V to 14V. Continuous linear operationis guaranteed throughout this range allowing output volt-age setting from 0.8V to 14V. A differential NPN inputstage is biased with internal resistors from an internal2.4V source as shown in the Functional Diagram. Thisrequires that current either be sourced or sunk from theSENSE pins depending on the output voltage. If the outputvoltage is below 2.4V current will flow out of both SENSEpins to the main output. The output can be easily preloadedby the VOUT resistive divider to compensate for the currentcomparator’s negative input bias current. The maximumcurrent flowing out of each pair of SENSE pins is:

ISENSE+ + ISENSE

– = (2.4V – VOUT)/24k

Since VOSENSE is servoed to the 0.8V reference voltage, wecan choose R1 in Figure 2 to have a maximum value toabsorb this current.

R kV

V VMAXOUT

1 240 8

2 4( ).

. –= ⎛

⎝⎜⎞⎠⎟

for VOUT < 2.4V

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EXTVCC

FCB

SGND

VIN

TG1

SW

BG1

PGND

LTC3727

RSENSEVOUT

VSEC

+COUT

+1μF

3727 F06

N-CH

N-CH

R6

+CIN

VIN

T11:N

OPTIONAL EXTVCCCONNECTION7.5V < VSEC < 8.5V

R5

19

LTC3727/LTC3727-1

3727fc

Regulating an output voltage of 1.8V, the maximum valueof R1 should be 32K. Note that for an output voltage above2.4V, R1 has no maximum value necessary to absorb thesense currents; however, R1 is still bounded by theVOSENSE feedback current.

Soft-Start/Run Function

The RUN/SS1 and RUN/SS2 pins are multipurpose pinsthat provide a soft-start function and a means to shutdown the LTC3727. Soft-start reduces the input powersource’s surge currents by gradually increasing thecontroller’s current limit (proportional to VITH). This pincan also be used for power supply sequencing.

An internal 1.2μA current source charges up the CSScapacitor. When the voltage on RUN/SS1 (RUN/SS2)reaches 1.5V, the particular controller is permitted to startoperating. As the voltage on RUN/SS increases from 1.5Vto 3.0V, the internal current limit is increased from 45mV/RSENSE to 135mV/RSENSE. The output current limit rampsup slowly, taking an additional 1.25s/μF to reach fullcurrent. The output current thus ramps up slowly, reduc-ing the starting surge current required from the inputpower supply. If RUN/SS has been pulled all the way toground there is a delay before starting of approximately:

tVA

C s F CDELAY SS SS=μ

= μ( )1 51 2

1 25.

.. /

tV V

AC s F CIRAMP SS SS= −

μ= μ( )3 1 5

1 21 25

..

. /

By pulling both RUN/SS pins below 1V, the LTC3727 isput into low current shutdown (IQ = 20μA). The RUN/SSpins can be driven directly from logic as shown in Fig-ure 7. Diode D1 in Figure 7 reduces the start delay butallows CSS to ramp up slowly providing the soft-startfunction. Each RUN/SS pin has an internal 6V zener clamp(See Functional Diagram).

Fault Conditions: Overcurrent Latchoff (LTC3727 Only)

The RUN/SS pins also provide the ability to latch off thecontroller(s) when an overcurrent condition is detected.

The RUN/SS capacitor, CSS, is used initially to turn on andlimit the inrush current. After the controller has beenstarted and been given adequate time to charge up theoutput capacitor and provide full load current, the RUN/SScapacitor is used for a short-circuit timer. If the regulator’soutput voltage falls to less than 70% of its nominal valueafter CSS reaches 4.1V, CSS begins discharging on theassumption that the output is in an overcurrent condition.If the condition lasts for a long enough period as deter-mined by the size of the CSS and the specified dischargecurrent, the controller will be shut down until the RUN/SSpin voltage is recycled. If the overload occurs during start-up, the time can be approximated by:

tLO1 ≅ [CSS(4.1 – 1.5 + 4.1 – 3.5)]/(1.2μA)

= 2.7 • 106 (CSS)

If the overload occurs after start-up the voltage on CSS willbegin discharging from the zener clamp voltage:

tLO2 ≅ [CSS (6 – 3.5)]/(1.2μA) = 2.1 • 106 (CSS)

This built-in overcurrent latchoff can be overridden byproviding a pull-up resistor to the RUN/SS pin as shownin Figure 7. This resistance shortens the soft-start periodand prevents the discharge of the RUN/SS capacitorduring an over current condition. Tying this pull-up resis-tor to VIN, as in Figure 7a, defeats overcurrent latchoff.Diode-connecting this pull-up resistor to INTVCC, as inFigure 7b, eliminates any extra supply current duringcontroller shutdown while eliminating the INTVCC loadingfrom preventing controller start-up. This pull-up resistoris not needed in LTC3727-1 designs.

Figure 7. RUN/SS Pin Interfacing

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3.3V OR 5V RUN/SSVIN INTVCC

RUN/SSD1

CSS

RSS*

CSS

RSS*

3727 F07

(7a) (7b)

*OPTIONAL TO DEFEAT OVERCURRENTLATCHOFF (NOT NEEDED WITH THE LTC3727-1)

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Why should you defeat overcurrent latchoff? During theprototyping stage of a design, there may be a problemwith noise pickup or poor layout causing the protectioncircuit to latch off. Defeating this feature will easily allowtroubleshooting of the circuit and PC layout. The internalshort-circuit and foldback current limiting still remainsactive, thereby protecting the power supply system fromfailure. After the design is complete, a decision can bemade whether to enable the latchoff feature. If latchoff isnot required, the LTC3727-1 can be used.

The value of the soft-start capacitor CSS may need to bescaled with output voltage, output capacitance and loadcurrent characteristics. The minimum soft-start capaci-tance is given by:

CSS > (COUT )(VOUT) (10 –4) (RSENSE)

The minimum recommended soft-start capacitor ofCSS = 0.1μF will be sufficient for most applications.

Fault Conditions: Current Limit and Current Foldback

The LTC3727 current comparator has a maximum sensevoltage of 135mV resulting in a maximum MOSFET cur-rent of 135mV/RSENSE. The maximum value of currentlimit generally occurs with the largest VIN at the highestambient temperature, conditions that cause the highestpower dissipation in the top MOSFET.

The LTC3727 includes current foldback to help furtherlimit load current when the output is shorted to ground.The foldback circuit is active even when the overloadshutdown latch described above is overridden. If theoutput falls below 70% of its nominal output level, then themaximum sense voltage is progressively lowered from135mV to 45mV. Under short-circuit conditions with verylow duty cycles, the LTC3727 will begin cycle skipping inorder to limit the short-circuit current. In this situation thebottom MOSFET will be dissipating most of the power butless than in normal operation. The short-circuit ripplecurrent is determined by the minimum on-time tON(MIN) ofthe LTC3727 (less than 200ns), the input voltage andinductor value:

ΔIL(SC) = tON(MIN) (VIN/L)

The resulting short-circuit current is:

ImV

RISC

SENSEL SC= +45 1

2Δ ( )

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a systeminput fuse when the output voltage of the regulator risesmuch higher than nominal levels. The crowbar causeshuge currents to flow, that blow the fuse to protect againsta shorted top MOSFET if the short occurs while thecontroller is operating.

A comparator monitors the output for overvoltage condi-tions. The comparator (OV) detects overvoltage faultsgreater than 7.5% above the nominal output voltage.When this condition is sensed, the top MOSFET is turnedoff and the bottom MOSFET is turned on until the overvolt-age condition is cleared. The output of this comparator isonly latched by the overvoltage condition itself and willtherefore allow a switching regulator system having a poorPC layout to function while the design is being debugged.The bottom MOSFET remains on continuously for as longas the OV condition persists; if VOUT returns to a safe level,normal operation automatically resumes. A shorted topMOSFET will result in a high current condition which willopen the system fuse. The switching regulator will regu-late properly with a leaky top MOSFET by altering the dutycycle to accommodate the leakage.

Phase-Locked Loop and Frequency Synchronization

The LTC3727 has a phase-locked loop comprised of aninternal voltage controlled oscillator and phase detector.This allows the top MOSFET turn-on to be locked to therising edge of an external source. The frequency range ofthe voltage controlled oscillator is ±50% around thecenter frequency fO. A voltage applied to the PLLFLTR pinof 1.2V corresponds to a frequency of approximately380kHz. The nominal operating frequency range of theLTC3727 is 250kHz to 550kHz.

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The phase detector used is an edge sensitive digital typewhich provides zero degrees phase shift between theexternal and internal oscillators. This type of phase detec-tor will not lock up on input frequencies close to theharmonics of the VCO center frequency. The PLL hold-inrange, ΔfH, is equal to the capture range, ΔfC:

ΔfH = ΔfC = ±0.5 fO (250kHz-550kHz)

The output of the phase detector is a complementary pairof current sources charging or discharging the externalfilter network on the PLLFLTR pin.

If the external frequency (fPLLIN) is greater than the oscil-lator frequency f0SC, current is sourced continuously,pulling up the PLLFLTR pin. When the external frequencyis less than f0SC, current is sunk continuously, pullingdown the PLLFLTR pin. If the external and internal fre-quencies are the same but exhibit a phase difference, thecurrent sources turn on for an amount of time correspond-ing to the phase difference. Thus the voltage on thePLLFLTR pin is adjusted until the phase and frequency ofthe external and internal oscillators are identical. At thisstable operating point the phase comparator output isopen and the filter capacitor CLP holds the voltage. TheLTC3727 PLLIN pin must be driven from a low impedancesource such as a logic gate located close to the pin. Whenusing multiple LTC3727s for a phase-locked system, thePLLFLTR pin of the master oscillator should be biased ata voltage that will guarantee the slave oscillator(s) abilityto lock onto the master’s frequency. A DC voltage of 0.7Vto 1.7V applied to the master oscillator’s PLLFLTR pin isrecommended in order to meet this requirement. Theresultant operating frequency can range from 310kHz to470kHz.

The loop filter components (CLP, RLP) smooth out thecurrent pulses from the phase detector and provide astable input to the voltage controlled oscillator. The filtercomponents CLP and RLP determine how fast the loopacquires lock. Typically RLP =10kΩ and CLP is 0.01μF to0.1μF.

Minimum On-Time Considerations

Minimum on-time tON(MIN) is the smallest time durationthat the LTC3727 is capable of turning on the top MOSFET.It is determined by internal timing delays and the gatecharge required to turn on the top MOSFET. Low duty cycleapplications may approach this minimum on-time limitand care should be taken to ensure that

tVV fON MIN

OUT

IN( ) ( )

<

If the duty cycle falls below what can be accommodated bythe minimum on-time, the LTC3727 will begin to skipcycles. The output voltage will continue to be regulated,but the ripple voltage and current will increase.

The minimum on-time for the LTC3727 is generally lessthan 200ns. However, as the peak sense voltage decreasesthe minimum on-time gradually increases up to about300ns. This is of particular concern in forced continuousapplications with low ripple current at light loads. If theduty cycle drops below the minimum on-time limit in thissituation, a significant amount of cycle skipping can occurwith correspondingly larger inductor current and outputvoltage ripple.

FCB Pin Operation

The FCB pin can be used to regulate a secondary windingor as a logic level input. Continuous operation is forced onboth controllers when the FCB pin drops below 0.8V.During continuous mode, current flows continuously inthe transformer primary. The secondary winding(s) drawcurrent only when the bottom, synchronous switch is on.When primary load currents are low and/or the VIN/VOUTratio is low, the synchronous switch may not be on for asufficient amount of time to transfer power from theoutput capacitor to the secondary load. Forced continuousoperation will support secondary windings providing thereis sufficient synchronous switch duty factor. Thus, theFCB input pin removes the requirement that power must

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loading conditions. The open-loop DC gain of the controlloop is reduced depending upon the maximum load stepspecifications. Voltage positioning can easily be added tothe LTC3727 by loading the ITH pin with a resistive dividerhaving a Thevenin equivalent voltage source equal to themidpoint operating voltage range of the error amplifier, or1.2V (see Figure 8).

The resistive load reduces the DC loop gain while main-taining the linear control range of the error amplifier. Themaximum output voltage deviation can theoretically bereduced to half or alternatively the amount of outputcapacitance can be reduced for a particular application. Acomplete explanation is included in Design Solutions 10(see www.Linear.com).

be drawn from the inductor primary in order to extractpower from the auxiliary windings. With the loop incontinuous mode, the auxiliary outputs may nominally beloaded without regard to the primary output load.

The secondary output voltage VSEC is normally set asshown in Figure 6 by the turns ratio N of the transformer:

VSEC ≅ (N + 1) VOUT

However, if the controller goes into Burst Mode operationand halts switching due to a light primary load current,then VSEC will droop. An external resistive divider fromVSEC to the FCB pin sets a minimum voltage VSEC(MIN):

V VRRSEC MIN( ) .≅ +⎛

⎝⎜⎞⎠⎟

0 8 165

where R5 and R6 are shown in Figure 2.

If VSEC drops below this level, the FCB voltage forcestemporary continuous switching operation until VSEC isagain above its minimum.

In order to prevent erratic operation if no external connec-tions are made to the FCB pin, the FCB pin has a 0.18μAinternal current source pulling the pin high. Include thiscurrent when choosing resistor values R5 and R6.

The following table summarizes the possible states avail-able on the FCB pin:Table 1FCB PIN CONDITION

0V to 0.75V Forced Continuous Both Controllers(Current Reversal Allowed—Burst Inhibited)

0.85V < VFCB < 6.8V Minimum Peak Current InducesBurst Mode OperationNo Current Reversal Allowed

Feedback Resistors Regulating a Secondary Winding

>7.3V Burst Mode Operation DisabledConstant Frequency Mode EnabledNo Current Reversal Allowed NoMinimum Peak Current

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peakoutput voltage excursions under worst-case transient

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Figure 8. Active Voltage Positioning Applied to the LTC3727

Efficiency Considerations

The percent efficiency of a switching regulator is equal tothe output power divided by the input power times 100%.It is often useful to analyze individual losses to determinewhat is limiting the efficiency and which change wouldproduce the most improvement. Percent efficiency can beexpressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentageof input power.

Although all dissipative elements in the circuit producelosses, four main sources usually account for most of thelosses in LTC3727 circuits: 1) LTC3727 VIN current (in-cluding loading on the 3.3V internal regulator), 2) INTVCCregulator current, 3) I2R losses, 4) Topside MOSFETtransition losses.

1. The VIN current has two components: the first is the DCsupply current given in the Electrical Characteristics table,

ITH

RCRT1

INTVCC

CC

3727 F08

LTC3727

RT2

23

LTC3727/LTC3727-1

3727fc

4. Transition losses apply only to the topside MOSFET(s),and become significant only when operating at high inputvoltages (typically 15V or greater). Transition losses canbe estimated from:

Transition Loss = (1.7) VIN2 IO(MAX) CRSS f

Other “hidden” losses such as copper trace and internalbattery resistances can account for an additional 5% to10% efficiency degradation in portable systems. It is veryimportant to include these “system” level losses duringthe design phase. The internal battery and fuse resistancelosses can be minimized by making sure that CIN hasadequate charge storage and very low ESR at the switch-ing frequency. A 25W supply will typically require a mini-mum of 22μF to 47μF of capacitance having a maximumof 20mΩ to 50mΩ of ESR. The LTC3727 2-phase architec-ture typically halves this input capacitance requirementover competing solutions. Other losses, including Schot-tky diode conduction losses during dead-time and induc-tor core losses, generally account for less than 2% totaladditional loss.

Checking Transient Response

The regulator loop response can be checked by looking atthe load current transient response. Switching regulatorstake several cycles to respond to a step in DC (resistive)load current. When a load step occurs, VOUT shifts by anamount equal to ΔILOAD (ESR), where ESR is the effectiveseries resistance of COUT. ΔILOAD also begins to charge ordischarge COUT generating the feedback error signal thatforces the regulator to adapt to the current change andreturn VOUT to its steady-state value. During this recoverytime VOUT can be monitored for excessive overshoot orringing, which would indicate a stability problem. OPTI-LOOP compensation allows the transient response to beoptimized over a wide range of output capacitance andESR values. The availability of the ITH pin not only allowsoptimization of control loop behavior but also provides aDC coupled and AC filtered closed loop response testpoint. The DC step, rise time and settling at this test pointtruly reflects the closed loop response. Assuming a pre-dominantly second order system, phase margin and/ordamping factor can be estimated using the percentage of

which excludes MOSFET driver and control currents; thesecond is the current drawn from the 3.3V linear regulatoroutput. VIN current typically results in a small (<0.1%) loss.

2. INTVCC current is the sum of the MOSFET driver andcontrol currents. The MOSFET driver current results fromswitching the gate capacitance of the power MOSFETs.Each time a MOSFET gate is switched from low to high tolow again, a packet of charge dQ moves from INTVCC toground. The resulting dQ/dt is a current out of INTVCC thatis typically much larger than the control circuit current. Incontinuous mode, IGATECHG =f(QT + QB), where QT and QBare the gate charges of the topside and bottom sideMOSFETs.

Supplying INTVCC power through the EXTVCC switch inputfrom an output-derived source will scale the VIN currentrequired for the driver and control circuits by a factor of(Duty Cycle)/(Efficiency). For example, in a 20V to 5Vapplication, 10mA of INTVCC current results in approxi-mately 2.5mA of VIN current. This reduces the mid-currentloss from 10% or more (if the driver was powered directlyfrom VIN) to only a few percent.

3. I2R losses are predicted from the DC resistances of thefuse (if used), MOSFET, inductor, current sense resistor,and input and output capacitor ESR. In continuous modethe average output current flows through L and RSENSE,but is “chopped” between the topside MOSFET and thesynchronous MOSFET. If the two MOSFETs have approxi-mately the same RDS(ON), then the resistance of oneMOSFET can simply be summed with the resistances of L,RSENSE and ESR to obtain I2R losses. For example, if eachRDS(ON) = 30mΩ, RL = 50mΩ, RSENSE = 10mΩ and RESR= 40mΩ (sum of both input and output capacitancelosses), then the total resistance is 130mΩ. This results inlosses ranging from 3% to 13% as the output currentincreases from 1A to 5A for a 5V output, or a 4% to 20%loss for a 3.3V output. Efficiency varies as the inversesquare of VOUT for the same external components andoutput power level. The combined effects of increasinglylower output voltages and higher currents required byhigh performance digital systems is not doubling butquadrupling the importance of loss terms in the switchingregulator system!

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overshoot seen at this pin. The bandwidth can also beestimated by examining the rise time at the pin. The ITHexternal components shown in the Figure 1 circuit willprovide an adequate starting point for most applications.

The ITH series RC-CC filter sets the dominant pole-zeroloop compensation. The values can be modified slightly(from 0.5 to 2 times their suggested values) to optimizetransient response once the final PC layout is done and theparticular output capacitor type and value have beendetermined. The output capacitors need to be selectedbecause the various types and values determine the loopgain and phase. An output current pulse of 20% to 80% offull-load current having a rise time of 1μs to 10μs willproduce output voltage and ITH pin waveforms that willgive a sense of the overall loop stability without breakingthe feedback loop. Placing a power MOSFET directlyacross the output capacitor and driving the gate with anappropriate signal generator is a practical way to producea realistic load step condition. The initial output voltagestep resulting from the step change in output current maynot be within the bandwidth of the feedback loop, so thissignal cannot be used to determine phase margin. This iswhy it is better to look at the ITH pin signal which is in thefeedback loop and is the filtered and compensated controlloop response. The gain of the loop will be increased byincreasing RC and the bandwidth of the loop will beincreased by decreasing CC. If RC is increased by the samefactor that CC is decreased, the zero frequency will be keptthe same, thereby keeping the phase shift the same in themost critical frequency range of the feedback loop. Theoutput voltage settling behavior is related to the stability ofthe closed-loop system and will demonstrate the actualoverall supply performance.

A second, more severe transient is caused by switching inloads with large (>1μF) supply bypass capacitors. Thedischarged bypass capacitors are effectively put in parallelwith COUT, causing a rapid drop in VOUT. No regulator canalter its delivery of current quickly enough to prevent thissudden step change in output voltage if the load switchresistance is low and it is driven quickly. If the ratio ofCLOAD to COUT is greater than 1:50, the switch rise timeshould be controlled so that the load rise time is limited to

approximately 25 • CLOAD. Thus a 10μF capacitor wouldrequire a 250μs rise time, limiting the charging current toabout 200mA.

Automotive Considerations: Plugging into theCigarette Lighter

As battery-powered devices go mobile, there is a naturalinterest in plugging into the cigarette lighter in order toconserve or even recharge battery packs during opera-tion. But before you connect, be advised: you are plugginginto the supply from Hell. The main power line in anautomobile is the source of a number of nasty potentialtransients, including load-dump, reverse-battery, anddouble-battery.

Load-dump is the result of a loose battery cable. When thecable breaks connection, the field collapse in the alternatorcan cause a positive spike as high as 60V which takesseveral hundred milliseconds to decay. Reverse-battery isjust what it says, while double-battery is a consequence oftow-truck operators finding that a 24V jump start crankscold engines faster than 12V.

The network shown in Figure 9 is the most straight forwardapproach to protect a DC/DC converter from the ravagesof an automotive power line. The series diode preventscurrent from flowing during reverse-battery, while thetransient suppressor clamps the input voltage duringload-dump. Note that the transient suppressor should notconduct during double-battery operation, but must stillclamp the input voltage below breakdown of the converter.Although the LTC3727 has a maximum input voltage of36V, most applications will be limited to 30V by theMOSFET BVDSS.

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WU UUFigure 9. Automotive Application Protection

VIN

3727 F09

LTC3727

TRANSIENT VOLTAGESUPPRESSORGENERAL INSTRUMENT1.5KA24A

50A IPK RATING

12V

25

LTC3727/LTC3727-1

3727fc

Design Example

As a design example for one channel, assume VIN =24V(nominal), VIN = 30V(max), VOUT = 12V, IMAX = 5A andf = 250kHz.

The inductance value is chosen first based on a 40% ripplecurrent assumption. The highest value of ripple currentoccurs at the maximum input voltage. Tie the PLLFLTR pinto the SGND pin for 250kHz operation. The minimuminductance for 40% ripple current is:

ΔIVf L

VVL

OUT OUT

IN= ⎛

⎝⎜⎞⎠⎟( )( )

–1

A 14μH inductor will result in 40% ripple current. The peakinductor current will be the maximum DC value plus onehalf the ripple current, or 6A, for the 14μH value.

The RSENSE resistor value can be calculated by using themaximum current sense voltage specification with someaccommodation for tolerances:

RmVASENSE ≤ ≈ Ω90

60 015.

Choosing 1% resistors; R1 = 20k and R2 = 280k yields anoutput voltage of 12V.

The power dissipation on the top side MOSFET can beeasily estimated. Choosing a Siliconix Si4412DY resultsin: RDS(ON) = 0.042Ω, CRSS = 100pF. At maximum inputvoltage with T(estimated) = 50°C:

PVV

C C

V A pF kHz

mW

MAIN = ( ) + ° °[ ]Ω( ) + ( ) ( )( )( )

=

1230

5 1 0 005 50 25

0 042 1 7 30 5 100 250

664

2

2

( . )( – )

. .

A short-circuit to ground will result in a folded back currentof:

ImV ns V

HASC =

Ω+

μ⎛⎝⎜

⎞⎠⎟

=450 015

12

200 3014

3 2.

( ).

with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1.The resulting power dissipated in the bottom MOSFET is:

PV V

VA

mW

SYNC = ( ) ( ) Ω( )

=

30 1230

3 2 1 1 0 042

284

2–. . .

which is less than under full-load conditions.

CIN is chosen for an RMS current rating of at least 3A attemperature assuming only this channel is on. COUT ischosen with an ESR of 0.02Ω for low output ripple. Theoutput ripple in continuous mode will be highest at themaximum input voltage. The output voltage ripple due toESR is approximately:

VORIPPLE = RESR (ΔIL) = 0.02Ω(2A) = 40mVP–P

PC Board Layout Checklist

When laying out the printed circuit board, the followingchecklist should be used to ensure proper operation of theLTC3727. These items are also illustrated graphically inthe layout diagram of Figure 10; Figure 11 illustrates thecurrent waveforms present in the various branches of the2-phase synchronous regulators operating in continuousmode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 locatedwithin 1cm of each other with a common drain connectionat CIN? Do not attempt to split the input decoupling for thetwo channels as it can cause a large resonant loop.

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2. Are the signal and power grounds kept separate? Thecombined LTC3727 signal ground pin and the groundreturn of CINTVCC must return to the combined COUT (–)terminals. The path formed by the top N-channel MOSFET,Schottky diode and the CIN capacitor should have shortleads and PC trace lengths. The output capacitor (–)terminals should be connected as close as possible to the(–) terminals of the input capacitor by placing the capaci-tors next to each other and away from the Schottky loopdescribed above.

3. Do the LTC3727 VOSENSE pins resistive dividers con-nect to the (+) terminals of COUT? The resistive dividermust be connected between the (+) terminal of COUT andsignal ground. The R2 and R4 connections should not be

along the high current input feeds from the inputcapacitor(s).

4. Are the SENSE – and SENSE + leads routed togetherwith minimum PC trace spacing? The filter capacitorbetween SENSE + and SENSE – should be as close aspossible to the IC. Ensure accurate current sensing withKelvin connections at the SENSE resistor.

5. Is the INTVCC decoupling capacitor connected close tothe IC, between the INTVCC and the power ground pins?This capacitor carries the MOSFET drivers current peaks.An additional 1μF ceramic capacitor placed immediatelynext to the INTVCC and PGND pins can help improve noiseperformance substantially.

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WU UUFigure 10. LTC3727 Recommended Printed Circuit Layout Diagram

CB2

CB1

RPU

PGOOD

VPULL-UP(<7V)

CINTVCC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

+

CIN

D1M1 M2

M3 M4

D2

+

CVIN

VIN

RIN

INTVCC

3.3V

R4R3

R2R1

RUN/SS1

SENSE1+

SENSE1–

VOSENSE1

PLLFLTR

PLLIN

FCB

ITH1

SGND

3.3VOUT

ITH2

VOSENSE2

SENSE2–

SENSE2+

PGOOD

TG1

SW1

BOOST1

VIN

BG1

EXTVCC

INTVCC

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3727

L1

L2

COUT1

VOUT1

GND

VOUT2

3727 F10

+

COUT2

+

RSENSE

RSENSE

fIN

27

LTC3727/LTC3727-1

3727fc

6. Keep the switching nodes (SW1, SW2), top gate nodes(TG1, TG2), and boost nodes (BOOST1, BOOST2) awayfrom sensitive small-signal nodes, especially from theopposites channel’s voltage and current sensing feedbackpins. All of these nodes have very large and fast movingsignals and therefore should be kept on the “output side”of the LTC3727 and occupy minimum PC trace area.

7. Use a modified “star ground” technique: a low imped-ance, large copper area central grounding point on thesame side of the PC board as the input and outputcapacitors with tie-ins for the bottom of the INTVCC

decoupling capacitor, the bottom of the voltage feedbackresistive divider and the SGND pin of the IC.

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to usea DC-50MHz current probe to monitor the current in theinductor while testing the circuit. Monitor the outputswitching node (SW pin) to synchronize the oscilloscopeto the internal oscillator and probe the actual outputvoltage as well. Check for proper performance over theoperating voltage and current range expected in the

APPLICATIO S I FOR ATIO

WU UU

Figure 11. Branch Current Waveforms

RL1D1

L1SW1 RSENSE1 VOUT1

COUT1+

VIN

CIN

RIN +

RL2D2BOLD LINES INDICATEHIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH

L2SW2

3727 F11

RSENSE2 VOUT2

COUT2+

28

LTC3727/LTC3727-1

3727fc

APPLICATIO S I FOR ATIO

WU UU

application. The frequency of operation should be main-tained over the input voltage range down to dropout anduntil the output load drops below the low current opera-tion threshold—typically 10% to 20% of the maximumdesigned current level in Burst Mode operation.

The duty cycle percentage should be maintained fromcycle to cycle in a well-designed, low noise PCB imple-mentation. Variation in the duty cycle at a subharmonicrate can suggest noise pickup at the current or voltagesensing inputs or inadequate loop compensation. Over-compensation of the loop can be used to tame a poor PClayout if regulator bandwidth optimization is not required.Only after each controller is checked for its individualperformance should both controllers be turned on at thesame time. A particularly difficult region of operation iswhen one controller channel is nearing its current com-parator trip point when the other channel is turning on itstop MOSFET. This occurs around 50% duty cycle on eitherchannel due to the phasing of the internal clocks and maycause minor duty cycle jitter.

Short-circuit testing can be performed to verify properovercurrent latchoff, or 5μA can be provided to the RUN/SS pin(s) by resistors from VIN to prevent the short-circuitlatchoff from occurring.

Reduce VIN from its nominal level to verify operation of theregulator in dropout. Check the operation of theundervoltage lockout circuit by further lowering VIN whilemonitoring the outputs to verify operation.

Investigate whether any problems exist only at higheroutput currents or only at higher input voltages. If prob-lems coincide with high input voltages and low outputcurrents, look for capacitive coupling between the BOOST,SW, TG, and possibly BG connections and the sensitivevoltage and current pins. The capacitor placed across thecurrent sensing pins needs to be placed immediatelyadjacent to the pins of the IC. This capacitor helps tominimize the effects of differential noise injection due tohigh frequency capacitive coupling. If problems are en-countered with high current output loading at lower inputvoltages, look for inductive coupling between CIN, Schottkyand the top MOSFET components to the sensitive currentand voltage sensing traces. In addition, investigate com-mon ground path voltage pickup between these compo-nents and the SGND pin of the IC.

An embarrassing problem, which can be missed in anotherwise properly working switching regulator, resultswhen the current sensing leads are hooked up backwards.The output voltage under this improper hookup will still bemaintained but the advantages of current mode controlwill not be realized. Compensation of the voltage loop willbe much more sensitive to component selection. Thisbehavior can be investigated by temporarily shorting outthe current sensing resistor—don’t worry, the regulatorwill still maintain control of the output voltage.

29

LTC3727/LTC3727-1

3727fc

TYPICAL APPLICATIO S

U

0.1μF

4.7μF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

+

22μF50V

D1MBRM140T3

D2MBRM140T3

M1A M1B

M2A M2B

1μF10V

0.1μF

10Ω

0.015Ω

0.015Ω

fSYNC

3.3V

0.1μF

10k

105k1%

33pF

15k

33pF

15k220pF

220pF

0.01μF1000pF

1000pF

1000pF

0.1μF

20k1%

280k1%

20k1%

RUN/SS1

SENSE1+

SENSE1–

VOSENSE1

PLLFLTR

PLLIN

FCB

ITH1

SGND

3.3VOUT

ITH2

VOSENSE2

SENSE2–

SENSE2+

PGOOD

TG1

SW1

BOOST1

VIN

BG1

EXTVCC

INTVCC

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3727

L18μH

L215μH

COUT147μF6.3V

COUT2 100μF 16V

GND

VOUT212V4A; 5A PEAK

VOUT15V5A; 6A PEAK

VIN15V TO28V

3727 F12

++

VIN: 15V TO 28VVOUT: 5V, 5A/12V, 4A

SWITCHING FREQUENCY = 250kHzMI, M2: FAIRCHILD FDS6680A

L1: 8μH SUMIDA CDEP134-8R0L2: 15μH COILTRONICS UP4B-150

27pF

27pF

0.1μF

CMDSH-3

CMDSH-3

PGOOD

VPULL-UP(<7V)

COUT1: PANASONIC EEFCDOJ470RCOUT2: SANYO OS-CON 16SVP100M

Figure 12. LTC3727 12V/4A, 5V/5A Regulator with External Frequency Synchronization

30

LTC3727/LTC3727-1

3727fc

TYPICAL APPLICATIO S

U

0.1μF

4.7μF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

+

22μF50V

D1MBRM140T3

D2MBRM140T3

M1A M1B

M2A M2B

1μF10V

0.1μF

10Ω

0.015Ω

0.015Ω

3.3V

0.1μF

105k1%

33pF

15k

33pF

15k220pF

220pF

1000pF

1000pF

0.1μF

20k1%

192.5k1%

20k1%

RUN/SS1

SENSE1+

SENSE1–

VOSENSE1

PLLFLTR

PLLIN

FCB

ITH1

SGND

3.3VOUT

ITH2

VOSENSE2

SENSE2–

SENSE2+

PGOOD

TG1

SW1

BOOST1

VIN

BG1

EXTVCC

INTVCC

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3727

L18μH

L28μH

COUT147μF6.3V

COUT2 100μF 16V

GND

VOUT28.5V3A; 4A PEAK

VOUT15V5A; 6A PEAK

VIN10V TO 15V

3727 F13

++

VIN: 10V TO 15VVOUT: 5V, 5A/8.5V, 3A

SWITCHING FREQUENCY = 250kHzMI, M2: FAIRCHILD FDS6680A

L1, L2: 8μH SUMIDA CDEP134-8R0

27pF

27pF

0.1μF

CMDSH-3

CMDSH-3

PGOOD

VPULL-UP(<7V)

COUT1: PANASONIC EEFCDOJ470RCOUT2: SANYO OS-CON 16SVP100M

Figure 13. LTC3727 8.5V/3A, 5V/5A Regulator

31

LTC3727/LTC3727-1

3727fc

U

PACKAGE DESCRIPTIOG Package

28-Lead Plastic SSOP (5.3mm)(Reference LTC DWG # 05-08-1640)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

UH Package32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

G28 SSOP 0204

0.09 – 0.25(.0035 – .010)

0° – 8°

0.55 – 0.95(.022 – .037)

5.00 – 5.60**(.197 – .221)

7.40 – 8.20(.291 – .323)

1 2 3 4 5 6 7 8 9 10 11 12 1413

9.90 – 10.50*(.390 – .413)

2526 22 21 20 19 18 17 16 1523242728

2.0(.079)MAX

0.05(.002)MIN

0.65(.0256)

BSC0.22 – 0.38

(.009 – .015)TYPMILLIMETERS

(INCHES)

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDEDIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

*

**

NOTE:1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

0.42 ±0.03 0.65 BSC

5.3 – 5.77.8 – 8.2

RECOMMENDED SOLDER PAD LAYOUT

1.25 ±0.12

5.00 ± 0.10(4 SIDES)

NOTE:1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED)2. DRAWING NOT TO SCALE3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1TOP MARK(NOTE 6)

0.40 ± 0.10

31

1

2

32

BOTTOM VIEW—EXPOSED PAD

3.50 REF(4-SIDES)

3.45 ± 0.10

3.45 ± 0.10

0.75 ± 0.05 R = 0.115TYP

0.25 ± 0.05(UH32) QFN 0406 REV D

0.50 BSC

0.200 REF

0.00 – 0.05

0.70 ±0.05

3.50 REF(4 SIDES)

4.10 ±0.05

5.50 ±0.05

0.25 ± 0.05

PACKAGE OUTLINE

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUTAPPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH R = 0.30 TYPOR 0.35 × 45° CHAMFERR = 0.05

TYP

3.45 ± 0.05

3.45 ± 0.05

32

LTC3727/LTC3727-1

3727fc

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2001

LT 0507 REV C • PRINTED IN USA

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