LSI Product Selector Guide Rev Jan10 FIN

Networking PCS CatalogMay 2009

C o n n e C t i v i t y S t a n d a r d P r o d u C t S P a g e

• IEEE 1394B

FW643E 3

FW420 4

FW430 5

FW843 6

• IEEE 1394A

FW533E 7

FW323 8

FW322 9

FW802 10

• 1394 Cards

FireStorm™ FW643/FW533 11

FireSide™ FW643 ExpressCard™ 12

1394 PC OEM Card 13

• Modem - PC

SV92EX 14

SV92A3 15

SV92U2 16

SV99PP 17

• Modem - Embedded Data

CV22A 18

CV92/34/22 19

• Modem - Embedded FAX

CFAX 20

DP3 21

SFAX 22

• Voice

FX1000 23

• Gigabit Ethernet Transceiver

ET1011C 24

Personal Connectivity SolutionsMay 2009

Networking PCS Catalog 3

FW643EPCI Express® 1394b Link / PHY Open Host Controller Interface

F e a t u r e S

n Single chip, integrated Link and PHY for PCI Express 1394b

n Supports three 1394b 800Mb/s ports

n High performance, pipelined data transfer

n Sustained performance of 87 MByte/s read and 78 MByte/s write

n Dedicated asynchronous and isochronous descriptor-based DMA engines

n Large DMA FIFOs

n Enhanced power management

n 480 mW typical power consumption

n Full ASPM and CLKREQ power management support

n Single 24.576 MHz. crystal for lower BOM costs

n Single 3.3V supply

n Optional configuration EEPROM support

n Small form factor Halogen Free BGA package – 7x7mm footprint

n Also available in 11x11 mm BGA package for lower-cost board layouts

n Support for Windows and MacOS operating systems

n Supports 8 isochronous contexts for greater number of concurrent video streams

Brief Description

The LSI FW643E is a second generation 1394b OHCI controller designed specifically for high performance, PCI Express applications. Based on LSI’s proven TrueFire® technology, the FW643E has enhanced performance and power management features to deliver improved data transfer rates with lower power consumption.

The FW643E is the fastest 1394b device and the only single-chip PCI Express 1394b device available on the market today.

The FW643E is ideally suited for high-end PC desktops and notebooks, adapter cards, PC gaming systems, external disk drive backups, industrial vision systems, and other applications where high performance, reliable data transfer is required.

LSI provides support for the FW643 with:

n Evaluation adapter board

n Ready-to-manufacture adapter card reference design

n Manufacturing test utilities

n Configuration EEPROM image

i e e e 1 3 9 4 B P r o d u C t S


FW4201394b PCI Link Open Host Controller Interface

F e a t u r e S

n Available in a 120-pin TQFP or 129-pin VTFSBGA lead-free package.

n 1394a link and 1394b link:

— Compatible with current Microsoft Windows® drivers and other common applications.

— Compatible with existing and older, 1394 consumer electronics and peripherals products.

— Supports low-power system designs (CMOS implementation, power management features).

— Provides LPS, LKON, and CNA outputs to support legacy power management implementations.

— Cycle master and isochronous resource manager capable.

— Supports 1394a and 1394b acceleration features.

— Provides an 8-bit interface running at 50 MHz for 1394a and 100 MHz for 1394b.

n PCI:

— Revision 2.3 compliant.

— 33 MHz/32-bit operation.

— Programmable burst size for PCI data transfer.

— Supports PCI Bus Power Management Interface Specification v.1.1.

— Supports clockrun protocol per PCI Mobile Design Guide.

— Global byte swap function.

n 1394 OHCI specification revision 1.0 and 1.1:

— Isochronous receive dual-buffer mode.

— Enhanced isochronous transmit skip/ over flow support.

— ack_data_error improvements for asynchronous and physical requests.

— Enhanced CSR control register implementation.

— Autonomous configuration ROM updates.

— Enhanced power management support, including ack_tardy event.

— Enhanced SelfID protocol, including

selfIDComplete2 event.

— Compatible with Microsoft Windows and MacOS® operating systems.

— 4 Kbyte isochronous transmit FIFO.

— 2 Kbyte asynchronous transmit FIFO.

— 4 Kbyte isochronous receive FIFO.

— 2 Kbyte asynchronous receive FIFO.

— Dedicated asynchronous and isochronous descriptor-based DMA engines.

o t h e r F e a t u r e S

n I2C serial ROM interface.

n CMOS process.

n 3.3 V operation, 5 V tolerant inputs.

The FW420 is the LSI imple-menta-tion of a high performance, PCI bus-based open host controller for implementation of IEEE® 1394b compliant systems and devices. Link layer functions are handled by the FW420, utilizing the on-chip 1394b compliant link core. A high-performance and cost-ef-fective solution for connecting and servicing multiple IEEE 1394 (1394—1995, 1394a, and 1394b) peripheral devices can be realized.

i e e e 1 3 9 4 B P r o d u C t S


FW430

1394a/b PCI PHY/Link Open Host Controller Interface

F e a t u r e S

n 1394a-2000 OHCI link and PHY core function in a single device:

— Single-chip link and PHY enables smaller, simpler, more efficient motherboard and add-in card designs.

— Compatibility with current Microsoft Windows® drivers and common applications.

n OHCI:

— Complies with the 1394 OHCI 1.1 Specification.







— Eight isochronous transmit/receive contexts.

— Supports parallel processing of incoming physical read and write requests.

n 1394b link:

— Cycle master and isochronous resource manager capable.

— Support for 1394b acceleration features.

— Support for 1394a-2000 acceleration features.

— Eight-bit interface running at 100 MHz.

n 1394a-2000 PHY core:

— Compliant with IEEE ® 1394a-2000, Standard for a High Performance Serial Bus.

— Provides three fully compliant cable ports, each supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic.

n PCI:



— Supports optimized memory read line, memory read multiple, and memory write invalidate burst commands.

— Supports PCI Bus Power Management Interface Specification v.1.1, including D3cold wakeups.

— Supports CLKRUN# protocol per PCI Mobile Design Guide.

— CardBus support per PC Card Standard Release 8.0, including 128 bytes of on- chip tuple memory.

— Supports Mini PCI Specification v1.0, including Mini PCI® power requirements.



n 144-pin TQFP or 161-ball VTFSBGA package.

n NAND tree test mode.

FW430 Functional Overview

LSI’ s FW430 is a high-performance PCI busbased open host controller for implementation of IEEE 1394a or 1394b compliant systems and devices. The FW430 features a switch to select 1394a mode or 1394b mode. The switch selects between a 1394a-2000 compliant on-chip physical layer core or an off-chip 1394a (FW802b) or 1394b (FW843) external PHY. In this way, a high-performance and cost-effective solution for connection and servicing multiple IEEE 1394 (1394-1995, 1394a, and 1394b) peripheral devices can be realized.

i e e e 1 3 9 4 B P r o d u C t S


i e e e 1 3 9 4 B P r o d u C t S

FW843IEEE® 1394b Bilingual Three-Port Cable Transceiver/Arbiter

F e a t u r e S

n Provides three backward-compatible IEEE-1394 bilingual cable ports.

n Fully supports provisions of IEEE 1394b-2002.

n Fully supports provisions of IEEE 1394a-2000 and IEEE 1394-1995 standards.

n Supports 1394a speeds of S100, S200, and S400.

n Supports 1394b-2002 speeds of S400B and S800B.

n On-chip (PLL) for high-speed clock generation.

n Full 1394a-2000 support includes the following: — Connection debounce.

— Extended resume signaling for compatibility with legacy DV (digital video) devices.

— Arbitrated short reset.

— Port disable/suspend/resume.

— Multispeed concatenation.

— Fly-by concatenation.

— Arbitration acceleration.

n Single 3.3 V supply and on-chip 1.2 V voltage regulator.

n Low-power sleep mode.

n Powerdown modes to conserve energy for battery-operated applications.

n Fully compliant with open host controller interface (OHCI) requirements.

n Cable power sense function to detect external cable power.

n Register bits give software control of contender bit, power class bits, link active control bit, and 1394a-2000 features.

n External pin control of power-class bits.

n Data interface to link-layer mode is pin-selectable from 1394a-2000 mode or 1394b-2002 mode.

n Interoperable with other 1394 physical layers using 1.8 V, 3.3 V, and 5.0 V supplies.

n Low-jitter on-chip crystal oscillator provides transmit and receive data at 98.304 Mbits/s, 196.608 Mbits/s, 393.216 Mbits/s, 983.04 Mbits/s, and a link-layer controller clock at 49.152 MHz or 98.304 MHz.

n Fail-safe circuitry senses sudden loss of power to the device. The ports are disabled to ensure that the FW843 does not load the TPBIAS with any connected device and blocks any leakage from the port back to the power plane.

n 1394a-2000 compliant common-mode noise filter on the incoming bias detect circuit filters out crosstalk noise.

n Scan test modes.

n 84-pin MLCC package.

The FW843 provides the digital and analog functions needed to implement a three-port node in a cable-based IEEE 1394 network. All three ports are compli-ant with IEEE-1394b-2002 and backward-compatible with IEEE 1394a-2000 and IEEE 1394-1995. The three ports are capable of monitoring the line conditions for determining the connection status, initialization and arbitration, and for the packet reception and transmission.

Description

The FW843 provides the digital and analog functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each of the three ports can be configured to work in data-strobe mode only (1394a-2000) by pulling the corresponding DSMO input pin to the 3.3 V supply.

The FW843 supports the following 1394 speeds:

n S100 (98.304 Mbits/s)

n S200 (196.608 Mbits/s)

n S400 (393.216 Mbits/s)

n S400B (491.52 Mbits/s)

n S800B (983.04 Mbits/s)


i e e e 1 3 9 4 a P r o d u C t S

FW533EPCI Express® 1394a PHY/LinkOpen Host Controller Interface

F e a t u r e S

n Single chip, integrated Link and PHY for PCI Express 1394a

n Supports three 1394a 400Mb/s ports

n High performance, pipelined data transfer

n Sustained performance of 37 MByte/s read and 34 MByte/s write

n Dedicated asynchronous and isochronous descriptor-based DMA engines

n Large DMA FIFOs

n Enhanced power management

n 480 mW typical power consumption

n Full ASPM and CLKREQ power management support

n Single 24.576 MHz. crystal for lower BOM costs

n Single 3.3V supply

n Configuration via an external EEPROM – no need for BIOS changes or configuration utility

n 11x11 mm BGA package with 0.8 mm ball pitch for lower-cost board layouts

n Also available in a small form factor Halogen Free BGA package – 7x7mm footprint

n Support for Windows and MacOS operating systems

n Supports 8 isochronous contexts for greater number of concurrent video streams

Brief Description

The LSI FW533E is a second genera-tion 1394a OHCI controller designed specifically for high performance, PCI Express applications. Based on LSI’s proven TrueFire® technology, the F533E has enhanced performance and power management features to deliver improved data transfer rates with lower power consumption.

The FW533E is ideally suited for adapt-er card applications. The FW533E is pin compatible with the LSI FW643E device, so that a single design and layout can be populated with either device to support 1394a or 1394b applications.

The FW533E also supports high-end PC desktops and notebooks, PC gaming systems, external disk drive backups, industrial vision systems, and other applications where high performance, reliable data transfer is required.

LSI provides support for the FW533 with:n Evaluation adapter board

n Ready-to-manufacture adapter card reference design

n Manufacturing test utilities

n Configuration EEPROM image


i e e e 1 3 9 4 a P r o d u C t S

FW3231394a PCI PHY/Link Open Host Controller Interface

F e a t u r e S


— Single-chip link and PHY enable smaller, simpler, more efficient motherboard and add-in card designs.

— Enables lower system costs.


— Supports low-power system designs (CMOS implementation, power management features).

— Provides LPS, LKON, and CNA outputs to support legacy power management implementations.

n OHCI:


— OHCI 1.0 backwards compatible—configurable via EEPROM to operate in either OHCI 1.0 or OHCI 1.1 mode.

— Listed on Windows hardware compatibility list

http://testedproducts.windowsmarketplace.com/.








— Prefetches isochronous transmit data.

— Supports posted write transactions.


— May be used without an EEPROM when the system BIOS is programmed with the EEPROM contents.

n 1394a-2000 PHY core: — Compliant with IEEE ® 1394a-2000, Standard for a High Performance Serial Bus (Supplement).

— Provides three fully compliant cable ports, each supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic.

— Does not require external filter capacitor for PLL.

— Supports link-on as a part of the internal PHY corelink interface.

— Supports arbitrated short bus reset to improve utilization of the bus.

— Supports multispeed packet concatenation.

— Supports PHY pinging and remote PHY access packets.

— Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V.

n PCI:



— Programmable burst size thresholds for PCI data transfer.



— Supports Mini PCI® Specification v1.0, including Mini PCI power requirements.

— CardBus support per PC Card Standard Release 8.0, including 128 bytes of on-chip tuple memory.

— Supports PCI Bus Power Management Interface Specification v.1.1, including D3cold wake-ups.

— I2C serial ROM interface.

n CMOS process.


n 128-pin TQFP or 129-ball VTFSBGA package.

n NAND tree test mode.


FW3221394a PCI PHY/Link Open Host Controller Interface

F e a t u r e S

n 129-ball VTFSBGA

n 100-ball FSBGA

n 100-pin TQFP lead-free package.


— Single-chip link and PHY enable smaller, simpler, more efficient motherboard and add-in card designs.


— Interoperability with existing, as well as older, 1394 consumer electronics and peripherals products.

n OHCI:


— OHCI 1.0 backwards compatible: configurable via PCI bus commands to operate in either OHCI 1.0 or OHCI 1.1 mode.

— Listed on Windows hardware compatibility list

http://testedproducts.windowsmarketplace.com.








— Prefetches isochronous transmit data.

— Supports posted write transactions.


— May be used without an EEPROM when the system BIOS is programmed with the EEPROM contents.

n 1394a-2000 PHY core:

— Compliant with IEEE ® 1394a-2000, Standard for a High Performance Serial Bus.

— Two fully compliant cable ports, each supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic.

— Does not require external filter capacitor for PLL.

— Supports link-on as a part of the internal PHY core-link interface.

— Supports arbitrated short bus reset to improve utilization of the bus.

— Supports multispeed packet concatenation.

— Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V. n PCI:



— Programmable burst size thresholds for PCI data transfer.


— Supports PCI Bus Power Management Interface Specification v.1.1.


— Supports Mini PCI Specification v1.0, including Mini PCI ® power requirements.

— CardBus support per PC card standard release 8.0, including 128 bytes of on-chip tuple memory.

Other Features

n CMOS process.



Note: The T100 device does not support D3cold wakeup, CLKRUN protocol, Mini PCI applications, or Card-Bus applications.

i e e e 1 3 9 4 a P r o d u C t S

PCI CORE

ASYNCHRONOUS DATA

TRANSFER

ROM I/F

LINK CORE

PHY COREOHCI

ISOCHRONOUS DATA

TRANSFER

CABLE PORT 1

CABLE PORT 0

PCI BUS


i e e e 1 3 9 4 a P r o d u C t S

FW802Low-Power PHY 1394a-2000 Two-Port Transceiver/Arbiter Devices

F e a t u r e S

n Available in the following package options:

— 64-pin TQFP (lead-free) — 48-pin TQFP (lead-free) — 48-ball VTFSBGA (lead-free)

n Compliant with IEEE® Standard 1394a-2000, IEEE Standard for a High Performance Serial Bus Amendment 1.

n Low-power consumption during powerdown or microlow-power sleep mode.

n Support extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders.

n While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port.

n Do not require external filter capacitors for PLL.

n Do not require a separate 5 V supply for 5 V link controller interoperability.

n Interoperable across 1394 cable with 1394 physical layers (PHY) using 5 V supplies.

n Interoperable with 1394 link-layer controllers using 5 V supplies.

n 1394a-2000 compliant common mode noise filter on incoming TPBIAS.

n Powerdown features to conserve energy in battery powered applications include the following:

— Device powerdown pin/ball.

— Link interface disable using LPS.

— Inactive ports power down.

— Automatic micro-low-power sleep mode during suspend.

n Interface to link-layer controller supports Annex J electrical isolation as well as bus-keeper isolation.

n Provides two compliant cable ports at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.

n Supports OHCI requirements.

n Supports arbitrated short bus reset to improve utilization of the bus.

n Supports ack-accelerated arbitration and fly-by concatenation.

n Supports connection debounce.

n Supports multispeed packet concatenation.

n Supports PHY pinging and remote PHY access packets.

n Supports full suspend/resume.

n Supports PHY-link interface initialization and reset

n Supports 1394a-2000 register set.

n Supports LPS/link-on as a part of PHY-link interface.

n Supports provisions of IEEE 1394-1995 Standard for a High Performance Serial Bus.

n Fully interoperable with FireWire® and i.LINK® implementations of IEEE 1394-1995.

n Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V.

n Separate cable bias and driver termination voltage supply for each port.

n Meets Intel® Mobile Power Guideline 2000.

Other Features

n 48- and 64-pin TQFP, 48-ball VTFSBGA packages.

n Single 3.3 V supply operation.

n Data interface to link-layer controller provided through 2/4/8 parallel lines at 50 Mbits/s.

n 25 MHz crystal oscillator and PLL provide transmit/receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s, and link-layer controller clock at 50 MHz.

n Node power-class information signaling for system power management.

n Multiple separate package signals provided for analog and digital supplies and grounds.


FireStorm™ FW643/FW533

Evaluation Platform

F e a t u r e S :

FW643 Features:

n PCI Express to 1394b

n Three 1394b (S800) PHY ports

n Only single-chip PCIe to 1394b available

n Backward compatible to 1394a

FW533 Features:

n PCI Expressto 1394a

n Three 1394a (S400) PHY ports

Both Devices Feature:

n Single-lane PCI Expressversion 1.1

n OHCI version 1.1+

n Improved performance with large FIFOs

n Low power through support for ASPM

n Very small 7 mm x 7 mm VTFSBGA package

Each FireStormEvaluation Board Features:

n FW533 or FW643 device, 7 mm x 7 mm form-factor 127-pin VTFSBGA package

n Three 1394 bilingual interface ports

n Atmel®2-wire serial EEPROM, 100 kHz

n Single external 24.576 MHz crystal

n Disk drive power header

n Complete bill of materials

n Board schematics in OrCAD®Capture v9.0Ordering

Brief Description

The FireStorm is a low-cost, flexible, 4-layer PCB designed to allow users to quickly evaluate the performance of the LSI’s TrueFIRE™ SOCs, the FW533/FW643, or aid in develop-ment of custom solutions.

The FireStormFW533 platform combines an OHCI (open host controller interface) with LSI’s IEEE® 1394a-2000 technology and a high- performance, standards-compliant PCI Express® 1.0a host system interface.

The FireStorm FW643 platform combines an OHCI with LSI’s 1394b-2002 technology and a PCI Express 1.1 host system interface to provide S800 1394b-2002 compliant throughput.

FireStorm evaluation boards feature plug and play for Microsoft® Windows® (2000/XP/Vista) operating systems. The OS will detect the FireStorm presence and load the appropriate drivers automatically. Drivers for Linux® and MacOS® are also available.

i e e e 1 3 9 4 C a r d S


FireSide™ FW643 ExpressCard™

Reference Platform

F e a t u r e S

FW643 Features:

n PCI Express to 1394b

n Three 1394b (S800) PHY ports

n Only single-chip PCIe to 1394b available

n Backward compatible to 1394a

n Single-lane PCI Express version 1.1

n OHCI version 1.1+

n Improved performance with large FIFOs

n Low power through support for ASPM

n Very small 7 mm x 7 mm VTFSBGA package

Each FireSide Expansion Card Features:

n FW643 device, 7 mm x 7 mm form-factor 127-pin VTFSBGA package

n Two 1394 bilingual interface ports

n Atmel®2-wire serial EEPROM, 100 kHz

n Single external 24.576 MHz crystal

n Board schematics in OrCAD® Capture v9.0

n Turnkey design ready for volume production

n Complete bill of materials

Brief Description

FireSide is an expansion card that conveniently inserts into an ExpressCard slot on PC laptops/notebooks and thereby enables a quick and seamless transition to IEEE® 1394b capabilities. The platform is produced in a compact, ExpressCard/34 form-factor configuration, which offer two 800 Mbits/s1394 ports for high-speed connectivity.

FireSide is developed as a refer-ence design for a fully packaged, consumer-quality product. It is designed for rapid technology transfer to original design manu-facturers (ODMs) worldwide. This targeted approach enables reduced engineering costs and faster time to market for products based upon LSI’s TrueFIRE™ technology.

At the heart of the FireSide platform is the LSI FW643 chip that combines an OHCI with LSI’s 1394b-2002 technology and a PCI Express® 1.1 host system interface to provide S800 1394b-2002 compliant throughput.

The FireSide expansion card features plug and play for Microsoft® Windows® (2000/XP/Vista) operating systems. The OS will detect the FireSide presence and load the appropriate drivers automatically. Drivers for Linux® and MacOS® are also available.

i e e e 1 3 9 4 C a r d S


i e e e 1 3 9 4 C a r d S

1394 PC OEM Card

F e a t u r e S

n LSI Inc. FWA323 1394 Host Controller PCA.

n 1394a 400 Mbits/s, 3 ports, OHCI 1.0, Power Management 1.1.

n PCI 2.1s 32 bit, 33 MHz, 3.3 V powered.

n 2 external 1394 6-pin rear connectors. Options for internal 1394 connection.

n Optional 1394 bus power provides up to 15 W.

n Single chip reliability with LSIFW323 integrated PHY/Link.

n Short card form factor.

n MS Windows® compatible including DV and SBP-2 drivers, supports all common camcorders, disk drives, printers and scanners with 1394 interfaces.

n Compatible with leading video editing applications, including MGI VideoWave II, III,and IV® and Ulead VideoStudio5®.

n WHQL certified.

n FCC, UL® approved.


M o d e M - P C

Product Brief

SV92EXPCI-Express Soft Modem

F e a t u r e S

n Two-chip, single-lane PCI-Express soft modem solution with an integrated interface that supports the PCI-Express revision 1.1 standard:

— SV92EX host interface in a 32-pin MLCC.

— CSP1040 DAA in a 20-pin TSSOP.

n Data mode capabilities:

— ITU-T ™ V.92*: 56000 bits/s—28000 bits/s.

— ITU-T V.90*: 56000 bits/s—28000 bits/s.

— ITU-T V.34: 33600 bits/s—2400 bits/s.

— V.32bis and fallbacks.

— V.44, V.42, V.42 bis, and MNP ™ - Class 5 data compression.

— High compression throughput due to parallel access directly to the host PC.

n FAX mode capabilities:

— ITU-T T.31 class 1 FAX.

— ITU-T V.17: 14400 bits/s, 12000 bits/s, 9600 bits/s, 7200 bits/s (TCM).

— ITU-T V.29: 9600 bits/s, 7200 bits/s (QAM).

— ITU-T V.27ter: 4800 bits/s, 2400 bits/s (DPSK).

— ITU-T V.21 Channel 2: 300 bits/s (FSK).

n CSP1040:

— System-powered.

— Proprietary isolation barrier.

— Programmable event detect for caller-ID reception and power ring detection.

— Programmable pulse shaping and spark quench.

— Programmable dc-impedance termination for country-specific VI templates.

— Programmable ac-impedance termination for return-loss matching.

— Programmable ringer-impedance emulation.

n Hardware support for pulse dialing for accurate make/break timing.

n Wake-on-ring and caller ID support.

n Common driver across multiple platforms.

The SV92EX chip set using LSI’s third-generation silicon DAA is a soft modem solution for PCI-Express applications. The chip set works with LSI’s standard soft modem drivers and supports V.92 and lower rates.

The CSP1040 device is LSI’s third-generation

silicon DAA, which reduces the number of

components and board area required to imple-

ment a full-featured modem, while achiev-

ing compliance with worldwide regulatory

requirements. A low-profile digital transformer

provides the communications link between the

CSP1040 and SV92EX devices. This digital link

also provides power to the CSP1040, allowing

full operation on marginal phone lines.

The CSP1040 includes hardware support for

detecting line-in-use status, overcurrent, polar-

ity reversals, caller ID, and ringing, without

the need for additional external circuitry. This

allows for full-featured modem designs without

increased bill-of-materials or board space.

* Actual speeds over U.S. telephone lines vary and are less than 56K due to current FCC regulations and line conditions.

o P e r a t i n g S y S t e M S u P P o r t

n Windows ® 98, Windows 2000, Windows ME ®, and Windows XP 32/64-bit Editions, Windows VISTA 32/64-bit Editions

n Microsoft Designed for Windows logo device requirement compliant


M o d e M - P C

SV92A3HDA/AC97 Soft Modem

F e a t u r e S

n Two-chip HDA/AC97 soft modem solution: — SV92A3 host interface in a 16-pin TSSOP (3.3v only), or — SV92A35 host interface in a 16-pin TSSOP (1.5v or 3.3v), and — CSP1040 DAA in a 20-pin TSSOP.

n Data mode capabilities: — ITU-T ™ V.92: 56000 bits/s—28000 bits/s. — ITU-T V.90: 56000 bits/s—28000 bits/s. — ITU-T V.34: 33600 bits/s—2400 bits/s. — V.32bis and fallbacks. — V.44, V.42, V.42 bis, and MNP ™ Class 5 data compression. — High compression throughput due to parallel access directly to the host PC.

n FAX mode capabilities: — ITU-T T.31 class 1 FAX. — ITU-T V.17: 14400 bits/s, 12000 bits/s, 9600 bits/s, 7200 bits/s (TCM). — ITU-T V.29: 9600 bits/s, 7200 bits/s (QAM). — ITU-T V.27ter: 4800 bits/s, 2400 bits/s (DPSK). — ITU-T V.21 Channel 2: 300 bits/s (FSK).

n AC’97 bus interface: — AC’97 specification 2.3 compliant. — Configurable for secondary device 1 or 2.

n HD Audio bus interface: — HD Audio specification 1.0 compliant. — 1.5v or 3.3v signalling

n Hardware support for pulse dialing.


n Single 3.3 V power supply.

n CSP1040: — System-powered. — Proprietary transformer-based isolation barrier. — Programmable event detect for caller-ID reception and power ring detection. — Programmable pulse shaping and spark quench. — Programmable dc-impedance termination for country-specific VI templates. — Programmable ac-impedance termination for return-loss matching. — Programmable ringer-impedance emulation.

The SV92A3 chip set using LSI’s CSP1040 silicon DAA is a soft-modem solution for AC’97 and HD Audio applications. The chip set works with LSI’s standard soft modem drivers and supports V.92 and lower rates. The SV92A3 chip set enables modem designs with lowest parts count and minimum board area, creating the best possible solution for MDC 1.0/1.5 and modem-on-motherboard applications.

The SV92A3 device provides a dual-mode

AC’97 and HD Audio interface with automatic

mode detection. The SV92A3 is available

in a 16-pin TSSOP package. A new version

(SV92A35) is also available that supports 1.5v

as well as 3.3v signalling. The SV92A3 includes

logic to provide robust ring detection and

qualification eliminating unintended wake-

on-ring events due to activity on the phone

line other than ringing. The SV92A3 also

handles pulse dial timing control in hardware

to eliminate system timing dependencies

common with earlier soft modem products.


silicon DAA and reduces the number of

components and board area required to

implement a full-featured modem, while

achieving compliance with worldwide

regulatory requirements. A low-profile digital

transformer provides the communications link

between the CSP1040 and SV92A3 devices. This

digital link also provides power to the CSP1040,

allowing full operation on even marginal

phone lines that caused problems with earlier

generation silicon DAAs. The CSP1040 includes

hardware support for detecting line-in-use

status, overcurrent, polarity reversals, caller ID,

and ringing, without the need for additional

external circuitry. This allows for full-featured

modem designs without increased bill-of-

materials or board.


M o d e M - P C

SV92U2USB Soft Modem

F e a t u r e S

n Two-chip, USB 2.0-compliant soft modem solution: — SV92U2 host interface in a 48-pin TQFP. — CSP1040 DAA in a 20-pin TSSOP.

n USB 2.0 compliant device controller: — Supports high-speed (480 Mbits/s and full-speed (12 Mbits/s) data rates. — Integrated high-/full-speed USB transceivers. — Bus-powered USB — 2 Kbytes USB FIFO memory.

n Data mode capabilities: — ITU-T ™ V.92*: 56000 bits/s—28000 bits/s. — ITU-T V.90*: 56000 bits/s—28000 bits/s. — ITU-T V.34: 33600 bits/s—2400 bits/s. — V.32bis and fallbacks— V.44, V.42, V.42 bis, and MNP ™ Class 5 data compression. — High compression throughput due to parallel access directly to the host PC.

n FAX mode capabilities: — ITU-T T.31 class 1 FAX. — ITU-T V.17: 14400 bits/s, 12000 bits/s, 9600 bits/s, 7200 bits/s (TCM). — ITU-T V.29: 9600 bits/s, 7200 bits/s (QAM). — ITU-T V.27ter: 4800 bits/s, 2400 bits/s (DPSK). — ITU-T V.21 channel 2: 300 bits/s (FSK).

n CSP1040: — System-powered. — Digital transformer-based isolation barrier. — Programmable event detect for caller-ID reception and power ring detection. — Programmable pulse shaping and spark quench — Programmable dc-impedance termination for country-specific VI templates. — Programmable ac-impedance termination for return-loss matching. — Programmable ringer-impedance emulation.

n Serial EPROM support for optional vendor ID information. May be eliminated to recover cost.

The SV92U2 chip set using LSI’s third-generation silicon DAA is a soft modem solution for both high-speed (480 MHz) and full-speed (12 MHz) USB2.0 applica-tions. The chip set works with LSI’s standard soft modem drivers and supports V.92 and lower rates.

The SV92U2 is available in a 48-pin TQFP

package. The SV92U2 includes logic to provide

robust ring detection and qualification elimi-

nating unintended wake-on-ring events due to

activity on the phone line other than ringing.

The SV92U2 also handles pulse dial control in

hardware to eliminate system timing depen-

dencies common with earlier soft modem

products.


silicon DAA and reduces the number of compo-

nents and board area required to implement a

full-featured modem, while achieving compli-

ance with worldwide regulatory requirements.

A low-profile digital transformer provides the

communications link between the CSP1040

and SV92U2 devices. This digital link also

provides power to the CSP1040, allowing full

operation on even marginal phone lines. The

CSP1040 includes hardware support for detect-

ing line-in-use status, overcurrent, polarity re-

versals, caller ID, and ringing, without the need

for additional external circuitry. This allows for

full-featured modem designs without increased

bill-of-material or board space.


M o d e M - P C

SV92PPPCI Soft Modem

F e a t u r e S

n Two-chip PCI soft modem solution with an integrated 5 V tolerant interface that supports the PCI revision 2.3 standard: — SV92PP host interface in a 68-pin MLCC. — CSP1040 DAA in a 20-pin TSSOP.

n Data mode capabilities: — ITU-T ™ V.92*: 56000 bits/s—28000 bits/s. — ITU-T V.90*: 56000 bits/s—28000 bits/s. — ITU-T V.34: 33600 bits/s—2400 bits/s. — V.32bis and fallbacks. — V.44, V.42, V.42 bis, and MNP ™ Class 5 data compression. — High compression throughput due to parallel access directly to the host PC.

n FAX mode capabilities: — ITU-T T.31 class 1 FAX. — ITU-T V.17: 14400 bits/s, 12000 bits/s, 9600 bits/s, 7200 bits/s (TCM). — ITU-T V.29: 9600 bits/s, 7200 bits/s (QAM). — ITU-T V.27ter: 4800 bits/s, 2400 bits/s (DPSK). — ITU-T V.21 Channel 2: 300 bits/s (FSK).

n CSP1040: — System-powered. — Proprietary isolation barrier. — Programmable event detect for caller-ID reception and power ring detection. — Programmable pulse shaping and spark quench. — Programmable dc-impedance termination for country-specific VI templates. — Programmable ac-impedance termination for return-loss matching. — Programmable ringer-impedance emulation.



n Common driver across multiple platforms.

The SV92PP chip set using LSI’s third-generation silicon DAA is a soft modem solution for PCI applications. The chip set works with LSI’s standard soft modem drivers and supports V.92 and lower rates.


silicon DAA, which reduces the number of


implement a full-featured modem, while




between the CSP1040 and SV92PP devices. This


allowing full operation on marginal phone lines.


detecting line-in-use status, overcurrent,

polarity reversals, caller ID, and ringing, without

the need for additional external circuitry. This

allows for full-featured modem designs without

increased bill-of-materials or board space.


M o d e M - e M B e d d e d d a t a

CV22AV.22bis Modem Chipset for Low Speed Data Applications

F e a t u r e S

n Two-chip controller-based modem solution:

– CV22A modem device in a 24-pin ETSSOP or 48-pin TQFP.

– CSP1040 data access arrangement (DAA) in a 20-pin ETSSOP.

n Data-mode capabilities:

– ITU-T V.29 fast connect: 9600 bits/s, 7200 bits/s for point of sale (POS).

– ITU-T V.22 fast connect: 2400 bits/s. (for POS)

– ITU-T V.22bis: 2400 bits/s.

– ITU-T V.23: 1200/75 bits/s.

– ITU-T V.21: 350 bits/s.

– Bell 212A: 1200 bits/s.

– Bell 103: 300 bits/s.

– MNP™ 2-4 error correction.

– SDLC/HDLC for POS applications.

n RS232 asynchronous serial data terminal equipment (DTE). interface with rates to 230.4K bits/s.

n CSP1040 features:

– System powered.

– Type I caller-ID support.

– Remote handset detection.

– Line-in-use detection.

– Digital transformer-based isolation barrier.

The CV22A Modem Chipset is designed to serve embedded applications that require lower- speed dial-up data connections. These applications include: digital tv, set-top boxes, point of sale (POS), alarm systems, remote monitoring, and other telemetry applications.

The CV22A chip set includes the LSI CV22A

modem device and LSI CSP1040 silicon data

access arrangement (DAA), thereby providing

a complete V.22bis controller-based modem.

The CV22A device incorporates an ARM7

microcontroller for AT command processing,

modem protocols, and data modulation tasks.

It provides an RS232 serial host (system side)

interface as well as an interface to the CSP1040

(DAA side).


silicon DAA. It reduces the number of


implement a full-featured modem while




between the CSP1040 and CV22A devices. This


allowing full operation on even marginal phone

lines. The CSP1040 includes hardware support

for detecting line-in-use status, overcurrent,

polarity reversals, caller ID, and ringing without

additional external circuitry. This allows for

full-featured modem designs without increased

bill-of-material (BOM) or board space.

LSI CV22A-T48

CV22A- E24

LSI CV22A-T48

CV22A- E24

Actual Size


CV92, CV90, CV34 and CV22Controller-Based Modem Devices

F e a t u r e S

n Two-chip modem solution:

— CVxx Modem Device in 48-pin TQFP or 100-pin FSBGA (CV92-F100 only)

— CSP1040 DAA in 20-pin ETSSOP

n Data mode capabilities:

— V.92, V.90, V.34, V.32bis, V.32

— V.22bis, V.22. V.21

— Bell 212A, Bell 103

— V.17 and lower fax rates

— V.44, V.42bis, MNP 5 Data Compression

— V.42, MNP 2–4 Error Correction

n CVxx Modem Device features:

— ARM7TDMS Microcontroller

— DSP1600S Digital Signal Processor

— DAA interface and filters

— Host interface configurable for 8-bit parallel, asynchronous serial or SPI mode

— On-chip PWM speaker driver

— SIO interface for audio codec used in voice and handset applications

— 24.576 MHz crystal or external 27.0 MHz clock CSP1040 DAA features:

— Derives power from system for reliable operation on all phone lines

— Digital transformer isolation barrier

— Programmable event detect for caller-ID reception and power ring detection

— Programmable pulse shaping and spark quench

— Programmable dc-impedance termination for country-specific VI templates

— Programmable ac-impedance termination for return loss matching

— Programmable ringer-impedance emulation


n Hardware support for ringing level and frequency qualification for accurate ring detection.

n Line-in-use and remote handset detection

n Single 3.3V supply required for chip set.

n World-wide caller ID support

The CVxx family of devices is designed to serve embedded applications that require high-speed dial-up data connections. There are several versions available based on modulations and other features. For designs that must support field-upgradeability or customized features, a version of the CV92 device is available in a 100 FSBGA that can support external flash ROM. All other versions run from on-chip ROM. The table on page 2 shows the features supported for the various versions.

The CVxx devices support RS232 and 8-bit mi-

croprocessor interfaces. Additionally, the CVxx

devices can be configured for operation on a

4-wire SPI bus.

Figure 1 shows a reference design using the 48-

pin CVxx and the CSP1040. This is a 2-layer PCB

with components on top-side only. The layout

can be integrated into a larger PCB or built as a

separate module with connectors.

Typical applications include point-of-sale ter-

minals, TV set-top-box, gaming consoles, video

phones, alarm systems, remote monitoring and

other telemetry applications.

Figure 1. “Pisa” Embedded Modem Module

(shown approximately actual size when printed on 8.5” x 11” paper.)

M o d e M - e M B e d d e d d a t a


M o d e M S - e M B e d d e d F a x

CFAX34 and CFAX17FAX Modem Devices

F e a t u r e S


— CFAXxx modem in 48-pin TQFP or 100 FSBGA with external memory interface.

— CSP1040 DAA in 20-pin ETSSOP.n FAX mode capabilities:

— ITU-T T.31 (FAX class 1) interface.

— ITU-T T.32 (FAX class 2.1) interface.

— V.34: 33600—2400 bits/s (CFAX34 only).

— V.17: 14400—2400 bits/s.

— V.29, V.27, V.21.

— ECM with on-chip 64 Kbytes buffer.

n CFAX modem controller includes:

— ARM7 microcontroller with on-chip RAM and ROM.

— DP3S with on-chip RAM and ROM.

— DAA interface and filters.

— Host interface configurable for 8-bit parallel, serial, or SPI mode.

— On-chip PWM speaker driver.

— SIO interface for audio codec used in voice and handset applications.

— Internal PLL with external low-cost crystal.

n CSP1040 DAA features:

— Derives power from system for reliable operation on all phone lines.

— Programmable event detect for caller-ID reception and power ring detection.

— Programmable pulse shaping and spark quench.

— Programmable dc-impedance termination for country-specific VI templates.

— Programmable ac-impedance termination for return-loss matching.

— Programmable ringer-impedance emulation.



n Line-in-use and remote handset detection.n Single 3.3 V supply required for chip set.

n Worldwide caller ID support.

The CFAX family of devices is designed to serve embedded applications where a complete FAX subsystem including protocol processing is desired. The CFAX family includes two devices:

n CFAXV34. Supports V.34, V.17, V.29, and lower

FAX rates.

n CFAXV17. Supports V.17, V.29, and lower

FAX rates.

The CFAX devices support RS232 and 8-bit

micro-processor interfaces. Additionally, the

CFAX devices can be configured for operation

on a 4-wire SPI bus. Figure 1 shows a reference

design using the 48-pin CFAX and the CSP1040.

This is a 2-layer PCB with components on top-

side only. The layout can be integrated into a

larger PCB or built as a separate module with

connectors.

t y P i C a l a P P l i C a t i o n S

n FAX machines

n Multifunction printers (MFPs)

n Multiport FAX servers

Figure 1 shows a typical application using a CFAX34 modem controller along with a CSP1040 silicon

DAA to add FAX capability to a system.



DP3VxxFamily of Data Pump Devices

F e a t u r e S


— DP3xx data pump in 48-pin TQFP

— CSP1040 DAA in 20-pin ETSSOP

n FAX mode capabilities:

— V.34: 33600—2400 bits/s (DP3V34X only)

— V.17: 14400—2400 bits/s

— V.29: 9600, 7200 bits/s

— V.27ter: 4800, 2400 bits/s

— V.21 ch 2: 300 bits/s

n DP3 data pump includes:

— Digital signal processor

— DAA interface and filters

— Host interface configurable for 8-bit parallel or SPI mode

— On-chip PWM speaker-driver

— SIO interface for audio codec used in voice and handset applications

n CSP1040 DAA features:

— Derives power from system for reliable operation on all phone lines

— Programmable event detect for caller-ID reception and power ring detection

— Programmable pulse shaping and spark quench

— Programmable dc-impedance termination for country-specific VI templates

— Programmable ac-impedance termination for return-loss matching

— Programmable ringer-impedance emulation



n Line-in-use and remote handset detection.

n Single 3.3 V supply required for chip set.

n Worldwide caller ID support.

The DP3 family of devices is designed to serve embedded applications where a separate modem microcontroller is not required—e.g., where a suitable system controller is already available to perform protocol processing. The DP3 family includes two devices:

n DP3V34X. Supports V.34/V.17/V.29 (and

lower) fax rates for fax-only applications.

n DP3V17X. Supports V.17/V.29 fax modes, as

well as V.32 and lower data rates.

The DP3xx devices support an 8-bit micropro-

cessor interface similar to earlier DP2 devices.

Additionally, the DP3 devices can be config-

ured for operation on a four-wire SPI bus.

The DP3 devices are used in conjunction with

the CSP1040 DAA. The CSP1040 device is

LSI’s third-generation silicon DAA. It reduces

the number of components and board area

required to implement a full-featured modem,

while achieving compliance with worldwide


pulse transformer provides the communica-

tions link between the CSP1040 and DP3

devices. This digital link also provides power

to the CSP1040, allowing full operation on all

phone lines.


detecting line-in-use status, overcurrent, polar-

ity reversals, and caller ID, as well as for ringing

without the need for additional external

circuitry. This allows for fullfeatured modem

designs without increased bill-of- material or

board space.

Figure 1. DP3V with T38 Audio Codec


LSI SFAX34-T48

LSI SFAX34

-M24


SFAX34/SFAX17 Soft FAX Modem for Embedded Products

F e a t u r e S

nSFAX34 and SFAX17 devices for V.34 and V.17 FAX solutions

n 24-pin MLCC production package

– 48-pin TQFP for backward compatibility to DP3/CFAX

n DTE interface:

– Serial Peripheral Interface (SPI)

n Single 3.3V supply with 5V tolerant I/O

n Supports all CSP1040 features and allows a single world-wide hardware design

n LSI Soft FAX modem supports:

– V.34 and lower Fax rates

– T.32 Command Set (T.30 w/ECM)

– World-wide caller ID

– Handset, speakerphone and TAM (with T38 audio codec)

– Supports proprietary OS’s with RTOS- independent architecture

SFAX is a family of chips that are designed to support soft embedded FAX applications for MFP and FAX machine. The family includes two devices:

n SFAX34: Soft embedded V.34 FAX chipset

n SFAX17: Soft embedded V.17 FAX chipset

The SFAX devices support a SPI interface which

provides the interface between the embedded

processor and the modem chip set. It provides

interfaces to the CSP140 Codec, the T38

voice codec for handset and speakerphone

applications and the call progress speaker

circuit.

The chipset would be used in conjunction with

Soft Modem code running on the System’s

embedded processor to implement the

complete FAX function including modulation

speeds up to V.34 and the T.30 protocol stack.

LSI SFAX34-T48

LSI SFAX34

-M24

Figure 1. SFAX System Block Diagram

Soft FAX Modem Stack running on SoC

SPI

To UNF

LSI CSP1040

LSI T38

LSI CSP1040

Actual Size


v o i C e P r o d u C t S

FX1000/FX1041FXO for Voice over IP Applications

F e a t u r e S

n FX1000 plus FX1041 implements complete Foreign Exchange Office (FXO) functionality

n 24-pin MLCC (4 x 4 mm) FX1000 package

n SoC interface (compatible with other Foreign Exchange Subscriber (FXS) and FXO devices):

– Serial Peripheral Interface (SPI) for control

– Time-division multiplexed (TDM) interface for data (up to 8.192 MHz)

n Single 3.3-V supply with 5-V-tolerant I/O

n No external crystal required (uses TDM clock)

n System-powered solution

n Greater than 4KV Isolation

n Single programmable solution for worldwide support

n Overcurrent Protection

n Line snooping

n Supports multiple interrupt events

n FXO functionality:

– Highest voice quality with low noise (16-bit linear codec w/ >80 dB dynamic range)

– Ring detect

– Support for Type I and Type II caller ID

– General-purpose I/O (GPIO) interface to support ground start applications

– FXO call-disconnect detection on loop start lines

– Hardware support for pulse dialing

The FX1000, when used with the FX1041 line-side codec, provides all of

the functionality required to implement an FXO for Voice over IP (VoIP)

applications. The FX1000 provides the interface to the VoIP SoC through

its TDM interface (for data) and SPI bus (for control), and an interface to the

FX1041 Line-side codec through a high-voltage isolation barrier.

Actual Size

LSI FXO1000-

M24

LSI FX1041-E11

LSI FXO1000-

M24

LSI FX1041-E11


e t h e r n e t P r o d u C t S

ET1011CTruePHY™ Gigabit Ethernet Transceiver

F e a t u r e S

n 10Base-T, 100Base-TX, and 1000Base-T Gigabit Ethernet transceiver: — 0.13 µm CMOS process — 84-pin MLCC: • RGMII, GMII, MII, RTBI, and TBI interfaces to MAC or switch — 68-pin MLCC: RGMII and RTBI interfaces to MAC or switch

n Low power consumption: — Typical power less than 750 mW in 1000Base-T mode — Advanced power management — ACPI compliant wake-on-LAN support

n Oversampling architecture to improve signal integrity and SNR

n Optimized, extended performance echo and NEXT filters

n All-digital baseline wander correction

n Digital PGA control

n On-chip diagnostic support

n Automatic speed negotiation

n Automatic speed downshift

n Single supply 3.3 V or 2.5 V operation: — On-chip regulator controllers — 3.3 V or 2.5 V digital I/O — 3.3 V tolerant I/O pins (MDC, MDIO, COMA, RESET_N, and JTAG pins) — 1.0 V or 1.1 V core power supplies — 1.8 V or 2.5 V for transformer center tap

n JTAG

n ET1011C is a pin-compatible replacement for the ET1011 device

n Commercial and industrial temperature versions available.

The LSI ET1011C is a Gigabit Ethernet transceiver fabricated on a single CMOS chip. Packaged in either a 128-pin TQFP, an 84-pin MLCC, or a 68-pin MLCC, the ET1011C is built on 0.13 µm technology for low power consumption and application in server and desktop NIC cards. It features single power supply operation using on-chip regulator controllers. The 10/100/1000Base-T device is fully compliant with IEEE ® 802.3, 802.3u and 802.3ab standards.

The ET1011C uses an oversampling architec-

ture to gather more signal energy from the

communication channel than possible with

traditional architectures. The additional signal

energy or analog complexity transfers into the

digital domain. The result is an analog front end

that delivers robust operation, reduced cost,

and lower power consumption than traditional

architectures.Using oversampling has allowed

for the implementation of a fractionally spaced

equalizer, which provides better equalization

and has greater immunity to timing jitter,

resulting in better signal-to-noise ratio (SNR),

and thus improved BER. In addition, advanced

timing algorithms are used to enable operation

over a wider range of cabling plants.

For more information and sales office locations, please visit the LSI web sites at: lsi.com lsi.com/contacts

LSI and the LSI logo are trademarks or registered trademarks of LSI Corporation.

All other brand and product names may be trademarks of their respective companies. LSI Corporation reserves the right to make changes to any products and services herein at any time without notice. LSI does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by LSI; nor does the purchase, lease, or use of a product or service from LSI convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI or of third parties.

Copyright ©2009 by LSI Corporation. All rights reserved. May 2009PR

Documents

LSI Product Selector Guide Rev Jan10 FIN