LS TTL Data

7/31/2019 LS TTL Data

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LS

Formerly Titled FAST and LS

Re

Please Note: As ON Semiconductor has exited the FAST TTL business, all FAST data sheets have been removepublication. For further assistance, please contact your local ON Semiconductor representative.


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CONTENTS

CHAPTER 1 SELECTION INFORMATION, LS TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 2 CIRCUIT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Family Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LS TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Circuit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AC Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LS ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 3 DESIGN CONSIDERATIONS, TESTING AND APPLICATIONS ASSISTANCE FORMDESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Fan-In and Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Wired-OR Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Line Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Output Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Interconnection Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DEFINITION OF SYMBOLS AND TERMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AC Switching Parameters and Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TESTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DC Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AC Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

APPLICATIONS ASSISTANCE FORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 4 DATA SHEETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 5 RELIABILITY DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RAP Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 6 PACKAGE INFORMATION INCLUDING SURFACE MOUNT . . . . . . . . . . . . . . . . . . . . . . . .Surface Mount Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tape and Reel Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Worldwide Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Document Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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Device Description

SN74LS00 Quad 2-Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS04 Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS05 Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS08 Quad 2-Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS14 Schmitt Triggers Dual Gate/Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS32 Quad 2-Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS38 Quad 2-Input NAND Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS42 One-of-Ten Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS47 BCD to 7-Segment Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74LS74A Dual DType Positive EdgeTriggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74LS76A Dual JK Flip-Flop with Set and Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74LS85 4-Bit Magnitude Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS86 Quad 2Input Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS109A Dual JK Positive Edge-Triggered Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS122 Retriggerable Monostable Multivibrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS125A Quad 3-State Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS132 Quad 2-Input Schmitt Trigger NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS138 1-of-8 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS139 Dual 1-of-4 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS145 1-of-10 Decoder/Driver Open-Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS147 10-Lineto4Line and 8-Lineto3Line Priority Encoders . . . . . . . . . . . . . . . . . . . . .SN74LS151 8-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS153 Dual 4-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS156 Dual 1-of-4 Decoder/Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS157 Quad 2-Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS161A BCD Decade Counters/4Bit Binary Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS164 Serial-In ParallelOut Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS165 8-Bit Parallel-To-Serial Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74LS166 8-Bit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74LS174 Hex D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74LS175 Quad D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS193 Presettable 4Bit Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS194A 4-Bit Bidirectional Universal Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74LS195A Universal 4-Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS221 Dual Monostable Multivibrators with SchmittTrigger Inputs . . . . . . . . . . . . . . . . . . . .SN74LS240 Octal Buffer/Line Driver with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74LS245 Octal Bus Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS247 BCDtoSevenSegment Decoders/Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS251 8-Input Multiplexer with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74LS253 Dual 4-Input Multiplexer with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS257B Quad 2-Input Multiplexer with 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS259 8-Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74LS260 Dual 5-Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SN74LS273 Octal D Flip-Flop with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS280 9-Bit Odd/Even Parity Generators/Checkers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SN74LS283 4-Bit Binary Full Adder with Fast Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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CHSelection Infor


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GENERAL INFORMATIONTTL in Perspective

Since its introduction, TTL has become the most popular

form of digital logic. It has evolved from the originalgold-doped saturated 7400 logic, to Schottky-Clampedlogic, and finally to the modern advanced families of TTLlogic. The popularity of these TTL families stem from theirease of use, low cost, medium-to-high speed operation, andgood output drive capability.

Low Power Schottky (LSTTL) was the industry standardlogic family for many years. Since its inception, severalmore modern families have come out, with equal or better

performance. We therefore recommend

Speed and FACT products for all new Further improvements in power reductiousing the LVX, LCX or VCX runnImprovements in electrostatic dischargethese newer CMOS products now make thneed for LSTTL in new designs. The VHand lower power with similar drivcompared to LSTTL. We highly recommuse one or more of these CMOS families

TTL Family Comparisons

General Characteristics for Schottky TTL Logic (All Maximum Ratings)

Characteristic Symbol 74LSxxx Unit

Operating Voltage Range V CC 5 5% Vdc

Operating Temperature Range T A 0 to 70 C

Input Current I IH 20

IN IIL 400

Output Drive I OH 0.4 mA

Standard Output I OL 8.0 mA

ISC 20 to 100 mA

IOH 15 mA

Buffer Output I OL 24 mA

ISC 40 to 225 mA

Speed/Power Characteristics for Schottky TTL Logic (1)(All Typical Ratings)

Characteristic Symbol Typ Unit

Quiescent Supply Current/Gate I G 0.4 mA

Power/Gate (Quiescent) P G 2.0 mW

Propagation Delay t p 9.0 ns

Speed Power Product 18 pJ

Clock Frequency (D-F/F) f max 33 MHz

Clock Frequency (Counter) f max 40 MHz

NOTES: 1. Specifications are shown for the following conditions:NOTES: 1. a) V CC = 5.0 Vdc (AC),NOTES: 1. b) TA = 25 C,NOTES: 1. c) C L = 15 pF.


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Functional Selection

Abbreviations

S = SynchronousA = AsynchronousB = Both Synchronous and Asynchronous

2S = 2-State Output3S = 3-State OutputOC = Open-Collector Output

Inverters

DescriptionType ofOutput No.

Hex 2S 04OC 05

AND Gates


Quad 2-Input 2S 08

NAND Gates


Quad 2-Input 2S 00

OR Gates


Quad 2-Input 2S 32

NOR Gates


Dual 5-Input 2S 260

Exclusive OR Gates


Quad 2-Input 2S 86

Schmitt Triggers


Hex, Inverting 2S 14

Multiplexers

Description

Quad 2-to-1, Non-Inverting

Quad 2-to-1, InvertingDual 4-to-1, Non-Inverting

8-to-1

Encoders

Description

10-to-4-Line BCD8-to-3-Line Priority Encoder

Register Files

Description

4 x 4

Decoders/Demultiplexers

Description

Dual 1-of-4

1-of-81-of-10

Latches

DescriptionNo. ofBits

Transparent, Non-Inverting 8Addressable 8


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Shift Registers

No. of Type of Mode*

Description

Bits

Output SR SL Hold

Serial In-Parallel Out 8 2S XParallel In-Serial Out 8 2S X X

8 2S X XParallel In-Parallel Out 4 2S X X X

4 2S XParallel In-Parallel Out, Bidirectional 8 3S X X X

* SR = Shift Right* SL = Shift Left

Asynchronous Counters Negative Edge-Triggered

Description Load Set Reset No.

Dual 4-Bit Binary X 393 *

* The 716 and 718 are positive edge-triggered.

Display Decoders/Drivers with Open-CollectorOutputs

Description No.

1-of-10BCD-to-7 Segment

145 *247 *

Cascadable Synchronous Counters Positive Edge-Triggered

DescriptionType ofOutput Load

4-Bit Binary 2S2S

SS

MSI Flip-Flops/Registers

DescriptionNo. ofBits

Type ofOutput

Set orReset

D-Type, Non-Inverting 4688

2S2S2S3S

AA

D-Type, Q and Q Outputs 4 2S A

Arithmetic OperatorsDescription No.

4-Bit Adder 283

Magnitude Comparators

DescriptionType ofOutput P = Q P >Q P


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CHCircuit Characte


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CIRCUIT CHARACTERISTICS

FAMILY CHARACTERISTICSLS TTLThe Low Power Schottky (LS TTL) family combines a

current and power reduction improvement over standard7400 TTL by a factor of 5. This is accomplished by usingSchottky diode clamping to prevent saturation and advancedprocessing.

CIRCUIT FEATURESCircuit features of the LS are be

examining the TTL 2-input NAND gate LS has been a popular series in the paproducts such as VHC should be replacidesigns. For applications where high FACT is an ideal choice.

110

Q4

OUTPUT

Q3

3.5K

15KD4B

AD3D1

7.6K

Q2

5K

Q1Q5

18K

D2

2.8K

Figure 1. LS00 2-Input NAND Gate

VCC


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INPUT CONFIGURATIONON Semiconductor LSTTL circuits do not use the

multi-emitter input structure that originally gave TTL itsname. Most LS elements use a DTL type input circuit withSchottky diodes to perform the AND function, asexemplified by D3 and D4 in Figure 1. Compared to theclassical multi-emitter structure, this circuit is faster andincreases the input breakdown voltage. Inputs of this typeare tested for leakage with an applied input voltage of 7.0 Vand the input breakdown voltage is typically 15 V or more.

Another input arrangement often used in LS MSI has threediodes connected as shown in Figure 2. This configurationgives a slightly higher input threshold than that of Figure 1.A third input configuration that is sometimes used in LSTTL employs a vertical PNP transistor as shown in Figure 3.This arrangement also gives a higher input threshold and has

the additional advantage of reducing the that the signal source must sink. Both arrangement and the PNP input cobreakdown voltage ratings greater than 7

All inputs are provided with exemplified by D1 and D2 in Figure 1. Thewhen an input signal goes negative, whichand helps to control ringing on long signa HIGH-to-LOW transition. These diodesfor the suppression of transient currents used as steady-state clamps in interfacclamp current exceeding 2.0 mA and withthan 500 ns can activate a parasitic laterawhich in turn can steal current from interncircuit and thus cause logic errors.

VCC

Figure 2. Diode Cluster Input Figure 3. PNP Input

INPUT CHARACTERISTICSFigure 4 shows the typical input characteristics of LS.

Typical transfer characteristics can be found in Figure 5 andinput threshold variation with temperatuprovided in Table 1.

0

100

200

300

400

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20

1

2

3

4

5

0.5 1 1.5

LS

LS

VIN(VOLTS) VIN, INPUT VOLTAGE

I I N

( A )

V O U T ,

O U T P U T V O L T A G E ( V O L T S )

Figure 4 Typical Input Current Figure 5 Typical Output versus Inp

TA = 25 CVCC = 5 V


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OUTPUT CONFIGURATIONThe output circuitry of LSTTL has several features not

found in conventional TTL. A few of these features arediscussed below.

Referring to Figure 1, the base of the pull-down outputtransistor Q5 is returned to ground through Q3 and a pair of resistors instead of through a simple resistor. Thisarrangement is called a squaring network since it squares upthe transfer characteristics (Figure 5) by preventingconduction in the phase splitter Q1 until the input voltagerises high enough to allow Q1 to supply base current to Q5.The squaring network also improves the propagation delayby providing a low resistance path to discharge capacitanceat the base of Q5 during turn-off.

The output pull-up circuit is a 2-transistor Darlingtoncircuit with the base of the output transistor returned through

a 5.0K resistor to the output terminals, unwhere it is returned to ground which consuming configuration. This configuoutput to pull up to one V

BEbelow V

output current.Figure 6 shows the extra circuitry u

high Z condition in 3-state outputs. Enable signal is HIGH, both the phasDarlington pull-up are turned off. In toutput circuitry is non-conducting, which of two or more such circuits to be connecteapplication wherein only one output iparticular time.

VCC

OUTPUT

Q5ACTIVE

PULLDOWN

FROMLOGIC

Figure 6. Typical 3-State Output Control

OUTPUTENABLE

OUTPUT CHARACTERISTICSFigure 7 shows the LOW-state output characteristics for

LS. For LOW I OL values, the pull-down transistor isclamped out of deep saturation to shorten Figure 8 shows the HIGH-state output ch

LS00LS240

1

0.50.5

1

V O L

, O U T P U T V O L T A G E ( V O L T S )

V O L


TA = 25 CVCC = 4.5 V

TA = 2VCC =


14/274

IOH, OUTPUT CURRENT (mA)

V O H


4

3

2

1

0 50 100 150

Figure 8. (a) Output High Characteristic

V O H


4

3

2

1

0

IOH, OUTPUT CURRE

50 100

Figure 8. (b) Output High Char

LS00

TA = 25 CVCC = 5.5 V

LS240

AC SWITCHING CHARACTERISTICSThe propagation through a logic element depends on

power supply voltage, ambient temperature, and outputload. The effect of each of these parameters on acpropagation is shown in Figures 9 through 11.

Propagation delays are specified with only one outputswitching, the delay through a logic-element will increase tosome extent when multiple outputs switch simultaneouslydue to inductance internal to the IC package.

For LS TTL, limits are guaranteed at 2and C L = 15 pF (normally, resistive load on propagation delay) TTL limits are gucommercial or military temperature an

ranges and with C L = 50 pF.

+4

+2

0

2

4 75 25 +25 +75 +125

t P D

, P R O P A G A T I O N D E L A Y C H A N G E ( n s

)

TA, AMBIENT TEMPERATURE (C)

Figure 9.

VCC = 5 VCL = 15 pFLS00

tPLH

tPHL

+4

+2

0

2

4 t P D

, P R O P A G A T I O N D E L A Y C H A N G E ( n s

)

4.5 4.75 5VCC, SUPPLY VOLTA

Figure 10.

tPLH

tPHL


15/274

20

16

12

8

4

200 40 60 80 100

t P D

, P R O P A G A T I O N D E L A Y ( n s

) VCC = 5 VTA = 25 CLS00

tPLH

tPHL

CL, LOAD CAPACITANCE (pF)

Figure 11. *

*Data for Figure 11 was taken with only one output switching at a time.

ESD CHARACTERISTICSElectrostatic Discharge (ESD) sensitivity for ON

Semiconductor TTL is characterized using severalmethodologies (HBM, MM, CDM). It is extremelyimportant to understand that ESD sensitivity values aloneare not sufficient when comparing devices. In an attempt toreduce correlation problems between various pieces of testequipment, all of which meet Mil-Std-883C requirements,tester specific information as well as actual device ESD

hardness levels are given in controlled davailable upon request. The continuing ESD sensitivity through redesigns of OTTL has resulted in minimum ESD leproducts and redesigns of >3500 volts fspecific values reference the following sp

LS: 12MRM 93831A


16/274

CHDesign Consider

Testing and Applications Assistance Form


17/274

DESIGN CONSIDERATIONS

NOISE IMMUNITYWhen mixing TTL families it is often desirable to know

the guaranteed noise immunity for both LOW and HIGHlogic levels. Table 2 lists the guaranteed logic levels forvarious TTL families and can be used to calculate noisemargin. Table 3 specifies these noise margins for systems

containing LS, S, and/or ALS TTL. Nrepresents worst case limits and assu

power supply and temperature variatiowhich are interconnected, as well as maxIncreased noise immunity can be achiewith decreased maximum allowable oper

Table 2.Worst Case TTL Logic Levels

Electrical Characteristics

Military (55 to +125 C) Commercial (0 to

TTL Families V IL VIH VOL VOH VIL VIH V

TTL Standard TTL 9000, 54/74 0.8 2.0 0.4 2.4 0.8 2.0 0.4HTTL High Speed TTL 54/74H 0.8 2.0 0.4 2.4 0.8 2.0 0.4LPTTL Low Power TTL 93L00 (MSI) 0.7 2.0 0.3 2.4 0.8 2.0 0.3STTL Schottky TTL 54/74S, 93S00 0.8 2.0 0.5 2.5 0.8 2.0 0.5LSTTL Low Power Schottky TTL 54/74LS 0.7 2.0 0.4 2.5 0.8 2.0 0.5ALS TTL (5% V CC ) Advanced LS TTL, 54/74ALS 0.8 2.0 0.5

(10% V CC ) 0.8 2.0 0.4 2.5 0.8 2.0 0.5

VOL and V OH are the voltages generated at the output V IL and V IH are the voltage required at the input to generate the approp

numbers given above are guaranteed worst-case values.

Table 3. (a)LOW Level Noise Margins (Commercial)

ToFrom LS S ALS Unit

LS 300 300 300 mVS 300 300 300 mVALS 300 300 300 mV

From V OL to VIL

Table 3. (b)HIGH Level Noise Margins (Com

ToFrom LS S

LS 700 700S 700 700

ALS (5% V CC ) 750 750ALS (10% V CC ) 500 500

From V OH to VIH

POWER CONSUMPTIONWith the exception of ECL, all logic families exhibit

increased power consumption at high frequencies. Caremust be taken when switching multiple gates at highfrequencies to assure that their combined dissipation doesnot exceed package and/or device capabilities. TTL devicesare more efficient at high frequencies than CMOS.

FANIN AND FANOUTIn order to simplify designing with O

TTL devices, the input and output loadingfamilies are normalized to the following v

1 TTL Unit Load (U.L.) = in the HIGH state (Logi

1 TTL Unit Load (U.L.) = in the LOW state (Logic


18/274

Input loading and output drive factors of all products described in this handbook are related to these definition

EXAMPLES INPUT LOAD1. A 7400 gate, which has a maximum I IL of 1.6 mA and I IH of 40 A is specified as having an inputU.L. (Also called a fan-in of 1 load.)

2. The 74LS95B which has a value of I IL = 0.8 mA and I IH of 40 A on the CP terminal, is specifiedinput LOW load factor of:

0.8 mA1.6 mA

and an input HIGH load factor of40 Aor 0.5 U.L. or 1 U.L.40 A

3. The 74LS00 gate which has an I IL of 0.4 mA and an I IH of 20 A, has an input LOW load factor o

0.4 mA1.6 mA

an input HIGH load factor of20 Aor 0.25 U.L. or 0.5 U.L.40 A

EXAMPLES OUTPUT DRIVE1. The output of the 7400 will sink 16 mA in the LOW (logic 0) state and source 800 A in the Hstate. The normalized output LOW drive factor is therefore:

16 mA

and the output HIGH drive factor is

1.6 mA= 10 U.L.

800 Aor 20 U.L.

40 A

2. The output of the 74LS00 will sink 8.0 mA in the LOW state and source 400 A in the HIGH staoutput LOW drive factor is:

8.0 mA

and the output HIGH drive factor is

1.6 mA= 5 U.L.

400 A

or 10 U.L.40 A

Relative load and drive factors for the basic TTL families are given in Table 4.

Table 4.

INPUT LOAD OUTPUT DRIVE

HIGH LOW HIGH LOW

74LS00 0.5 U.L. 0.25 U.L. 10 U.L. 5 U.L.

7400 1 U.L. 1 U.L. 20 U.L. 10 U.L.9000 1 U.L. 1 U.L. 20 U.L. 10 U.L.74H00 1.25 U.L. 1.25 U.L. 25 U.L. 12.5 U.L.74S00 1.25 U.L 1.25 U.L. 25 U.L. 12.5 U.L.74 ALS 0.5 U.L 0.0625 U.L 10 U.L. 5 U.L.

Values for MSI devices vary significantly from one element to another. Consult the appropriate data sheeth


19/274

WIREDOR APPLICATIONSCertain TTL devices are provided with an open

collector output to permit the Wired-OR (actuallyWired-AND) function. This is achieved by connecting opencollector outputs together and adding an external pull-upresistor.

The value of the pull-up resistor considering the fan-out of the OR tie adevices in the OR tie. The pull-up resistofrom a range between maximum valumaintain the required V

OHwith all

HIGH) and a minimum value (establishedfan-out is not exceeded when only one ou

MINIMUM AND MAXIMUM PULL-UP RESISTOR VALUES

RX(MIN)VCC(MIN) VOHVCC(MAX) VOL

IOL N 2(LOW) 1.6 mA= RX(MAX) = N1 IOH + N2(HIGH)

Rx = External Pull-up ResistorN1 = Number of Wired-OR OutputsN2 = Number of Input Unit Loads (U.L.) being DrivenIOH = ICEX = Output HIGH Leakage CurrentIOL = LOW Level Fan-out Current of Driving ElementVOL = Output LOW Voltage Level (0.5 V)VOH = Output HIGH Voltage Level (2.4 V)VCC = Power Supply Voltage

where:

Example: Four 74LS03 gate outputs driving four other LS gates or MSI inputs.

RX(MIN) =

RX(MAX) =

where:

N1 = 4N2 (HIGH) = 4 0.5 U.L. = 2 U.L.N2 (LOW) = 4 0.25 U.L. = 1 U.L.IOH = 100 AIOL = 8.0 mAVOL = 0.5 VVOH = 2.4 V

5.25 V 0.5 V8.0 mA 1.6 mA

=4.75 V6.4 mA

= 742

4.75 V 2.4 V4 100 A + 2 40 A =

2.35 V0.48 mA

= 4.9 k

Any value of pull-up resistor between 742 and 4.9 k can be used. The lower values yield the fastesthigher values yield the lowest power dissipation.

UNUSED INPUTSFor best noise immunity and switching speed, unused TTL inputs should not be left floating, but should be he

2.4 V and the absolute maximum input voltage.Two possible ways of handling unused inputs are:

1. Connect unused input to V CC, LS TTL inputs have a breakdown voltage >7.0 V and require, therefore no 2 C h d i h f d h i f d HIGH


20/274

integrity. Parameters associated with this application arelisted in Table 5.

It is also often necessary to construct load lines todetermine reflection waveforms in line driving applications.The input and output characteristics graphs of Section 2(Figures 4, 7, and 8) can be very useful for this purpose.

OUTPUT RISE AND FALL TIMESprovide important information in determining reflection

waveforms and crosstalk coefficients. Typical rise and falltimes are approximately 6 ns for LS with a 50 pF load(measured 1090%). Output rise and fall times becomelonger as capacitive load is increased.

INTERCONNECTION DELAYSFor those parts of a system in which timing is critical,

designers should take into account the finite delay along theinterconnections. These range from about 0.12 to 0.15ns/inch for the type of interconnections normally used inTTL systems. Exceptions occur in systems using groundplanes to reduce ground noise during a logic transition;ground planes give higher distributed capacitance anddelays of about 0.15 to 0.22 ns/inch.

Most interconnections on a logic board are short enoughthat the wiring and load capacitance can be treated as alumped capacitance for purposes of estimating their effect

on the propagation delay of the drivinginterconnection is long enough that its delone-half of the signal transition time, waveform exhibits noticeable slope ctransition. This is evidence that during thethe output voltage transition the driver seesimpedance of the interconnection (no200 ), which for transient conditions apreturned to the quiescent voltage existinbeginning of the transition. This charactforms a voltage divider with the driver otending to produce a signal transition havor fall time as in the no-load condition bamplitude. This attenuated signal travels tinterconnection, which is essentially transmission line, whereupon the signaSimultaneously, a reflection voltage is genthe same amplitude and polarity as the orif the driver output signal is positive-gowill be positive-going, and as it travelsdriver it adds to the line voltage. At the insarrives at the driver it adds algebraicallydriver output, accelerating the transition rthe noticeable change in slope.

Table 5.Output Characteristics for Schottky TTL Logic

(ALL MAXIMUM RATINGS) LS

Characteristic Symbol 74LSxxx Unit

Operating Voltage Range V CC 5 5% Vdc

Output Drive: I OH 0.4 mA

Standard Output I OL 8.0 mA

ISC 20 to 100 mA

IOH 15 mA

Buffer Output I OL 24 mA

ISC 40 to 225 mA


21/274

If an interconnection is of such length that its delay islonger than half the signal transition time, the attenuatedoutput of the driver has time to reach substantial completionbefore the reflection arrives. In the limit, the waveformobserved at the driver output is a 2-step signal with apedestal. In this circumstance the first load circuit to receivea full signal is the one at the far end, because of the doublingeffect, while the last one to receive a full signal is the onenearest the driver since it must wait for the reflection tocomplete the transition. Thus, in a worst-case situation, thenet contribution to the overall delay is twice the delay of theinterconnection because the initial part of the signal musttravel to the far end of the line and the reflection must return.

When load circuits are distributed along aninterconnection, the input capacitance of each will cause asmall reflection having a polarity opposite that of the signal

transition, and each capacitance also slowsof the signal as it passes by. The series ofarriving back at the driver, is subtractive of reducing the apparent amplitude osuccessive slowing of the transition rate signal means that it takes longer for the sito the threshold level of any particular loabut workable approach is to treat the load cincrease in the intrinsic distributed cainterconnection. Increasing the distributetransmission line reduces its impedancedelay. A good approximation forinterconnections is that distributed decreases the characteristic impedance band increases the delay by one-half.

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)

Functional operation under these conditions is not implied.

CHARACTERISTIC LS

Storage Temperature 65 C to +150 CTemperature (Ambient) Under Bias 55 C to +125 CVCC Pin Potential to Ground Pin 0.5 V to +7.0 V*Input Voltage (dc) Diode Inputs 0.5 V to +15 V*Input Current (dc) 30 mA to +5.0 mAVoltage Applied to Open Collector Outputs

(Output HIGH) 0.5 V to +10 VHigh Level Voltage Applied to Disabled

3-State Output 5.5 VCurrent Applied to Output in Low State (Max) Twice Rated I OL

*Either input voltage limit or input current limit is sufficient to protect the inputs Circuits with 5.5 V maximum limits are listed below.

Device types having inputs limited to 5.5 V are as follows:SN74LS245 Inputs connected to outputs.SN74LS640/641/642/645 Inputs connected to outputs.SN74LS299 Certain Inputs.SN74LS151/251 Multiplexer Inputs.


22/274

DEFINITION OF SYMBOLS AND TERMS USED IN THIS DATA B

CURRENTS Positive current is defined as conventional current flow into a device. Negative current is defined aconventional current flow out of a device. All current limits are specified as absolute values.

ICC Supply Current The current flowing into the V CC supply terminal of a circuit with the specified iand the outputs open. When not specified, input conditions are chosen to guarantee worst case operation

IIH Input HIGH current The current flowing into an input when a specified HIGH voltage is applied to

IIL Input LOW current The current flowing out of an input when a specified LOW voltage is applied to

IOH Output HIGH current. The leakage current flowing into a turned off open collector output with a specoutput voltage applied. For devices with a pull-up circuit, the I OH is the current flowing out of ain the HIGH state.

IOL Output LOW current The current flowing into an output which is in the LOW state.IOS Output short-circuit current The current flowing out of an output which is in the HIGH state when

is short circuit to ground (or other specified potential).

IOZH Output off current HIGH The current flowing into a disabled 3-state output with a specified Hvoltage applied.

IOZL Output off current LOW The current flowing out of a disabled 3-state output with a specified Lvoltage applied.

VOLTAGES All voltages are referenced to ground. Negative voltage limits are specified as absolute values (is greater than 1.0 V).

VCC Supply voltage The range of power supply voltage over which the device is guaranteed to operate wspecified limits.

VIK(MAX) Input clamp diode voltage The most negative voltage at an input when the specified current isof that input terminal. This parameter guarantees the integrity of the input diode which is intended to clamptive ringing at the input terminal.

VIH Input HIGH voltage The range of input voltages recognized by the device as a logic HIGH.VIH(MIN) Minimum input HIGH voltage The minimum allowed input HIGH in a logic system. This value re

guaranteed input HIGH threshold for the device.

VIL Input LOW voltage The range of input voltages recognized by the device as a logic LOW.

VIL(MAX) Maximum input LOW voltage The maximum allowed input LOW in a system. This value reguaranteed input LOW threshold for the device.

VOH(MIN) Output HIGH voltage The minimum guaranteed voltage at an output terminal for the specified outpIOH and at the minimum value of V CC .

VOL(MAX) Output LOW voltage The maximum guaranteed voltage at an output terminal sinking the maximumload current I OL.

VT+ Positive-going threshold voltage The input voltage of a variable threshold device ( ie.,is interpreted as a V IH as the input transition rises from below V T(MIN).

VT Negative-going threshold voltage The input voltage of a variable threshold device ( ie.,


23/274

AC SWITCHING PARAMETERS AND WAVEFORMS

tPLH LOW-TO-HIGH propagation delay time :The time delay between specified reference points, typically 1.3 V for LS, on the input and output voltageforms, with the output changing from the defined LOW level to the defined HIGH level.

tPHL HIGH-TO-LOW propagation delay time:The time delay between specified reference points, typically 1.3 V for LS, on the input and output voltageforms, with the output changing from the defined HIGH level to the defined LOW level.

For Inverting Function For Non-Inverting

VIN

Vout

tPHL tPLHtPLH

VIN

Vout

tr Waveform Rise Time:LOW to HIGH logic transition time, measured from the 10% to 90% points of the waveform.

tf Waveform Fall Time:HIGH to LOW logic transition time, measured the 90% to the 10% points of the waveform.

90% 90%

10% 10%

tr tf

tPHZ Output disable time: HIGH to ZThe time delay between the specified reference points on the input and output voltage waveforms, w3-state output changing from the defined HIGH level to a high impedance (OFF) state. Reference point output voltage waveform is V OH 0.5 V for LS and V OH 0.3 V for FAST.

tPZH Output enable time: Z to HIGHThe time delay between the specified reference points on the input and output voltage waveforms, w3-state output changing from a high impedance (OFF) state to a HIGH level.

Enable


24/274

tPLZ Output disable time: LOW to ZThe time delay between the specified reference points on the input and output voltage waveforms, w3-state output changing from the defined LOW level to a high impedance (OFF) state. Reference point output voltage waveform is V OL + 0.5 V for LS.

tPZL

Output enable time: Z to LOWThe time delay between the specified reference points on the input and output voltage waveforms with the 3output changing from a high impedance (OFF) state to a HIGH level.

Enable

Vout

Enable

tPZL

tPLZ

VOZ= 1.5 V.5 for LS

trec Recovery timeTime required between an asynchronous signal (SET, RESET, CLEAR or PARALLEL load) and the activof a synchronous control signal, to insure that the device will properly respond to the synchronous sign

Asynch

Asynch

Control

trec

th Hold TimeThe interval of time from the active edge of the control signal (usually the clock) to when the data to be recogis no longer required to ensure proper interpretation of the data. A negative hold time indicates that the databe removed at some time prior to the active edge of the control signal.

ts Setup time

The interval of time during which the data to be recognized is required to remain constant prior to the activof the control signal to ensure proper data recognition. A negative setup time indicates that data may be inisometime after the active transition of the timing pulse and still be recognized.

VIN VIN


25/274

tw or Pulse widthtpw The time between the specified amplitude points (1.3 V for LS) on the leading and trailing edges of a pu

twL

twH

fMAX Toggle frequency/operating frequencyThe maximum rate at which clock pulses meeting the clock requirements ( ie., tWH, tWL, and tto a sequential circuit. Above this frequency the device may cease to function.

fMAXmin Guaranteed maximum clock frequencyThe lowest possible value for f MAX.

TESTING

DC TEST CIRCUITSThe following test circuits and forcing functions represent ON Semiconductors typical DC test procedures.

*Unless otherwise indicated, input conditions are selected to produce a worst case condition.

VIHMINor VILMAX

DUT

DUT DUT

DUT

D

Io

Io

VoIi = 18 mA

VIHMINor VILMAX

Vik

+

GNDor

4.5 V*

DU

ICC T

Measure ICC

IOH, IOZH, and IOZLTESTSForce 5.5, 2.4, or 0.4 V

Measure IO

VIKTESTForce Ii

Measure VIK

IOIIHH, IIHAND IILTESTSForce 7, 5.5, 2.7, or 0.4 VMeasure I

IHH, I

IH, or I

IL

VOHAND VOLTESTSForce IOHMAXor IOLMAX

Measure VOH

or VOL

+

VoVi


26/274

AC TEST CIRCUITS

The following test circuits and conditions represent ON Semiconductors typical test procedures. AC waveterminology can be found on pages 22 to 24.

FUNCTIONAL TESTING OF TTL IN A NOISY ENVIRONMENT/DYNAMIC THRESHOLDTesting noise (noise generated by the test system itself and

noise generated by TTL devices under test interacting withthe test system) adds to, or subtracts from the thresholdvoltage applied to the TTL device under test. For this reasonON Semiconductor does not recommend functional testingof TTL devices using threshold levels of 0.8 V and 2.0 V.

Instead, good TTL testing techniques callless than 0.5 V V IL and greater than 2.4for functional testing. Input threshold vtested separately, and only (for noise reasetting the device state with a hard level.

VOUT

VOL

VIN DynamicThreshold

TriggerThreshold

VOH

Region of output instability;

Dynamic Noise contribution to apparent input threshold

The V IN versus V OUT plot shows the practical effect of testing noise on a logic IC device. The actual device Trigger threshold is represented by the initial low to high outputtransition. The device will oscillate if the input voltage doesnot exceed the trigger threshold plus the noise generated bythe interaction of the test system or given application withthe device.

The Dynamic threshold (that creates Quiescent outputs),is the input logic level required to overcome the interactiveDYNAMIC NOISE generated by a device switching states.

The amount of interactive DYNAMICcharacterized by the difference betwthreshold and the Dynamic threshold oftest. A simple number cannot be assignedas it is heavily dependent on any given aenvironment.

So although the Trigger threshold of any

correlate well between any test system, Dynamic threshold cannot be made diremeaning only in a relative sense.


27/274

Optional LS Load (GuaranteedNot Tested)

*includes all probe and jig capacitance

Test Circuit for Open Collector Output Devices

LS TEST CIRCUITS

Test Circuit for Standard Output Devices

DUTPULSE GEN

VINVOUT

15 pF*51

VCC

DUTPULSE GEN

VINVOUT

15 pF*51

VCC VCC

RL

VCC

CL

RL

PULSE GENERATOR SE(UNLESS OTHERWISE S

LSFrequency = 1 MH

Duty Cycle = 50%1 TLH (t r) = 6 n1 THL (t f) = 6 nAmplitude = 0 to

* The specified propagation delay limits with a 15 ns input rise time on all paramrequiring narrow pulse widths. Any frequover 15 MHz or pulse width less than 30 nswith a 6 ns input rise time.


28/274

APPLICATIONS ASSISTANCE FORMIn the event that you have any questions or concerns about the performance of any ON Semiconductor device listed icatalog, please contact your local ON Semiconductor sales office or the ON Semiconductor Help line for assistance. If information is required, you can request direct factory assistance.

Please fill out as much of the form as is possible if you are contacting ON Semiconductor for assistance or are sending deback to ON Semiconductor for analysis. Your information can greatly improve the accuracy of analysis and can dramimprove the correlation response and resolution time.

Items 4 thru 8 of the following form contains important questions that can be invaluable in analyzing application oproblems. It can be used as a self-help diagnostic guideline or for a baseline of information gathering to begin a dialog wSemiconductor representatives.

ON Semiconductor Device Correlation/Component Analysis Request Form Please fill out entire form and return with devices to ON Semiconductor, R&QA Dept., 5005 E. McDowell, Phoenix, A

1) Name of Person Requesting Correlation:

Phone No: Job Title: Company:2) Alternate Contact: Phone/Position:

3) Device Type (user part number):4) Industry Generic Device Type:5) # of devices tested/sampled:

# of devices in question*:# returned for correlation:* In the event of 100% failure, does Customer have other date codes of ON Semiconductor devices that pass inspe

Yes No Please specify passing date code(s) if applicableIf none, does customer have viable alternate vendor(s) for device type?

Yes No Alternate vendors name6) Date code(s) and Serial Number(s) of devices returned for correlation If possible, please provide one or two goo

(ON Semiconductors and/or other vendor) for comparison:7) Describe USER process that device(s) are questionable in:

Incoming component inspection {test system = ?}:Design prototyping:

Board test/burn-in:Other (please describe):

8) Please describe the device correlation operating parameters as completely as possible for device(s) in question:> Describe all pin conditions (e.g. floating, high, low, under test, stimulated but not under test, whatever ...), including an

or output loading conditions (resistors, caps, clamps, driving devices or devices being driven ...). Potentiallyinformation includes:

Input waveform timing relationshipsInput edge ratesInput Overshoot or Undershoot Magnitude and DurationOutput Overshoot or Undershoot Magnitude and Duration

> Photographs, plots or sketches of relevent inputs and outputs with voltages and time divisions clearly identifiewaveforms are greatly desirable.

> VCC and Ground waveforms should be carefully described as these characteristics vary greatly between applicatiotest systems. Dynamic characteristics of Ground and V CC during device switching can dramatically effect i


29/274


30/274

CHLS Dat


31/274

ESD > 3500 Volts

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 4.75 5.0 5.25 V

TA Operating AmbientTemperature Range

0 25 70 C

IOH Output Current High 0.4 mA

IOL Output Current Low 8.0 mA

LOW

POWESCHOTT

Device Package

ORDERING INFO

SN74LS00N 14 Pin DIP

SN74LS00D 14 Pin

SOICD SUFFI

CASE 751

http://onsemi.

PLASTIN SUFFICASE 64

14

1

14

1

SN74LS00


32/274

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter Min Typ Max Unit Test C

VIH Input HIGH Voltage 2.0 VGuaranteed Inp

All Inputs

VIL Input LOW Voltage0.8

VGuaranteed Inp

All Inputs

VIK Input Clamp Diode Voltage 0.65 1.5 V V CC = MIN, II

VOH Output HIGH Voltage2.7 3.5 V V CC = MIN, IO

or V IL per Tr

p0.25 0.4 V I OL = 4.0 mA

OL

0.35 0.5 V I OL = 8.0 mA

p20 A VCC = MAX, V

IH 0.1 mA V CC = MAX, V

IIL Input LOW Current 0.4 mA V CC = MAX, V

IOS Short Circuit Current (Note 1) 20 100 mA V CC = MAX

Power Supply Current

ICC Total, Output HIGH 1.6 mA VCC = MAX

Total, Output LOW 4.4Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25 C)

Limits


tPLH TurnOff Delay, Input to Output 9.0 15 ns VCtPHL TurnOn Delay, Input to Output 10 15 ns C


33/274

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND





0 25 70 C



LOW

POWESCHOTT

SOICD SUFFI

CASE 751

http://onsemi.


14

1

14

1

Device Package

ORDERING INFO


SN74LS04D 14 Pin

SN74LS04


34/274


Limits


VIH Input HIGH Voltage 2.0 VGuaranteed Inp

All Inputs


VGuaranteed Inp

All Inputs



or V IL per Tr

p0.25 0.4 V I OL = 4.0 mA

OL

0.35 0.5 V I OL = 8.0 mA

p20 A VCC = MAX, V








Limits




35/274

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND

* * *

* * *

*OPEN COLLECTOR OUTPUTS





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VOH Output Voltage High 5.5 V


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SN74LS05D 14 Pin

SN74LS05


36/274


Limits


VIH Input HIGH Voltage 2.0 V

Guaranteed Inp

All Inputs


VGuaranteed Inp

All Inputs


IOH Output HIGH Current 100 A VCC = MIN, V

p0.25 0.4 V I OL = 4.0 mA

OL 0.35 0.5 V I OL = 8.0 mA

p20 A VCC = MAX, V





Total, Output LOW 6.6

AC CHARACTERISTICS (TA = 25 C)Limits


tPLH TurnOff Delay, Input to Output 17 32 ns VCtPHL TurnOn Delay, Input to Output 15 28 ns CL = 15 p


37/274

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND





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SN74LS08D 14 Pin

SN74LS08


38/274


Limits


VIH

Input HIGH Voltage 2.0 VGuaranteed Inp

All Inputs


VGuaranteed Inp

All Inputs



or V IL per Tr

p0.25 0.4 V I OL = 4.0 mA

OL 0.35 0.5 V I

OL= 8.0 mA

p20 A VCC = MAX, V








Limits




39/274

The SN74LS14 contains logic gates/ inverters which acceptstandard TTL input signals and provide standard TTL output levels.They are capable of transforming slowly changing input signals intosharply defined, jitter-free output signals. Additionally, they havegreater noise margin than conventional inverters.

Each circuit contains a Schmitt trigger followed by a Darlingtonlevel shifter and a phase splitter driving a TTL totem pole output. TheSchmitt trigger uses positive feedback to effectively speed-up slowinput transitions, and provide different input threshold voltages forpositive and negative-going transitions. This hysteresis between thepositive-going and negative-going input thresholds (typically800 mV) is determined internally by resistor ratios and is essentiallyinsensitive to temperature and supply voltage variations.

LOGIC AND CONNECTION DIAGRAMS

SN74LS14

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND




TA

Operating AmbientTemperature Range

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DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE ( l h i ifi d)


40/274


Limits

Symbol Parameter Min Typ Max Unit Test Con

VT+ Positive-Going Threshold Voltage 1.5 2.0 V V CC = 5.0 V

VT Negative-Going Threshold Voltage 0.6 1.1 V V CC = 5.0 V

VT+ VT Hysteresis 0.4 0.8 V V CC = 5.0 V

VIK Input Clamp Diode Voltage 0.65 1.5 V V CC = MIN, IIN =

VOH Output HIGH Voltage 2.7 3.4 V V CC = MIN, IOH =

p0.25 0.4 V V CC = MIN, IOL = 4

OL u u0.35 0.5 V V CC = MIN, IOL = 8

IT+ Input Current at Positive-Going Threshold 0.14 mA V CC = 5.0 V, V IN =

IT Input Current at Negative-Going Threshold 0.18 mA V CC = 5.0 V, V IN =

p1.0 20 A VCC = MAX, VIN =

IH u u0.1 mA V CC = MAX, VIN =

IIL Input LOW Current 0.4 mA V CC = MAX, VIN =

IOS Short Circuit Current (Note 1) 20 100 mA V CC = MAX, VOUT


Total, Output HIGH

8.6 16

CC

Total, Output LOW

12 21 CC =

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.


Symbol Parameter Max Unit Test Conditio

tPLH Propagation Delay, Input to Output 22 ns VCC

tPHL Propagation Delay, Input to Output 22 nsC

L=

3 V

0 VVIN

VOUT

1.6 V 0.8 V

tPHL

1.3 V 1.3 V

tPLH

SN74LS14


41/274

Figure 2. V IN versus V OUT Transfer Function Figure 3. Threshold Voltage and Hversus Power Supply Volt

Figure 4. Threshold Voltage Hysteresisversus Temperature

5

4

3

2

1

00 0.4 0.95 1.2 1.8 2

VIN, INPUT VOLTAGE (VOLTS)

V O

, O U T P U T V O L T A G E

( V O L T S )

VCC = 5 VTA= 25C

2

1.6

1.2

0.8

0.4

04.5 4.75 5

VCC, POWER SUPPLY VOLT

V T

, T H R E S H O L D V O L T A G E ( V O L T S )

V T

, H Y S T E R E S I S ( V O L T S )

1.9

1.7

1.5

1.3

1.1

0.9

0.7 55 0 25 75 125

TA, AMBIENT TEMPERATURE (C)

V T

, T H R E S H O L D V O L T A G E ( V O L T S )

V T

, H Y S T E R E S I S ( V O L T S )

TA= 25C

VT+

VT

VT

VT

VT

VT+


42/274

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND





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SN74LS32D 14 Pin

SN74LS32



43/274


Limits


VIH

Input HIGH Voltage 2.0 VGuaranteed Inpu

All Inputs


VGuaranteed InpuAll Inputs

VIK Input Clamp Diode Voltage 0.65 1.5 V V CC = MIN, IIN


or V IL per Truth

p0.25 0.4 V I OL = 4.0 mA

OL u u0.35 0.5 V I OL = 8.0 mA

p20 A VCC = MAX, V

IH u u0.1 mA V CC = MAX, V



ICC

Power Supply CurrentTotal, Output HIGH 6.2 mA VCC = MAXTotal, Output LOW 9.8



Limits


tPLH Turn-Off Delay, Input to Output 14 22 ns VCtPHL Turn-On Delay, Input to Output 14 22 ns C


44/274

14 13 12 11 10 9

1 2 3 4 5 6

VCC

8

7

GND

* *

* *

*OPEN COLLECTOR OUTPUTS





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VOH Output Voltage High 5.5 V

IOL Output Current Low 24 mA

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SN74LS38D 14 Pin

SN74LS38



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Limits

Symbol Parameter Min Typ Max Unit Test Co

VIH Input HIGH Voltage 2.0 VGuaranteed Input

All Inputs


VGuaranteed Input All Inputs


IOH Output HIGH Current 250 A VCC = MIN, VOH

p0.25 0.4 V I OL = 12 mA

OL u u0.35 0.5 V I OL = 24 mA

p 20 A VCC = MAX, VIN

IH u u0.1 mA V CC = MAX, VIN

IIL Input LOW Current 0.4 mA V CC = MAX, VIN

ICC

Power Supply CurrentTotal, Output HIGH 2.0 mA VCC = MAXTotal, Output LOW 12


Limits


tPLH Turn-Off Delay, Input to Output 20 32 ns VCC = 5.0

tPHL Turn-On Delay, Input to Output 18 28 nsCL


46/274

The LSTTL/MSI SN74LS42 is a Multipurpose Decoder designedto accept four BCD inputs and provide ten mutually exclusive outputs.The LS42 is fabricated with the Schottky barrier diode process forhigh speed and is completely compatible with all ON SemiconductorTTL families. Multifunction Capability Mutually Exclusive Outputs Demultiplexing Capability

Input Clamp Diodes Limit High Speed Termination Effects





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CONNECTION DIAGRAM DIP (TOP VIEW)


47/274

LOGIC DIAGRAM

A0 A1 A2 A3

LOGIC SYMBOL

VCC = PIN 16GND = PIN 8

15 14 13 12

0 1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 9 10 11

A0 A1 A2 A3

14 13 12 11 10 9

1 2 3 4 5 6

VCC

7

16 15

8

A0 A1 A2 A3 9 8 7

0 1 2 3 4 5 6 GND


NOTE:The Flatpak versiohas the same pinou(Connection Diagras the Dual In-LinePackage.

Address InputsOutputs, Active LOW

A0 A30 to 9

0.5 U.L.10 U.L.

0.25 U.L.5 U.L.

NOTES:a) 1 TTL Unit Load (U.L.) = 40A HIGH/1.6 mA LOW.

HIGH LOW

(Note a)LOADING

PIN NAMES

15 14 13 12

SN74LS42

FUNCTIONAL DESCRIPTION


48/274

The LS42 decoder accepts four active HIGH BCD inputsand provides ten mutually exclusive active LOW outputs, asshown by logic symbol or diagram. The active LOW outputsfacilitate addressing other MSI units with LOW inputenables.

The logic design of the LS42 ensures that all outputsare HIGH when binary codes greater than nine are appliedto the inputs.

The most significant input A 3 prodfunction when the LS42 is used as a oneThe A 3 input can also be used as the Data idemultiplexer application.

TRUTH TABLE

A0 A1 A2 A3 0 1 2 3 4 5 6 7 8 9

LHLHLHLHLHL

HLHLH

LLHHLLHHLLH

HLLHH

LLLLHHHHLLL

LHHHH

LLLLLLLLHHH

HHHHH

LHHHHHHHHHH

HHHHH

HLHHHHHHHHH

HHHHH

HHLHHHHHHHH

HHHHH

HHHLHHHHHHH

HHHHH

HHHHLHHHHHH

HHHHH

HHHHHLHHHHH

HHHHH

HHHHHHLHHHH

HHHHH

HHHHHHHLHHH

HHHHH

HHHHHHHHLHH

HHHHH

HHHHHHHHHLH

HHHHH

H = HIGH Voltage LevelL = LOW Voltage Level

SN74LS42



49/274

Limits


VIH Input HIGH Voltage 2.0 VGuaranteed Inpu

All Inputs


VGuaranteed InpuAll Inputs



or V IL per Truth

p0.25 0.4 V I OL = 4.0 mA

OL u u0.35 0.5 V I OL = 8.0 mA

p20 A VCC = MAX, V

IH u u0.1 mA V CC = MAX, V



ICC Power Supply Current 13 mA V CC = MAX




tPLHtPHL

Propagation Delay(2 Levels)

1515

2525

ns Figure 2

tPLHtPHL

Propagation Delay(3 Levels)

2020

3030

ns Figure 1

AC WAVEFORMS

VIN

VOUT

1.3 V 1.3 V

1.3 V 1.3 V

tPHL tPLH

Figure 1. Figure 2.

1.3 V

1.3 V

tPHL

VIN

VOUT


50/274

The SN74LS47 are Low Power Schottky BCD to 7-SegmentDecoder/Drivers consisting of NAND gates, input buffers and sevenAND-OR-INVERT gates. They offer active LOW, high sink currentoutputs for driving indicators directly. Seven NAND gates and onedriver are connected in pairs to make BCD data and its complementavailable to the seven decoding AND-OR-INVERT gates. Theremaining NAND gate and three input buffers provide lamp test,

blanking input/ripple-blanking output and ripple-blanking input.The circuits accept 4-bit binary-coded-decimal (BCD) and,

depending on the state of the auxiliary inputs, decodes this data todrive a 7-segment display indicator. The relative positive-logic outputlevels, as well as conditions required at the auxiliary inputs, are shownin the truth tables. Output configurations of the SN74LS47 aredesigned to withstand the relatively high voltages required for7-segment indicators.

These outputs will withstand 15 V with a maximum reverse current

of 250 A. Indicator segments requiring up to 24 mA of current maybe driven directly from the SN74LS47 high performance outputtransistors. Display patterns for BCD input counts above nine areunique symbols to authenticate input conditions.

The SN74LS47 incorporates automatic leading and/ or trailing-edgezero-blanking control (RBI and RBO). Lamp test (LT) may beperformed at any time which the BI/RBO node is a HIGH level. Thisdevice also contains an overriding blanking input (BI) which can beused to control the lamp intensity by varying the frequency and duty

cycle of the BI input signal or to inhibit the outputs. Lamp Intensity Modulation Capability (BI/RBO) Open Collector Outputs Lamp Test Provision Leading/Trailing Zero Suppression Input Clamp Diodes Limit High-Speed Termination Effects





0 25 70 C

I O t t C t Hi h 50 A

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SN74LS47D 16 Pin

SN74LS47



51/274

LOGIC SYMBOL

BCD InputsRippleBlanking InputLampTest InputBlanking Input orRippleBlanking OutputOutputs

A, B, C, DRBILTBI/RBO

a, to g

0.5 U.L.0.5 U.L.0.5 U.L.0.5 U.L.1.2 U.L.

OpenCollector

0.25 U.L.0.25 U.L.0.25 U.L.0.75 U.L.2.0 U.L.15 U.L.

NOTES:a) 1 Unit Load (U.L.) = 40A HIGH, 1.6 mA LOW.b) Output current measured at VOUT= 0.5 Vb) The Output LOW drive factor is 15 U.L. for Commercial (74) Temperature Range

HIGH LOW

(Note a)LOADING

PIN NAMES

14 13 12 11 10 9

1 2 3 4 5 6

VCC

7

16 15

8

f g a b c d e

B C LT BI / RBO RBI D A GND

VCC = PIN 16

GND = PIN 8

7 1 2 6 3 5

13 12 11 10 9 15 14 4

A B C D LT RBI

a b c d e f gBI/

RBO

SN74LS47

LOGIC DIAGRAM


52/274

TRUTH TABLEINPUTS OUTPUTS

14 15

NUMERICAL DESIGNATIONS RESULTANT DISPLAYS

0 1 2 3 4 5 6 7 8 9 10 11 12 13

INPUT

BLANKING INPUT ORRIPPLE-BLANKING

OUTPUT

RIPPLE-BLANKINGINPUT

LAMP-TEST INPUT

A

B

C

D

a a

b b

c c

d d

e e

f f

g g

OUTPU

DECIMALOR

FUNCTIONLT RBI D C B A BI/RBO a b c d e f g NOTE

0 H H L L L L H L L L L L L H A

1 H X L L L H H H L L H H H H A2 H X L L H L H L L H L L H L

3 H X L L H H H L L L L H H L

4 H X L H L L H H L L H H L L

5 H X L H L H H L H L L H L L

6 H X L H H L H H H L L L L L

7 H X L H H H H L L L H H H H

8 H X H L L L H L L L L L L L

9 H X H L L H H L L L H H L L

10 H X H L H L H H H H L L H L

11 H X H L H H H H H L L H H L

12 H X H H L L H H L H H H L L13 H X H H L H H L H H L H L L

14 H X H H H L H H H H L L L L

15 H X H H H H H H H H H H H H

BI X X X X X X L H H H H H H H B

RBI H L L L L L L H H H H H H H C

LT L X X X X X H L L L L L L L D

SN74LS47


Limits


53/274

tsSymbol Parameter Min Typ Max Unit Test Cond

VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGHfor All Inputs

VIL Input LOW Voltage0.8 V Guaranteed Input LOW for All Inputs

VIK Input Clamp Diode Voltage 0.65 1.5 V V CC = MIN, IIN = 18

pVCC = MIN, IOH = 50

OH u u , . . VIN = VIN or VIL per Tr

Output LOW Voltage 0.25 0.4 V I OL = 1.6 mA VOL BI/RBO 0.35 0.5 V I OL = 3.2 mA or

IO (off)Off-State Output Currenta thru g 250 A

VCC = MAX, VIN = VINTable, V O (off) = 15 V

On-State Output Voltage 0.25 0.4 V I O (on) = 12 mA VO (on) a thru g 0.35 0.5 V I O (on) = 24 mA or

p20 A VCC = MAX, VIN = 2.7

IH u u 0.1 mA V CC = MAX, VIN = 7.0

IILInput LOW Current BI/ RBOAny Input except BI/ RBO

1.2 0.4 mA VCC = MAX, VIN = 0.4

IOS BI / RBO Output Short Circuit Current (Note 1) 0.3 2.0 mA V CC = MAX, VOUT = 0

ICC Power Supply Current 7.0 13 mA V CC = MAX



Symbol Parameter Min Typ Max Unit Test Cond

tPHLtPLH

Propagation Delay, AddressInput to Segment Output

100100

nsns VCC =

tPHLtPLH

Propagation Delay, RBI InputTo Segment Output

100100

nsns

CL =

AC WAVEFORMS

VIN

VOUT

1.3 V 1.3 V

1.3 V 1.3 V

tPHL tPLH

Fi 1 Fi 2

1.3 V

1.3 V

tPHL

VIN

VOUT


54/274

The SN74LS74A dual edge-triggered flip-flop utilizes SchottkyTTL circuitry to produce high speed D-type flip-flops. Each flip-flophas individual clear and set inputs, and also complementary Q and Qoutputs.

Information at input D is transferred to the Q output on thepositive-going edge of the clock pulse. Clock triggering occurs at avoltage level of the clock pulse and is not directly related to the

transition time of the positive-going pulse. When the clock input is ateither the HIGH or the LOW level, the D input signal has no effect.

MODE SELECT TRUTH TABLE

INPUTS OUTPUTS

S D S D D Q Q

SetReset (Clear)*UndeterminedLoad 1 (Set)Load 0 (Reset)

LHLHH

HLLHH

XXXhl

HLHHL

LHHLH

* Both outputs will be HIGH while both S D and C D are LOW, but the outputstates are unpredictable if S D and C D go HIGH simultaneously. If the levelsat the set and clear are near V IL maximum then we cannot guarantee to meetthe minimum level for V OH.

H, h = HIGH Voltage Level

L, I = LOW Voltage LevelX = Dont Care

l, h (q) = Lower case letters indicate the state of the referenced input

i, h (q) = (or output) one set-up time prior to the HIGH to LOW clock transition.




TA Operating Ambient 0 25 70 C

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LOGIC DIAGRAM (Each Flip-Flop)


55/274

LOGIC SYMBOL

SET (SD)4 (10)

CLEAR (CD)1 (13)

CLOCK3 (11)

D2 (12)

Q5 (9)

Q6 (8)


2

3

5D Q

CP

QCD

1

4

6

12

11

9D Q

CP

QCD

13

10

8

SD SD

SN74LS74A


Limits


56/274

Symbol Parameter Min Typ Max Unit Test Co

VIH Input HIGH Voltage 2.0 VGuaranteed Input All Inputs


VGuaranteed Input All Inputs


VOH Output HIGH Voltage2.7 3.5 V V CC = MIN, IOH

or V IL per Truth T

p0.25 0.4 V I OL = 4.0 mA

OL u u0.35 0.5 V I OL = 8.0 mA

IIH

Input High CurrentData, ClockSet, Clear

2040

A VCC = MAX, VIN

Data, ClockSet, Clear

0.10.2 mA VCC = MAX, VIN

IILInput LOW Current

Data, ClockSet, Clear

0.4 0.8

mA VCC = MAX, VIN

IOS Output Short Circuit Current (Note 1) 20 100 mA V CC = MAX

ICC Power Supply Current 8.0 mA V CC = MAX


AC CHARACTERISTICS (TA = 25 C, VCC = 5.0 V)

Limits


fMAX Maximum Clock Frequency 25 33 MHz Figure 1

tPLHp

13 25 ns

tPHL , , u u 25 40 ns u

AC SETUP REQUIREMENTS (TA = 25 C)

Limits


tW(H) Clock 25 ns Figure 1

tW(L) Clear, Set 25 ns Figure 2

Data Setup Time HIGH 20 nss Data Setup Time LOW 20 ns u

th Hold Time 5.0 ns Figure 1

SN74LS74A

AC WAVEFORMS


57/274

Figure 1. Clock to Output Delays, DataSet-Up and Hold Times, Clock Pulse Width

*The shaded areas indicate when the input is permitted to change for predictable output performance.

D *

CP

Q

Q

1.3 V 1.3 V

1.3 V1.3 V

1.3 V

1.3 V1.3 V

tPLHtPHL

tPLHtPHL

th(L)ts(L) tW(H)

tW(L)

ts(H)

th(H)

1fMAX

1.3 V

tW

1.3 V 1.3 V

tW

1.3 V 1.3 V

1.3 V

1.3 V1.3 V

1.3 V

tPLH tPHL

tPLHtPHL

SET

CLEAR

Q

Q


58/274

The SN74LS76A offers individual J, K, Clock Pulse, Direct Set andDirect Clear inputs. These dual flip-flops are designed so that whenthe clock goes HIGH, the inputs are enabled and data will be accepted.The Logic Level of the J and K inputs will perform according to theTruth Table as long as minimum set-up times are observed. Input datais transferred to the outputs on the HIGH-to-LOW clock transitions.

MODE SELECT TRUTH TABLE

OPERATING INPUTS OUTPUTSMODE S D CD J K Q Q

SetReset (Clear)*UndeterminedToggle

Load 0 (Reset)Load 1 (Set)Hold

LHLH

HHH

HLLH

HHH

XXXh

lhl

XXXh

hll

HLHq

LHq

LHHq

HLq

* Both outputs will be HIGH while both S D and C D are LOW, but the outputstates are unpredictable if S D and C D go HIGH simultaneously.

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Immaterial

l, h (q) = Lower case letters indicate the state of the referenced input

i, h (q) = (or output) one setup time prior to the HIGHtoLOW clock transition





0 25 70 C


I Output Current Low 8 0 mA

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LOGIC DIAGRAM LOGIC SY2


59/274

Q

CLEAR (CD)

J

CLOCK (CP)

K

SET (SD)

Q 16

1

4

15

14

K Q

CP

J Q

SD

VCC = PIGND = P

3

CD


Limits


VIH Input HIGH Voltage 2.0 VGuaranteed InputAll Inputs


VGuaranteed InputAll Inputs


VOH Output HIGH Voltage2.7 3.5 V V CC = MIN, IOH

or V IL per Truth T

p0.25 0.4 V I OL = 4.0 mA

OL u u0.35 0.5 V I OL = 8.0 mA

p

J, KClearClock

206080

A VCC = MAX, VI

IH u uJ, KClearClock

0.10.30.4

mA VCC = MAX, VI

IIL Input LOW CurrentJ, KClear, Clock

0.4 0.8 mA VCC = MAX, VI


ICC Power Supply Current 6.0 mA V CC = MAX


AC CHARACTERISTICS (TA = 25 C, VCC = 5.0 V)

Limits


fMAX Maximum Clock Frequency 30 45 MHz

tPLH p15 20 ns

VCC

tPHLoc , ear, e o u pu

15 20 ns


60/274

The SN74LS85 is a 4-Bit Magnitude Camparator which comparestwo 4-bit words (A, B), each word having four Parallel Inputs(A0 A 3, B0 B3); A 3, B3 being the most significant inputs. Operationis not restricted to binary codes, the device will work with anymonotonic code. Three Outputs are provided: A greater than B(OA > B ), A less than B (O A < B ), A equal to B (O A = B ). ThreeExpander Inputs, I A >B , IA < B , IA = B , allow cascading without external

gates. For proper compare operation, the Expander Inputs to the leastsignificant position must be connected as follows: I A < B = I A > B = L,IA = B = H. For serial (ripple) expansion, the O A > B , O A < B and O A = BOutputs are connected respectively to the I A > B , IA < B , and I A = BInputs of the next most significant comparator, as shown in Figure 1.Refer to Applications section of data sheet for high speed method of comparing large words.

The Truth Table on the following page describes the operation of theSN74LS85 under all possible logic conditions. The upper 11 lines

describe the normal operation under all conditions that will occur in asingle device or in a series expansion scheme. The lower five linesdescribe the operation under abnormal conditions on the cascadinginputs. These conditions occur when the parallel expansion techniqueis used. Easily Expandable Binary or BCD Comparison OA > B , O A < B , and O A = B Outputs Available





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V A B A A AB B


61/274

LOGIC SYMBOL

Parallel InputsA = B Expander InputsA < B, A > B, Expander InputsA Greater than B OutputB Greater than A OutputA Equal to B Output

A0 A3, B0 B3IA = BIA < B, IA > BOA > BOA < BOA= B

1.5 U.L.1.5 U.L.0.5 U.L.10 U.L.10 U.L.10 U.L.

0.75 U.L.0.75 U.L.0.25 U.L.

5 U.L.5 U.L.5 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40A HIGH/1.6 mA LOW.

HIGH LOW

(Note a)LOADING

PIN NAMES


10 12 13 15 9 11 14 1

423

576

A0 A1 A2 A3 B0 B1 B2 B3IA>BIABOAB OA=B OA


62/274

OA

OA

OA

(5)

(6)

(7)

A3B3

A2B2

Documents

LS TTL Data