lpd_9_pseudoNMOS

7/25/2019 lpd_9_pseudoNMOS

1/23

Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9ELEC6270 Spring 11, Lecture 9 11

ELEC 5270/6270 Spring 2011ELEC 5270/6270 Spring 2011

Low- ower !e"ign o# Electronic Circuit"Low- ower !e"ign o# Electronic Circuit"

"eu$o-n%&S, !yna'ic C%&S"eu$o-n%&S, !yna'ic C%&S

an$ !o'ino C%&S Logican$ !o'ino C%&S LogicVishwani D. AgrawalVishwani D. Agrawal James J. Danaher Professor James J. Danaher Professor

Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer Engineering

Auburn University Auburn A! "#$%&Auburn University Auburn A! "#$%&

[email protected]://www.eng.auburn.edu/~

vagrawal/COURSE/E6270_Spr11/ !ur"e.ht#l
mailto:[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.htmlmailto:[email protected]


2/23


Static C%&S( ro" an$ Con"Static C%&S( ro" an$ Con"

A$)antage"( Static *ro+u"t operation, low A$)antage"( Static *ro+u"t operation, lowpower, "cala+le with technologypower, "cala+le with technology!i"a$)antage"(!i"a$)antage"(

Large "i.e( An input gate re uire" 2 tran"i"tor"Large "i.e( An input gate re uire" 2 tran"i"tor"Large capacitance( Each #anout 'u"t $ri)e twoLarge capacitance( Each #anout 'u"t $ri)e two$e)ice"$e)ice"

Alternati)e"( a""-tran"i"tor logic * L , Alternati)e"( a""-tran"i"tor logic * L ,p"eu$o-n%&S, $yna'ic C%&S, $o'ino C%&Sp"eu$o-n%&S, $yna'ic C%&S, $o'ino C%&S


3/23

Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9ELEC6270 Spring 11, Lecture 9

A "eu$o-n%&S 3ate A "eu$o-n%&S 3ate

4

!

!!

C%&S 3ate

!

!!

"eu$o-n%&S 3ate

&utput

6 n p u

t "

6 n p u

t "

&utput


4/23

Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9ELEC6270 Spring 11, Lecture 9

"eu$o-n%&S &8"eu$o-n%&S &8!!

nput 1

&utput

nput 2 nput


5/23


"eu$o-n%&S A !"eu$o-n%&S A !!!

nput 1

&utput

nput 2


6/23


"eu$o-n%&S n)erter "eu$o-n%&S n)erter !!

nput

&utput


7/23


n)erter Characteri"tic"n)erter Characteri"tic"

/L p :

/L p : 2

/L p : 0 25

/L p: 0 5

/L p: 1

0 0 0 5 1 0 1 5 2 0 2 5

nput )oltage,

& u

t p u

t ) o l

t a g e ,

5

0

2 5

2 0

1 5

1 0

0 5

0 0

o'inal $e)ice(

0 5;


8/23

Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9ELEC6270 Spring 11, Lecture 9 ==

er#or'ance o# n)erter er#or'ance o# n)erter Si.e, /LSi.e, /L pp Logic 0 )oltageLogic 0 )oltage Logic 0 "taticLogic 0 "taticpower power

!elay!elay0 > 10 > 1

0 69 0 69 5656 ;; 1 p"1 p"

22 0 27 0 27 29=29= ;; 56 p"56 p"

11 0 1 0 1 160160 ;; 12 p"12 p"

0 50 5 0 06 0 06 =0=0 ;; 26= p"26= p"

0 250 25 0 0 1 0 0 1 11 ;; 569 p"569 p"

? % 8a+aey, A Chan$ra@a"an an$ o@oliB, Digital Integrated Circuits , 4pper Sa$$le 8i)er, ew ?er"ey( ear"on E$ucation, 200 ,page 262


9/23


egati)e A"pect" o# "eu$o-n%&Segati)e A"pect" o# "eu$o-n%&S

&utput 0 "tate i" ratioe$ logic&utput 0 "tate i" ratioe$ logica"ter gate" 'ean higher "tatic powera"ter gate" 'ean higher "tatic power

Low "tatic power 'ean" "low gate"Low "tatic power 'ean" "low gate"


10/23


A !yna'ic C%&S 3ate A !yna'ic C%&S 3ate

!

!!

6 n p u

t "&utput

CD

C L

rechargetran"i"tor

E)aluatetran"i"tor


11/23


wo- ha"e &peration in a ectorwo- ha"e &peration in a ector

erio$erio$

ha"eha"e CDCD nput"nput" &utput&utput

rechargerecharge lowlow $on t care$on t care highhigh

E)aluationE)aluation highhigh ali$ input"ali$ input" ali$ output"ali$ output"


12/23


- nput A ! !yna'ic C%&S 3ate- nput A ! !yna'ic C%&S 3ate

&utput: CD F *A C! G CD

CL

CD

A

C

!

CD

!!

tL>H I 0


13/23


Characteri"tic" o# !yna'ic C%&SCharacteri"tic" o# !yna'ic C%&S

onratioe$ logic J "i.ing o# p%&S tran"i"tor i" not i'portantonratioe$ logic J "i.ing o# p%&S tran"i"tor i" not i'portant#or output le)el"#or output le)el"S'aller nu'+er o# tran"i"tor", F2 )" 2S'aller nu'+er o# tran"i"tor", F2 )" 2Larger precharge tran"i"tor re$uce" output #all ti'e, +utLarger precharge tran"i"tor re$uce" output #all ti'e, +ut

increa"e" precharge power a"ter "witching $ue to "'allerincrea"e" precharge power a"ter "witching $ue to "'allercapacitancecapacitanceStatic power J negligi+leStatic power J negligi+leShort-circuit power J noneShort-circuit power J none!yna'ic power !yna'ic power

no glitche" J #ollowing precharge, "ignal" can either 'a@e tran"ition"no glitche" J #ollowing precharge, "ignal" can either 'a@e tran"ition"only in one $irection, 1>0, or no tran"ition, 1>1only in one $irection, 1>0, or no tran"ition, 1>1only logic tran"ition" J all no$e" at logic 0 are charge$ to !! $uringonly logic tran"ition" J all no$e" at logic 0 are charge$ to !! $uringprecharge pha"eprecharge pha"e


14/23


Switching Spee$ an$ ower Switching Spee$ an$ ower

ewer tran"i"tor" 'ean "'aller no$eewer tran"i"tor" 'ean "'aller no$ecapacitancecapacitance

o "hort-circuit current to "low $owno "hort-circuit current to "low $own$i"charging o# capacitance$i"charging o# capacitance&nly $yna'ic power con"u'e$, +ut can&nly $yna'ic power con"u'e$, +ut can+e higher than C%&S+e higher than C%&S


15/23


Logic Acti)ityLogic Acti)ity

ro+a+ility o# 0 > 1 tran"ition(ro+a+ility o# 0 > 1 tran"ition(Static C%&S, p0 p1 : p0*1 J p0Static C%&S, p0 p1 : p0*1 J p0!yna'ic C%&S, p0!yna'ic C%&S, p0 K p0 p1K p0 p1

E a'ple( 2-input &8 gateE a'ple( 2-input &8 gateStatic C%&S, $yn : 0 1=75 CStatic C%&S, $yn : 0 1=75 C LL !!!! 22 # # CDCD!yna'ic C%&S, $yn : 0 75 C!yna'ic C%&S, $yn : 0 75 C LL !!!! 22 # # CDCD

p1 : 0 5

p1 : 0 5

p1 : 0 25 p0 : 0 75


16/23

Copyright Agrawal, 2007Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9ELEC6270 Spring 11, Lecture 9

1616

Charge Lea@ageCharge Lea@age

&utput A

C L

CD

A:0

CD

!!CD

A

i'e

r e c

h a r g e

E ) a

l u a

t e

$eal Actual

? % 8a+aey, A Chan$ra@a"an an$ o@oliB, Digital Integrated Circuits , 4pper Sa$$le 8i)er, ew ?er"ey( ear"on E$ucation, 200


17/23

Copyright Agrawal, 2007Copyright Agrawal, 2007

ELEC6270 Spring 11, Lecture 9ELEC6270 Spring 11, Lecture 9

1717

lee$er ran"i"tor lee$er ran"i"tor

&utput

C L

CD

A

C

!

CD

!!

&utput

C L

CD

A

C

!

CD

!!


18/23

Copyright Agrawal, 2007Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 9ELEC6270 Spring 11, Lecture 9 1=1=

A ro+le'" ith !yna'ic C%&S A ro+le'" ith !yna'ic C%&S

CD

A:0>1

CD

!!CD

A

C

? % 8a+aey, A Chan$ra@a"an an$ o@oliB, Digital Integrated Circuits , 4pper Sa$$le 8i)er, ew ?er"ey( ear"on E$ucation, 200

CD

CD

!!

C

prech e)aluate


19/23


8e'e$y8e'e$y

Set all input" to gate" to 0 $uringSet all input" to gate" to 0 $uringprechargeprechargeSince precharge rai"e" all output" to 1,Since precharge rai"e" all output" to 1,in"erting in)erter" +etween gate" will $oin"erting in)erter" +etween gate" will $othe tric@the tric@


20/23


!o'ino C%&S!o'ino C%&S

CD

A:0>1

CD

!!CD

A

C

8 H Dra'+ec@, C % Lee an$ H - S Law, MHigh-Spee$ Co'pactCircuit" with C%&S,N IEEE J. Solid-State Circuits , )ol SC-17, no ,pp 61 -619, ?une 19=2

CD

CD

!!

C

prech e)aluate


21/23


lee$er in !o'ino C%&Slee$er in !o'ino C%&S

&utput

C L

CD

A

C

!

CD

!!


22/23


Logic %apping #or onin)erting 3ate"Logic %apping #or onin)erting 3ate"

A

C

!

E

3

H

A C

3FH

A !

&8 A !/&8

O

P

P

A C

!E

3FH


23/23


Selecting a Logic StyleSelecting a Logic StyleStatic C%&S( 'o"t relia+le an$ pre$icta+le,Static C%&S( 'o"t relia+le an$ pre$icta+le,rea"ona+le in power an$ "pee$, )oltage "calingrea"ona+le in power an$ "pee$, )oltage "calingan$ $e)ice "i.ing are well un$er"too$an$ $e)ice "i.ing are well un$er"too$a""-tran"i"tor logic( +ene#icial #or 'ultiple era""-tran"i"tor logic( +ene#icial #or 'ultiple eran$ O&8 $o'inate$ circuit" li@e a$$er", etcan$ O&8 $o'inate$ circuit" li@e a$$er", etcor large #anin gate", "tatic C%&S i" ine##icientQor large #anin gate", "tatic C%&S i" ine##icientQa choice can +e 'a$e +etween p"eu$o-n%&S,a choice can +e 'a$e +etween p"eu$o-n%&S,

$yna'ic C%&S an$ $o'ino C%&S$yna'ic C%&S an$ $o'ino C%&S

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lpd_9_pseudoNMOS