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Vol 04, Article 10162; October 2013 International Journal of VLSI and Embedded Systems-IJVES

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Low Power Dissipation of 4 bit Parallel adder/subtractor using

Dual sleep and ground bounce technique in 120nm and 90nm

Technology

T KRISHNA MOORTHY 1, M.BALAJI2, G.NARESH3 1 Department of ECE, Sree Vidyanikethan Engineering College, Tirupati, INDIA.

2,3 Department of ECE, Sree Vidyanikethan Engineering College, Tirupati, INDIA. 1 [email protected] , [email protected] , [email protected]

ABSTRACT

In CMOS circuit, there is a relationship between power consumption and scaling. Leakage power is the major

drawback in the chip designing and is defined as the power consumed by a device not related to state changes

(also referred to as static power). Leakage power is actually consumed when a device is both static and

switching, but generally the main concern with leakage power is when the device is in its inactive state, as all

the power consumed in this state is considered “wasted” power. The power that is consumed by a device when

it is actively switching from one state to another [1]. Dynamic power consists of switching power, consumed

while charging and discharging the loads on a device, and internal power (also referred to as short circuit

power), consumed internal to the device while it is changing state Various techniques have been developed to

reduce both dynamic and leakage power. One of the techniques is dual sleep transistor approach. In this

paper, we have performed the simulation and implementation of 4-bit parallel adder/Subtractor using dual

sleep transistor approach.

Keywords—Low power leakage, delay, full adder cell, Pass transistor.

[1] INTRODUCTION

The most common design style in modern VLSI design is the Static CMOS logic style. Digital circuits can be

operated within fraction of time. If there is any interconnection problem or short circuit occurs between the

blocks which increase the power dissipation in the circuit. In deep submicron technology, the power dissipation

or leakage power will be reduced by using Scaling process [1]. The amount of leakage power is 30 to 50% of

total power consumption. Leakage power reduction is very Important factor in low power design. MOS

technology feature size and threshold voltage have been scaling down for decades for achieving high density

and high performance. As the feature size becomes smaller, shorter channel lengths result Increased Sub-

threshold leakage current through a transistor when it is off. Lower the threshold voltage will increase sub

threshold leakage current in turn leads to static power consumption. There are several techniques to reduce

leakage power. Power gating is one such well known technique where a sleep transistor is added between

actual ground rail and circuit ground (called virtual ground) [2]. In electronics, pass transistor logic (PTL)

reduces the count of transistors used to make different logic gates, by eliminating redundant transistors.

2. FULL ADDER CIRCUITS

Adder is the most important operation in any digital logic design. High speed and accurate operation of any

digital system is influenced by its performance of the adder design. Pseudo NMOS and Pass-transistor logic

can reduce the number of transistors required to implement a given logic function but suffers with power

dissipation. The XOR gate using CMOS inverter and pass transistor and the conventional full adder and full

adder design using dual sleep approach. These circuits are considered as the basic circuits in this paper. The

size of the transistor is defined as a ratio of Width/Length (W/L). Ground bounce noise is estimated when the

circuits are connected with a sleep transistor. Sub-threshold current is directly proportional to the

Width/Length ratio of transistor.

Fig.1. Conventional Full adder design

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The conventional full adder and full adder using dual sleep approach is shown in the Figure 1 and Figure 2.

The width/Length of PMOS is 3 times greater than the width/Length of NMOS transistor in full adder circuit

[3]. The conventional full adder and full adder with dual sleep transistors are considered as basic blocks for 4-

bit parallel adder/Subtractor design. Dual sleep approach is a technique for reducing the leakage power.

Fig.2. Full adder using dual sleep transistor

Fig.3. Power dissipation of conventional and dual sleep method for Full Adder

Fig.4. Delay of conventional and dual sleep method for Full Adder

3. PERFORMANCE ANALYSIS

3.1. Active Power Power dissipated by the circuit when the circuit is in active state is termed as Active power. Input vectors are

fed into the circuit and the average power dissipation is measured. Almost all of the input combinations are

considered for simulation. Same input vector combinations have been given to the all two designs- Paralel

adder/subtractor and dual sleep approach in both 120nm and 90nm technology.

3.2. Standby leakage power Standby leakage power is measured when the circuit is in Standby mode. Dual sleep transistor is connected to

the pull down network and pull up network of 1 bit full adder circuit. Dual Sleep transistor which are connected

to pull down network is on by asserting an input 1v[2]. Size of a sleep transistor is equal tothe size of largest

transistor in the network (pull up or pulldown) connected to the sleep transistor.Leakage power can be reduced

in conventional Parallel adder/Subtractor by using full adder with dual sleep approach method in 120nm and

90nm technology.

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4. PROPOSED DESIGN

4.1. XOR gate using CMOS Inverter

Parallel Adder/Subtractor can be designed with 1-bit full adder and XOR gate. The XOR gate using CMOS

consisting of 4 PMOS and 5 NMOS transistors as shown in the Figure 5.

Fig.5. XOR using CMOS inverter

4.2. Parallel Adder/Subtractor A 4-bit parallel Adder/Subtractor can be implemented with four one bit full adders and 4 one bit xor gates.

Parallel adder/subtractor has one control signal SUB. If SUB is 0, then circuit works as an addition else

subtraction operation will be performed. The conventional and dual sleep approach parallel adder/Subtractor

design shown in the below Figures

Fig.6. Conventional Parallel adder/Subtractor design

Fig.7. Parallel adder/Subtractor using dual sleep approach

5. SIMULATION RESULTS

Fig.8. Simulated waveform of XOR gate

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Fig.9. Simulated waveform of Conventional Full adder

Fig.10. Simulated waveform of full adder with dual sleep approach

Fig.11. Simulated waveform of Conventional Parallel Adder/Subtractor

Fig.12. Layout for Conventional Parallel adder/Subtractor design

Fig.13. Simulated waveform of Parallel Adder/Subtractor using dual sleep transistor

Fig.14. Layout for Parallel adder/Subtractor using dual sleep approach

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Fig.15. Power dissipation of Conventional and dual sleep approach for Parallel adder/Subtractor

Fig.16. Delay of Conventional and dual sleep approach for Parallel adder/subtractor

CONCLUSION

Leakage power is actually consumed when a device is both static and switching, but generally the main

concern with leakage power is when the device is in its inactive state. Dynamic power consists of switching

power, consumed while charging and discharging the loads on a device, and internal power (also referred to

as short circuit power), consumed internal to the device while it is changing state Various techniques have

been developed to reduce both dynamic and leakage power. One of the technique is dual sleep transistor

approach. We have designed dual sleep approach for 4 bit parallel adder/subtractor to reduces the amount of

leakage power compare with the conventional 4-bit parallel adder/Subtractor.

REFERENCES

[1]. Y Jagadeesh, T Krishnamurthy, ”Four-Bit Cmos Full Adder Design in Submicron Technology with Low

Leakage Power and Ground Bounce Noise Reduction Using Dual Sleep Approach“ in IJCA&IT, Vol. 2, Issue

II Feb-March 2013.

[2]. K.Navi, O. Kavehei, M. Rouholamini, A. Sahafi, S. Mehrabi, N.Dadkhai, "Low-Power and High-

Performance I-bit CMOS Full Adder Cell",Journal of Computers, Academy Press, vol. 3, no. 2, Feb. 2008.

[3] J.C. Park, V. J. Mooney III and P. Pfeiffenberger,“Sleepy Stack Reduction of Leakage Power,” Proceeding

of the International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 148-158,

September 2004.

[4].S G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies. New York: Springer-

verlag, 2006.

[5] N.West. K.Eshragian, Principles of CMOS V LSI Design: A systems Perspective, Addison-wesley, 1993.

[6] Ku He, Rong Luo, Yu Wang, "A Power Gating Scheme for Ground Bounce Reduction During Mode

Transition, " in ICCD07, pp. 388-394,2007.

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Low Power Dissipation of 4 bit Parallel adder/subtractor ...ijves.com/wp-content/uploads/2012/07/IJVES-Y13-10162.pdf · Keywords—Low power leakage, delay, full adder cell, ... V