low power

5/27/2018 low power

1/51 Digital Integrated Circuits2nd Inverter

POWER

Introduction to Low P

VLSI Design

Dr Anu Mehra

5/27/2018 low power


Where Does Power Go in C

Dynamic Power Consumption

Short Circuit Currents

Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Sw

Leaking diodes and transistors

5/27/2018 low power


Power dissipation can be

dynamic

due to capacitive switching

short circuit power due to crowbar curr

Glitches in output waveform

Static

leakage currents

sub threshold current + reverse bias

standby current pseudo nmos

5/27/2018 low power


Dynamic Power

Charging and discharging o

capacitors due to logic

switching event

5/27/2018 low power


Each time the input switches fro

or 1 to 0 power is consumed.

PART IS DISSPATED in charging adischarging the capacitor

PART IS STORED in the load capaci

5/27/2018 low power


Dynamic Power Dissipat

Energy/transition = CL* V

dd

2

Power = Energy/transition *f = CL* V

dd

2* f

0 to1 or 1 to 0

Need to reduce CL, V

dd, andfto reduce power.

Vin Vout

CL

Vdd

Not a function of transistor sizes!

iVDD

f0 to1 or 1 to 0is the frequency of transition

5/27/2018 low power


2

000

)(DDL

VDD

outDDL

out

LDDDDVDDVDD VCdvVCdt

dt

dvCVdtVtiE

2

)(

2

000

DDL

VDD

outoutLout

out

LoutVDDC

VCdvvCdtv

dt

dvCdtvtiE

Half the energy stored in the Capacito

the other half is lost !

5/27/2018 low power


Node Transition Activ

Consider switching a CMOS gate forN clock cycles

EN

CL Vdd

2n N =

n(N ): the number of 0->1 transition inN clock cycles

EN: the energy consumed forN clock cycles

Pavg

N

lim

EN

N-------- f

clk=

n N

N------------

N

lim

C

L

Vdd

2fclk

=

0 1

n N

N------------

N

lim=

Pavg

= 0 1

CL

Vdd

2fclk

5/27/2018 low power


Transistor Sizing for

A quick review of delay

5/27/2018 low power


Delay Formula

Cint= gCginwithg 1

f= Cext/Cgin- effective fanoutCext=fC

gin

R = Runit/W ; C

int=WC

unit

tp 0= 0.69R

unitCunit

Let tp=0.69 Req(Cint+Cext)

=0.69 ReqCint(1+Cext/Cint)

=tp0(1+Cext/Cint)

=tp0(1+f/g)

5/27/2018 low power


Transistor Sizing fo

Energy

Goal: Minimize Energy of wholDesign parameters:fandV

DD

tp tpref of circuit withf=1 andVDD=V

ref

1Cg1

In

fCext

Out

TEDD

DD

p

pp

VV

Vt

fFftt

0

0 11gg

5/27/2018 low power


Delay as a function of VDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD(V)

tp

(norm

alized)

5/27/2018 low power

13/51

Digital Integrated Circuits2nd Inverter

Total Capacitance of inverter c

Cg1+Cint1+Cext1+Cint2+Cext2

=Cg1+gCg1+fCg1+fgCg1+FCg1

=Cg1(1+g ffg F)

E=VDD

2(totalcapacitance)

5/27/2018 low power

14/51


Transistor Sizing (2

Performance Constraint (g=1)

Energy for single Transition

1

3

2

3

2

0

0

F

f

Ff

VV

VV

V

V

F

f

Ff

t

t

t

t

TEDD

TEref

ref

DD

refp

p

pref

p

F

Ff

V

V

E

E

FfCVE

ref

DD

ref

gDD

4

22

11

2

1

2

g

5/27/2018 low power

15/51

5/27/2018 low power

16/51


ref

DD

TEDD

TEref

TEref

ref

TEDD

DD

V

V

VV

VV

reftp

tp

VV

V

reftp

VV

V

tp

Freftp

f

Fftp

tpref

tp

Freftptpref

0

0

0

0

30

20

30

5/27/2018 low power

17/51


1 2 3 4 5 6 7

0

0.5

1

1.5

2

2.5

3

3.5

4

f

vdd

(V

)

1 2 3 4 5 6 7

0

0.5

1

1.5

f

norm

alized

energy

Transistor Sizing (3

F=1

2

5

10

20

VDD=f(f) E/Eref=f(f)

5/27/2018 low power

18/51

5/27/2018 low power

19/51

5/27/2018 low power

20/51


Short Circuit Curren- another ap

Rise/Fall time of input wave is greater than 0, so short

circuit current will flow

Let VTn=VTp=VT

Consider 0 to 1 transition. Initially when Vin was 0,

pmos was on and nmos was off

As point 1 approaches nmos is turned on as Vin =VT.

pmos is still on

Short circuit current flows from VDD to GND

Current increases to maximum when both devices

enter saturation

As point 2 approaches, pmos shuts down, crowbar

current stops flowing

VT

VDD-VT

1 2 time

voltage

5/27/2018 low power

21/51


Direct Path currents con

Area of an equilateral triangle is

1/2base. perpendicularP=VI, E=Pt

5/27/2018 low power

22/51

5/27/2018 low power

23/51


How to minimize crowbar

Consider a CMOS inverter with a 0 to 1 transition at the input

Let C Lbe very large

Thus, output will make a a 1 to 0 transition t f=0.69R

NCL

This delay will also be large

Assume that input rise time is very small

Input will change through transition before output changes

Vs of pmos is at VDD

VD of pmos will be approximately at VDD

Thus VDS of pmos is approx 0

Device shuts off before delivering any current

5/27/2018 low power

24/51


How to minimize crowbar

Consider again a CMOS inverter with a 0 to 1 transition at theinput

Let C Lbe very small

Thus, output will make a a 1 to 0 transition t f=0.69R

NCL

This delay will also be small

Assume that input rise time is very large

Input will change through transition slowly

Vs of pmos is at VDD

VD of pmos will be approximately at 0

Thus VDS of pmos is approx VDD

Maximum short circuit current is

delivered

5/27/2018 low power

25/51


Short Circuit Curren

Vin Vout

CL

Vdd

IVD

D

(m

A

)

0.15

0.10

0.05

Vin(V)

5.04.03.02.01.00.0

5/27/2018 low power

26/51


How to keep Short-Circuit Cur

Short circuit current goes to zero if tfall>> t

rise,

but can t do this for cascade logic, so ..

Input

slope isfixed

5/27/2018 low power

27/51


Conclusion

Large CLmay mean less short circuit power, but it

will also mean longer delays

Will lead to short circuit currents in fan out gate as

their tin will be slow!!

Local Optimization pointless!

To minimize power consumption in a global way

Match rise/fall times of input and

output waveforms

5/27/2018 low power

28/51


Minimizing Short-Cir

0 1 2 3 4 5

0

1

2

3

4

5

6

7

8

tsin/tsout

Pnorm

Vdd =1.5

Vdd =2.5

Vdd =3.3

5/27/2018 low power

29/51

5/27/2018 low power

30/51


Dynamic Power -GlitchesGlitches are caused by arrival time oftwo separate input signals. If a given

input signal arrives first and causes the output to switch, later another

signal arrives and causes the output to switch back to original value.

Undesired Power dissipation ! Glitches propagate thought the fanout ga

cause further unintended transitions

5/27/2018 low power

31/51

5/27/2018 low power

32/51


Static Power Consumptio

Caused by leakage currents due to

Reverse biased Source and drain jun

Subthreshold currents and ie curre

flow when VGS is less than VT

5/27/2018 low power

33/51


Leakage

Vout

Vdd

Sub-Threshold

Current

Drain Junction

Leakage

Sub-threshold current one of most co

in low-energy circuit design!

5/27/2018 low power

34/51


Reverse-Biased Diode Lea

Np+ p

+

Reverse Leakage Current

+

-

Vdd

GATE

IDL = JS A

JS = 10-100 pA/m2 at 25 deg C for 0.25m CMOS

JSdoubles for every 9 deg C!

5/27/2018 low power

35/51

5/27/2018 low power

36/51


Subthreshold Leakage Com

5/27/2018 low power

37/51

5/27/2018 low power

38/51


Delay as a function of VDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD(V)

tp

(norm

alized)

VT=0.5V

5/27/2018 low power

39/51


Static Power Consumptio

Vin=5V

Vout

CL

Vdd

Istat

Pstat= P (In=1).Vdd. Istat

Wasted energy

Should be avoided in almost all cases,

but could help reducing energy in other

5/27/2018 low power

40/51


Principles for Power R

Prime choice: Reduce voltage!

Recent years have seen an accelera

supply voltage reduction

Design at very low voltages stillquestion (0.6 0.9 V by 2010!)

Reduce switching activity

Reduce physical capacitanceDevice Sizing: forF=20

fopt(energy)=3.53,f

opt(performance)=4.47

5/27/2018 low power

41/51


Modification for Circuits with

CL

Vdd

Vdd

Vdd-V

t

E0 1

CL Vdd

Vdd

Vt

=

Can exploit reduced swing to lower p

(e.g., reduced bit-line swing in me

5/27/2018 low power

42/51

5/27/2018 low power

43/51


POWER DELAY TRADE OFF

We want low power and small delay. Why not minimize th

Pavgis average Power consum

tpis average delay

Only dominant term

in Power Equation

Assume Gate switches at

maximum possible rate so rise

and fall

5/27/2018 low power

44/51


To Reduce PDP

Reduce Load Capacitance

Reduce Supply Voltage

PDP does not capture the fact that reducing

Supply Voltage lowers Power consumption,

but increases delay

New metric Energy Delay Product is defined

(EDP)

EDP=PDP tp

5/27/2018 low power

45/51


Differentiating EDp w.r.t. VDDand

putting the result equal to 0

5/27/2018 low power

46/51

S S SS T

5/27/2018 low power

47/51


LPVD Lecture-1

Three com ponents :

Dynamic Capacitive (Switching) Power:

- Charging and Discharging the capacitan

- Still dominant component in current t

Short-circuit Power:

- Due to current flow from Vdd to GND.

- Worst in case of slow transition.

Leakage Current:

- Diodes L eakage around transistor and N-

- Increases 20 times for each new technolo

- Becoming insignificant to the domina.

SOURCES OF POWER DISSIPATI

R R S

5/27/2018 low power

48/51


LPVD Lecture-1

Reduced switching voltage:

- P=CfV2Saving in power but p erformance is l

- Transistors become slow due to low V t, leakage

current increases. Noise margins prob

Reduced leakage and Static Current:

- Can be reduce by transistor sizing, layou

and careful circuit design.

- Circuit models can be turned off if not in

Use Standby Mode :

- Clock disabling and power-off of selectblocks.

LOW POWER APPROACHES

5/27/2018 low power

49/51

5/27/2018 low power

50/51

5/27/2018 low power

51/51

Documents

low power