15

Low Power Project

Embed Size (px)

DESCRIPTION

mcc adder with cadence

Citation preview

Page 1: Low Power Project
Page 2: Low Power Project

MANCHESTER CARRY CHAIN ADDER

A single block of MCC consists of three main cell types identified as Propagate, Generate, Annihilate (kill) and a full adder. The NOR and AND functions (Kill and Generate) are implemented in static CMOS logic. For each input bit(Ai and Bi),carry-propagate(Pi),carry-generate(Gi),carry-annihilate (Ani) and sum(Si) is calculated. These signals are given by the following Boolean expressionsPi=Ai XOR BiGi=Ai AND BiAni=Ai NOR BiSi=Ai XOR Bi XOR Ci where Ci is the input carry. A one stage MCC can be conceptually analyzed as having three switches, each manipulated by control signals, Gi, Pi and Ani. From the expressions of the above mentioned control signals it is clear that at any time, only one of the three signals will be at logic ‘1’. The carry out signal is connected to Ci(carry in) when Pi is at logic ‘1’. The carry out signal is connected to logic ‘1’ when Gi is at logic ‘1’ irrespective of Ci. Similarly when Ani is at logic ‘1’ then carry out becomes logic ‘0’ that is carry is killed.

Page 3: Low Power Project

Schematics and result of different components1.Ani block

(Ani schematic)

(Ani symbol)

Page 4: Low Power Project

(Ani output)

2.Pi block

(Pi schematic)

Page 5: Low Power Project

(Pi symbol)

(Pi output)

3.Gi BAR block

Page 6: Low Power Project

(Gi bar schematic)

(Gi bar symbol)

Page 7: Low Power Project

(Gi bar output)

4. Full adder block

(Full adder schematic)

Page 8: Low Power Project

(Full adder symbol)

(Full adder output)

Page 9: Low Power Project

5.Invereter block

(Inverter schematic)

Page 10: Low Power Project

(Inverter output)6.Single bit MCC block

(Single bit MCC adder schematic)

Page 11: Low Power Project

(Single bit MCC adder symbol)

(Single bit MCC adder output)

Page 12: Low Power Project

4-bit MCC adder block

(4-Bit MCC adder schematic)

(Final output section 1)

Page 13: Low Power Project

(Final output section 2)

(Final output section 3)