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Low Latency Ethernet 10G MACIntel® Arria® 10 FPGA IP DesignExample User Guide
Updated for Intel® Quartus® Prime Design Suite: 19.1
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UG-20016 | 2019.09.23Latest document on the web: PDF | HTML
Contents
1. Quick Start Guide............................................................................................................51.1. Directory Structure................................................................................................ 61.2. Generating the Design............................................................................................8
1.2.1. Procedure.................................................................................................81.2.2. Design Example Parameters........................................................................9
1.3. Compiling and Simulating the Design......................................................................101.3.1. Procedure............................................................................................... 101.3.2. Testbench............................................................................................... 11
1.4. Compiling and Testing the Design in Hardware.........................................................121.4.1. Procedure............................................................................................... 121.4.2. Hardware Setup.......................................................................................13
2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices..................... 142.1. Features............................................................................................................. 142.2. Hardware and Software Requirements.................................................................... 142.3. Functional Description.......................................................................................... 15
2.3.1. Design Components................................................................................. 152.3.2. Clocking Scheme..................................................................................... 182.3.3. Reset Scheme......................................................................................... 19
2.4. Simulation.......................................................................................................... 202.4.1. Test Case—Design Example with the IEEE 1588v2 Feature.............................212.4.2. Test Case—Design Example without the IEEE 1588v2 Feature........................ 22
2.5. Hardware Testing.................................................................................................232.5.1. Test Cases.............................................................................................. 242.5.2. Signal Tap Debug Signals.......................................................................... 25
2.6. Interface Signals..................................................................................................282.7. Configuration Registers.........................................................................................29
3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices........................................ 303.1. Features............................................................................................................. 303.2. Hardware and Software Requirements.................................................................... 303.3. Functional Description.......................................................................................... 31
3.3.1. Design Components................................................................................. 313.3.2. Clocking Scheme..................................................................................... 333.3.3. Reset Scheme......................................................................................... 34
3.4. Simulation.......................................................................................................... 353.4.1. Test Case—Design Example with the IEEE 1588v2 Feature.............................363.4.2. Test Case—Design Example without the IEEE 1588v2 Feature........................ 37
3.5. Hardware Testing.................................................................................................383.5.1. Test Cases.............................................................................................. 393.5.2. Signal Tap Debug Signals.......................................................................... 40
3.6. Interface Signals..................................................................................................423.7. Configuration Registers.........................................................................................43
4. 10GBASE-R Ethernet Design Example for Intel Arria 10 Devices...................................444.1. Features............................................................................................................. 444.2. Hardware and Software Requirements.................................................................... 444.3. Functional Description.......................................................................................... 45
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4.3.1. Design Components................................................................................. 454.3.2. Clocking and Reset Scheme.......................................................................46
4.4. Simulation.......................................................................................................... 474.5. Hardware Testing.................................................................................................47
4.5.1. Test Cases.............................................................................................. 484.5.2. Signal Tap Debug Signals.......................................................................... 49
4.6. Interface Signals..................................................................................................504.7. Configuration Registers.........................................................................................50
5. 1G/2.5G Ethernet Design Example for Intel Arria 10 Devices....................................... 515.1. Features............................................................................................................. 515.2. Hardware and Software Requirements.................................................................... 515.3. Functional Description.......................................................................................... 52
5.3.1. Design Components................................................................................. 535.3.2. Clocking Scheme..................................................................................... 545.3.3. Reset Scheme......................................................................................... 565.3.4. Partial Reconfiguration Ready.................................................................... 57
5.4. Simulation.......................................................................................................... 605.4.1. Test Case—Design Example with the IEEE 1588v2 Feature.............................605.4.2. Test Case—Design Example without the IEEE 1588v2 Feature........................ 61
5.5. Hardware Testing.................................................................................................625.5.1. Test Procedure.........................................................................................62
5.6. Interface Signal...................................................................................................655.7. Configuration Registers.........................................................................................66
6. 1G/2.5G/10G Ethernet Design Example for Intel Arria 10 Devices............................... 676.1. Features............................................................................................................. 676.2. Hardware and Software Requirements.................................................................... 676.3. Functional Description.......................................................................................... 67
6.3.1. Design Components................................................................................. 686.3.2. Clocking Scheme..................................................................................... 696.3.3. Reset Scheme......................................................................................... 696.3.4. Partial Reconfiguration Ready.................................................................... 706.3.5. Timing Constraints................................................................................... 71
6.4. Simulation.......................................................................................................... 726.5. Hardware Testing.................................................................................................73
6.5.1. Test Procedure.........................................................................................746.6. Interface Signals..................................................................................................766.7. Configuration Registers.........................................................................................76
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel Arria10 Devices............................................................................................................... 787.1. Features............................................................................................................. 787.2. Hardware and Software Requirements.................................................................... 787.3. Functional Description.......................................................................................... 78
7.3.1. Design Components................................................................................. 797.3.2. Clocking Scheme..................................................................................... 807.3.3. Reset Scheme......................................................................................... 80
7.4. Simulation.......................................................................................................... 817.4.1. Test Case................................................................................................81
7.5. Hardware Testing.................................................................................................827.5.1. Test Procedure.........................................................................................83
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7.6. Interface Signals..................................................................................................867.7. Configuration Registers.........................................................................................86
8. Interface Signals Description........................................................................................888.1. Clock and Reset Interface Signals.......................................................................... 888.2. Avalon-MM Interface Signals................................................................................. 898.3. Avalon-ST Interface Signals...................................................................................908.4. PHY Interface Signals........................................................................................... 938.5. Status Interface...................................................................................................938.6. IEEE 1588v2 Timestamp Interface Signals...............................................................948.7. Packet Classifier Interface Signals.......................................................................... 958.8. ToD Interface Signals........................................................................................... 96
9. Configuration Registers Description..............................................................................979.1. Register Access Definition..................................................................................... 979.2. Low Latency Ethernet 10G MAC............................................................................. 979.3. PHY..................................................................................................................101
9.3.1. 1G/10G PHY.......................................................................................... 1019.3.2. 1G/2.5G/5G/10G Multi-rate PHY...............................................................103
9.4. Transceiver Reconfiguration................................................................................. 1099.5. TOD................................................................................................................. 109
10. Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example UserGuide Archives.......................................................................................................111
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel Arria 10FPGA IP Design Example User Guide..................................................................... 112
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1. Quick Start GuideThe Low Latency 10G Ethernet (LL 10GbE) MAC Intel® FPGA IP core for Intel Arria®
10 devices provides the capability of generating design examples for selectedconfigurations.
Figure 1. Development Stages for the Design Example
DesignExample
Generation
Compilation(Simulator)
FunctionalSimulation
Compilation(Quartus Prime)
HardwareTesting
Related Information
• 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices on page14
Provides details on the 10M/100M/1G/10G Ethernet design examples.
• 1G/10G Ethernet Design Example for Intel Arria 10 Devices on page 30Provides details on the 1G/10G Ethernet design examples.
• 10GBASE-R Ethernet Design Example for Intel Arria 10 Devices on page 44Provides details on the 10GBASE-R Ethernet design examples.
• 1G/2.5G Ethernet Design Example for Intel Arria 10 Devices on page 51Provides details on the 1G/2.5G Ethernet design examples.
• 1G/2.5G/10G Ethernet Design Example for Intel Arria 10 Devices on page 67Provides details on the 1G/2.5G/10G Ethernet design example.
• 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel Arria10 Devices on page 78
Provides details on the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernetdesign example.
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
1.1. Directory Structure
Figure 2. Directory Structure for the Design Example
<Design Example>
rtl
altera_eth_multi_channel.sv
altera_eth_channel.sv
<Design Component>
<Design Component>
altera_eth_top.svaltera_eth_top.sdcaltera_eth_top.sof
altera_eth_top.qpfaltera_eth_top.qsfsimulation
models
hwtesting
system_console
output_files
ed_sim
cadence
mentor
synopsys
vcs
xcelium
Note: Xcelium* simulator is supported in Intel Quartus® Prime Pro Edition software only.
Table 1. Directory and File Description
Directory/File Description
altera_eth_top.qpf Intel Quartus Prime project file.
altera_eth_top.qsf Intel Quartus Prime settings file.
altera_eth_top.sv Design example top-level HDL.
altera_eth_top.sdc Synopsys Design Constraints (SDC) file.
rtl The folder that contains the design example synthesizable components.
rtl/altera_eth_10g_mac_base_r.sv
rtl/altera_10g_mac_base_r_wrap.v
Design example DUT top-level files for 10GBASE-R Ethernet design example.
rtl/altera_mge_rd.sv
rtl/altera_mge_channel.v
Design example DUT top-level files for the following Ethernet design examples:• 1G/2.5G with 1588v2 feature• 1G/2.5G/10G
rtl/altera_eth_channel.v
rtl/altera_eth_multi_channel.sv
Design example DUT top-level files for the following Ethernet design examples:• 10M/100M/1G/10G• 1G/10G
rtl/altera_eth_channel_1588.v
rtl/altera_eth_multi_channel_1588.sv
Design example DUT top-level files for the following Ethernet design examples:• 10M/100M/1G/10G with with 1588v2 feature• 1G/10G with 1588v2 feature
rtl/altera_mge_multi_channel.sv
rtl/altera_mge_channel.v
Design example DUT top-level files for 10M/100M/1G/2.5G/5G/10G (USXGMII)Ethernet design example.
rtl/<Design Component> The folder for each synthesizable component including Platform Designergenerated IPs, such as LL 10GbE MAC, PHY, and FIFO.
simulation/ed_sim/models The folder that contains the testbench files.
continued...
1. Quick Start Guide
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Directory/File Description
simulation/ed_sim/cadence
simulation/ed_sim/mentor
simulation/ed_sim/synopsys/vcs
simulation/ed_sim/xcelium
The folder that contains the simulation script. It also serves as a working area forthe simulator.
hwtesting/system_console The folder that contains system console scripts for hardware testing.
output_files The folder that contains Intel Quartus Prime output files including Intel QuartusPrime compilation reports and design programing file (.sof file).
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1.2. Generating the Design
1.2.1. Procedure
You can generate the design example from the IP Parameter Editor.
Start ParameterEditor
Specify IP Variationand Select Device
SelectDesign Parameters
InitiateDesign Generation
Specify Example Design
Figure 3. Example Design Tab
InitiatesDesignGeneration
PresetLibrary
1. Select Tools ➤ IP Catalog to open the IP Catalog and select Low LatencyEthernet 10G MAC Intel FPGA IP.The IP parameter editor appears.
2. Specify a top-level name and the folder for your custom IP variation, and thetarget device. Click OK.
3. To generate a design example, select a design example preset from the Presetslibrary and click Apply. When you select a design, the system automaticallypopulates the IP parameters for the design.
The Parameter Editor automatically sets the parameters required to generate thedesign example. Do not change the preset parameters in the IP tab.
4. Specify the parameters in the Example Design tab.
5. Click the Generate Example Design button.
The software generates all design files in sub-directories. You require these files to runsimulation, compilation, and hardware testing.
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Related Information
Directory Structure on page 6Provides more information about the generated design example directories andfiles.
1.2.2. Design Example Parameters
Table 2. Parameters in the Example Design Tab
Parameter Description
Select Design Available example designs for the IP parameter settings. When youselect an example design from the Preset library, this field shows theselected design.
Example Design Files The files to generate for the different development phase.• Simulation—generates the necessary files for simulating the example
design.• Synthesis—generates the synthesis files. Use these files to compile
the design in the Intel Quartus Prime software for hardware testingand perform static timing analysis.
Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board Supported hardware for design implementation. When you select anIntel FPGA development board, the Target Device is the one thatmatches the device on the Development Kit.If this menu is not available, there is no supported board for the optionsthat you select.Intel Arria 10 GX Transceiver Signal Integrity Development Kit:This option allows you to test the design example on the selected IntelFPGA IP development kit. This option automatically selects the TargetDevice to match the device on the Intel FPGA IP development kit. If yourboard revision has a different device grade, you can change the targetdevice.Custom Development Kit: This option allows you to test the designexample on a third party development kit with Intel FPGA IP device, acustom designed board with Intel FPGA IP device, or a standard IntelFPGA IP development kit not available for selection. You can also select acustom device for the custom development kit.No Development Kit: This option excludes the hardware aspects forthe design example.
Change Target Device Select this parameter to display and select all devices for the Intel FPGAIP development kit.
Specify Number of Channels The number of Ethernet channels.
Enable Native PHY Debug Master Endpoint(NPDME)
Turn on this option to enable the Transceiver Native PHY Debug MasterEndpoint (NPDME) feature.Note: This option is only available from Intel Quartus Prime Pro Edition
version 17.0 onwards
Partial Reconfiguration Ready When this option is enabled, the generated hierarchy of the designexample is compliance with the partial reconfiguration flow, where thereis clear separation between hard IP and soft IP, without any functionalitychanges. Hard IPs such as Native PHY, JTAG, transmitter PLL, and FPLLare instantiated at the top-level wrapper of design example.Note: This option is only available from Intel Quartus Prime Pro Edition
version 17.1 onwards
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1.3. Compiling and Simulating the Design
1.3.1. Procedure
You can compile and simulate the design by running a simulation script from thecommand prompt.
Change to Testbench Directory
Run<Simulation Script>
AnalyzeResults
1. At the command prompt, change the working directory to <Example Design>\simulation\ed_sim\<Simulator>.
2. Run the simulation script for the simulator of your choice.
Simulator Working Directory Command
ModelSim* <Example Design>/simulation/ed_sim/mentor vsim -c -do tb_run.tcl
VCS* <Example Design>/simulation/ed_sim/synopsys/vcs
sh tb_run.sh
NCSim <Example Design>/simulation/ed_sim/cadence sh tb_run.sh
Xcelium (1) <Example Design>/simulation/ed_sim/xcelium sh tb_run.sh
A successful simulation ends with the following message:
Simulation stopped due to successful completion! Simulation passed.
After successful completion, you can analyze the results.
(1) Xcelium simulator is supported in Intel Quartus Prime Pro Edition software only.
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1.3.2. Testbench
Figure 4. Block Diagram of the Testbench
Avalon-MMControlRegister
Avalon-STTransmit
FrameGenerator
Avalon-STReceiveFrame
Monitor
EthernetPacket
Monitor
avalon_bfm_wrapper.sv
Avalon Driver
Channel 0
Channel 1
Ordinary Clock
EthernetPacket
Monitor
Loopbackon Serial
DUT
TX data
RX data
Testbench
Avalon-MM
Channel n-1
Channel n
.
.
.
Table 3. Testbench Components
Component Description
Device under test (DUT) The design example.
Avalon driver Consists of Avalon-ST master bus functional models (BFMs). This driverforms the TX and RX paths. The driver also provides access to theAvalon-MM interface of the DUT.
Ethernet packet monitors Monitor TX and RX datapaths, and display the frames in the simulatorconsole.
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1.4. Compiling and Testing the Design in Hardware
1.4.1. Procedure
You can compile and test the design in the supported Intel FPGA development kit.
Compile Designin Quartus Prime
Software
Set up Hardware Program Device Test Designin Hardware
1. Launch the Intel Quartus Prime software and open the design example project file.Select Processing ➤ Start Compilation to compile the design example.
The timing constraints for the design example and the design components areautomatically loaded during compilation.
2. Connect the development board to the host computer.
3. Launch the Clock Control application, which is part of the development kit, and setnew frequencies for the design example.
Note: For the frequencies to set, refer to the Hardware Testing section in therespective design example chapter.
4. In the Intel Quartus Prime software, select Tools ➤ Programmer to configurethe FPGA on the development board using the generated .sof file.
5. Reset the system by pressing the PB0 push button.
6. In the Intel Quartus Prime software, select Tools ➤ System Debugging Tools ➤System Console to launch the system console.
7. Change the working directory to <Example Design>\hwtesting\system_console.
8. Initialize the design command list by running this command: source main.tcl.
Note: For a design example that does not provide the main.tcl file, refer to theHardware Testing section in the respective design example chapter.
You can now run any of the predefined hardware tests from the System Console.
Observe the test results displayed.
Related Information
Intel Arria 10 GX Transceiver Signal Integrity Development Kit Webpage
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1.4.2. Hardware Setup
Figure 5. Block Diagram of the Hardware Setup
Intel Arria 10 GX Transceiver Signal Integrity Development Board
JTAG TAPController
SystemController
Ethernet Frame Generation& Monitoring (Master) Ethernet Channel 0
Ethernet Frame Generation& Monitoring (Slave)
Ethernet Channel 1
Ethernet Frame Generation& Monitoring Ethernet Channel n - 1
Ethernet Frame Generation& Monitoring
Ethernet Channel n
Intel Arria 10 GX FPGA
Intel SystemConsole
Software
PC
(1)
(2)
(1)(2)
Use this type of loopback to test IEEE 1588v2 features.Use this type of loopback to test features other than IEEE 1588v2.
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2. 10M/100M/1G/10G Ethernet Design Example for IntelArria 10 Devices
The 10M/100M/10G/10G Ethernet design example demonstrates the functionalities ofthe LL 10GbE MAC Intel FPGA IP core operating at various speeds.
Generate the design example from the Example Design tab of the LL 10GbE IntelFPGA IP parameter editor. You can choose to generate the design with or without theIEEE 1588v2 feature.
2.1. Features
• Multi-speed Ethernet operation—10M, 100M, 1G, and 10G.
• Support for up to 12 channels.
• Packet monitoring on the TX and RX datapaths.
• Option to generate the design example with the IEEE 1588v2 feature.
• Tested with the Spirent TestCenter.
2.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linuxsystem:
• Intel Quartus Prime software
• ModelSim-AE, ModelSim-SE, NCSim (Verilog only), VCS, and Xcelium (IntelQuartus Prime Pro Edition only) simulators
• Intel Arria 10 GX Transceiver Signal Integrity Development Kit for hardwaretesting
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
2.3. Functional Description
The design examples consist of various components. The following block diagramsshow the design components and the top-level signals of the design examples.
Figure 6. Block Diagram—10M/100M/1G/10G Ethernet Design Example without IEEE1588v2 Feature
Input Clock Reset
Avalon-ST
Multi-channel Address Decoder
Avalon-MM
Avalon-MMMaster
FIFO
LL 10GbE MAC
PHY
Transceiver ResetController
ATX PLL fPLL
TX/RXSerialData
Ethernet channel n
Ethernet channel 0
PLLReset
Controller
Multi-channel Wrapper
Generated with Platform DesignerGenerated with IP Catalog
Address Decoder
Adapter
Adapter
(altera_eth_multi_channel)
(address_decoder_multi_channel)
(address_decoder_channel)
(altera_eth_channel)
(altera_eth_channel)
S
S
S
M
Avalon-MMMasterS M
Figure 7. Block Diagram—10M/100M/1G/10G Ethernet Design Example with IEEE1588v2 Feature
Input Clock Reset
Avalon-ST
Multi-channel Address Decoder
Avalon-MM
Address Decoder
PTP PacketClassifier
LL 10GbE MAC
PHY
TransceiverReset Controller
ATX PLL fPLL
TX/RXSerialData
Ethernet channel n
Ethernet channel 0
PLL ResetController
LocalTOD
Pulse PerSecond
TODSync
Pulse PerSecond
MasterTOD
MasterPulse PerSecond
1G/10G Pulse Per SecondIEEE 1588v2Timestamp
Generated from Platform DesignerGenerated from IP Catalog
Multi-channel Wrapper
Adapter
Adapter
(altera_eth_multi_channel_1588)
(address_decoder_multi_channel)
(altera_eth_channel_1588)
(altera_eth_channel_1588)
(address_decoder_channel)
Avalon-MMMasterS M
Avalon-MMMasterS M
S
S
S
S
2.3.1. Design Components
Table 4. Design Components
Component Description
LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration:
continued...
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Component Description
• Speed: 10M/100M/1G/10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• All Legacy Ethernet 10G MAC Interfaces options: SelectedFor the design example with the IEEE 1588v2 feature, the following additional parameters areconfigured:• Enable time stamping: Selected• Enable PTP one-step clock support: Selected• Timestamp fingerprint width: 4• Time Of Day format: Enable both 96b and 64b Time of Day Format
PHY The 1G/10G and 10GBASE-KR PHY Intel Arria 10 FPGA IP. The design example uses the 1G/10GIP variant.
Address decoder Decodes the addresses of the components in each Ethernet channel.
Multi-channel addressdecoder
Decodes the addresses of the components used by all channels, such as the Master TOD module.
Reset controller Synchronizes the reset of all design components.
Transceiver ResetController
The Transceiver PHY Reset Controller Intel FPGA IP core. Resets the transceiver.
PLL Generates clocks for all design components.
ATX PLL Generates a TX serial clock for the Intel Arria 10 10G transceiver.
fPLL Generates a TX serial clock for the Intel Arria 10 1G transceiver.
MDIO Provides an MDIO interface to the external PHY.
FIFO The Avalon® Streaming (Avalon-ST) single-clock FIFO. Buffers the RX and TX data between theMAC IP core and the client. The default depth is 512. To increase the depth of the FIFO, changethe DC_FIFO_DEPTH and SC_FIFO_DEPTH parameter values from 512 to 2048, underaltera_eth_fifo instance in <Example Design>/rtl/altera_eth_channel.sv.
Design Components for the IEEE 1588v2 Feature
Master TOD The master TOD for all channels.
TOD Sync Synchronizes the Master TOD to all Local TODs.
Local TOD The TOD for each channel.
Master Pulse PerSecond
Returns pulse per second (pps) for all channels.
Pulse Per Second Returns pulse per second (pps) for each channel.
PTP packet classifier Decodes the packet type of incoming PTP packets and returns the decoded information to the LL10GbE MAC Intel FPGA IP core.
Related Information
• Low Latency Ethernet 10G MAC Intel FPGA IP Core User GuideFor more information on the MAC parameters.
• Intel Arria 10 Transceiver PHY User GuideFor more information on the PHY parameters.
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• KDB Link: Why do I see underflow errors when receiving Jumbo frames on theLow Latency Ethernet 10G MAC Design Examples?
External FIFO buffer limitation for Intel Arria 10 Low Latency Ethernet 10GMAC Design Example.
2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices
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2.3.2. Clocking Scheme
The following diagrams show the clocking scheme for the design example.
Figure 8. Clocking Scheme for Ethernet Design Example with IEEE 1588v2 Feature
Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcingreference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitterto the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core inyour design.
address_decoder_multi_channel
Avalon-MM
address_decoder_channel
PTP Packet Classifier
LL 10GbE MACS
Adapters
Adapters
Transceiver Reset Controller
altera_eth_channel_1588altera_eth_channel_1588
PLL 1
altera_eth_multi_channel_1588
N Channels
0x02_0000
0x03_0000
tx/rx_312_5_clk
csr_clktx/rx_156_25_clk
gmii_tx_clk
gmii_rx_clk
PHYS
tx_serial_clk_10gtx_serial_clk_1g
mgmt_clkxgmii_tx_clkxgmii_rx_clk
tx_clkout
rx_pma_clkout
pll_ref_clk_10g(0) pll_ref_clk_1g(0)
xgmii_clk[n] pll_ref_clk_10g[n]644.53125 MHz
pll_ref_clk_1g[n]125 MHz mm_clk
125 MHzrx_recovered_clk[N]
125 MHz
n Channel (1)
156.25 MHz 312.5 MHz
Notes:1. n = (SHARED_REFCLK_EN == 1) ? 1 : NUM_CHANNELS.2. Sampling clock for 10G TOD sync is 31.746031MHz.
Legend156.25 MHz312.5 MHz125 MHz125 MHz
0x01_0000(Master TOD)
10G LocalTOD
S
10G TODSync
Slave Master
period_clk
clk
10G PulsePer Second
1G LocalTOD
S
1G TODSync
Master Slave
period_clk
clk
1G PulsePer Second
MasterTOD
S
period_clk
clk
Master PulsePer Second
(2) (3)
(NUM CHANNEL - 1) / 6 + 1
5156.25 MHz 625 MHz
(NUM CHANNEL - 1) / 12 + 1 PLL 2
3. Sampling clock for 1G TOD sync is 126.984125 MHz .4. For Intel Arria 10 devices, the design example uses IOPLL.
(4)ATX PLL fPLL
Figure 9. Clocking Scheme for Ethernet Design Example without IEEE 1588v2 Feature
Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcingreference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitterto the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core inyour design.
address_decoder_multi_channel
Avalon-MM
address_decoder_channel
TX / RX FIFO
Transceiver Reset Controller
ATX PLL fPLL
altera_eth_channelaltera_eth_channel
PLL
altera_eth_multi_channel
Legend
N Channels
0x02_0000
0x03_0000
LL 10GbE MACS
Adapters
Adapters
tx/rx_312_5_clk
csr_clktx/rx_156_25_clk
gmii_tx_clk
gmii_rx_clk
Arria 10 PHYS
tx_serial_clk_10gtx_serial_clk_1g
mgmt_clkxgmii_tx_clkxgmii_rx_clk
tx_clkout
rx_pma_clkout
pll_ref_clk_10g(0) pll_ref_clk_1g(0)
xgmii_clk[n] pll_ref_clk_10g[n]644.53125 MHz
pll_ref_clk_1g[n]125 MHz
dc_fifo_tx_clk156.25 MHz
dc_fifo_rx_clk156.25 MHzrx_recovered_clk[N]
125 MHz
n Channel (1)
156.25 MHz 312.5 MHz
(NUM CHANNEL - 1) / 6 + 1
5156.25 MHz 625 MHz
Note:1. n = (SHARED_REFCLK_EN == 1)? 1: NUM_CHANNELS
156.25 MHz312.5 MHz125 MHz125 MHz
(NUM CHANNEL - 1) / 12 + 1
2. For Intel Arria 10 devices, the design example uses IOPLL.
(2)
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2.3.3. Reset Scheme
The reset signals of the design example—master_reset_n andchannel_reset_n[n:0]—are asynchronous and active-low signals. Asserting themaster_reset_n signal resets all channels and their components; asserting thechannel_reset_n[n] signal resets only the n channel and its components.
Upon power-up, reset the example design by asserting the master_reset_n signal.The following diagram shows the master reset scheme for the design example.
Figure 10. Master Reset
PLL 1644 MHz
ATX PLL fPLL
master_reset_n
channel_reset_n[n:0]
mm_reset[n:0]
datapath_reset[n:0]
MasterPPS
MasterTOD
PLL 2125 MHz
Ethernet Design Example with IEEE 1588v2 Feature
ATX PLL
master_reset_n
channel_reset_n[n:0]
mm_reset[n:0]
datapath_reset[n:0]
Ethernet Design Example without IEEE 1588v2 Feature
EthernetChannel 0
EthernetChannel n
PLL 1644 MHz
fPLL
EthernetChannel 0
EthernetChannel n
TransceiverReset Controller
TransceiverReset Controller
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The following diagram shows the channel reset scheme for the design example. Themm_reset signal is used to reset the registers of the design components, whereas thedatapath_reset is used to reset all digital blocks including the transceiver resetcontroller. The mm_reset and datapath_reset are triggered at the same timebecause they are tied together.
The reset csr block triggers the MAC reset only when the PHY's speed changes, whichis indicated by the pcs_mode_rc signal. To always reset the MAC when the PHY link islost, you can set the parameter PHY2MAC_RESET_EN to 1 inaltera_eth_channel_1588.v/altera_eth_channel.sv
Figure 11. Channel Reset
LL 10GbEMAC
PHY TransceiverReset Controller
mm_reset
datapath_reset
TOD10G
PPS10G
TOD SYN96B_10G
TOD SYN64B_10G
AddressDecoder
TOD1G
PPS1G
TOD SYN96B_1G
TOD SYN64B_1G
Ethernet Design Example with IEEE 1588v2 Feature
MAC PHY
mm_reset
datapath_reset
AddressDecoder
TransceiverReset Controller
Ethernet Design Example without IEEE 1588v2 Feature
ResetCSR
ResetCSR pcs_mode_rc
rx_block_lockled_link
pcs_mode_rcrx_block_lockled_link
2.4. Simulation
The simulation test cases demonstrate how the channel speed and the configuration ofthe PHY are changed. These test cases use circular loopback on the total number ofEthernet channels. The following table describes the steps to change the speed andconfiguration.
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Table 5. Ethernet Operations
Operation Description
Configuring the PHY speed. Upon reset, all ports are set to 10G. To change the PHY speed, set thePHY memory map to change to other modes: 10G SerDes FramerInterface (SFI), 1G1000Base-X or 1G/100M/10M SGMII.
Changing the speed between 1 Gbps and10Gbps in 1000BASE-X.
Write one of the following values to the PHY's register at address offset0x12C0.• 0x01: Turn on the auto-detection mode. In this mode, the PHY
automatically detects the speed.• 0x11: Turn off the auto-detection mode and set the speed to 1 Gbps.• 0x41: Turn off the auto-detection mode and set the speed to 10
Gbps.ExampleTo set port 0 to 1000BASE-X: write_32 0x02_52C0 0x11To set port 0 to auto-detection mode: write_32 0x02_52C0 0x01
Changing the speed between 1 Gbps, 100Mbps, and 10 Mbps in SGMII.
• Set the port to 1000BASE-X.• Write one of the following values to the PHY's register at offset
0x1290.— 0x01: Enable SGMII and set the speed to 10 Mbps.— 0x03: Enable SGMII and auto-negotiation.— 0x05: Enable SGMII mode and set the speed to 100 Mbps— 0x09: Enable SGMII mode and set the speed to 1 GbpsExample:To set port 0 to SGMII and 100 Mbps:Set port 0 to 1000Base-X: write_32 0x02_52C0 0x11Set port 0 to 100-Mbps SGMII: write_32 0x02_5290 0x05
Related Information
Compiling and Simulating the Design on page 10Provides information on the procedure and testbench.
2.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
The simulation test case performs the following steps:
1. Starts up the design example with an operating speed of 10G.
2. Configures the MAC, PHY, and FIFO buffer for all channels.
3. Waits until the design example asserts the channel_ready signal for eachchannel.
4. Sends the following packets:
• Non-PTP
• No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
• VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP
• Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
• No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
• VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
• Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
5. Repeats steps 2 to 4 for other operating speeds.
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When simulation ends, the values of the MAC statistics counters are displayed in thetranscript window. The transcript window also displays PASSED if the RX Avalon-STinterface of channel 0 received all packets successfully, all statistics error counters arezero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
Figure 12. Sample Simulation Output
2.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
The simulation test case performs the following steps:
1. Starts up the example design with an operating speed of 10G.
2. Configures the MAC, PHY, and FIFO buffer for all channels.
3. Waits until the example design asserts the channel_ready signal for eachchannel.
4. Sends the following packets:
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• Normal data frame, 64Bytes
• SVLAN data frame, broadcast, 64Bytes
• VLAN data frame, unicast, 500Bytes
5. Repeats steps 2 to 4 for other operating speeds.
When simulation ends, the values of the MAC statistics counters are displayed in thetranscript window. The transcript window also displays PASSED if the RX Avalon-STinterface of channel 0 received all packets successfully, all statistics error counters arezero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
Figure 13. Sample Simulation Output
2.5. Hardware Testing
Follow the procedure at the provided link to test the design example in the selectedhardware.
In the Clock Control application, which is part of the development kit, set the followingfrequencies:
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• Y5—644.53125 MHz
• Y6—125 MHz
Related Information
• Compiling and Testing the Design in Hardware on page 12More information on the procedure and hardware setup.
• Clock ControlMore information on using the Clock Control application.
2.5.1. Test Cases
You can run any of the following tests from the System Console.
Table 6. Hardware Test Cases
Test Case Command Example
PHY internal serialloopback
TEST_PHYSERIAL_LOOPBACK <channel><speed_test> <burst_size>
TEST_PHYSERIAL_LOOPBACK 0 10G 1000
SMA loopback For the design with the IEEE 1588v2 feature:TEST_SMA_LB <channel> <speed_test><burst_size>
TEST_SMA_LB 0 10G 1000
For the design without the IEEE 1588v2feature:TEST_SMA_LOOPBACK <channel><speed_test> <burst_size>
Table 7. Command Parameters
Parameter Valid Values Description
channel 0 to the number of channel specified for thedesign
The number of channels for the test.
speed_test 10G, 1G, 100M, 10M The PHY speed.
burst_size — The number of packets to generate for thetest.
When the test is completed, observe the output displayed in the System Console. Thefollowing diagrams show samples of the output.
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Figure 14. Sample Test Output—Ethernet Packet Monitor
Figure 15. Sample Test Output—Statistics Counters
2.5.2. Signal Tap Debug Signals
The Signal Tap file is included for debugging. By default, this feature is disabled. Toenable it, set the following assignment as below:
set_global_assignment -name ENABLE_SIGNALTAP ON
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Table 8. Signal Tap Debug Signals
Component Module Name Signal
Top-level design example altera_eth_top • mm_clk
• ref_clk_1g
• ref_clk_10g
• channel_ready_n
• channel_reset_n
• master_reset_n
Multi-channel wrapper Design example without the IEEE1588v2 feature:altera_eth_top.altera_eth_multi_channel
Design example with the IEEE 1588v2feature:altera_eth_top.altera_eth_multi_channel_1588
• pll_locked
• pll_1_locked
• pll_2_locked (only for the designexample with the IEEE 1588v2feature)
• pll_locked_10g
• pll_locked_1g
MAC IP core <n>.altera_eth_10g_mac(2) • avalon_st_tx_startofpacket
• avalon_st_tx_endofpacket
• avalon_st_tx_data
• avalon_st_tx_ready
• avalon_st_tx_valid
• avalon_st_tx_error
• avalon_st_tx_empty
• avalon_st_rx_startofpacket
• avalon_st_rx_endofpacket
• avalon_st_rx_data
• avalon_st_rx_ready
• avalon_st_rx_valid
• avalon_st_rx_error
• avalon_st_rx_empty
PHY <n>.altera_eth_10gkr_phy(2) • led_an
• led_char_err
• led_disp_err
• led_link
• mii_speed_sel
• rx_analogreset
• rx_block_lock
• rx_cal_busy
• rx_is_lockedtodata
• rx_digitalreset
• rx_data_ready
• tx_analogreset
• tx_digitalreset
continued...
(2) Replace n with:• altera_eth_top.altera_eth_multi_channel.altera_eth_channel for the design
example without the IEEE 1588v2 feature.• altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_1588
for the design example with the IEEE 1588v2 feature.
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Component Module Name Signal
XGMII <n>.altera_eth_10g_mac.alt_em10g32.alt_em10g32unit(2)
• xgmii_tx_control
• xgmii_tx_data
• xgmii_rx_control
• xgmii_rx_data
• link_fault_status_xgmii_rx_data
GMII <n>.altera_eth_10g_mac(2) • gmii_tx_d
• gmii_tx_en
• gmii_tx_err
• gmii_rx_d
• gmii_rx_dv
• gmii_rx_err
MII <n>.altera_eth_10g_mac(2) • mii_tx_d
• mii_tx_en
• mii_tx_err
• mii_rx_dv
• mii_rx_err
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2.6. Interface Signals
Figure 16. Interface Signals of the 10M/100M/1G/10G Ethernet Design Example
MAC RX
10M/100M/1G/10G Ethernet Design Example
avalon_st_rxstatus_valid[n]avalon_st_rxstatus_data[n][40]avalon_st_rxstatus_error[n][7]
Avalon-ST ReceiveStatus Interface
avalon_st_rx_endofpacket[n]avalon_st_rx_startofpacket[n]
avalon_st_rx_valid[n]avalon_st_rx_ready[n]avalon_st_rx_error[n][6]avalon_st_rx_data[n][64]avalon_st_rx_empty[n][3]
Avalon-ST ReceiveData Interface
Avalon-ST TransmitStatus Interface
avalon_st_txstatus_valid[n]avalon_st_txstatus_data[n][40]avalon_st_txstatus_error[n][7]
Avalon-ST TransmitFlow Control Interface
avalon_st_pause_data[n][2]
Avalon-ST TransmitData Interface
avalon_st_tx_startofpacket[n]avalon_st_tx_endofpacket[n]avalon_st_tx_valid[n]avalon_st_tx_ready[n]avalon_st_tx_error[n]avalon_st_tx_data[n][64]avalon_st_tx_empty[n][3]
PHY Interfacerx_serial_data[n]tx_serial_data[n]
ethernet_1g_an[n]ethernet_1g_char_err[n]ethernet_1g_disp_err[n]
channel_ready[n]
Avalon-MMInterface
readreaddata[32]
writewritedata[32]
address[20]waitrequest
Clock andReset
mm_clk
channel_reset_n[n]
pll_ref_clk_10g[s]cdr_ref_clk_1g[s]
cdr_ref_clk_10g[s]
pll_ref_clk_1g[s]
master_reset_nxgmii_clk[s]
rx_recovered_clk[n]
Additional Signals for Example Design With IEEE 1588v2 Feature
IEEE 1588v2Time-Stamp
Interface
tx_egress_timestamp_96b_valid[n]tx_egress_timestamp_96b_data[n][96]tx_egress_timestamp_96b_fingerprint[n][f]tx_egress_timestamp_64b_valid[n]tx_egress_timestamp_64b_data[n][64]tx_egress_timestamp_64b_fingerprint[n][f]rx_ingress_timestamp_96b_valid[n]rx_ingress_timestamp_96b_data[n][96]rx_ingress_timestamp_64b_valid[n]rx_ingress_timestamp_64b_data[n][64]
n: Number of channelss: Number of unshared channelsf: Timestamp fingerprint width
master_pulse_per_secondstart_tod_sync[n]
pulse_per_second_10g[n]pulse_per_second_1g[n]
TOD Interface
Packet ClassifierInterface
tx_egress_timestamp_request_in_valid[n]tx_egress_timestamp_request_in_fingerprint[n][f]
clock_operation_mode_mode[n][2]pkt_with_crc_mode[n]
tx_ingress_timestamp_valid[n]tx_ingress_timestamp_96b_data[n][96]tx_ingress_timestamp_64b_data[n][64]
tx_ingress_timestamp_format[n]
Status Interface
Related Information
Interface Signals Description on page 88For more information on each interface signal.
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2.7. Configuration Registers
You can access the 32-bit configuration registers of the design components throughthe Avalon-MM interface.
Table 9. Register Map
Byte Offset Block
0x00_0000 Client logic
0x00_F000 Reserved
0x01_0000 Master TOD
Channel 0
0x02_0000 Reserved
0x02_4000 PHY
0x02_7800 10G TOD
0x02_7900 1G TOD
0x02_8000 LL 10GbE MAC
Channel 1
0x03_0000 Reserved
0x03_4000 PHY
0x03_7800 10G TOD
0x03_7900 1G TOD
0x03_8000 LL 10GbE MAC
.. and so forth up to Channel 11.
0x0E_0000 onwards Client Logic
Related Information
Configuration Registers Description on page 97For more information on each configuration register.
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3. 1G/10G Ethernet Design Example for Intel Arria 10Devices
The 1G/10G Ethernet design example demonstrates the functionalities of the LL10GbE MAC Intel FPGA IP core operating at 1G and 10G.
Generate the design example from the Example Design tab of the LL 10GbE IntelFPGA IP parameter editor. You can choose to generate the design with or without theIEEE 1588v2 feature.
3.1. Features
• Dual-speed Ethernet operation—1G and 10G.
• Support for up to 12 channels.
• Packet monitoring on the TX and RX datapaths.
• Option to generate the design example with the IEEE 1588v2 feature.
• Tested with the Spirent TestCenter.
3.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linuxsystem:
• Intel Quartus Prime software
• ModelSim-AE, ModelSim-SE, NCSim (Verilog only), VCS, and Xcelium (IntelQuartus Prime Pro Edition only) simulators
• Intel Arria 10 GX Transceiver Signal Integrity Development Kit for hardwaretesting
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
3.3. Functional Description
The design example consists of various components. The following block diagramsshow the design components and the top-level signals of the design example.
Figure 17. Block Diagram—1G/10G Ethernet Design Example with IEEE 1588v2 Feature
Input Clock Reset
Avalon-ST
Multi-channel Address Decoder
Avalon-MM
Address Decoder
PTP PacketClassifier
LL 10GbE MAC
PHY
TransceiverReset Controller
ATX PLL fPLL
TX/RXSerialData
Ethernet channel n
Ethernet channel 0
PLL ResetController
LocalTOD
Pulse PerSecond
TODSync
Pulse PerSecond
MasterTOD
MasterPulse PerSecond
1G/10G Pulse Per SecondIEEE 1588v2Timestamp
Generated from Platform DesignerGenerated from IP Catalog
Multi-channel Wrapper
Adapter
Adapter
(altera_eth_multi_channel_1588)
(address_decoder_multi_channel)
(altera_eth_channel_1588)
(altera_eth_channel_1588)
(address_decoder_channel)
Avalon-MMMasterS M
Avalon-MMMasterS M
S
S
S
S
Figure 18. Block Diagram—1G/10G Ethernet Design Example without IEEE 1588v2Feature
Input Clock Reset
Avalon-ST
Multi-channel Address Decoder
Avalon-MM
Avalon-MMMaster
FIFO
LL 10GbE MAC
PHY
Transceiver ResetController
ATX PLL fPLL
TX/RXSerialData
Ethernet channel n
Ethernet channel 0
PLLReset
Controller
Multi-channel Wrapper
Generated with Platform DesignerGenerated with IP Catalog
Address Decoder
Adapter
Adapter
(altera_eth_multi_channel)
(address_decoder_multi_channel)
(address_decoder_channel)
(altera_eth_channel)
(altera_eth_channel)
S
S
S
M
Avalon-MMMasterS M
3.3.1. Design Components
Table 10. Design Components of the 1G/10G Ethernet Design Example
Component Description
LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the followingconfiguration:
continued...
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Component Description
• Speed: 1G/10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• All Legacy Ethernet 10G MAC Interfaces options: SelectedFor the design example with the IEEE 1588v2 feature, the following additionalparameters are configured:• Enable time stamping: Selected• Enable PTP one-step clock support: Selected• Timestamp fingerprint width: 4• Time Of Day format: Enable both 96b and 64b Time of Day Format
PHY The 1G/10G and 10GBASE-KR PHY Intel Arria 10 FPGA IP. The design exampleuses the 1G/10G IP variant.
Address Decoder Decodes the addresses of the components in each Ethernet channel.
Reset Controller Synchronizes the reset of all design components.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel FPGA IP core. Resets the transceiver.
PLL Generates clocks for all design components.
ATX PLL Generates a TX serial clock for the Intel Arria 10 10G transceiver.
FIFO The Avalon Streaming (Avalon-ST) single-clock FIFO. Buffers the RX and TX databetween the MAC IP core and the client. The default depth is 512. To increasethe depth of the FIFO, change the DC_FIFO_DEPTH & SC_FIFO_DEPTHparameter values from 512 to 2048, under altera_eth_fifo instance in<Example Design>/rtl/altera_eth_channel.sv.
Related Information
• Low Latency Ethernet 10G MAC Intel FPGA IP Core User GuideFor more information on the MAC parameters.
• Intel Arria 10 Transceiver PHY User GuideFor more information on the PHY parameters.
• KDB Link: Why do I see underflow errors when receiving Jumbo frames on theLow Latency Ethernet 10G MAC Design Examples?
External FIFO buffer limitation for Intel Arria 10 Low Latency Ethernet 10GMAC Design Example.
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3.3.2. Clocking Scheme
The following diagrams show the clocking scheme for the design example.
Figure 19. Clocking Scheme for Ethernet Design Example with IEEE 1588v2 Feature
Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcingreference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitterto the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core inyour design.
address_decoder_multi_channel
Avalon-MM
address_decoder_channel
PTP Packet Classifier
LL 10GbE MACS
Adapters
Adapters
Transceiver Reset Controller
altera_eth_channel_1588altera_eth_channel_1588
PLL 1
altera_eth_multi_channel_1588
N Channels
0x02_0000
0x03_0000
tx/rx_312_5_clk
csr_clktx/rx_156_25_clk
gmii_tx_clk
gmii_rx_clk
PHYS
tx_serial_clk_10gtx_serial_clk_1g
mgmt_clkxgmii_tx_clkxgmii_rx_clk
tx_clkout
rx_pma_clkout
pll_ref_clk_10g(0) pll_ref_clk_1g(0)
xgmii_clk[n] pll_ref_clk_10g[n]644.53125 MHz
pll_ref_clk_1g[n]125 MHz mm_clk
125 MHzrx_recovered_clk[N]
125 MHz
n Channel (1)
156.25 MHz 312.5 MHz
Notes:1. n = (SHARED_REFCLK_EN == 1) ? 1 : NUM_CHANNELS.2. Sampling clock for 10G TOD sync is 31.746031MHz.
Legend156.25 MHz312.5 MHz125 MHz125 MHz
0x01_0000(Master TOD)
10G LocalTOD
S
10G TODSync
Slave Master
period_clk
clk
10G PulsePer Second
1G LocalTOD
S
1G TODSync
Master Slave
period_clk
clk
1G PulsePer Second
MasterTOD
S
period_clk
clk
Master PulsePer Second
(2) (3)
(NUM CHANNEL - 1) / 6 + 1
5156.25 MHz 625 MHz
(NUM CHANNEL - 1) / 12 + 1 PLL 2
3. Sampling clock for 1G TOD sync is 126.984125 MHz .4. For Intel Arria 10 devices, the design example uses IOPLL.
(4)ATX PLL fPLL
Figure 20. Clocking Scheme for Ethernet Design Example without IEEE 1588v2 Feature
Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcingreference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitterto the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core inyour design.
address_decoder_multi_channel
Avalon-MM
address_decoder_channel
TX / RX FIFO
Transceiver Reset Controller
ATX PLL fPLL
altera_eth_channelaltera_eth_channel
PLL
altera_eth_multi_channel
Legend
N Channels
0x02_0000
0x03_0000
LL 10GbE MACS
Adapters
Adapters
tx/rx_312_5_clk
csr_clktx/rx_156_25_clk
gmii_tx_clk
gmii_rx_clk
Arria 10 PHYS
tx_serial_clk_10gtx_serial_clk_1g
mgmt_clkxgmii_tx_clkxgmii_rx_clk
tx_clkout
rx_pma_clkout
pll_ref_clk_10g(0) pll_ref_clk_1g(0)
xgmii_clk[n] pll_ref_clk_10g[n]644.53125 MHz
pll_ref_clk_1g[n]125 MHz
dc_fifo_tx_clk156.25 MHz
dc_fifo_rx_clk156.25 MHzrx_recovered_clk[N]
125 MHz
n Channel (1)
156.25 MHz 312.5 MHz
(NUM CHANNEL - 1) / 6 + 1
5156.25 MHz 625 MHz
Note:1. n = (SHARED_REFCLK_EN == 1)? 1: NUM_CHANNELS
156.25 MHz312.5 MHz125 MHz125 MHz
(NUM CHANNEL - 1) / 12 + 1
2. For Intel Arria 10 devices, the design example uses IOPLL.
(2)
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3.3.3. Reset Scheme
The reset signals of the design example—master_reset_n andchannel_reset_n[n:0]—are asynchronous and active-low signals. Asserting themaster_reset_n signal resets all channels and their components; asserting thechannel_reset_n[n] signal resets only the n channel and its components.
Upon power-up, reset the example design by asserting the master_reset_n signal.The following diagram shows the master reset scheme for the design example.
Figure 21. Master Reset
PLL 1644 MHz
ATX PLL fPLL
master_reset_n
channel_reset_n[n:0]
mm_reset[n:0]
datapath_reset[n:0]
MasterPPS
MasterTOD
PLL 2125 MHz
Ethernet Design Example with IEEE 1588v2 Feature
ATX PLL
master_reset_n
channel_reset_n[n:0]
mm_reset[n:0]
datapath_reset[n:0]
Ethernet Design Example without IEEE 1588v2 Feature
EthernetChannel 0
EthernetChannel n
PLL 1644 MHz
fPLL
EthernetChannel 0
EthernetChannel n
TransceiverReset Controller
TransceiverReset Controller
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The following diagram shows the channel reset scheme for the design example. Themm_reset signal is used to reset the registers of the design components, whereas thedatapath_reset is used to reset all digital blocks including the transceiver resetcontroller. The mm_reset and datapath_reset are triggered at the same timebecause they are tied together.
The reset csr block triggers the MAC reset only when the PHY's speed changes, whichis indicated by the pcs_mode_rc signal. To always reset the MAC when the PHY link islost, you can set the parameter PHY2MAC_RESET_EN to 1 inaltera_eth_channel_1588.v/altera_eth_channel.sv
Figure 22. Channel Reset
LL 10GbEMAC
PHY TransceiverReset Controller
mm_reset
datapath_reset
TOD10G
PPS10G
TOD SYN96B_10G
TOD SYN64B_10G
AddressDecoder
TOD1G
PPS1G
TOD SYN96B_1G
TOD SYN64B_1G
Ethernet Design Example with IEEE 1588v2 Feature
MAC PHY
mm_reset
datapath_reset
AddressDecoder
TransceiverReset Controller
Ethernet Design Example without IEEE 1588v2 Feature
ResetCSR
ResetCSR pcs_mode_rc
rx_block_lockled_link
pcs_mode_rcrx_block_lockled_link
3.4. Simulation
The simulation test cases demonstrate how the channel speed and the configuration ofthe PHY are changed. These test cases use circular loopback on the total number ofEthernet channels. The following table describes the steps to change the speed andconfiguration.
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Table 11. Ethernet Operations
Operation Description
Configuring the PHY speed. Upon reset, all ports are set to 10G. To change the PHY speed, set thePHY memory map to change to other modes: 10G SerDes FramerInterface (SFI), or 1G1000Base-X.
Changing the speed between 1 Gbps and10Gbps in 1000BASE-X.
Write one of the following values to the PHY's register at address offset0x12C0.• 0x01: Turn on the auto-detection mode. In this mode, the PHY
automatically detects the speed.• 0x11: Turn off the auto-detection mode and set the speed to 1 Gbps.• 0x41: Turn off the auto-detection mode and set the speed to 10
Gbps.ExampleTo set port 0 to 1000BASE-X: write_32 0x02_52C0 0x11To set port 0 to auto-detection mode: write_32 0x02_52C0 0x01
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
The simulation test case performs the following steps:
1. Starts up the design example with an operating speed of 10G.
2. Configures the MAC, PHY, and FIFO buffer for all channels.
3. Waits until the design example asserts the channel_ready signal for eachchannel.
4. Sends the following packets:
• Non-PTP
• No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
• VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP
• Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
• No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
• VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
• Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
5. Repeats steps 2 to 4 for other operating speeds.
When simulation ends, the values of the MAC statistics counters are displayed in thetranscript window. The transcript window also displays PASSED if the RX Avalon-STinterface of channel 0 received all packets successfully, all statistics error counters arezero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
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Figure 23. Sample Simulation Output
3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
The simulation test case performs the following steps:
1. Starts up the example design with an operating speed of 10G.
2. Configures the MAC, PHY, and FIFO buffer for all channels.
3. Waits until the example design asserts the channel_ready signal for eachchannel.
4. Sends the following packets:
• Normal data frame, 64Bytes
• SVLAN data frame, broadcast, 64Bytes
• VLAN data frame, unicast, 500Bytes
5. Repeats steps 2 to 4 for other operating speeds.
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When simulation ends, the values of the MAC statistics counters are displayed in thetranscript window. The transcript window also displays PASSED if the RX Avalon-STinterface of channel 0 received all packets successfully, all statistics error counters arezero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
Figure 24. Sample Simulation Output
3.5. Hardware Testing
Follow the procedure at the provided link to test the design example in the selectedhardware.
In the Clock Control application, which is part of the development kit, set the followingfrequencies:
• Y5—644.53125 MHz
• Y6—125 MHz
Related Information
• Compiling and Testing the Design in Hardware on page 12More information on the procedure and hardware setup.
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• Clock ControlMore information on using the Clock Control application.
3.5.1. Test Cases
You can run any of the following tests from the System Console.
Table 12. Hardware Test Cases
Test Case Command Example
PHY internal serialloopback
TEST_PHYSERIAL_LOOPBACK <channel><speed_test> <burst_size>
TEST_PHYSERIAL_LOOPBACK 0 10G 1000
SMA loopback For the design with the IEEE 1588v2 feature:TEST_SMA_LB <channel> <speed_test><burst_size>
TEST_SMA_LB 0 10G 1000
For the design without the IEEE 1588v2feature:TEST_SMA_LOOPBACK <channel><speed_test> <burst_size>
Table 13. Command Parameters
Parameter Valid Values Description
channel 0 to the number of channel specified for thedesign
The number of channels for the test.
speed_test 10G, 1G The PHY speed.
burst_size — The number of packets to generate for thetest.
When the test is completed, observe the output displayed in the System Console. Thefollowing diagrams show samples of the output.
Figure 25. Sample Test Output—Packet Monitor
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Figure 26. Sample Test Output—Statistics Counters
3.5.2. Signal Tap Debug Signals
The Signal Tap file is included for debugging. By default, this feature is disabled. Toenable it, set the following assignment as below:
set_global_assignment -name ENABLE_SIGNALTAP ON
Table 14. Signal Tap Debug Signals
Component Module Name Signal
Top-level design example altera_eth_top • mm_clk
• ref_clk_1g
• ref_clk_10g
• channel_ready_n
• channel_reset_n
• master_reset_n
Multi-channel wrapper Design example without the IEEE1588v2 feature:altera_eth_top.altera_eth_multi_channel
Design example with the IEEE 1588v2feature:altera_eth_top.altera_eth_multi_channel_1588
• pll_locked
• pll_1_locked
• pll_2_locked (only for the designexample with the IEEE 1588v2feature)
• pll_locked_10g
• pll_locked_1g
continued...
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Component Module Name Signal
MAC IP core <n>.altera_eth_10g_mac (3) • avalon_st_tx_startofpacket
• avalon_st_tx_endofpacket
• avalon_st_tx_data
• avalon_st_tx_ready
• avalon_st_tx_valid
• avalon_st_tx_error
• avalon_st_tx_empty
• avalon_st_rx_startofpacket
• avalon_st_rx_endofpacket
• avalon_st_rx_data
• avalon_st_rx_ready
• avalon_st_rx_valid
• avalon_st_rx_error
• avalon_st_rx_empty
PHY <n>.altera_eth_10gkr_phy (3) • led_an
• led_char_err
• led_disp_err
• led_link
• mii_speed_sel
• rx_analogreset
• rx_block_lock
• rx_cal_busy
• rx_is_lockedtodata
• rx_digitalreset
• rx_data_ready
• tx_analogreset
• tx_digitalreset
XGMII <n>.altera_eth_10g_mac.alt_em10g32.alt_em10g32unit (3)
• xgmii_tx_control
• xgmii_tx_data
• xgmii_rx_control
• xgmii_rx_data
• link_fault_status_xgmii_rx_data
GMII <n>.altera_eth_10g_mac (3) • gmii_tx_d
• gmii_tx_en
• gmii_tx_err
• gmii_rx_d
• gmii_rx_dv
• gmii_rx_err
(3) Replace n with:
• altera_eth_top.altera_eth_multi_channel.altera_eth_channel for the designexample without the IEEE 1588v2 feature.
• altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_1588for the design example with the IEEE 1588v2 feature.
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3.6. Interface Signals
Figure 27. Interface Signals of the 1G/10G Ethernet Design Example
MAC RX
1G/10G Ethernet Design Example
avalon_st_rxstatus_valid[n]avalon_st_rxstatus_data[n][40]avalon_st_rxstatus_error[n][7]
Avalon-ST ReceiveStatus Interface
avalon_st_rx_endofpacket[n]avalon_st_rx_startofpacket[n]
avalon_st_rx_valid[n]avalon_st_rx_ready[n]avalon_st_rx_error[n][6]avalon_st_rx_data[n][64]avalon_st_rx_empty[n][3]
Avalon-ST ReceiveData Interface
Avalon-ST TransmitStatus Interface
avalon_st_txstatus_valid[n]avalon_st_txstatus_data[n][40]avalon_st_txstatus_error[n][7]
Avalon-ST TransmitFlow Control Interface
avalon_st_pause_data[n][2]
Avalon-ST TransmitData Interface
avalon_st_tx_startofpacket[n]avalon_st_tx_endofpacket[n]avalon_st_tx_valid[n]avalon_st_tx_ready[n]avalon_st_tx_error[n]avalon_st_tx_data[n][64]avalon_st_tx_empty[n][3]
PHY Interfacerx_serial_data[n]tx_serial_data[n]
ethernet_1g_an[n]ethernet_1g_char_err[n]ethernet_1g_disp_err[n]
channel_ready[n]
Avalon-MMInterface
readreaddata[32]
writewritedata[32]
address[20]waitrequest
Clock andReset
mm_clk
channel_reset_n[n]
pll_ref_clk_10g[s]cdr_ref_clk_1g[s]
cdr_ref_clk_10g[s]
pll_ref_clk_1g[s]
master_reset_nxgmii_clk[s]
rx_recovered_clk[n]
Additional Signals for Example Design With IEEE 1588v2 Feature
IEEE 1588v2Time-Stamp
Interface
tx_egress_timestamp_96b_valid[n]tx_egress_timestamp_96b_data[n][96]tx_egress_timestamp_96b_fingerprint[n][f]tx_egress_timestamp_64b_valid[n]tx_egress_timestamp_64b_data[n][64]tx_egress_timestamp_64b_fingerprint[n][f]rx_ingress_timestamp_96b_valid[n]rx_ingress_timestamp_96b_data[n][96]rx_ingress_timestamp_64b_valid[n]rx_ingress_timestamp_64b_data[n][64]
n: Number of channelss: Number of unshared channelsf: Timestamp fingerprint width
master_pulse_per_secondstart_tod_sync[n]
pulse_per_second_10g[n]pulse_per_second_1g[n]
TOD Interface
Packet ClassifierInterface
tx_egress_timestamp_request_in_valid[n]tx_egress_timestamp_request_in_fingerprint[n][f]
clock_operation_mode_mode[n][2]pkt_with_crc_mode[n]
tx_ingress_timestamp_valid[n]tx_ingress_timestamp_96b_data[n][96]tx_ingress_timestamp_64b_data[n][64]
tx_ingress_timestamp_format[n]
Status Interface
Table 15. Clock Domains
Clock Frequency(MHz)
Interface Signals
xgmii_clk 156.25 • Avalon-ST interfaces• Packet Classifier interface• IEEE 1588v2 time-stamp interface• channel_ready[n] (PHY interface)
mm_clk 125 • Avalon-MM interface
pll_ref_clk_1g 125 • master_pulse_per_second (ToD interface)
Related Information
Interface Signals Description on page 88For more information on each interface signal.
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3.7. Configuration Registers
You can access the 32-bit configuration registers of the design components throughthe Avalon-MM interface.
Table 16. Register Map
Byte Offset Block
0x00_0000 Client logic
0x00_F000 Reserved
0x01_0000 Master TOD
Channel 0
0x02_0000 Reserved
0x02_4000 PHY
0x02_7800 10G TOD
0x02_7900 1G TOD
0x02_8000 LL 10GbE MAC
Channel 1
0x03_0000 Reserved
0x03_4000 PHY
0x03_7800 10G TOD
0x03_7900 1G TOD
0x03_8000 LL 10GbE MAC
.. and so forth up to Channel 11.
0x0E_0000 onwards Client Logic
Related Information
Configuration Registers Description on page 97For more information on each configuration register.
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4. 10GBASE-R Ethernet Design Example for Intel Arria 10Devices
The 10GBASE-R Ethernet design example demonstrates an Ethernet solution for IntelArria 10 devices using the LL 10GbE MAC Intel FPGA IP core, the native PHY IP core,and a small form factor pluggable plus (SFP +) module.
Generate the design example from the Example Design tab of the LL 10GbE IntelFPGA IP parameter editor.
4.1. Features
• Supports single Ethernet channels operating at 10G using Intel Arria 10 NativePHY.
• Option to generate the design example with the 10GBASE-R register modeenabled.
• 140 ns round-trip latency in simulation when the register mode is enabled.
• Packet monitoring on the TX and RX datapaths.
• Tested with the Spirent TestCenter.
4.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linuxsystem:
• Intel Quartus Prime software
• ModelSim-AE, ModelSim-SE, NCSim (Verilog only), VCS, and Xcelium (IntelQuartus Prime Pro Edition only) simulators
• For hardware testing:
— Intel Arria 10 GX Transceiver Signal Integrity Development Kit
— Cables—SFP+ and fiber optic cable
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
4.3. Functional Description
Figure 28. Block Diagram—10GBASE-R Ethernet Design Example
Input Clock Reset
Avalon-STFIFOLL 10GbE MAC
PHY
Transceiver ResetController
TX/RXSerialData
PLL ResetSynchronizer
Design Example
Adapter
Adapter
(altera_eth_top)
ATX PLL
address_decoder_channel
altera_eth_10g_mac_base_r_wrap
Generated with Platform DesignerGenerated with IP Catalog
S
S
Avalon-MMMasterS M
Avalon-MMMasterS M
Avalon-MM
4.3.1. Design Components
Table 17. Design Components
Component Description
LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration:• Speed: 10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable 10GBASE-R register mode: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• TX and RX datapath Reset/Default To Enable: Selected• Use legacy XGMII Interface: Selected.• Use legacy Avalon Memory-Mapped Interface: Not Selected• Use legacy Avalon Streaming Interface: Not selectedThe settings when the 10GBASE-R Register mode is enabled:• Enable 10GBASE-R register mode: Selected• Use legacy XGMII Interface: Not selected• Use legacy Avalon Memory-Mapped Interface: Selected
PHY • The Transceiver Native PHY Intel Arria 10/Intel Cyclone® 10 FPGA IP configured for the10GBASE-R protocol.
• The register mode preset sets the PHY's TX FIFO MODE to Fast Register.• The non-register mode preset sets the PHY's TX FIFO MODE to Phase Compensation and RX
FIFO MODE to 10GBASE-R.
Transceiver ResetController
The Transceiver PHY Reset Controller Intel FPGA IP core. Resets the transceiver.
Address decoder Decodes the addresses of the components.
continued...
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Component Description
Reset synchronizer Synchronizes the reset of all design components.
ATX PLL Generates a TX serial clock for the Intel Arria 10 10G transceiver.
FIFO • Avalon Streaming (Avalon-ST) single-clock FIFO.• Buffers the RX and TX data between the MAC IP core and the client.
Related Information
• Low Latency Ethernet 10G MAC Intel FPGA IP Core User GuideFor more information on the MAC parameters.
• Intel Arria 10 Transceiver PHY User GuideFor more information on the PHY parameters.
4.3.2. Clocking and Reset Scheme
Figure 29. Clocking and Reset Scheme for 10GBASE-R Design Example
Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcingreference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitterto the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core inyour design.
Generator andChecker
reset_n clk
FIFO
rx_sc_fifo_clk_reset_reset tx_sc_fifo_clk_reset_reset
rx_sc_fifo_clk_clk tx_sc_fifo_clk_clk
Avalon-ST Adapteravalon_st_rx_clk_312avalon_st_rx_312_reset_n
avalon_st_tx_clk_312avalon_st_tx_312_reset_n
avalon_st_rx_clk_156avalon_st_rx_156_reset_n
avalon_st_tx_clk_156avalon_st_tx_156_reset_n
LL 10GbE MAC
csr_clkcsr_rst_n
rx_312_5_clkrx_156_25_clk
rx_rst_n
tx_312_5_clktx_156_25_clk
tx_rst_n
Address Decodertx_xcvr_half_clk_clksync_tx_half_rst_reset_n
clk_csr_clkcsr_reset_n
rx_xcvr_clk_clksync_rx_rst_reset_n
tx_xcvr_clk_clksync_tx_rst_reset_n
TransceiverReset
Controllerreset clock
ResetSynchronizer
TX PLL
125 MHz csr_clk
ref_clk_clk322.265625 MHz
master_reset_n
IOPLLoutclk_0
outclk_1
Avalon-MM Adaptersl_clocksl_reset
ms_clockms_reset
(1)
PHY
reconfig_clkrx_cdr_refclk0reconfig_reset
tx_xcvr_half_clktx_serial_clk
tx_clkoutrx_clkout
tx_coreclkinrx_coreclkin
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Figure 30. Clocking and Reset Scheme for 10GBASE-R Design Example with the RegisterMode Enabled
Generator andChecker
reset_n clk
FIFO
rx_sc_fifo_clk_reset_reset tx_sc_fifo_clk_reset_reset
rx_sc_fifo_clk_clk tx_sc_fifo_clk_clk
Adapteravalon_st_rx_clk_312avalon_st_rx_312_reset_n
avalon_st_tx_clk_312avalon_st_tx_312_reset_n
avalon_st_rx_clk_156avalon_st_rx_156_reset_n
avalon_st_tx_clk_156avalon_st_tx_156_reset_n
LL 10GbE MACcsr_clkcsr_rst_n
rx_xcvr_clkrx_rst_n
tx_xcvr_clktx_rst_n
PHY
reconfig_clkrx_cdr_refclk0reconfig_reset
tx_xcvr_half_clktx_serial_clk
tx_clkoutrx_clkout
Address Decodertx_xcvr_half_clk_clksync_tx_half_rst_reset_n
clk_csr_clkcsr_reset_n
rx_xcvr_clk_clksync_rx_rst_reset_n
tx_xcvr_clk_clksync_tx_rst_reset_n
TransceiverReset
Controllerreset clock
ResetSynchronizer
PLL
125-MHz csr_clk
ref_clk_clk322.265625 MHz
master_reset_n
1. For Intel Arria 10 devices, the design example uses IOPLL.Notes:
(1)
4.4. Simulation
The simulation test case demonstrates how the MAC and PHY configuration is changedat 10-Gbps throughput. The test case is for a single Ethernet channel.
At the end of the simulation, the simulator generates the statistics of TX and RXpackets in the Transcript window.
In the Wave window, the roundtrip latency for the serial loopback is indicated by themeasurement cursors that show the time taken to transmit the first data from theAvalon-ST TX interface to be available at the Avalon-ST RX interface.
Related Information
Compiling and Simulating the Design on page 10Provides information on the procedure and testbench.
4.5. Hardware Testing
Follow the procedure at the provided link to test the design example in the selectedhardware.
In the Clock Control application, which is part of the development kit, set the followingfrequencies:
• Y5—322.265625 MHz
• Y6—125 MHz
Related Information
• Compiling and Testing the Design in Hardware on page 12More information on the procedure and hardware setup.
• Clock ControlMore information on using the Clock Control application.
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4.5.1. Test Cases
You can run any of the following tests from the System Console.
Table 18. Hardware Test Cases
Test Case Command Description
SFP+ loopback source gen_conf.tcl The generator generates and sends about 4 billion packets. Wait6 minutes for it to complete its tasks.
source monitor_conf.tcl The monitor checks the number of good and bad packetsreceived.
source show_stats.tcl This script displays the values of the statistics counters.
Avalon-ST loopback source loopback_conf.tcl This command enables the Avalon-ST loopback. This test is usedwith an external tester such as Spirent tester.
After the test is completed, observe the output displayed in the System Console.
Figure 31. Sample Test Output—Ethernet Packet Monitor
Figure 32. Sample Test Output—Statistics Counters
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4.5.2. Signal Tap Debug Signals
The Signal Tap file is included for debugging.
This feature is disabled by default. To enable it, set the following assignment:
set_global_assignment -name ENABLE_SIGNALTAP ON
Table 19. Signal Tap Debug Signals
Component Module Name Signal
Top-leveldesignexample
altera_eth_top • csr_clk
• ref_clk_clk
• master_reset_n
• block_lock_n
• tx_ready_export_n
• rx_ready_export_n
DesignExample
altera_eth_top.altera_eth_10g_mac_base_r_low_latency
• atx_pll_locked
• iopll_locked
MAC IP core altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac
• avalon_st_tx_startofpacket
• avalon_st_tx_endofpacket
• avalon_st_tx_data
• avalon_st_tx_ready
• avalon_st_tx_valid
• avalon_st_tx_error
• avalon_st_tx_empty
• avalon_st_rx_startofpacket
• avalon_st_rx_endofpacket
• avalon_st_rx_data
• avalon_st_rx_ready
• avalon_st_rx_valid
• avalon_st_rx_error
• avalon_st_rx_empty
MAC TX altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_em10g32_tx_top.alt_em10g32_tx_rs_layer.alt_em10g32_tx_rs_xgmii_layer_ultra
• xgmii_tx_valid
• xgmii_tx_data
• xgmii_tx_control
MAC RX altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_em10g32_rx_top.alt_em10g32_rx_rs_layer.alt_em10g32_rx_rs_xgmii_ultra
• xgmii rx valid
• xgmii rx data
• xgmii rx control
• xgmii rx link fault status
PHY altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_baser
• tx_analogreset
• tx_digitalreset
• rx_analogreset
• rx_digitalreset
• tx_cal_busy
• rx_cal_busy
• rx_is_lockedtodata
• tx_clkout
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4.6. Interface Signals
Figure 33. Interface Signals of the 10GBASE-R Ethernet Design Example
10GBASE-R Ethernet Design Example
PHY Interface
tx_ready_export[n]rx_ready_export[n]block_lock[n]atx_pll_locked tx_serial_data[n]
rx_serial_data[n]
Clock andReset
csr_clk
rx_rst_n
tx_rst_nrx_xcvr_clk (1)
csr_rst_n
rx_xcvr_half_clk (1)tx_xcvr_half_clk (1)
ref_clk_clktx_clk_312 (2)tx_clk_156 (2)
(1) Signal is present only in design example with the 10GBASE-R Register Mode enabled.(2) Signal is present only in design example with the 10GBASE-R Register Mode disabled.
avalon_st_rxstatus_valid[n]avalon_st_rxstatus_data[n][40]avalon_st_rxstatus_error[n][7]
Avalon-ST ReceiveStatus Interface
avalon_st_rx_endofpacket[n]avalon_st_rx_startofpacket[n]
avalon_st_rx_valid[n]avalon_st_rx_ready[n]avalon_st_rx_error[n][6]avalon_st_rx_data[n][32]avalon_st_rx_empty[n][2]
Avalon-ST ReceiveData Interface
Avalon-ST TransmitStatus Interface
avalon_st_txstatus_valid[n]avalon_st_txstatus_data[n][40]avalon_st_txstatus_error[n][7]
Avalon-ST TransmitFlow Control Interface
avalon_st_pause_data[n][2]
Avalon-ST TransmitData Interface
avalon_st_tx_startofpacket[n]avalon_st_tx_endofpacket[n]avalon_st_tx_valid[n]avalon_st_tx_ready[n]avalon_st_tx_error[n]avalon_st_tx_data[n][32]avalon_st_tx_empty[n][2]
link_fault_status_xgmii_rx_data[2]
tx_xcvr_clk (1)
rx_clk_312 (2)rx_clk_156 (2)
Avalon-MMInterface
mac_csr_read[n]mac_csr_readdata[32][n]
mac_csr_write[n]mac_csr_writedata[32][n]
mac_csr_address[n][10]mac_csr_waitrequest[n]
phy_csr_read[n]phy_csr_readdata[32][n]
phy_csr_write[n]phy_csr_writedata[32][n]
phy_csr_address[n][16]phy_csr_waitrequest[n]
Status Interface
n: Number of channels
Notes:
4.7. Configuration Registers
You can access the 32-bit configuration registers of the design components throughthe Avalon-MM interface.
Table 20. Register Map
Byte Offset Block
0x0000_0000 LL 10GbE MAC
0x0000_8000 Native PHY
0x0000_D400 RX SC FIFO
0x0000_D600 TX SC FIFO
0x0000_C000 Packet Generator and Checker
0x0000_D000 – 0xFFFF_FFFF Client Logic
Related Information
• Configuration Registers Description on page 97For more information on each configuration register.
• Intel FPGA Low Latency Ethernet 10G MAC User GuideFor the description of the MAC registers.
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5. 1G/2.5G Ethernet Design Example for Intel Arria 10Devices
The 1G/2.5G Ethernet design example demonstrates the functionalities of the LL10GbE MAC Intel FPGA IP core operating at 1G and 2.5G.
Generate the design example from the Example Design tab of the LL 10GbE IntelFPGA IP parameter editor. You can choose to generate the design with or without theIEEE 1588v2 feature.
5.1. Features
• Dual-speed Ethernet operation—1G and 2.5G.
• Support for two channels.
• Option to generate the design example with the IEEE 1588v2 feature.
• Testbench and simulation script.
• Tested with the Spirent TestCenter.
• Option to generate design example with Partial Reconfiguration Ready.
5.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linuxsystem:
• Intel Quartus Prime Pro Edition software (Partial Reconfiguration Ready)
• ModelSim-AE, ModelSim-SE, NCSim (Verilog only), VCS, and Xcelium (IntelQuartus Prime Pro Edition only) simulators
• For hardware testing:
— Intel Arria 10 GX Signal Integrity Development Board(10AX115S3F45E2SGE3)—for the design example with the IEEE 1588v2feature
— Intel Arria 10 GX Signal Integrity Development Board(10AX115S4F45E3SGE3)—for the design example without the IEEE 1588v2feature
Note: Partial Reconfiguration Ready feature is supported from Intel Quartus Prime ProEdition software version 17.0 onwards.
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
5.3. Functional Description
The design example consists of various components. The following block diagramsshows the design components and the top-level signals of the design example.
Figure 34. Block Diagram—1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
Input ClockReset
Avalon-ST
Avalon-MM
LL 10GbE MAC
TX/RXSerialData
Ethernet channel 0
Transceiver Reconfig
Generated from Platform DesignerGenerated from IP Catalog
Design Example
(alt_mge_channel)
(alt_mge_rd)
ATX PLL
Avalon-MM MuxTransceiver
ReconfigS
TransceiverReset
ControllerfPLL
PHY
PTP PacketClassifier
Pulse PerSecond
TODSynch
LocalTOD
S
IOPLL
Pulse PerSecond
Local TODPulse PerSecond
MasterPulse PerSecond
MasterTOD
AddressDecoder
.
.
.S
M
M
MS
S
S
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Figure 35. Block Diagram—1G/2.5G Ethernet Design Example without IEEE 1588v2Feature
Input ClockReset
Avalon-ST
Avalon-MM
LL 10GbE MAC
TX/RXSerialData
Ethernet channel 0
Transceiver Reconfig
Generated with Platform DesignerGenerated from IP Catalog
Design Example
(alt_mge_channel)
(alt_mge_rd)
Avalon-MM MuxTransceiver
Reconfig
TransceiverReset
Controller
PHY
fPLLATX PLL
S
S
S
AddressDecoder
.
.
.S
M
M
M
5.3.1. Design Components
Table 21. Design Components
Component Description
LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP with the following configuration:• Speed: 1G/2.5G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• All Legacy Ethernet 10G MAC Interfaces options: SelectedFor the design example with the IEEE 1588v2 feature, the following additional parametersare configured:• Enable time stamping: Selected• Enable PTP one-step clock support: Selected• Timestamp fingerprint width: 4• Time Of Day format: Enable both 96b and 64b Time of Day Format
PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel FPGA IPIP core. Resets the transceiver.
Avalon-MM Mux TransceiverReconfig
Provides the transceiver reconfig block and system console access to the PHY's Avalon-MMinterface.
Transceiver Reconfig Reconfigures the transceiver channel speed from 1 Gbps to 2.5 Gbps, and vice versa.
continued...
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Component Description
ATX PLL Generates a TX serial clock for the Intel Arria 10 2.5G transceiver.
fPLL Generates a TX serial clock for the Intel Arria 10 1G transceiver.
Design Components for the IEEE 1588v2 Feature
IO PLL Generates the clocks for the 1588 design components.
Master TOD The master time-of-day (TOD) for all channels.
TOD Synch Synchronizes the master TOD to all local TODs.
Local TOD The TOD for each channel.
Master Pulse Per Second Returns pulse per second (pps) for all channels.
Pulse Per Second Returns pulse per second (pps) for each channel.
PTP Packet Classifier Decodes the packet type of incoming PTP packets and returns the decoded information tothe LL 10GbE MAC Intel FPGA IP core.
5.3.2. Clocking Scheme
Figure 36. Clocking Scheme for the 1G/2.5G Ethernet Design Example with IEEE 1588v2Feature
MAC
PHY
Channel n
TOD2.5G
TOD 1G
Design Example
125 MHzReference
Clock
User Logic
CSR Clock
Core PLL
125 MHz Reference Clock2.5G TX Serial Clock (1562.5 MHz)1G TX Serial Clock (625 MHz)
HSSI RX Clock Out 62.5 MHz at 1G, 156.25 MHz at 2.5G
125 MHz CSR Clock53.33 MHz Sampling Clock
HSSI TX Clock Out 62.5 MHz at 1G, 156.25 MHz at 2.5G80 MHz Sampling Clock
PTP PacketClassifier
TOD 2.5GSync
TOD 1GSync
PPS2.5G
PPS 1G
MACClock
AddressDecoder
TransceiverReset
Controller
1G/2.5GReconfiguration
Block1G FPLL
2.5G ATXPLL
SamplingIOPLL
TODMaster
PPSMaster
156.25 MHz MAC Clock
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Figure 37. Clocking Scheme for the 1G/2.5G Ethernet Design Example without IEEE1588v2 Feature
MAC PHY
Transceiver ResetController
1G/2.5G/10GReconfiguration
Block
Channel 0
MAC PHY
Channel 1
2.5G PLL
1G PLL
Design Example
125 MHzReference
Clock
User Logic
User Logic
CSR Clock
2.5G TXSerialClock
1G TXSerialClock
PLL
125 MHz Reference Clock2.5G TX Serial Clock (3125 Mbps)1G TX Serial Clock (1250 Mbps)
HSSI TX Clock Out 62.5 MHz at 1G, 156.25 MHz at 2.5G125 MHz CSR Clock156.25 MHz MAC Clock
MAC ClockCDR Reference Clock
CDR Reference Clock
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5.3.3. Reset Scheme
The global reset signal of the design example is asynchronous and active-low.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.
Figure 38. Reset Scheme for the 1G/2.5G Ethernet Design Example without IEEE 1588v2Feature
MAC PHY
Transceiver ResetController
1G/2.5G/10GReconfiguration
Block
Channel 0
MAC PHY
Channel 1
2.5G PLL
1G PLL
Design Example
User Logic
User Logic
Global ResetAnalog Reset
PLL PowerdownDigital Reset
Global Reset
Reconfiguration Done (triggers reset)
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Figure 39. Reset Scheme for the 1G/2.5G Ethernet Design Example with IEEE 1588v2Feature
MAC
PHY
Channel n
TOD2.5G
TOD 1G
Design Example
User Logic
Global ResetDigital Reset
Analog Reset Reconfiguration Done (triggers reset)PLL Powerdown
GlobalReset
PTP PacketClassifier
TOD 2.5GSync
TOD 1GSync
PPS2.5G
PPS 1G
AddressDecoder
TransceiverReset
Controller1G FPLL
1.5G ATXPLL
SamplingIOPLL
TODMaster
PPSMaster
1G/2.5G/10GReconfiguration
Block
5.3.4. Partial Reconfiguration Ready
When the Partial Reconfiguration Ready option is turned on, the generatedhierarchy of the design example is in compliance with the partial reconfiguration flow.There is a clear separation between the hard IP and the soft IP. Hard IPs such asNative PHY, JTAG, transmitter (TX) PLL, and fPLL are instantiated at the top-levelwrapper of the design example. Certain soft IPs such as transceiver reset controllerand TX PLL reset controller are also instantiated at the top-level wrapper of the designexample because their functions are tightly coupled to the hard IPs. A wrapper calledalt_eth_pr contains the soft IP logic that you can add to the partial reconfigurationregion of your design. There is no functionality change after the PartialReconfiguration Ready option is turned on.
Figure 40. 1G/2.5G Ethernet Design Example Hierarchy Without IEEE 1588v2 FeatureWhen the Partial Reconfiguration Ready Option is Turned Off
Traffic Controller
altera_eth_top
TX PLL/fPLLCore PLL
JTAG Master
Address Decoder
TX PLL Reset Controller
Reconfiguration
MAC Soft PCS Native PHY
Transceiver Reset Controller
alt_mge_rdmge_channel
mge_phy
Hard Logic Soft Logic
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Figure 41. 1G/2.5G Ethernet Design Example Hierarchy Without IEEE 1588v2 FeatureWhen the Partial Reconfiguration Ready Option is Turned On
TrafficController
altera_eth_top
TX PLL/fPLL
Core PLL
JTAG Master
AddressDecoder
TX PLL Reset Controller
Reconfiguration
Native PHY
TransceiverReset
Controller
alt_mge_rd
MAC Soft PCS
mge_channelmge_phy
Hard Logic Soft Logic
alt_eth_pr
Figure 42. Design Example Hierarchy With the IEEE 1588v2 Feature When the PartialReconfiguration Ready Option is Turned Off
Traffic Controller
altera_eth_top
TX PLL/fPLLCore PLL
JTAG Master
Address Decoder
TX PLL Reset Controller
Master TOD & PPS
MAC Soft PCS Native PHY
Transceiver Reset Controller
alt_mge_rdmge_channel
mge_phy
Hard Logic Soft Logic
Reconfiguration
Slave TOD TOD Sync Packet Classifier
Figure 43. Design Example Hierarchy With the IEEE 1588v2 Feature When the PartialReconfiguration Ready Option is Turned On
altera_eth_top
TX PLL/fPLL
Core PLL
JTAG Master
TX PLL Reset ControllerNative PHY
TransceiverReset
Controller
Hard Logic Soft Logic
TrafficController
AddressDecoder Reconfiguration
alt_mge_rd
MAC Soft PCS
mge_channelmge_phy
alt_eth_pr
Slave TOD Packet Classifier
Master TOD & PPS
TOD Sync
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Related Information
Intel Quartus Prime Pro Edition Handbook Volume 1: Design and CompilationProvides information about partial reconfiguration design.
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5.4. Simulation
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
The simulation test case performs the following steps:
1. Starts up the design example with an operating speed of 2.5G.
2. Configures the MAC, PHY, and FIFO buffer for both channels.
3. Waits until the design example asserts the channel_tx_ready andchannel_rx_ready signals for each channel.
4. Sends the following packets:
• Non-PTP
• No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
• VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP
• Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
• No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
• VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
• Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
5. Repeats steps 2 to 4 for 1G.
When simulation ends, the values of the MAC statistics counters are displayed in thetranscript window. The transcript window also displays PASSED if the RX Avalon-STinterface of channel 0 received all packets successfully, all statistics error counters arezero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
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Figure 44. Sample Simulation Output
5.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
The simulation test case performs the following steps:
1. Starts up the example design with an operating speed of 2.5G.
2. Configures the MAC, PHY, and FIFO buffer for both channels.
3. Waits until the design example asserts the channel_tx_ready andchannel_rx_ready signals for both channels.
4. Sends the following packets:
• 64-byte packet
• 1518-byte packet
• 100-byte packet
5. Repeats steps 2 to 4 for 1G.
When simulation ends, the values of the MAC statistics counters are displayed in thetranscript window. The transcript window also displays PASSED if the RX Avalon-STinterface of channel 0 received all packets successfully, all statistics error counters arezero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
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5.5. Hardware Testing
Follow the procedure at the provided link to test the design example in the selectedhardware.
In the Clock Control application, which is part of the development kit, set the followingfrequencies:
• Y5—644.53125 MHz
• Y6—125 MHz
Related Information
• Compiling and Testing the Design in Hardware on page 12More information on the procedure and hardware setup.
• Clock ControlMore information on using the Clock Control application.
5.5.1. Test Procedure
Follow these steps to test the design examples in hardware:
1. Run the following command in the system console to start the test.
TEST_EXT_LB <channel> <speed> <burst_size>
Example: TEST_EXT_LB 0 2.5G 1000000000
Table 22. Command Parameters
Parameter Valid Values Description
channel 0, 1 The channel number to test.
speed 1G, 2.5G The PHY speed.
burst_size An integer value The number of packets to generate for the test.
2. When the test is completed, observe the output displayed. The following diagramsshow excerpts of the output, which shows that the Ethernet packet monitor blockreceives the same number of packets generated without error, and the TX and RXstatistics counters.
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Figure 45. Sample Test Output—Ethernet Packet Monitor
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Figure 46. Sample Test Output—Statistics Counters
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5.6. Interface Signal
Figure 47. Interface Signals of the 1G/2.5G Ethernet Design Example
MAC RX
1G/2.5G Ethernet Design Example
avalon_st_rxstatus_valid[n]avalon_st_rxstatus_data[n][40]avalon_st_rxstatus_error[n][7]
Avalon-ST ReceiveStatus Interface
avalon_st_rx_endofpacket[n]avalon_st_rx_startofpacket[n]
avalon_st_rx_valid[n]avalon_st_rx_ready[n]avalon_st_rx_error[n][6]avalon_st_rx_data[n][32]avalon_st_rx_empty[n][2]
Avalon-ST ReceiveData Interface
Avalon-ST TransmitStatus Interface
avalon_st_txstatus_valid[n]avalon_st_txstatus_data[n][40]avalon_st_txstatus_error[n][7]
Avalon-ST TransmitFlow Control Interface
avalon_st_pause_data[n][2]
Avalon-ST TransmitData Interface
avalon_st_tx_startofpacket[n]avalon_st_tx_endofpacket[n]avalon_st_tx_valid[n]avalon_st_tx_ready[n]avalon_st_tx_error[n]avalon_st_tx_data[n][32]avalon_st_tx_empty[n][2]
Avalon-MM Interface
Clock andReset
csr_clk
refclkmac_clk
reset
tx_digital_reset[n]rx_digital_reset[n]
rx_pma_clkout
Additional Signals for Example Design With IEEE 1588v2 Feature
IEEE 1588v2Time-Stamp
Interface
tx_egress_timestamp_96b_valid[n]tx_egress_timestamp_96b_data[n][96]tx_egress_timestamp_96b_fingerprint[n][f]tx_egress_timestamp_64b_valid[n]tx_egress_timestamp_64b_data[n][64]tx_egress_timestamp_64b_fingerprint[n][f]rx_ingress_timestamp_96b_valid[n]rx_ingress_timestamp_96b_data[n][96]rx_ingress_timestamp_64b_valid[n]rx_ingress_timestamp_64b_data[n][64]
n: Number of channelsf: Timestamp fingerprint width
master_pulse_per_secondstart_tod_sync[n]
pps[n] TOD Interface
Packet ClassifierInterface
tx_egress_timestamp_request_in_valid[n]tx_egress_timestamp_request_in_fingerprint[n][f]
clock_operation_mode_mode[n][2]pkt_with_crc_mode[n]
tx_ingress_timestamp_valid[n]tx_ingress_timestamp_96b_data[n][96]tx_ingress_timestamp_64b_data[n][64]
tx_ingress_timestamp_format[n]
PHY Interfacerx_serial_data[n]tx_serial_data[n]
led_char_err[n]led_disp_err[n]led_an[n]channel_tx_ready[n]
led_link[n]
channel_rx_ready[n]
csr_mac_read[n]csr_mac_readdata[n][32]
csr_mac_write[n]csr_mac_writedata[32]
csr_mac_address[n][10]csr_mac_waitrequest[n]
csr_master_tod_waitrequest[n]
csr_master_tod_read[n]csr_master_tod_readdata[n][32]
csr_master_tod_write[n]csr_master_tod_writedata[n][32]
csr_master_tod_address[n][4]
csr_phy_read[n]csr_phy_readdata[n][32]
csr_phy_write[n]csr_phy_writedata[32]csr_phy_address[n][5]
csr_phy_waitrequest[n]csr_rcfg_read[n]
csr_rcfg_readdata[32]csr_rcfg_write[n]
csr_rcfg_writedata[32]csr_rcfg_address[2]
csr_native_phy_rcfg_read[n]csr_native_phy_rcfg_readdata[32]
csr_native_phy_rcfg_write[n]csr_native_phy_rcfg_writedata[32]
csr_native_phy_rcfg_waitrequest[n]csr_native_phy_rcfg_address[10]
(LL 10GbE MAC)
Avalon-MM Interface(1G/2.5G/10G Multi-rate Ethernet PHY)
Avalon-MM Interface(Reconfiguration)
Avalon-MM Interface(Native PHY Reconfiguration)
Avalon-MM Interface(Master ToD Clock)
Status Interface
Related Information
Interface Signals Description on page 88For more information on each interface signal.
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5.7. Configuration Registers
You can access the 32-bit configuration registers of the design components throughthe Avalon-MM interface.
Table 23. Register Map
Byte Offset Block
0x00_0000 Transceiver Reconfiguration
0x00_4000 Reserved
Channel 0
0x01_0000 MAC
0x01_8000 PHY
0x01_A000 Native PHY Reconfiguration
Channel 1
0x02_0000 MAC
0x02_8000 PHY
0x02_A000 Native PHY Reconfiguration
Traffic Controller
0x10_0000 Traffic Controller
Related Information
Configuration Registers Description on page 97For more information on each configuration register.
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6. 1G/2.5G/10G Ethernet Design Example for Intel Arria10 Devices
The 1G/2.5G/10G Ethernet design example demonstrates the functionalities of the LL10GbE MAC Intel FPGA IP core operating at 1G, 2.5G, and 10G.
Generate the design example from the Example Design tab of the LL 10GbE IntelFPGA IP parameter editor.
6.1. Features
• Tri-speed Ethernet operation—1G, 2.5G, and 10G.
• Support for two channels.
• Testbench and simulation script.
• Tested with the Spirent TestCenter.
• Option to generate design example with Partial Reconfiguration Ready.
6.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linuxsystem:
• Intel Quartus Prime Pro Edition software (Partial Reconfiguration Ready)
• ModelSim-AE, ModelSim-SE, NCSim (Verilog only), VCS, and Xcelium (IntelQuartus Prime Pro Edition only) simulators
• For hardware testing:
— Intel Arria 10 GX Signal Integrity Development Board(10AX115S4F45E3SGE3)
— Cables—SMA cable, SFP+, and fiber optic cable
Note: Partial Reconfiguration Ready feature is supported from Intel Quartus Prime ProEdition software version 17.0 onwards.
6.3. Functional Description
The design example consists of various components. The following block diagramshows the design components and the top-level signals of the design example.
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
Figure 48. Block Diagram—1G/2.5G/10G Ethernet Design Example
1G Input ClockReset
AddressDecoder
Avalon-MM
LL 10GbE MAC
TX/RXSerialData
Ethernet channel 0..(n-1)
Transceiver Reconfig
Avalon-ST
Design Example
(alt_mge_channel)
(alt_mge_rd)
Avalon-MM MuxTransceiver
Reconfig
TransceiverReset
Controller
PHY
.
.
.
ATX PLL(10G)
ATX PLL(2.5G)
10G Input ClockGenerated with Platform DesignerGenerated from IP Catalog
S
S
S
M
M
M
S fPLL(1G)
6.3.1. Design Components
Table 24. Design Components
Component Description
LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration:• Speed: 1G/2.5G/10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• All Legacy Ethernet 10G MAC Interfaces options: Selected
PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel FPGA IP core. Resets the transceiver.
Avalon-MM Mux TransceiverReconfig
Provides the transceiver reconfig block and system console access to the PHY's Avalon-MMinterface.
Transceiver Reconfig Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa.
ATX PLL Generates a TX serial clock for the Intel Arria 10 2.5G and 10G transceiver.
fPLL Generates a TX serial clock for the Intel Arria 10 1G transceiver.
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6.3.2. Clocking Scheme
Figure 49. Clocking Scheme for the 1G/2.5G/10G Ethernet Design Example
MAC PHY
Transceiver ResetController
1G/2.5G/10GReconfiguration
Block
Channel 0
MAC PHY
Channel 1
2.5G PLL
1G PLL
Design Example
125 MHzReference
Clock
User Logic
User Logic
CSR Clock2.5G TXSerial Clock
1G TXSerial Clock
10G TXSerial Clock
PLL
125 MHz Reference Clock
2.5G TX Serial Clock (1562.5 Mbps)
1G TX Serial Clock (625 Mbps)HSSI TX Clock Out 62.5 MHz at 1G, 156.25 MHz at 2.5G125 MHz CSR Clock
156.25 MHz MAC Clock
MAC Clock CDR Reference Clocks
CDR Reference Clock
10G PLL
644.53125 MHzReference
Clock
10G TX Serial Clock (5156.25 Mbps)644.53125 MHz Reference Clock
6.3.3. Reset Scheme
The global reset signal of the design example is asynchronous and active-high.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.
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Figure 50. Reset Scheme for the 1G/2.5G/10G Ethernet Design Example
MAC PHY
Transceiver ResetController
1G/2.5G/10GReconfiguration
Block
Channel 0
MAC PHY
Channel 1
2.5G PLL
1G PLL
Design Example
User Logic
User Logic
Global ResetAnalog Reset
PLL PowerdownDigital Reset
Global Reset
Reconfiguration Done (triggers reset)
10G PLL
6.3.4. Partial Reconfiguration Ready
When the Partial Reconfiguration Ready option is turned on, the generatedhierarchy of the design example is in compliance with the partial reconfiguration flow.There is a clear separation between the hard IP and the soft IP. Hard IPs such asNative PHY, JTAG, transmitter (TX) PLL, and fPLL are instantiated at the top-levelwrapper of the design example. Certain soft IPs such as transceiver reset controllerand TX PLL reset controller are also instantiated at the top-level wrapper of the designexample because their functions are tightly coupled to the hard IPs. A wrapper calledalt_eth_pr contains the soft IP logic that you can add to the partial reconfigurationregion of your design. There is no functionality change after the PartialReconfiguration Ready option is turned on.
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Figure 51. 1G/2.5G/10G Ethernet Design Example Hierarchy when the PartialReconfiguration Ready Option is Turned Off
Traffic Controller
altera_eth_top
TX PLL/fPLLCore PLL
JTAG Master
Address Decoder
TX PLL Reset Controller
Reconfiguration
MAC Soft PCS Native PHY
Transceiver Reset Controller
alt_mge_rdmge_channel
mge_phy
Hard Logic Soft Logic
Figure 52. 1G/2.5G/10G Ethernet Design Example Hierarchy when the PartialReconfiguration Ready Option is Turned On
TrafficController
altera_eth_top
TX PLL/fPLL
Core PLL
JTAG Master
AddressDecoder
TX PLL Reset Controller
Reconfiguration
Native PHY
TransceiverReset
Controller
alt_mge_rd
MAC Soft PCS
mge_channelmge_phy
Hard Logic Soft Logic
alt_eth_pr
Related Information
Intel Quartus Prime Pro Edition Handbook Volume 1: Design and CompilationProvides information about partial reconfiguration design.
6.3.5. Timing Constraints
When you configure the PHY in 1G/2.5G/10G (MGBASE-T) configuration, Intelrecommends that you refer to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IntelFPGA IP Core section of Intel Arria 10 Transceiver PHY User Guide for details on thetiming constraint examples.
In addition, you must set the false path from 10G PHY clock to Low Latency (LL)Ethernet 10G (10GbE) MAC logic and vice versa. Since the LL 10GbE MAC logic is notrunning 10G PHY clock, you do not need to ensure timing closure for LL 10GbE MACdata path at 10G PHY clock. For example:
set_false_path -from [get_clocks "$rx_pma_clk_10g_name $rx_clkout_10g_name $tx_pma_clk_10g_name $tx_clkout_10g_name"] -to [get_registers *|alt_em10g32:*|*]set_false_path -from [get_registers *|alt_em10g32:*|*] -to [get_clocks "$rx_pma_clk_10g_name $rx_clkout_10g_name $tx_pma_clk_10g_name $tx_clkout_10g_name"]
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where the path indicated by rx_pma_clk_10g_name, rx_clkout_10g_name,tx_clkout_10g_name, and tx_clkout_10g_name is associated with the 10G PHYclock, whereas the alt_em10g32 path indicates the LL 10GbE MAC logic.
Related Information
Intel Arria 10 Transceiver PHY User Guide
6.4. Simulation
The simulation test case performs the following steps:
1. Starts up the example design with an operating speed of 10 Gbps.
2. Configures the MAC, PHY, and FIFO buffer for both channels.
3. Waits until the design example asserts the channel_tx_ready andchannel_rx_readysignals for both channels.
4. Sends the following packets:
• 64-byte packet
• 1518-byte packet
• 100-byte packet
5. Repeats steps 2 to 4 for 1G and 2.5G.
When simulation ends, the values of the MAC statistics counters are displayed in thetranscript window. The transcript window also displays PASSED if the RX Avalon-STinterface of channel 0 received all packets successfully, all statistics error counters arezero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
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Figure 53. Sample Simulation Output
6.5. Hardware Testing
Follow the procedure at the provided link to test the design example in the selectedhardware.
In the Clock Control application, which is part of the development kit, set the followingfrequencies:
• Y5—644.53125 MHz
• Y6—125 MHz
Related Information
• Compiling and Testing the Design in Hardware on page 12More information on the procedure and hardware setup.
• Clock ControlMore information on using the Clock Control application.
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6.5.1. Test Procedure
Follow these steps to test the design examples in hardware:
1. Run the following command in the system console to start the test.
TEST_EXT_LB <channel> <speed> <burst_size>
Example: TEST_EXT_LB 0 10G 80000000
Table 25. Command Parameters
Parameter Valid Values Description
channel 0, 1 The channel number to test.
speed 1G, 2.5G, 10G The PHY speed.
burst_size An integer value The number of packets to generate for the test.
2. When the test is completed, observe the output displayed. The following diagramsshow excerpts of the output, which shows that the packet monitor block receivesthe same number of packets generated without error, and the TX and RX statisticscounters.
Figure 54. Sample Test Output—Packet Monitor
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Figure 55. Sample Test Output—Statistics Counters
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6.6. Interface Signals
Figure 56. Interface Signals of the 1G/2.5G/10G Ethernet Design Example
MAC RX
1G/2.5G/10G Ethernet Design Example
avalon_st_rx_status_valid[n]avalon_st_rx_status_data[n][40]avalon_st_rx_status_error[n][7]
Avalon-ST ReceiveStatus Interface
avalon_st_rx_endofpacket[n]avalon_st_rx_startofpacket[n]
avalon_st_rx_valid[n]avalon_st_rx_ready[n]avalon_st_rx_error[n][6]avalon_st_rx_data[n][64]avalon_st_rx_empty[n][3]
Avalon-ST ReceiveData Interface
Avalon-ST TransmitStatus Interface
avalon_st_tx_status_valid[avalon_st_tx_status_data[n][40]avalon_st_tx_status_error[n][7]
n]
Avalon-ST TransmitFlow Control Interface
avalon_st_pause_data[n][2]
Avalon-ST TransmitData Interface
avalon_st_tx_startofpacket[n]avalon_st_tx_endofpacket[n]avalon_st_tx_valid[n]avalon_st_tx_ready[n]avalon_st_tx_error[n]avalon_st_tx_data[n][64]avalon_st_tx_empty[n][3]
Avalon-MM Interface
Clock andReset
csr_clk
refclk_10g
mac_clk
reset
tx_digitalreset[n]rx_digitalreset[n]
rx_pma_clkout
mac64b_clk
refclk_1g2p5g
n: Number of channels
PHY Interface rx_serial_data[n]tx_serial_data[n]
led_link[n]
led_char_err[n]led_disp_err[n]led_an[n]
channel_tx_ready[n]channel_rx_ready[n]
rx_block_lock[n]
csr_mac_read[n]csr_mac_readdata[n][32]
csr_mac_write[n]csr_mac_writedata[32]
csr_mac_address[n][10]csr_mac_waitrequest[n]
csr_phy_read[n]csr_phy_readdata[n][32]
csr_phy_write[n]csr_phy_writedata[32]csr_phy_address[n][11]
csr_phy_waitrequest[n]
csr_rcfg_readcsr_rcfg_readdata[32]
csr_rcfg_writecsr_rcfg_writedata[32]
csr_rcfg_address[2]
(LL 10GbE MAC)
Avalon-MM Interface(1G/2.5G/10G Multi-rate Ethernet PHY)
Avalon-MM Interface(Reconfiguration)
Status Interface
led_panel_link[n]
Related Information
Interface Signals Description on page 88For more information on each interface signal.
6.7. Configuration Registers
You can access the 32-bit configuration registers of the design components throughthe Avalon-MM interface.
Table 26. Register Map
Byte Offset Block
0x00_0000 Transceiver Reconfiguration
0x00_4000 Reserved
Channel 0
0x01_0000 MAC
0x01_8000 PHY
0x01_A000 Native PHY Reconfiguration
Channel 1
0x02_0000 MAC
0x02_8000 PHY
continued...
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Byte Offset Block
0x02_A000 Native PHY Reconfiguration
Traffic Controller
0x10_0000 Traffic Controller
Related Information
Configuration Registers Description on page 97For more information on each configuration register.
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7. 10M/100M/1G/2.5G/5G/10G (USXGMII) EthernetDesign Example for Intel Arria 10 Devices
The 10G USXGMII Ethernet design example demonstrates the functionalities of the LL10GbE MAC Intel FPGA IP core operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.
Generate the design example from the Example Design tab of the LL 10GbE IntelFPGA IP parameter editor.
7.1. Features
• Supports dual Ethernet channel operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.
• On the transmit and receive paths:
— Provides packet monitoring system.
— Reports Ethernet MAC statistics counter.
• Supports testing using different types of Ethernet packet transfer protocol.
7.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linuxsystem:
• Intel Quartus Prime software
• ModelSim-AE, ModelSim-SE, NCSim (Verilog only), VCS, and Xcelium (IntelQuartus Prime Pro Edition only) simulators
• For hardware testing:
— Intel Arria 10 GX Signal Integrity Development Board(10AX115S4F45E3SGE3)
— Cables—SFP+ and fiber optic cable
7.3. Functional Description
The design example consists of various components. The following block diagramshows the design components and the top-level signals of the design example.
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
Figure 57. Block Diagram—10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet DesignExample
Reset
Avalon-MM
LL 10GbE MAC
TX/RXSerialData
Ethernet channel 0..(n-1)
Design Example
(alt_mge_channel)
(alt_mge_rd)
TransceiverReset
Controller
PHY
ATX PLL(10G) Core fPLL
10G Input Clock
Avalon-ST
312.5 MHz156.25 MHz
AddressDecoder
.
.
.S
M
M
Generated with Platform DesignerGenerated from IP Catalog
S
S
7.3.1. Design Components
Table 27. Design Components
Component Description
LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration:• Speed: 10M/100M/1G/2.5G/5G/10G (USXGMII)• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• TX and RX datapath Reset/Default To Enable: Selected• Use legacy XGMII Interface: Not selected• Use legacy Avalon Memory-Mapped Interface: Not selected• Use legacy Avalon Streaming Interface: Selected
PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP with the followingconfiguration:• Speed: 10M/100M/1G/2.5G/5G/10G• Connect to MGBASE-T PHY: Not selected• Connect to NBASE-T PHY: Selected• Reference clock frequency for 10GbE (MHz): 644.53125• Enable Native PHY Debug Master Endpoint: Not selected• Enable capability registers: Not selected• Enable control and status registers: Not selected• Enable PRBS soft accumulators: Not selected
continued...
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Component Description
Channel address decoder Decodes the addresses of the components in each Ethernet channel, such as PHY and LL10GbE MAC.
Multi-channel addressdecoder
Decodes the addresses of the components used by all channels, such as the Master ToDmodule.
Top address decoder Decodes the addresses of the top-level components, such as the Traffic Controller.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel FPGA IP core. Resets the transceiver.
ATX PLL Generates a TX serial clock for the Intel Arria 10 10G transceiver.
Core fPLL Generates clocks for all design components.
7.3.2. Clocking Scheme
Figure 58. Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) EthernetDesign Example
MAC PHY
Transceiver ResetController
Channel 0
MAC PHY
Channel 1
10G PLL
Design Example
644.53125 MHzReference Clock
User Logic
User Logic
CSR Clock10G TXSerial Clock
PLL
644.53125 MHz Reference Clock 10G TX Serial Clock (5156.25 MHz)
312.5 MHz MAC Clock
MAC ClockCDR Reference Clock
CDR Reference Clock
125 MHz CSR Clock
7.3.3. Reset Scheme
The global reset signal of the design example is asynchronous and active-high.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.
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Figure 59. Reset Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet DesignExample
MAC PHY
Transceiver ResetController
Channel 0
MAC PHY
Channel 1
10G PLL
Design Example
XGMII withData Valid
XGMII withData Valid
User Logic
User Logic
Global Reset
Global Reset Analog Reset
Digital ResetPLL Powerdown
7.4. Simulation
7.4.1. Test Case
The simulation test case performs the following steps:
1. Starts up the example design with an operating speed of 10G.
2. Configures the MAC, PHY, and FIFO buffer for both channels.
3. Waits until the design example asserts the channel_tx_ready andchannel_rx_readysignals for both channels.
4. Sends the following packets:
• 64-byte packet
• 1518-byte packet
• 100-byte packet
5. Repeats steps 2 to 4 for 10M, 100M, 1G, 2.5G, and 5G.
When simulation ends, the values of the MAC statistics counters are displayed in thetranscript window. The transcript window also displays PASSED if the RX Avalon-STinterface of channel 0 received all packets successfully, all statistics error counters arezero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
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Figure 60. Sample Simulation Output
7.5. Hardware Testing
Follow the procedure at the provided link to test the design example in the selectedhardware.
In the Clock Control application, which is part of the development kit, set the followingfrequencies:
• Y5—644.53125 MHz
• Y6—125 MHz
Related Information
• Compiling and Testing the Design in Hardware on page 12More information on the procedure and hardware setup.
• Clock ControlMore information on using the Clock Control application.
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7.5.1. Test Procedure
Follow these steps to test the design examples in hardware:
1. Run the following command in the system console to enable PHY serial loopbackon Channel 0:
SET_CHANNEL_BASE_ADDR 0
SETPHY_SERIAL_LLPBK
Note: This step is only required if you are using Intel Arria 10 GX SI DevelopmentBoard rev E and above, and on Channel 0 only.
2. Run the following command in the system console to start the test.
TEST_EXT_LB <channel> <speed> <burst_size>
Example: TEST_EXT_LB 0 10G 80000000
Table 28. Command Parameters
Parameter Valid Values Description
channel 0, 1 The channel number to test.
speed 10M, 100M, 1G, 2P5G, 5G,10G
The PHY speed.
burst_size An integer value The number of packets to generate for the test.
3. When the test is completed, observe the output displayed. The following diagramsshow excerpts of the output, which shows that the Ethernet packet monitor blockreceives the same number of packets generated without error, and the TX and RXstatistics counters.
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Figure 61. Sample Test Output—Ethernet Packet Monitor
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Figure 62. Sample Test Output—Statistics Counters
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7.6. Interface Signals
Figure 63. Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) EthernetDesign Example
10M/100M/1G/2.5G/5G/10G (USXGMII)Ethernet Design Example
Clock andReset
csr_clk
mac32b_clk
reset
refclk_10g
mac64_clkrx_pma_clkout[
tx_digitalreset[rx_digitalreset[
avalon_st_rx_status_valid[n]avalon_st_rx_status_data[n][40]avalon_st_rx_status_error[n][7]
Avalon-ST ReceiveStatus Interface
avalon_st_rx_endofpacket[n]avalon_st_rx_startofpacket[n]
avalon_st_rx_valid[n]avalon_st_rx_ready[n]avalon_st_rx_error[n][6]avalon_st_rx_data[n][64]avalon_st_rx_empty[n][3]
Avalon-ST ReceiveData Interface
Avalon-ST TransmitStatus Interface
avalon_st_tx_status_valid[n]avalon_st_tx_status_data[n][40]avalon_st_tx_status_error[n][7]
Avalon-ST TransmitFlow Control Interface
avalon_st_pause_data[n][2]
Avalon-ST TransmitData Interface
avalon_st_tx_startofpacket[n]avalon_st_tx_endofpacket[n]avalon_st_tx_valid[n]avalon_st_tx_ready[n]avalon_st_tx_error[n]avalon_st_tx_data[n][64]avalon_st_tx_empty[n][3]
Avalon-MMInterface
csr_mch_readcsr_mch_readdata[32]
csr_mch_writecsr_mch_writedata[32]
csr_mch_address[20]csr_mch_waitrequest
channel_tx_ready[n]channel_rx_ready[n]
rx_block_lock[n]led_an[n]
tx_serial_data[rx_serial_data[
PHY Interface
Status Interface
n]n]
n]
n]n]
n : Number of channels
Related Information
Interface Signals Description on page 88For more information on each interface signal.
7.7. Configuration Registers
You can access the 32-bit configuration registers of the design components throughthe Avalon-MM interface.
Table 29. Register Map
Byte Offset Block
0x00_0000 Reserved
Channel 0
0x02_0000 Reserved
0x02_4000 PHY
0x02_6000 Native PHY Reconfiguration
0x02_8000 MAC
Channel 1
0x03_0000 Reserved
continued...
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Byte Offset Block
0x03_4000 PHY
0x03_6000 Native PHY Reconfiguration
0x03_8000 MAC
Traffic Controller
0x10_0000 Traffic Controller
Related Information
Configuration Registers Description on page 97For more information on each configuration register.
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel Arria 10 Devices
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8. Interface Signals DescriptionUse the following tables to find the description of the signals in the LL 10GbE MACIntel FPGA IP design examples. The pinout diagram for each design example specifiesthe width of the signals.
8.1. Clock and Reset Interface Signals
Table 30. Clock and Reset Interface Signals
Signal Direction Width Description
mm_clk
csr_clk
In 1 125 MHz configuration clock for theAvalon-MM interface.
mac_clk In 1 156.25 MHz configuration clock for theAvalon-ST interface.
refclk In 1 125 MHz reference clock for the TX PLLs.
pll_ref_clk_1g[] In [NUM_UNSHARED_CHANNELS] Reference clock for the TX PLL in 1Gmode. Frequency is 125 MHz.
pll_ref_clk_10g[] In [NUM_UNSHARED_CHANNELS] Reference clock for the TX PLL in 10Gmode. Frequency is 644.53125 MHz.
cdr_ref_clk_1g[] In [NUM_UNSHARED_CHANNELS] Reference clock for the RX PLL in 1Gmode. Frequency is 125 MHz.
cdr_ref_clk_10g[] In [NUM_UNSHARED_CHANNELS] Reference clock for the RX PLL in 10Gmode. Frequency is 644.53125 MHz.
xgmii_clk Out [NUM_UNSHARED_CHANNELS] Clock used for single data rate (SDR)XGMII TX and RX interface in betweenMAC and PHY. Whenever present, thisclock is also used for Avalon-ST interface.Frequency is 156.25 MHz.
rx_pma_clkout Out 1 CDR recovered clock.
rx_recovered_clk Out [NUM_CHANNELS] RX clock, recovered from the RX data.
tx_xcvr_clk Out 1 322.265625 MHz clock for the TXdatapath.
rx_xcvr_clk Out 1 322.265625 MHz clock for the RXdatapath.
rx_xcvr_half_clk Out 1 161.133 MHz synchronous clock derivedfrom rx_xcvr_clk
tx_xcvr_half_clk Out 1 161.133 MHz synchronous clock derivedfrom tx_xcvr_clk
ref_clk_clk In 1 322.265625 MHz clock for the TX PLL.
core_clk_312 Out 1 312.5 MHz clock for the fast domain.
continued...
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ISO9001:2015Registered
Signal Direction Width Description
core_clk_156 Out 1 156.25-MHz clock for the slow domain.
channel_reset_n In [NUM_CHANNELS] Assert this asynchronous and active-lowsignal to reset individual Ethernetchannel. This does not impact thecomponents running at multi_channellevel, for example, master TOD, masterPPS and fPLLs.
master_reset_n In 1 Assert this asynchronous and active-lowsignal to reset the whole design example.
reset In 1 Assert this asynchronous and active-highsignal to reset the whole design example.
csr_rst_n In 1 Active-low reset signal for the Avalon-MMinterface.
tx_rst_n In 1 Active-low reset signal for the TXdatapath.
rx_rst_n In 1 Active-low reset signal for the RXdatapath.
tx_digitalreset In [NUM_CHANNELS] Asynchronous and active-high signal toreset PCS TX portion of the transceiverPHY.
rx_digitalreset In [NUM_CHANNELS] Asynchronous and active-high signal toreset PCS RX portion of the transceiverPHY.
tx_analogreset In [NUM_CHANNELS] Asynchronous and active-high signal toreset PMA TX portion of the transceiverPHY.
rx_analogreset In [NUM_CHANNELS] Asynchronous and active-high signal toreset PMA RX portion of the transceiverPHY.
8.2. Avalon-MM Interface Signals
Table 31. Avalon-MM Interface Signals
Signal Direction Description
write
csr_mac_write
csr_phy_write
csr_rcfg_write
csr_native_phy_rcfg_write
csr_master_tod_write
csr_mch_write
In Assert this signal to request a write.
read
csr_mac_read
csr_phy_read
csr_rcfg_read
csr_native_phy_rcfg_read
csr_master_tod_read
In Assert this signal to request a read.
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Signal Direction Description
csr_mch_read
address
csr_mac_address
csr_phy_address
csr_rcfg_address
csr_native_phy_rcfg_address
csr_master_tod_addresscsr_mch_address
In Use this bus to specify the register address you want to read from or write to.
writedata
csr_mac_writedata
csr_phy_writedata
csr_rcfg_writedata
csr_native_phy_rcfg_writedata
csr_master_tod_writedata
csr_mch_writedata
In Carries the data to be written to the specified register.
readdata
csr_mac_readdata
csr_phy_readdata
csr_rcfg_readdata
csr_native_phy_rcfg_readdata
csr_master_tod_readdata
csr_mch_readdata
Out Carries the data read from the specified register.
waitrequest
csr_mac_waitrequest
csr_phy_waitrequest
csr_native_phy_rcfg_waitrequest
csr_master_tod_waitrequest
csr_mch_waitrequest
Out When asserted, this signal indicates that the IP core is busy and not ready toaccept any read or write requests.
8.3. Avalon-ST Interface Signals
Table 32. Avalon-ST Interface Signals
Signal Direction Width Description
avalon_st_tx_startofpacket[]
In [NUM_CHANNELS] Assert this signal to indicate the beginning of the TXdata.
avalon_st_tx_endofpacket[]
In [NUM_CHANNELS] Assert this signal to indicate the end of the TX data.
avalon_st_tx_valid[] In [NUM_CHANNELS] Assert this signal to indicate thatavalon_st_tx_data[] and other signals on thisinterface are valid.
continued...
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Signal Direction Width Description
avalon_st_tx_ready[] Out [NUM_CHANNELS] When asserted, indicates that the MAC IP core isready to accept data. The reset value of this signalis non-deterministic.
avalon_st_tx_error[] In [NUM_CHANNELS] Assert this signal to indicate that the current TXpacket contains errors.
avalon_st_tx_data[][]
In [NUM_CHANNELS][m] TX data from the client.m is 64 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is32.
avalon_st_tx_empty[][]
In [NUM_CHANNELS][m] Use this signal to specify the number of emptybytes in the cycle that contain the end of the TXdata.m is 3 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is 2.• 0x0—All bytes are valid.• 0x1—The last byte is invalid.• 0x2—The last two bytes are invalid.• 0x3—The last three bytes are invalid.
avalon_st_rx_startofpacket[]
Out [NUM_CHANNELS] When asserted, indicates the beginning of the RXdata.
avalon_st_rx_endofpacket[]
Out [NUM_CHANNELS] When asserted, indicates the end of the RX data.
avalon_st_rx_valid[] Out [NUM_CHANNELS] When asserted, indicates that the avalon_st_rx_data[] signal and other signals on this interface arevalid.
avalon_st_rx_ready[] In [NUM_CHANNELS] Assert this signal when the client is ready to acceptdata.
avalon_st_rx_error[][]
Out [NUM_CHANNELS][6] When set to 1, the respective bits indicate an errortype:• Bit 0—PHY error. For 10 Gbps, the data on
xgmii_rx_data contains a control errorcharacter (FE). For 10 Mbps,100 Mbps,1 Gbps,gmii_rx_err or mii_rx_err is asserted.
• Bit 1—CRC error. The computed CRC valuediffers from the received CRC.
• Bit 2—Undersized frame. The receive framelength is less than 64 bytes.
• Bit 3—Oversized frame. The receive framelength is more than MAX_FRAME_SIZE.
• Bit 4—Payload length error. The actual framepayload length is different from the value in thelength/type field.
• Bit 5—Overflow error. The receive FIFO buffer isfull while it is still receiving data from the MACIP core.
avalon_st_rx_data[][]
Out [NUM_CHANNELS][m] RX data to the client.m is 64 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is32.
avalon_st_rx_empty[][]
Out [NUM_CHANNELS][m] Contains the number of empty bytes during thecycle that contain the end of the RX data.m is 3 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is 2.
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Signal Direction Width Description
avalon_st_tx_status_valid[]
Out [NUM_CHANNELS] When asserted, this signal qualifies theavalon_st_txstatus_data[] andavalon_st_txstatus_error[] signals.
avalon_st_tx_status_data[][]
Out [NUM_CHANNELS][40] Contains information about the TX frame.• Bits 0 to 15—Payload length.• Bits 16 to 31—Packet length.• Bit 32—When set to 1, indicates a stacked VLAN
frame.• Bit 33—When set to 1, indicates a VLAN frame.• Bit 34—When set to 1, indicates a control frame.• Bit 35—When set to 1, indicates a pause frame.• Bit 36—When set to 1, indicates a broadcast
frame.• Bit 37—When set to 1, indicates a multicast
frame.• Bit 38—When set to 1, indicates a unicast frame.• Bit 39—When set to 1, indicates a PFC frame.
avalon_st_tx_status_error[][]
Out [NUM_CHANNELS][7] When set to 1, the respective bit indicates thefollowing error type in the RX frame.• Bit 0—Undersized frame.• Bit 1—Oversized frame.• Bit 2—Payload length error.• Bit 3—Unused.• Bit 4—Underflow.• Bit 5—Client error.• Bit 6—Unused.The error status is invalid when an overflow occurs.
avalon_st_rxstatus_valid[]
Out [NUM_CHANNELS] When asserted, this signal qualifies theavalon_st_rxstatus_data[] andavalon_st_rxstatus_error[] signals.The MAC IP core asserts this signal in the sameclock cycle the avalon_st_rx_endofpacketsignal is asserted.
avalon_st_rxstatus_data[][]
Out [NUM_CHANNELS][40] Contains information about the RX frame.• Bits 0 to 15—Payload length.• Bits 16 to 31—Packet length.• Bit 32—When set to 1, indicates a stacked VLAN
frame.• Bit 33—When set to 1, indicates a VLAN frame.• Bit 34—When set to 1, indicates a control frame.• Bit 35—When set to 1, indicates a pause frame.• Bit 36—When set to 1, indicates a broadcast
frame.• Bit 37—When set to 1, indicates a multicast
frame.• Bit 38—When set to 1, indicates a unicast frame.• Bit 39—When set to 1, indicates a PFC frame.
avalon_st_rxstatus_error[][]
Out [NUM_CHANNELS][7] When set to 1, the respective bit indicates thefollowing error type in the RX frame.• Bit 0—Undersized frame.• Bit 1—Oversized frame.• Bit 2—Payload length error.• Bit 3—Unused.
continued...
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Signal Direction Width Description
• Bit 4—Underflow.• Bit 5—Client error.• Bit 6—Unused.The error status is invalid when an overflow occurs.
avalon_st_pause_data[][]
In [NUM_CHANNELS][2] This signal takes effect when the register bits,tx_pauseframe_enable[2:1], are both set tothe default value 0.Set this signal to the following values to trigger thecorresponding actions.• 0x0—Stops pause frame generation.• 0x1—Generates an XON pause frame.• 0x2—Generates an XOFF pause frame. The MAC
IP core sets the pause quanta field in the pauseframe to the value in thetx_pauseframe_quanta register.
• 0x3—Reserved.
Related Information
Avalon-ST Data Interface Clocks, Low Latency Ethernet 10G MAC Intel FPGA IP UserGuide
8.4. PHY Interface Signals
Table 33. PHY Interface Signals
Signal Direction Description
rx_serial_data In RX serial input data
tx_serial_data Out TX serial output data
8.5. Status Interface
Table 34. Status Interface Signals
Signal Direction Description
block_lock Out Asserted when the link synchronization is successful.
led_an
ethernet_1g_an
Out Asserted when auto-negotiation is completed.
led_char_err
ethernet_1g_char_err
Out Asserted when a 10-bit character error is detected in the RX data.
led_disp_err
ethernet_1g_disp_err
Out Asserted when a 10-bit running disparity error is detected in the RX data.
channel_ready
channel_tx_ready
channel_rx_ready
tx_ready_export
rx_ready_export
Out Asserted when the channel is ready for data transmission.
atx_pll_locked Out Asserted when the TX PLL is locked.
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8.6. IEEE 1588v2 Timestamp Interface Signals
Table 35. IEEE 1588v2 Timestamp Interface Signals
Signal Direction Width Description
tx_egress_timestamp_96b_valid[]
Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,tx_egress_timestamp_96b_data[], and the fingerprint,tx_egress_timestamp_96b_fingerprint[], of the TX frame.
tx_egress_timestamp_96b_data[][]
Out [NUM_CHANNELS][96] Carries the 96-bit egress timestamp inthe following format:• Bits 48 to 95: 48-bit seconds field• Bits 16 to 47: 32-bit nanoseconds
field• Bits 0 to 15: 16-bit fractional
nanoseconds field
tx_egress_timestamp_96b_fingerprint[][]
Out [NUM_CHANNELS][TSTAMP_FP_WIDTH]
Specifies the fingerprint of the TXframe that the 96-bit timestamp is for.
tx_egress_timestamp_64b_valid[]
Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,tx_egress_timestamp_64b_data[], and the fingerprint,tx_egress_timestamp_64b_fingerprint[], of the TX frame.
tx_egress_timestamp_64b_data[][]
Out [NUM_CHANNELS][64] Carries the 64-bit egress timestamp inthe following format:• Bits 16 to 63: 48-bit nanoseconds
field• Bits 0 to 15: 16-bit fractional
nanoseconds field
tx_egress_timestamp_64b_fingerprint[][]
Out [NUM_CHANNELS][TSTAMP_FP_WIDTH]
Specifies the fingerprint of the TXframe that the 64-bit timestamp is for.
rx_ingress_timestamp_96b_valid[]
Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,rx_ingress_timestamp_96b_data[]. The MAC IP core asserts thissignal in the same clock cycle it assertsavalon_st_rx_startofpacket.
rx_ingress_timestamp_96b_data[][]
Out [NUM_CHANNELS][96] Carries the 96-bit ingress timestamp inthe following format:• Bits 48 to 95: 48-bit seconds field• Bits 16 to 47: 32-bit nanoseconds
field• Bits 0 to 15: 16-bit fractional
nanoseconds field
rx_ingress_timestamp_64b_valid[]
Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,rx_ingress_timestamp_64b_data[]. The MAC IP core asserts thissignal in the same clock cycle it assertsavalon_st_rx_startofpacket.
rx_ingress_timestamp_64b_data[][]
Out [NUM_CHANNELS][64] Carries the 64-bit ingress timestamp inthe following format:
continued...
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Signal Direction Width Description
• Bits 16 to 63: 48-bit nanosecondsfield
• Bits 0 to 15: 16-bit fractionalnanoseconds field
Related Information
IEEE 1588v2 Interface Clocks, Low Latency Ethernet 10G MAC Intel FPGA IP Core UserGuide
8.7. Packet Classifier Interface Signals
Table 36. Packet Classifier Interface Signals
Signal Direction Width Description
tx_egress_timestamp_request_in_valid[]
In [NUM_CHANNELS] Assert this signal to requesttimestamping for the TX frame.This signal must be asserted inthe same clock cycleavalon_st_tx_startofpacket is asserted.
tx_egress_timestamp_request_in_fingerprint[][]
In [NUM_CHANNELS][TSTAMP_FP_WIDTH]
Use this bus to specify thefingerprint that validates thetimestamp for the incomingpacket.
clock_operation_mode_mode[][] In [NUM_CHANNELS][2] Use this signal to specify theclock mode.• 00: Ordinary clock• 01: Boundary clock• 10: End to end transparent
clock• 11: Peer to peer transparent
clock
pkt_with_crc_mode[] In [NUM_CHANNELS] Use this signal to specifywhether or not a packetcontains CRC.• 0: Packet contains CRC• 1: Packet does not contain
CRC
tx_ingress_timestamp_valid[] In [NUM_CHANNELS] Indicates whether or not theresidence time can be updated.• 0: Prevents update for
residence time• 1: Allows update for
residence time based ondecoded results
When this signal is deasserted,thetx_etstamp_ins_ctrl_out_residence_ti me_updatesignal also gets deasserted.
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Signal Direction Width Description
tx_ingress_timestamp_96b_data[][]
In [NUM_CHANNELS][96] 96-bit format of ingresstimestamp that holds the dataso that the output can alignwith the start of an incomingpacket.
tx_ingress_timestamp_64b_data[][]
In [NUM_CHANNELS][64] 64-bit format of ingresstimestamp that holds the dataso that the output can alignwith the start of an incomingpacket.
tx_ingress_timestamp_format[] In [NUM_CHANNELS] The format of the timestampfor calculating the residencetime.• 0: 96 bits• 1: 64 bitsThis signal must be aligned tothe start of an incomingpacket.
8.8. ToD Interface Signals
Table 37. ToD Interface Signals
Signal Direction
Width Description
master_pulse_per_second
Out 1 Pulse per second (PPS) from the master PPS module. Thesignal stay asserted for 10 ms.
start_tod_sync[] In [NUM_CHANNELS] Use this signal to trigger the TOD synchronization process.The time of day of the local TOD is synchronized to the timeof day of the master TOD. The synchronization processcontinues as long as this signal remains asserted.
pulse_per_second_10g[] Out [NUM_CHANNELS] PPS from the 10G PPS module of channel n. The signal stayasserted for 10 ms.
pulse_per_second_1g[] Out [NUM_CHANNELS] PPS from the 1G PPS module of channel n. The signal stayasserted for 10 ms.
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9. Configuration Registers Description
9.1. Register Access Definition
Table 38. Types of Register Access
Access Definition
RO Read only.
RW Read and write.
RWC Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a definedinstruction. The IP core clears the bit(s) upon executing the instruction.
9.2. Low Latency Ethernet 10G MAC
This topic lists the byte offsets the MAC registers.
Table 39. Primary MAC Address
Byte Offset R/W Name HW Reset
0x2008 RW primary_mac_addr0 0x0
0x200C RW primary_mac_addr1 0x0
Table 40. TX Configuration and Status Registers
Byte Offset R/W Name HW Reset
0x4000 RW tx_packet_control 0x0
0x4004 RO tx_packet_status 0x0
0x4100 RW tx_pad_control 0x1
0x4200 RW tx_crc_control 0x3
0x4400 RW tx_preamble_control 0x0
0x6004 RW tx_frame_maxlength 0x5EE(1518)
0x4300 RO tx_underflow_counter0 0x0
0x4304 RO tx_underflow_counter1 0x0
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ISO9001:2015Registered
Table 41. Flow Control Registers
Byte Offset R/W Name HW Reset
0x4500 RW tx_pauseframe_control 0x0
0x4504 RW tx_pauseframe_quanta 0x0
0x4508 RW tx_pauseframe_enable 0x1
0x4680 RW tx_pfc_priority_enable 0x0
0x4600 RW pfc_pause_quanta_0 0x0
0x4604 RW pfc_pause_quanta_1 0x0
0x4608 RW pfc_pause_quanta_2 0x0
0x460C RW pfc_pause_quanta_3 0x0
0x4610 RW pfc_pause_quanta_4 0x0
0x4614 RW pfc_pause_quanta_5 0x0
0x4618 RW pfc_pause_quanta_6 0x0
0x461C RW pfc_pause_quanta_7 0x0
0x4640 RW pfc_holdoff_quanta_0 0x1
0x4644 RW pfc_holdoff_quanta_1 0x1
0x4648 RW pfc_holdoff_quanta_2 0x1
0x464C RW pfc_holdoff_quanta_3 0x1
0x4650 RW pfc_holdoff_quanta_4 0x1
0x4654 RW pfc_holdoff_quanta_5 0x1
0x4658 RW pfc_holdoff_quanta_6 0x1
0x465C RW pfc_holdoff_quanta_7 0x1
Table 42. RX Configuration and Status Registers
Byte Offset R/W Name HW Reset
0x0000 RW rx_transfer_control 0x0
0x0004 RO rx_transfer_status 0x0
0x0100 RW rx_padcrc_control 0x1
0x0200 RW rx_crccheck_control 0x2
0x0400 RW rx_custom_preamble_forward 0x0
0x0500 RW rx_preamble_control 0x0
0x2000 RW rx_frame_control 0x3
0x2004 RW rx_frame_maxlength 1518
0x2010 RW rx_frame_spaddr0_0 0x0
0x2014 RW rx_frame_spaddr0_1 0x0
0x2018 RW rx_frame_spaddr1_0 0x0
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Byte Offset R/W Name HW Reset
0x201C RW rx_frame_spaddr1_1 0x0
0x2020 RW rx_frame_spaddr2_0 0x0
0x2024 RW rx_frame_spaddr2_1 0x0
0x2028 RW rx_frame_spaddr3_0 0x0
0x202C RW rx_frame_spaddr3_1 0x0
0x2060 RW rx_pfc_control 0x1
0x0300 RO rx_pktovrflow_error 0x0
Table 43. TX Timestamp Registers
Byte Offset R/W Name HW Reset
0x4440 RW tx_period_10G 0x33333
0x4448 RW tx_fns_adjustment_10G 0x0
0x444C RW tx_ns_adjustment_10G 0x0
0x4460 RW tx_period_mult_speed 0x80000
0x4468 RW tx_fns_adjustment_mult_speed 0x0
0x446C RW tx_ns_adjustment_mult_speed 0x0
Table 44. RX Timestamp Registers
Byte Offset R/W Name HW Reset
0x0440 RW rx_period_10G 0x33333
0x0448 RW rx_fns_adjustment_10G 0x0
0x044C RW rx_ns_adjustment_10G 0x0
0x0460 RW rx_period_mult_speed 0x80000
0x0468 RW rx_fns_adjustment_mult_speed 0x0
0x046C RW rx_ns_adjustment_mult_speed 0x0
Table 45. TX and RX Statistics Registers
Byte Offset R/W Name HW Reset
0x7000 RO tx_stats_clr 0x0
0x3000 RO rx_stats_clr 0x0
0x7008:0x700C RO tx_stats_framesOK 0x0
0x3008:0x300C RO rx_stats_framesOK 0x0
0x7010:0x7014 RO tx_stats_framesErr 0x0
0x3010:0x3014 RO rx_stats_framesErr 0x0
0x7018:0x701C RO tx_stats_framesCRCErr 0x0
0x3018:0x301C RO rx_stats_framesCRCErr 0x0
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Byte Offset R/W Name HW Reset
0x7020:0x7024 RO tx_stats_octetsOK 0x0
0x3020:0x3024 RO rx_stats_octetsOK 0x0
0x7028:0x702C RO tx_stats_pauseMACCtrl_Frames 0x0
0x3028:0x302C RO rx_stats_pauseMACCtrl_Frames 0x0
0x7030:0x7034 RO tx_stats_ifErrors 0x0
0x3030:0x3034 RO rx_stats_ifErrors 0x0
0x7038:0x703C RO tx_stats_unicast_FramesOK 0x0
0x3038:0x303C RO rx_stats_unicast_FramesOK 0x0
0x7040:0x7044 RO tx_stats_unicast_FramesErr 0x0
0x3040:0x3044 RO rx_stats_unicast_FramesErr 0x0
0x7048:0x704C RO tx_stats_multicast_FramesOK 0x0
0x3048:0x304C RO rx_stats_multicast_FramesOK 0x0
0x7050:0x7054 RO tx_stats_multicast_FramesErr 0x0
0x3050:0x3054 RO rx_stats_multicast_FramesErr 0x0
0x7058:0x705C RO tx_stats_broadcast_FramesOK 0x0
0x3058:0x305C RO rx_stats_broadcast_FramesOK 0x0
0x7060:0x7064 RO tx_stats_broadcast_FramesErr 0x0
0x3060:0x3064 RO rx_stats_broadcast_FramesErr 0x0
0x7068:0x706C RO tx_stats_etherStatsOctets 0x0
0x3068:0x306C RO rx_stats_etherStatsOctets 0x0
0x7070:0x7074 RO tx_stats_etherStatsPkts 0x0
0x3070:0x3074 RO rx_stats_etherStatsPkts 0x0
0x7078:0x707C RO tx_stats_etherStatsUndersizePkts 0x0
0x3078:0x307C RO rx_stats_etherStatsUndersizePkts 0x0
0x7080:0x7084 RO tx_stats_etherStatsOversizePkts 0x0
0x3080:0x3084 RO rx_stats_etherStatsOversizePkts 0x0
0x7088:0x708C RO tx_stats_etherStatsPkts64Octets 0x0
0x3088:0x308C RO rx_stats_etherStatsPkts64Octets 0x0
0x7090:0x7094 RO tx_stats_etherStatsPkts65to127Octets 0x0
0x3090:0x3094 RO rx_stats_etherStatsPkts65to127Octets 0x0
0x7098:0x709C RO tx_stats_etherStatsPkts128to255Octets 0x0
0x3098:0x309C RO rx_stats_etherStatsPkts128to255Octets 0x0
0x70A0:0x70A4 RO tx_stats_etherStatsPkts256to511Octets 0x0
0x30A0:0x30A4 RO rx_stats_etherStatsPkts256to511Octets 0x0
continued...
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Byte Offset R/W Name HW Reset
0x70A8:0x70AC RO tx_stats_etherStatsPkts512to1023Octets 0x0
0x30A8:0x30AC RO rx_stats_etherStatsPkts512to1023Octets 0x0
0x70B0:0x70B4 RO tx_stats_etherStatPkts1024to1518Octets 0x0
0x30B0:0x30B4 RO rx_stats_etherStatPkts1024to1518Octets 0x0
0x70B8:0x70BC RO tx_stats_etherStatsPkts1519toXOctets 0x0
0x30B8:0x30BC RO rx_stats_etherStatsPkts1519toXOctets 0x0
0x70C0:0x70C4 RO tx_stats_etherStatsFragments 0x0
0x30C0:0x30C4 RO rx_stats_etherStatsFragments 0x0
0x70C8:0x70CC RO tx_stats_etherStatsJabbers 0x0
0x30C8:0x30CC RO rx_stats_etherStatsJabbers 0x0
0x70D0:0x70D4 RO tx_stats_etherStatsCRCErr 0x0
0x30D0:0x30D4 RO rx_stats_etherStatsCRCErr 0x0
0x70D8:0x70DC RO tx_stats_unicastMACCtrlFrames 0x0
0x30D8:0x30DC RO rx_stats_unicastMACCtrlFrames 0x0
0x70E0:0x70E4 RO tx_stats_multicastMACCtrlFrames 0x0
0x30E0:0x30E4 RO rx_stats_multicastMACCtrlFrames 0x0
0x70E8:0x70EC RO tx_stats_broadcastMACCtrlFrames 0x0
0x30E8:0x30EC RO rx_stats_broadcastMACCtrlFrames 0x0
0x70F0:0x70F4 RO tx_stats_PFCMACCtrlFrames 0x0
0x30F0:0x30F4 RO rx_stats_PFCMACCtrlFrames 0x0
Related Information
Intel FPGA Low Latency Ethernet 10G MAC User GuideFor the description of the MAC registers.
9.3. PHY
9.3.1. 1G/10G PHY
This topic lists the byte offsets of the 1G/10G variant registers for Intel Arria 10devices.
Table 46. PMA Registers
Byte Offset Bit R/W Name
0x1110 1 RW reset_tx_digital
2 RW reset_rx_analog
3 RW reset_rx_dgital
continued...
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Byte Offset Bit R/W Name
0x1184 0 RW phy_serial_loopback
0x1190 0 RW pma_rx_set_locktodata
0x1194 0 RW pma_rx_set_locktoref
0x1198 0 RO pma_rx_is_lockedtodata
0x119C 0 RO pma_rx_is_lockedtoref
0x12A0 0 RW tx_invpolarity
1 RW rx_invpolarity
2 RW rx_bitreversal_enable
3 RW rx_bytereversal_enable
4 RW force_electrical_idle
0x12A4 0 R rx_syncstatus
1 R rx_patterndetect
2 R rx_rlv
3 R rx_rmfifodatainserted
4 R rx_rmfifodatadeleted
5 R rx_disperr
6 R rx_errdetect
Table 47. PCS Registers
Byte Offset Bit R/W Name
0x1200 RW Indirect_addr
0x1204 2 RW RCLR_ERRBLK_CNT
3 RW RCLR_BER_COUNT
0x1208 1 RO HI_BER
2 RO BLOCK_LOCK
3 RO TX_FULL
4 RO RX_FULL
7 RO Rx_DATA_READY
Table 48. Intel Arria 10 GMII PCS Registers
Byte Offset Bit R/W Name
0x1240 9 RW RESTART_AUTO_NEGOTIATION
12 RW AUTO_NEGOTIATION_ENABLE
15 RW RESET
0x1244 2 R LINK_STATUS
continued...
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Byte Offset Bit R/W Name
3 R AUTO_NEGOTIATION_ ABILITY
5 R AUTO_NEGOTIATION_ COMPLETE
0x1250 5 RW FD
6 RW HD
8:7 RW PS2,PS1
13:12 RW RF2,RF1
14 R0 ACK
15 RW NP
0x1254 5 R FD
6 R HD
8:7 R PS2,PS1
13:12 R RF2,RF1
14 R ACK
15 R NP
0x1258 0 R LINK_PARTNER_AUTO_NEGOTIATION_ABLE
1 R PAGE_RECEIVE
0x1288 15:0 RW AN link timer[15:0]
0x128C 4:0 RW AN link timer[4:0]
0x1290 0 RW SGMII_ENA
1 RW USE_SGMII_AN
3:2 RW SGMII_SPEED
Related Information
Intel Arria 10 Transceiver PHY User GuideFor detailed description of the configuration registers of the 1G/10G PHY IP
9.3.2. 1G/2.5G/5G/10G Multi-rate PHY
This topic lists the byte offsets of the 1G/2.5G/5G/10G Multi-rate variant registers forIntel Arria 10 devices.
Register Map
You can access the 16-bit/32-bit configuration registers via the Avalon-MM interface.
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Table 50. Register Map Overview
Address Range Usage Register Width Configuration
0x00 : 0x1F 1000BASE-X/SGMII 16 2.5G, 1G/2.5G, 1G/2.5G/10G
0x400 : 0x41F USXGMII 32 1G/2.5G/5G/10G (USXGMII)
0x461 Serial Loopback 32 1G/2.5G/5G/10G (USXGMII)
Register Definitions
Observe the following guidelines when accessing the registers:
• Do not write to reserved or undefined registers.
• When writing to the registers, perform read-modify-write operation to ensure thatreserved or undefined register bits are not overwritten.
Table 51. 1G/2.5G/5G/10G Multi-rate Register Definitions
Address Name Description Access HW ResetValue
0x00 control Bit [15]: RESET. Set this bit to 1 to trigger a softreset.The PHY clears the bit when the reset is completed.The register values remain intact during the reset.
RWC 0
Bit[14]: LOOPBACK. Set this bit to 1 to enableloopback on the serial interface.
RW 0
Bit [12]: AUTO_NEGOTIATION_ENABLE. Set this bitto 1 to enable auto-negotiation.Auto-negotiation is supported only in 1GbE.Therefore, set this bit to 0 when you switch to aspeed other than 1GbE.
RW 0
Bit [9]: RESTART_AUTO_NEGOTIATION. Set this bitto 1 to restart auto-negotiation.The PHY clears the bit as soon as auto-negotiation isrestarted.
RWC 0
All other bits are reserved. — —
0x01 status Bit [5]: AUTO_NEGOTIATION_COMPLETE. A value of"1" indicates that the auto-negotiation is completed.
RO 0
Bit [3]: AUTO_NEGOTIATION_ABILITY. A value of"1" indicates that the PCS function supports auto-negotiation.
RO 1
Bit [2]: LINK_STATUS. A value of "0" indicates thatthe link is lost. A value of "1" indicates that the link isestablished.
RO 0
All other bits are reserved. — —
0x02:0x03 phy_identifier The value set in the PHY_IDENTIFIER parameter. RO Value ofPHY_IDEN
TIFIERparameter
0x04 dev_ability Use this register to advertise the device abilitiesduring auto-negotiation.
— —
Bits [13:12]: RF. Specify the remote fault. RW 00
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Address Name Description Access HW ResetValue
• 00: No error.• 01: Link failure.• 10: Off-line.• 11: Auto-negotiation error.
Bits [8:7]: PS. Specify the PAUSE support.• 00: No PAUSE.• 01: Symmetric PAUSE.• 10: Asymmetric PAUSE towards the link partner.• 11: Asymmetric and symmetric PAUSE towards
the link device.
RW 11
Bit [5]: FD. Ensure that this bit is always set to 1. RW 1
All other bits are reserved. — —
0x05(1000BASE-X
mode)
partner_ability The device abilities of the link partner during auto-negotiation.
— —
Bit [14]: ACK. A value of "1" indicates that the linkpartner has received three consecutive matchingability values from the device.
RO 0
Bits [13:12]: RF. The remote fault.• 00: No error.• 01: Link failure.• 10: Off-line.• 11: Auto-negotiation error.
RO 0
Bits [8:7]: PS. The PAUSE support.• 00: No PAUSE.• 01: Symmetric PAUSE.• 10: Asymmetric PAUSE towards the link partner.• 11: Asymmetric and symmetric PAUSE towards
the link device.
RO 0
Bit [6]: HD. A value of "1" indicates that half-duplexis supported.
RO 0
Bit [5]: FD. A value of "1" indicates that full-duplex issupported.
RO 0
All other bits are reserved. — —
0x05 (SGMIImode)
partner_ability The device abilities of the link partner during auto-negotiation.
— —
Bit [11:10]: COPPER_SPEEDLink partner speed:• 00: copper interface speed is 10 Mbps• 01: copper interface speed is 100 Mbps• 10: copper interface speed is 1 Gigabit• 11: reserved
RO 00
Bit [12]: COPPER_DUPLEX_STATUSLink partner capability:• 1: copper interface is capable of full-duplex
operation• 0: copper interface is capable of half-duplex
operation
RO 0
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Address Name Description Access HW ResetValue
Bit [14]: ACK. Link partner acknowledge. A value of 1indicates that the device received three consecutivematching ability values from its link partner.
RO 0
Bit [15]: COPPER_LINK_STATUSLink partner status:• 1: copper interface link is up• 0: copper interface link is down
RO 0
All other bits are reserved. — —
0x06 an_expansion The PCS capabilities and auto-negotiation status. — —
Bit [1]: PAGE_RECEIVE. A value of "1" indicates thatthe partner_ability register has been updated. Thisbit is automatically cleared once it is read.
RO 0
Bit [0]: LINK_PARTNER_AUTO_NEGOTIATION_ABLE.A value of "1" indicates that the link partner supportsauto-negotiation.
RO 0
0x07 device_next_page
The PHY does not support the next page feature.These registers are always set to 0.
RO 0
0x08 partner_next_page
RO 0
0x09:0x0F Reserved — — —
0x10 scratch Provides a memory location to test read and writeoperations.
RW 0
Bit [31:16]: Reserved — —
0x11 rev The current version of the PHY IP core. RO Currentversion ofthe PHY
Bit [31:16]: Reserved — —
0x12:0x13 link_timer 21-bit auto-negotiation link timer.• Offset 0x12: link_timer[15:0]. Bits [8:0] are
always be set to 0.• Offset 0x13: link_timer[20:16] occupies the lower
5 bits. The remaining 11 bits are reserved andmust always be set to 0.
RW 0
0x14 if_mode Interface Mode Register — —
Bit [0]: SGMII_ENADetermines the PCS function operating mode. Settingthis bit to 1b'1 enables SGMII mode. Setting this bitto 1b'0 enables 1000BASE-X gigabit mode.
RW 0
Bit [1]: USE_SGMII_ANIn SGMII mode, setting this bit to 1b'1 configures thePCS with the link partner abilities advertised duringauto-negotiation. If this bit is set to 1b'0, the PCSfunction should be configured with the SGMII_SPEEDbits.
RW 0
Bit [3:2]: SGMII_SPEED RW 0
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Address Name Description Access HW ResetValue
When the PCS operates in SGMII mode (SGMII_ENA= 1) and is not programmed for automaticconfiguration (USE_SGMII_AN = 0), the followingencodings specify the speed:• 2'b00: 10 Mbps• 2'b01: 100 Mbps• 2'b10: Gigabit• 2'b11: ReservedThese bits are not used when SGMII_ENA = 0 orUSE_SGMII_AN = 1.
All other bits are reserved. — —
0x15:0x1F Reserved — — —
0x400 usxgmii_control Control Register — —
Bit [0]: USXGMII_ENA:• 0: 10GBASE-R mode• 1: USXGMII mode
RW 0
Bit [1]: USXGMII_AN_ENA is used whenUSXGMII_ENA is set to 1:• 0: Disables USXGMII Auto-Negotiation and
manually configures the operating speed with theUSXGMII_SPEED register.
• 1: Enables USXGMII Auto-Negotiation, andautomatically configures operating speed with linkpartner ability advertised during USXGMII Auto-Negotiation.
RW 1
Bit [4:2]: USXGMII_SPEED is the operating speed ofthe PHY in USXGMII mode and USE_USXGMII_AN isset to 0.• 3’b000: 10M• 3’b001: 100M• 3’b010: 1G• 3’b011: 10G• 3’b100: 2.5G• 3’b101: 5G• 3’b110: Reserved• 3’b111: Reserved
RW 0
Bit [8:5]: Reserved — —
Bit [9]: RESTART_AUTO_NEGOTIATIONWrite 1 to restart Auto-Negotiation sequence The bitis cleared by hardware when Auto-Negotiation isrestarted.
RWC 0
Bit [31:10]: Reserved — —
0x401 usxgmii_status Status Register — —
Bit [1:0]: Reserved — —
Bit [2]: LINK_STATUS indicates link status forUSXGMII all speeds• 1: Link is established• 0: Link synchronization is lost, a 0 is latched
RO 0
Bit [4:3]: Reserved — —
continued...
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Address Name Description Access HW ResetValue
Bit [5]: AUTO_NEGOTIATION_COMPLETEA value of 1 indicates the Auto-Negotiation process iscompleted.
RO 0
Bit [31:6]: Reserved — —
0x402:0x404 Reserved — — —
0x405 usxgmii_partner_ability
Device abilities advertised to the link partner duringAuto-Negotiation
— —
Bit [6:0]: Reserved — —
Bit [7]: EEE_CLOCK_STOP_CAPABILITYIndicates whether or not energy efficient Ethernet(EEE) clock stop is supported.• 0: Not supported• 1: Supported
RO 0
Bit [8]: EEE_CAPABILITYIndicates whether or not EEE is supported.• 0: Not supported• 1: Supported
RO 0
Bit [11:9]: SPEED• 3'b000: 10M• 3'b001: 100M• 3'b010: 1G• 3'b011: 10G• 3'b100: 2.5G• 3'b101: 5G• 3'b110: Reserved• 3'b111: Reserved
RO 0
Bit [12]: DUPLEXIndicates the duplex mode.• 0: Half duplex• 1: Full duplex
RO 0
Bit [13]: Reserved — —
Bit [14]: ACKNOWLEDGEA value of 1 indicates that the device has receivedthree consecutive matching ability values from its linkpartner.
RO 0
Bit [15]: LINKIndicates the link status.• 0: Link down• 1: Link up
RO 0
Bit [31:16]: Reserved — —
0x406:0x411 Reserved — — —
0x412 usxgmii_link_timer
Auto-Negotiation link timer. Sets the link timer valuein bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensurethat it matches the link timer value of the externalNBASE-T PHY IP Core.The reset value sets the link timer to approximately1.6 ms.
[19:14]:RW
[13:0]: RO
[19:14]:1F
[13:0]: 0
continued...
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Address Name Description Access HW ResetValue
Bits [13:0] are reserved and always set to 0.
0x413:0x41F Reserved — — —
0x461 phy_serial_loopback
Configures the transceiver serial loopback in the PMAfrom TX to RX.
— —
Bit [0]• 0: Disables the PHY serial loopback• 1: Enables the PHY serial loopback
RW 0
Bit [31:1]: Reserved — —
9.4. Transceiver Reconfiguration
Table 52. Transceiver Reconfiguration Register Map
WordOffset Name Bits Description Access HW
Reset
0x00 logical_channel_number
[9:0] The logical number of the reconfiguration block. RW 0x000
[31:10] Reserved — —
0x01 control [1:0] Specify the new operating speed:• 00: 1 Gbps• 01: 2.5 Gbps• 10: Reserved• 11: 10 Gbps
RW 0x00
[15:2] Reserved — 0x000
[16] Writing 1 to this bit when it is 0 starts thereconfiguration process. The bit clears when theprocess is completed.
RWC 0x0
[31:17] Reserved — 0x000000
0x02 status [0] When set to 1, indicates the reconfiguration processis in progress.
RO 0x0
[31:1] Reserved — —
9.5. TOD
Table 53. TOD Register Map
Byte Offset Name Bits Description Access HW Reset
0x0000 SecondsH [15:0] The upper 16 bits of the second field. RW 0x0
[31:16] Reserved. — —
0x0004 SecondsL 32 The lower 32 bits of the second field. RW 0x0
0x0008 NanoSec 30 The nanosecond field. RW 0x0
0x0010 Period [15:0] The time of day. The period in fractionalnanosecond.
RW n (4)
[19:16] The time of day. The period in nanosecond.
continued...
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Byte Offset Name Bits Description Access HW Reset
[31:20] Reserved. — —
0x0014 AdjustPeriod
[15:0] The offset adjustment period. The period infractional nanosecond.
RW 0x0
[19:16] The offset adjustment period. The period innanosecond.
[31:20] Reserved. — —
0x0018 AdjustCount
[19:0] The number of adjusted period in clock cycles. RW 0x0
[31:20] Not used. — —
(4) The default value for the period depends on the frequency of the PHY speed. For example, iffrequency is 125 MHz, the period is 8 ns (PERIOD_NS = 0x0008 and PERIOD_FNS = 0x0000).
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10. Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IPDesign Example User Guide Archives
If an IP core version is not listed, the user guide for the previous IP core version applies.
IP Core Version User Guide
18.0 Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide
17.1 Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Arria 10Devices
16.1 Low Latency Ethernet 10G MAC Design Example User Guide
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
11. Document Revision History for the Low LatencyEthernet 10G MAC Intel Arria 10 FPGA IP Design ExampleUser Guide
Document Version Intel QuartusPrime Version
Changes
2019.09.23 19.1 • Added a note in the following topic to state that the Xcelium simulatoris supported in Intel Quartus Prime Pro Edition software only:— Directory Structure— Procedure in Compiling and Simulating the Design
• Updated the Hardware and Software Requirements topics for all designexample chapters.
2019.05.10 19.1 • Updated Table: Parameters in the Example Design Tab:— Updated the parameter name Example Design Files for
Simulation or Synthesis to Example Design Files.— Updated the parameter name Enable NPDME support to Enable
Native PHY Debug Master Endpoint (NPDME).• Updated Figure: Example Design Tab.
2019.04.15 19.1 • Changed Altera Debug Master Endpoint (ADME) to Native PHY DebugMaster Endpoint (NPDME).
continued...
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
Document Version Intel QuartusPrime Version
Changes
2018.10.05 18.0 • Updated Figure: Block Diagram—10M/100M/1G/2.5G/5G/10G(USXGMII) Ethernet Design Example.
• Updated Table: Avalon-MM Interface Signals:— Added the following signals: csr_mch_write,
csr_mch_writedata, csr_mch_read, csr_mch_readdata,csr_mch_address, and csr_mch_waitrequest.
— Removed the following signals: csr_write, csr_writedata,csr_read, csr_readdata, csr_address, andcsr_waitrequest
• Updated Table: Parameters in the Example Design Tab:— Added a note to parameter Enable ADME support to clarify that
this option is only available from Intel Quartus Prime Pro Editionversion 17.0 onwards.
— Added a note to parameter Partial Reconfiguration Ready toclarify that this option is only available from Intel Quartus Prime ProEdition version 17.1 onwards.
• Updated the Configuration Registers Description chapter:— Added the Register Access Definition topic.— Added the following PHY topics:
• 1G/10G PHY• 1G/2.5G/5G/10G PHY
• Added Timing Constraint topic to 1G/2.5G/10G Ethernet DesignExample for Intel Arria 10 Devices chapter.
2018.05.16 18.0 • Renamed the document as Low Latency Ethernet 10G MAC Intel Arria10 FPGA IP Design Example User Guide.
• Updated the 10G USXGMII Ethernet Design Example for Intel Arria 10Devices chapter:— Added 10M/100M speed support for 10M/100M/1G/2.5G/5G/10G
(USXGMII) Ethernet design example.— Updated all references to 10G USXGMII references to 10M/
100M/1G/2.5G/5G/10G (USXGMII).— Updated Table: Command Parameters.— Updated Table: Register Map to include byte offset for Native PHY
Reconfiguration block.• Added support for Xcelium simulator.• Updated the procedure steps of the Compiling and Testing the Design
in Hardware topic.• Restructured description for Hardware Testing topics for all design
example chapters.• Updated Table: Clock and Reset Interface Signals.• Updated the following Figures:
— Directory Structure for the Design Example— Clocking Scheme for Ethernet Design Example with IEEE 1588v2
Feature— Master Reset— Interface Signals of the 10GBASE-R Ethernet Design Example— Master Reset for 10M/100M/1G/10G and 1G/10G Ethernet design
examples.• Updated for latest branding standards.• Made editorial updates throughout the document.
2018.03.28 17.1 • Updated 10G USXGMII Ethernet Design Example section:— Corrected Y5 value from 322.265625 MHz to 644.53125 Mhz in the
Hardware Testing topic.— Updated Figure: Clocking Scheme for 10G USXGMII Ethernet Design
Example.— Added a step on Test Procedure topic to enable PHY serial loopback
on Channel 0.
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Date Version Changes
November 2017 2017.11.13 • Updated Figure: Example Design Tab.• Updated the Clocking and Reset scheme for 10GBASE-R Design
example: Added tx_coreclkin and rx_coreclkin clock ports to thePHY block.
2017.11.06 • Renamed the document as Intel FPGA Low Latency Ethernet 10G MACDesign Example User Guide for Intel Arria 10 Devices.
• Updated the descriptions for FIFO component in the "DesignComponents" table for the 10M/100M/1G/ 10G, 1G/10G, 10BASE-R,1G/2.5G, 1G/2.5G/10G, and 10G USXGMII Ethernet design examples.
• Added notes to clarify that the IOPLL input reference clock is sourcingfrom input clock through global clock network in the Clocking Schemestopics for the 10M/100M/1G/ 10G, 1G/10G, and 10GBASE-R Ethernetdesign examples.
• Updated the Quick Start Guide section:— Updated Figures: Example Design Tab and Block Diagram of the
Hardware Setup— Updated the "Directory and File Description" table.— Removed rtl directory from the "Directory and File Description"
table.— Changed heading title of the Design Parameters Description topic to
Design Example Parameters.— Changed heading title of the Design Parameters Description topic to
Design Example Parameters.— Updated the "Parameters in the Example Design Tab" table:
• Added Enable ADME support parameter and description.• Updated the descriptions for Generate File Format and Select
Board parameters.— Updated the Procedure subtopic under Compiling and Simulating the
Design topic.• Updated the 10M/100M/1G/10G Ethernet Design Example chapter:
— Renamed the topic Multi-speed 10M – 10G Ethernet DesignExamples to 10M/100M/1G/10G Ethernet Design Example.
• Updated the 10BASE-R Ethernet Design Example chapter:— Renamed the topic 10BASE-R Design Examples to 10BASE-R
Ethernet Design Examples.— Updated Figure: Block Diagram—10GBASE-R Design Example— Updated csr_clk value from 100 MHz to 125 MHz in the "Clocking
and Reset Scheme for 10GBASE-R Design Example" figure.— Updated "Register Map" table: Updated the byte offset values for RX
SC FIFO and TX SC FIFO.— Updated the description in the Hardware Description topic.
• Updated 1G/2.5G Ethernet Design Example chapter:— Updated the 1G/2.5G Ethernet Design Example topic.— Added Topic—Partial Reconfiguration Ready.
• Updated the 1G/2.5G/10G Ethernet Design Example chapter:— Updated the 1G/2.5G/10G Ethernet Design Example topic.— Added Topic—Partial Reconfiguration Ready.— Added Figure—Sample Simulation Output
continued...
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Date Version Changes
• Updated 10G USXGMII Ethernet Design Examples chapter:— Updated the 10G USXGMII Ethernet Design Example topic.— Updated "Design Components" table: Added channel address
decoder, multi-channel address decoder, and top address decodercomponents.
— Updated the description in the Hardware Description topic.— Added Figure—Sample Simulation Output— Updated "Clocking Scheme for 10G USXGMII Ethernet Design
Example" and "Reset Scheme for 10G USXGMII Ethernet DesignExample" figures: Updated the reference clock value from644.53125 MHz to 322.265625 MHz.
• Updated "Clock and Reset Interface Signals table: Updated thedescription for the mm_clk and csr_clk signals.
• Updated PHY topic:— Updated "PMA Registers" table: Updated bit values of five registers.— Updated "Intel Arria 10 GMII PCS Registers" table: Updated bit
names for 0x1240.• Merged the 10G TOD, and 1G TOD topics with the Master TOD and
changed heading title to ToD.• Updated "ToD Register Map" table: Added bits information.• Updated for latest branding standards.• Made editorial updates throughout the document.
June 2017 2017.06.20 Corrected typographical errors in the Design Components topic for 1G/2.5G Ethernet design example.
2017.06.19 • Rebranded as Intel.• Updated the "Transceiver Reconfiguration Register Map" table to include
operation speed support of 10 Gbps for control register.• Added Partial Reconfiguration Ready feature for the 1G/2.5G and 1G/
2.5G/10G Ethernet design examples.• Renamed the document as Intel Arria 10 Low Latency Ethernet 10G
MAC Design Example User Guide.
October 2016 2016.10.31 • Changed the title of the document to be consistent with other designexample user guides.
• Adjusted the rows in the table that describes the design parametersdescription to match the parameter editor user interface.
• Updated the steps to run the simulation scripts to clarify that thecommands are to be run at the system's command prompt.
• Updated the simulation script command for VCS and NCSim from"source tb_run.sh" to "sh tb_run.sh".
• Updated the features of the 10BASE-R design example from supportingsingle channel to now support dual channels.
• Added related information links that provide more information aboutthe Avalon-ST and IEEE 1588v2 interface clocks.
May 2016 2016.05.20 • Updated the Quick Start Guide to include the latest GUI and proceduresteps.
• Updated the Channel Reset diagrams and description for the Multi-speed 10M - 10G and 1G/10G Ethernet design examples.
• Updated the Clocking diagram the Multi-speed 10M - 10G Ethernetdesign example with the IEEE 1588v2 feature.
• Updated the Signal Tap Signals topic for the Multi-speed 10M - 10G,1G/10G, and 10GBASE-R Ethernet design examples.
• Updated Chapter 4 to include a 10GBASE-R design example with theRegister Mode disabled.
• Added Chapters 5, 6, and 7, which document 4 new design examples.• Updated Interface Signals appendix.
December 2015 2015.12.14 Initial release.
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IPDesign Example User Guide
UG-20016 | 2019.09.23
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