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Date: 1/6/2016

Revision: 1.0

Arria 10 SOC Scalable Multispeed 10M-10G

Ethernet Design

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Table of Contents

Table of Contents Introduction .................................................................................................................................................. 3

Feature: ..................................................................................................................................................... 3

Design Example Block Diagram ..................................................................................................................... 4

Using the reference Design: .......................................................................................................................... 6

Requirements: ........................................................................................................................................... 6

Hardware Test Procedures: ...................................................................................................................... 6

Design Example Debug features: ................................................................................................................ 12

Document Revision History ......................................................................................................................... 14

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Introduction This reference design describes a scalable Multispeed 10M-10G Ethernet design that

demonstrates Ethernet operations of the Altera® Low Latency Ethernet 10G MAC & Arria 10

1G/10G PHY MegaCore® functions targeted on Altera Arria 10 SOC FPGA development kit. It

provides flexible test and demonstration platforms on which user can control, test, and monitor

the Ethernet operations on the TX and RX datapaths.

Feature

The design example offers the following features:

• Support multi speed operation of 10 Megabits per second (Mbps) to 10 Gigabits per second

(Gbps) with Arria 10 1G/10G PHY.

• Support scalability from 1 to 12 channels Ethernet MAC and PHY.

• Provide packet monitoring system on transmit and receive data paths and report Ethernet

MAC statistics counters for transmit and receive data paths.

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Design Example Block Diagram

Figure 1: Block Diagram of the Design

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Table 1: Design Components of the design

Component Description

LL 10GbE MAC The Low Latency Ethernet 10G MAC IP core with the following configuration: • Speed: 1G/10G • Datapath options: TX & RX • Enable ECC on memory blocks: Not selected • Enable supplementary address: Selected • Enable statistics collection: Selected • Statistics counters: Memory-based • All Legacy Ethernet 10G MAC Interfaces options: Selected

PHY The Altera 1G/10G and 10GBASE-KR PHY IP. The design examples use the 1G/10G IP variant.

Address decoder Decodes the addresses of the components in each Ethernet channel.

Reset controller Synchronizes the reset of all design components

Transceiver Reset Controller

The Altera Transceiver PHY Reset Controller IP core. Resets the transceiver.

PLL Generates clocks for all design components.

ATX PLL Generates a TX serial clock for the Arria 10 10G transceiver.

FIFO The Avalon Streaming (Avalon-ST) single-clock FIFO. Buffers the RX and TX data between the MAC IP core and the client.

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Using the reference Design

Requirements

Altera uses the following software & hardware to test the design examples :

Altera Complete Design Suite (ACDS) version 16.0

A10 SOC clock control (https://www.altera.com/products/boards_and_kits/dev-

kits/altera/arria-10-soc-development-kit.html)

Arria 10 SoC Development Kit (10AS066N4F40I3SGES)

2 1G/10G Finisar SFP+ modules

SFP fiber cable & self-loopback fiber cable

Hardware Test Procedures

1. Upon power on the A10 SOC FPGA board and connect the board to PC via JTAG cable, open

the A10 SoC Clock controller tool to set the 10G reference clock ( 322.265625Mhz), 1G

reference clock (125Mhz) and mm_clk ( 100Mhz) for CLK2 , CLK3 and CLK0 respectively as

shown:

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2. Open the programmer and download the design sof file. (Design pre-compiled with 2

channels)

3. Open the “In system sources and probes“ and set the source [0] , [1] and [2] to 1 to release

the master reset, channel [0] and channel [1] resets respectively as shown:

4. Open System Console tool. Go to /hwtesting/system_console directory and source the

“main.tcl” file.

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5) Test cases:

Table 2: Hardware Test Cases

Test Case Command Example

PHY internal serial loopback

TEST_PHYSERIAL_LOOPBACK <channel> <speed_test> <burst_ size>

TEST_PHYSERIAL_LOOPBACK 0 10G 1000

External loopback TEST_SMA_LB <channel> <speed_ test> <burst_size>

TEST_SMA_LB 0 10G 1000

Table 3: Command Parameters:

Parameter Valid Values Description

channel 0 to the number of channel specified for the design

The number of channels for the test. speed_

speed_test 10G, 1G, 100M , 10M The PHY speed.

burst_size integer The number of packets to generate for the test.

A: PHYSERIAL LOOPBACK TEST:

i) From System Console, type command “ TEST_PHYSERIAL_LOOPBACK 0 10G 10000” to enable

the channel 0 PHY serial loopback , configure the PHY to 10G speed mode and test with 10000

packets. You may test for 1G, 100M and 10M speed modes with the same command with

speed_test parameter change.

ii) System console will print out total no of packets successfully received by the channel 0

packet checker and also report out the LL 10G MAC TX & RX statistic counters.

Note: The design is pre-compiled with 2 channels, thus, user can perform similar test for

channel 1 (SFP B).

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B: SFP SELF LOOPBACK TEST:

i) Configure the board SFP A and SFP B control registers to set the rate_select bits to 2’b11 for

10G Speed test. From System Console, type command “CONFIG_SFP_A_B_RATESEL” (Note:

user just need to configure it once as long as the board continues power ON).

ii). Connect the SFP A ( channel 0) / SFP B ( Channel 1) ports with a fiber self-loopback cable.

iii) From System Console , type command “TEST_SMA_LOOPBACK 0 10G 10000” to disable the

channel 0 PHY serial loopback , configure the PHY to 10G speed mode and test with 10000

packets. Similarly, you may trigger for 1G, 100M or 10M speed test with the similar command.

iv)System console will print out total no of packets successfully received by the channel 0

packet checker and also report out the LL 10G MAC TX & RX statistic counters.

Note: The design is pre-compiled with 2 channels, thus, user can perform similar test for

channel 1 (SFP B).

C: INTER SFP PORTS TEST ( SFP A SFP B):

i) Configure the SFP A and SFP B control registers to set the rate_select bits to 2’b11 . From

System Console, type command “CONFIG_SFP_A_B_RATESEL” . (skip the step if you have done

it once before).

ii). Connect the SFP A and SFP B port with a fiber cable.

iii). From System Console, type command “TEST_SFPP_ENA_ST_LOOPBACK 1” to enable the

channel 1 loopback mode at Avalon-ST user interface .

iv).Trigger the packet generator at channel 0 to send 10000 packets with command

“TEST_SFPP_WO_ENA_ST_LOOPBACK 0 10000 “ .

v). The 10000 packets will then be transmitted from channel 0 packet generator Channel 0

TX SFP A TX Fiber cable SFP B RX channel 1 RX loopback at Avalon-ST interface

Channel 1 TX SFP B TX fiber cable SFP A RX Channel 0 TX channel 0 packet

checker.

vi). System console will print out total no of packets successfully received by the channel 0

packet checker and also report out the LL 10G MAC TX & RX statistic counters.

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6. Example of System Console result (screenshot)

All 10000 good packets received

successfully by the monitor module

with throughput of 9.62Gbps ( running

in 10G mode)

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MAX TX statistic counter shows all

10000 good packets have been

transmitted out from the IP core.

MAX RX statistic counter shows all

10000 good packets have been

received successfully by the IP.

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Design Example Debug features

This design has included 1 STP file (stp1.stp) to enable user for self-debug if encounter

hardware design bring up issue. There are 3 instances in the stp file:

status – monitor design channel ready , master reset , channel reset , PHY status and

external clock frequency checker signals.

xgmii – monitor the packet condition at xgmii and client Avalon-ST interfaces.( 10G)

gmii - monitor the packet condition at gmii interface (1G)

a. status instance:

The stp screenshot shows that both channel 0 and 1 are ready with resets de-asserted. Channel

0 is UP in 10G mode ( speed_sel = 2’b00) whereas channel 1 is UP in 1G mode ( speed_sel =

2’b01).

Besides, there is 1 clock frequency checker module included in the design to check for the PHY

rx recovery clock, 10G xgmii_clk , 1G reference clock and 10G reference clock frequencies as

shown in the stp signals below:

Channel 0 10G & 1G

link status

Channel 1 10G & 1G

link status

Channels ready & resets

Channels Speed mode

phy_rx_recovered_clk xgmii_clk pll_ref_clk_1g pll_ref_clk_10g

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User needs to make sure that the design has been provided with correct 10G and 1G reference

clock sources : pll_ref_clk_10g = 322Mhz and pll_ref_clk_1g = 125Mhz. The xgmii_clk which is

the 10g core clock should be 156Mhz. The phy_rx_recovered_clk should be 257Mhz if the

design is running in 10G speed mode and 125Mhz if the design is running in 1G speed mode.

b. xgmii instance:

c. gmii :

Screenshots b) and c) consist of xgmii (10G) , gmii (1G) and Avalon-ST ( client ) interfaces

datapath signals to monitor and debug the packets condition during transmission and reception

time.

Note that the STP file provided consists only the channel 0 and channel 1 signals for issue

debug. Similar signals can be added for other channels ( channel 2 and onwards) if user scale

the design up to more than 2 channels by setting the “NUM_CHANNELS “ parameter in the top

level wrapper file (altera_eth_top.sv).

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Document Revision History Table 4 shows the revision history for this document.

Table 4: Document Revision History

Date Version Changes

1 June 2016 1.0 Initial release